Linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier

Abstract

The invention discloses a linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier. The circuit comprises a power divider, a delay network, a main path input matching network, an auxiliary path input matching network, a main path driving stage transistor, an auxiliary path driving stage transistor module, a main path intermediate stage matching network, an auxiliary path intermediate stage matching network, a main transistor, an auxiliary transistor module and a distributed output combining network based on a band-pass T structure. The distributed unit circuit based on the band-pass T structure is adopted to replace a traditional capacitor loading transmission line network, the matching bandwidth of the distributed output combining network based on the band-pass T structure under the optimal impedance Qopt value of a transistor can be remarkably improved, and compared with the prior art, the matching bandwidth of the distributed output combining network based on the band-pass T structure is greatly improved. The distributed output combining network based on the band-pass T structure has a certain gain expansion characteristic, and the high-linearity DEPA design expansion performance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless communication power amplifiers, and in particular to a linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier. Background Art

[0002] In current communication power amplifier circuit designs, gallium nitride transistors are typically used to provide high power density and excellent thermal performance in the millimeter wave frequency band, thereby improving the average efficiency of the power amplifier under high average-to-peak ratio modulation signals.

[0003] Several existing broadband high back-off efficiency functions include load-modulated balanced amplifier (LMBA), unbalanced amplifier and distributed efficient power amplifier (DEPA). Among them, the DEPA structure includes a traveling wave network and multiple sub-amplifiers. With the special characteristics of the non-uniform traveling wave network, DEPA can support a variety of impedance modulations and theoretically has the potential to achieve broadband operation and high back-off efficiency. For example, the implementation method of the DEPA input network is improved, and the amplitude and phase control of the sub-amplifier is achieved with the help of the traveling wave network, thereby achieving a compact volume, excellent bandwidth and efficiency performance in the sub-6GHz frequency band. However, the application of DEPA technology in the millimeter wave frequency band faces the following problems: First, in the existing DEPA technology, when the auxiliary transistor is turned on, the operation of the main transistor will enter or approach the saturation region, which leads to higher gain compression and poor linearity. Secondly, the high frequency characteristics of millimeter waves and the high bias voltage characteristics of gallium nitride devices lead to extremely high transistor optimal impedance value Q (Q = ωRoptMCout), which increases the complexity of the traveling wave network design.

[0004] Therefore, the prior art still needs to be improved and developed. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a linear broadband gallium nitride millimeter-wave integrated distributed high-efficiency power amplifier to solve the problems of serious parasitic parameter effects of gallium nitride transistors in existing distributed high-efficiency power amplifiers, when the auxiliary transistor is turned on, the operation of the main transistor will enter or approach the saturation region, the transistor impedance value is high, and the matching bandwidth is narrow.

[0006] The technical solution of the present invention is as follows:

[0007] The linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier comprises: a power divider, a delay network, a main input matching network, an auxiliary input matching network, a main driver-level transistor, an auxiliary driver-level transistor module, a main intermediate-level matching network, an auxiliary intermediate-level matching network, a main transistor, an auxiliary transistor module and a distributed output combining network based on a bandpass T structure; wherein the output end of the power divider is respectively connected to the input end of the main input matching network and the input end of the delay network, so as to perform unequal power distribution on the connected RF input signal;

[0008] The output end of the delay network is connected to the input end of the auxiliary input matching network, and is used to adjust the phase difference between the signal at the input end of the auxiliary input matching network and the main signal;

[0009] The output end of the main input matching network is connected to the gate of the main driving stage transistor, and the main input matching network is used to match the port output impedance of the main input matching network to the source impedance of the main driving stage transistor;

[0010] The input end of the auxiliary input matching network is connected to the output end of the delay network, and the output end of the auxiliary input matching network is connected to the auxiliary driving stage transistor module, so as to match the port output impedance of the auxiliary input matching network to the source impedance of the auxiliary driving stage transistor module;

[0011] The input end of the main intermediate-stage matching network is connected to the drain of the main driving-stage transistor, the output end of the main intermediate-stage matching network is connected to the gate of the main transistor, and the main intermediate-stage matching network is used to perform impedance transformation on the RF input signal;

[0012] The input end of the auxiliary circuit intermediate stage matching network is connected to the auxiliary circuit driving stage transistor module, and the output end of the auxiliary circuit intermediate stage matching network is connected to the auxiliary circuit driving stage transistor module, for performing impedance transformation on the RF input signal;

[0013] The input end of the distributed output combining network based on the bandpass T structure is respectively connected to the drain of the main transistor and the output end of the auxiliary transistor module, and the distributed output combining network based on the bandpass T structure is used to realize a broadband traveling wave network and absorb the parasitic parameters of the main transistor and the auxiliary transistor module.

[0014] According to a further configuration of the present invention, the distributed output combining network based on the bandpass T structure comprises: a first bandpass T structure unit, a second bandpass T structure unit, a third bandpass T structure unit, a first output capacitor, a second output capacitor, a third output capacitor, a fourth output capacitor, a first output resistor and a post-matching network;

[0015] One end of the first band-pass T structure unit is connected to the drain of the main transistor and one end of the first output capacitor respectively, and the other end of the first band-pass T structure unit is connected to the first output end of the auxiliary transistor module, the second output capacitor and the common end of the second band-pass T structure unit;

[0016] The other end of the second band-pass T structure unit is connected to the second output end of the auxiliary transistor module, one end of the third output capacitor and the common end of the third band-pass T structure unit;

[0017] The other end of the third band-pass T structure unit is connected to the third output end of the auxiliary transistor module, the fourth output capacitor and the common end of the post-matching network;

[0018] The other end of the first output capacitor, the other end of the second output capacitor, the other end of the third output capacitor and the other end of the fourth output capacitor are grounded;

[0019] The other end of the post-matching network is connected to the RF output end through the first output resistor.

[0020] According to a further configuration of the present invention, in the distributed output combining network based on the bandpass T structure, the first bandpass T structure unit includes a first transmission line, a second transmission line and a third transmission line; the second bandpass T structure unit includes a fourth transmission line, a fifth transmission line and a sixth transmission line; the third bandpass T structure unit includes a seventh transmission line and an eighth transmission line; the post-matching network includes a ninth transmission line, a tenth transmission line and a DC blocking capacitor C1;

[0021] The first transmission line is respectively connected to the drain of the main transistor and one end of the first output capacitor; one end of the second transmission line is respectively connected to one end of the first transmission line and one end of the third transmission line, and the other end of the second transmission line is grounded; the other end of the third transmission line is connected to the fourth transmission line, the first output end of the auxiliary transistor module and the common end of the second output capacitor;

[0022] The other end of the fourth transmission line is respectively connected to one end of the fifth transmission line and the sixth transmission line, the other end of the fifth transmission line is grounded, and the other end of the sixth transmission line is respectively connected to one end of the seventh transmission line and the second output end of the auxiliary transistor module;

[0023] The other end of the seventh transmission line is connected to one end of the eighth transmission line, and the other end of the eighth transmission line is connected to a common end of the third output end of the auxiliary transistor module, the fourth output capacitor and one end of the ninth transmission line;

[0024] The other end of the ninth transmission line is respectively connected to one end of the DC blocking capacitor C1 and the tenth transmission line, and the other end of the first output capacitor, the other end of the second output capacitor, the other end of the third output capacitor and the other end of the fourth output capacitor are grounded.

[0025] According to a further configuration of the present invention, the auxiliary path driving stage transistor module comprises: a first auxiliary path driving stage transistor, a second auxiliary path driving stage transistor and a third auxiliary path driving stage transistor;

[0026] The gate of the first auxiliary path driver stage transistor, the gate of the second auxiliary path driver stage transistor and the gate of the third auxiliary path driver stage transistor are respectively connected to the output end of the auxiliary path input matching network, the source of the first auxiliary path driver stage transistor, the second auxiliary path driver stage transistor and the third auxiliary path driver stage transistor are grounded, and the drain of the first auxiliary path driver stage transistor, the second auxiliary path driver stage transistor and the third auxiliary path driver stage transistor are respectively connected to the auxiliary path intermediate stage matching network.

[0027] According to a further configuration of the present invention, the auxiliary transistor module includes: a first auxiliary transistor, a second auxiliary transistor and a third auxiliary transistor, the gate of the first auxiliary transistor, the gate of the second auxiliary transistor and the gate of the third auxiliary transistor are respectively connected to the auxiliary intermediate stage matching network, the source of the first auxiliary transistor, the source of the second auxiliary transistor and the source of the third auxiliary transistor are grounded, and the drain of the first auxiliary transistor, the drain of the second auxiliary transistor and the drain of the third auxiliary transistor are respectively connected to the distributed output combining network based on the bandpass T structure.

[0028] According to a further configuration of the present invention, the auxiliary intermediate-stage matching network includes: a first auxiliary intermediate-stage matching network, a second auxiliary intermediate-stage matching network and a third auxiliary intermediate-stage matching network, the input end of the first auxiliary intermediate-stage matching network is connected to the drain of the first auxiliary driving-stage transistor, the input end of the second auxiliary intermediate-stage matching network is connected to the drain of the second auxiliary driving-stage transistor, the third auxiliary intermediate-stage matching network is connected to the drain of the third auxiliary driving-stage transistor, the first auxiliary intermediate-stage matching network, the second auxiliary intermediate-stage matching network and the third auxiliary intermediate-stage matching network are cascaded with each other to respectively absorb parasitic parameters in the first auxiliary driving-stage transistor, the second auxiliary driving-stage transistor and the third auxiliary driving-stage transistor.

[0029] According to a further configuration of the present invention, the circuit structure and size of the main intermediate-stage matching network and the first auxiliary intermediate-stage matching network, the second auxiliary intermediate-stage matching network and the third auxiliary intermediate-stage matching network are the same, and the main intermediate-stage matching network includes: a first intermediate transmission line, a second intermediate transmission line, a third intermediate transmission line, a fourth intermediate transmission line, a fifth intermediate transmission line, a sixth intermediate resistor, a seventh intermediate resistor, a first intermediate capacitor, a second intermediate capacitor, a third intermediate capacitor, a fourth intermediate capacitor, a fifth intermediate capacitor and a sixth intermediate capacitor; wherein,

[0030] One end of the first intermediate capacitor is connected to the drain of the main driving stage transistor, the other end of the first intermediate capacitor is respectively connected to one end of the second intermediate transmission line, the common end of the third intermediate transmission line and the second intermediate capacitor, the other end of the second intermediate transmission line is connected to one end of the first intermediate capacitor, and the other end of the first intermediate capacitor is grounded; the other end of the second intermediate capacitor is connected to the common end of the fourth intermediate transmission line and the fifth intermediate transmission line, the sixth intermediate resistor and the fifth intermediate capacitor are connected in parallel to the gate of the main transistor; the other end of the fifth intermediate transmission line is respectively connected to the common end of the sixth intermediate capacitor and the seventh intermediate resistor, the other end of the fourth intermediate transmission line is connected to one end of the fourth intermediate capacitor, the other end of the third intermediate transmission line is connected to one end of the third intermediate capacitor, and the other end of the third intermediate capacitor and the other end of the fourth intermediate capacitor are grounded.

[0031] According to a further configuration of the present invention, the main input matching network includes: a first main input transmission line, a second main input transmission line, a third main input transmission line, a fourth main input resistor, a fifth main input transmission line, a sixth main input resistor, a first main input capacitor, a second main input capacitor, a third main input capacitor and a fourth main input capacitor. Among them, one end of the first main input transmission line is connected to the main output end of the power divider, the other end of the first main input transmission line is connected to one end of the first main input capacitor, the other end of the first main input capacitor is connected to the common end of the second main input capacitor and the second main input transmission line, the other end of the second main input capacitor is grounded, and the other end of the second main input transmission line is respectively connected to one end of the third main input transmission line and one end of the fifth main input transmission line; the other end of the third main input transmission line is connected to the common end of the fourth main input resistor and the third main input capacitor, the other end of the fourth main input resistor is connected to the input end of the driving voltage, the other end of the third main input capacitor is grounded, the fifth main input transmission line is connected to the common end of the sixth main input resistor and the fourth main input capacitor, and the sixth main input resistor and the fourth main input capacitor are connected in parallel to the gate of the main driving stage transistor.

[0032] In a further configuration of the present invention, the delay network comprises: a first delay transmission line, a second delay transmission line, a third delay transmission line, a fourth delay transmission line, a fifth delay transmission line, a sixth delay transmission line, a first delay capacitor, a second delay capacitor, a third delay capacitor, a fourth delay capacitor, a fifth delay capacitor and a sixth delay capacitor, wherein:

[0033] One end of the first delay transmission line is connected to the auxiliary output end of the power divider, and the other end of the first delay transmission line is respectively connected to the second delay capacitor and the common end of the second delay transmission line;

[0034] The other end of the second delay transmission line is connected to one end of the first delay capacitor; the other end of the second delay capacitor is connected to one end of the third delay transmission line, the other end of the third delay transmission line is connected to the common end of the third delay capacitor and the fourth delay transmission line, the other end of the fourth delay transmission line is connected to the common end of the fourth delay capacitor and the fifth delay transmission line, the other end of the fifth delay transmission line is connected to one end of the fifth delay capacitor, the other end of the fifth delay capacitor is respectively connected to the input end of the auxiliary input matching network and one end of the sixth delay transmission line, the other end of the sixth delay transmission line is connected to the sixth delay capacitor, the other end of the first delay capacitor, the other end of the third delay capacitor, the other end of the fourth delay capacitor and the other end of the sixth delay capacitor are grounded.

[0035] According to a further configuration of the present invention, the auxiliary input matching network includes: a first auxiliary input capacitor, a second auxiliary input capacitor, a first auxiliary input transmission line, a third auxiliary input resistor, a third auxiliary input capacitor, a second auxiliary input transmission line, a fourth auxiliary input capacitor, a fourth auxiliary input transmission line, a fifth auxiliary input resistor, a fifth auxiliary input capacitor, a sixth auxiliary input transmission line, a sixth auxiliary input capacitor, a seventh auxiliary input transmission line, an eighth auxiliary input resistor, a seventh auxiliary input capacitor, a ninth auxiliary input transmission line, a tenth auxiliary input resistor and an eighth auxiliary input capacitor. Among them, one end of the first auxiliary input capacitor is connected to the delay network, the other end of the first auxiliary input capacitor is connected to the common end of the second auxiliary input capacitor and the first auxiliary input transmission line, and the other end of the second auxiliary input capacitor is grounded; the other end of the first auxiliary input transmission line is respectively connected to the common end of the second auxiliary input transmission line, the third auxiliary input resistor and the third auxiliary input capacitor; the third auxiliary input resistor and the third auxiliary input capacitor are connected in parallel and connected to the first auxiliary driving stage transistor; the other end of the second auxiliary input transmission line is connected to the common end of the fourth auxiliary input capacitor and the fourth auxiliary input transmission line, and the other end of the fourth auxiliary input transmission line is connected to the common end of the sixth auxiliary input transmission line, the fifth auxiliary input resistor and the fifth auxiliary input capacitor; The input resistor and the fifth auxiliary input capacitor are connected in parallel and then connected to the second auxiliary drive-stage transistor for outputting a matched traveling wave signal; the other end of the sixth auxiliary input transmission line is connected to the common end of the sixth auxiliary input capacitor and the seventh auxiliary input transmission line, and the other end of the seventh auxiliary input transmission line is respectively connected to the common end of the ninth auxiliary input transmission line, the eighth auxiliary input resistor and the seventh auxiliary input capacitor; the eighth auxiliary input resistor and the seventh auxiliary input capacitor are connected in parallel and then connected to the third auxiliary drive-stage transistor; the other end of the ninth auxiliary input transmission line is connected to one end of the tenth auxiliary input resistor, and the other end of the tenth auxiliary input resistor is respectively connected to the drive signal and the eighth auxiliary input capacitor, and the other end of the fourth auxiliary input capacitor, the other end of the sixth auxiliary input capacitor and the other end of the eighth auxiliary input capacitor are grounded.

[0036] A linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier provided by the present invention includes a power divider, a delay network, a main input matching network, an auxiliary input matching network, a main driving stage transistor, an auxiliary driving stage transistor module, a main intermediate matching network, an auxiliary intermediate matching network, a distributed output combining network based on a bandpass T structure, a main transistor and an auxiliary transistor module. The present invention adopts a distributed unit circuit based on a bandpass T structure to replace the traditional capacitor-loaded transmission line network, and significantly improves the matching bandwidth of the distributed output combining network based on the bandpass T structure under the optimal impedance value Qopt value of the transistor. Compared with the prior art, the distributed output combining network based on the bandpass T structure of the present invention has a certain gain expansion characteristic, which is convenient for the design of a high-linearity DEPA. In addition, the gain compression characteristic of the input network of the present invention can be adjusted by the power distribution ratio of the power divider, and this degree of freedom is used to construct an expanded DEPA gain characteristic and to compensate for the gain compression of the main transistor in the actual design, thereby improving the linearity of the entire DEPA. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary personnel in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0038] Figure 1 A block diagram of the structure of a linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier provided by the present invention;

[0039] Figure 2 It is a circuit schematic diagram of a conventional capacitor-loaded transmission line equivalent to a transmission line in the prior art;

[0040] Figure 3 A schematic diagram of a T-type structure in a linear broadband GaN millimeter-wave integrated distributed high-efficiency power amplifier provided by the present invention;

[0041] Figure 4 A circuit schematic diagram of a distributed output combining network based on a bandpass T structure in a linear broadband GaN millimeter-wave integrated distributed high-efficiency power amplifier provided by the present invention;

[0042] Figure 5 A circuit schematic diagram of a main path intermediate stage matching network in a preferred embodiment of the present invention;

[0043] Figure 6 A circuit schematic diagram of a main input matching network in a preferred embodiment of the present invention;

[0044] Figure 7 A circuit diagram of a delay network in a preferred embodiment of the present invention;

[0045] Figure 8 A circuit schematic diagram of an auxiliary input matching network in a preferred embodiment of the present invention;

[0046] Fig. 9 A schematic diagram of the gain and power added efficiency of DEPA under different power allocation ratios in a preferred embodiment of the present invention;

[0047] Fig.10 A schematic diagram of amplitude distortion of a distributed output combining network based on a bandpass T structure, an internal current source plane of a main transistor, an input network and a DEPA when PSR=3dB in a preferred embodiment of the present invention;

[0048] Fig.11 It is a schematic diagram of large signal test results of a fallback efficiency enhancement mode in a preferred embodiment of the present invention;

[0049] Fig.12 It is a schematic diagram of large signal test results of bandwidth enhancement mode in a preferred embodiment of the present invention.

[0050] Fig.13 It is a schematic diagram of the gain variation of the distributed output combining network based on the bandpass T structure, the internal current source plane of the main transistor, the input network and the DEPA as the input power increases in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0051] The present invention provides a linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier. In order to make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0052] In the embodiments and the scope of the patent application, unless the text specifically defines the article, "a", "an", "the" and "the" may also include plural forms. If there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of the features.

[0053] It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when an element is said to be "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can also be intermediate elements. In addition, the "connection" or "coupling" used herein can include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0054] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as herein.

[0055] In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0056] See also Figure 1The linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier provided by the present invention includes a power divider 100, a delay network 200, a main input matching network 300, an auxiliary input matching network 400, a main driving stage transistor Q510, an auxiliary driving stage transistor module 500, a main intermediate stage matching network 600, an auxiliary intermediate stage matching network 700, a main transistor Q810, an auxiliary transistor module 800 and a distributed output combining network 900 based on a bandpass T structure. The output end of the power divider 100 is respectively connected to the input end of the main input matching network 300 and the input end of the delay network 200, the output end of the delay network 200 is connected to the input end of the auxiliary input matching network 400, the output end of the main input matching network 300 is connected to the gate of the main driving stage transistor Q510, the input end of the auxiliary input matching network 400 is connected to the output end of the delay network 200, and each output end of the auxiliary input matching network 400 is respectively connected to the auxiliary driving stage transistor module 500. The input end of the main intermediate-stage matching network 600 is connected to the drain of the main driving-stage transistor Q510, the output end of the main intermediate-stage matching network 600 is connected to the gate of the main transistor Q810, the auxiliary driving-stage transistor module 500 is respectively connected to the input end of the auxiliary intermediate-stage matching network 700, the output end of the auxiliary intermediate-stage matching network 700 is connected to the auxiliary driving-stage transistor module 500, and the input end of the distributed output combining network 900 based on the bandpass T structure is respectively connected to the drain of the main transistor Q810 and the auxiliary transistor module 800.

[0057] In a specific implementation, the input end of the power divider 100 is connected to the RF input end, and the RF input signal is non-equally divided in power distribution, and the main signal and the auxiliary signal after the non-equal power distribution are output to the input end of the main input matching network 300 and the delay network 200 in the auxiliary path respectively. The main input matching network 300 is used to match the port output impedance of the main input matching network 300 with the source impedance of the main driving stage transistor Q510, and the delay network 200 is used to adjust the phase difference between the signal at the input end of the auxiliary input matching network 400 and the main input matching network 300 to ensure that the phase relationship between the main and auxiliary branches is matched. The impedance-matched main signal flows through the main driving stage transistor Q510 for signal amplification, and is output to the main intermediate stage matching network 600 to further perform impedance transformation on the main signal, and the main signal after the impedance transformation is completed is output to the gate of the main transistor Q810. The main signal is amplified by the main transistor Q810 and output to the distributed output combining network 900 based on the bandpass T structure. In the auxiliary branch, the auxiliary signal is input into the auxiliary input matching network 400 after the phase difference is adjusted by the delay network 200. The auxiliary input matching network 400 is used to match the port output impedance of the auxiliary input matching network 400 with the source impedance of the auxiliary driving stage transistor module 500, and output as multiple auxiliary signals. The multiple auxiliary signals are respectively input into the auxiliary driving stage transistor module 500, and each auxiliary signal after amplification flows through the auxiliary intermediate stage matching network 700. The auxiliary intermediate stage matching network 700 is used to perform impedance transformation on the input auxiliary signal, and after amplification by the auxiliary transistor module 800, it is output to the distributed output combining network 900 based on the bandpass T structure. The distributed output combining network 900 based on the bandpass T structure is used to realize a broadband traveling wave network and absorb the parasitic parameters of the output end of the main transistor Q810 and the auxiliary transistor module 800. The present invention replaces the traditional capacitor-loaded transmission line network with a distributed output combining network 900 based on a bandpass T structure to absorb the parasitic parameters of the transistor itself, thereby improving the matching bandwidth of the distributed output combining network at the optimal impedance value Qopt of the large transistor.

[0058] Specifically, the power divider 100 is a non-equal Wilkinson power divider 100, which performs non-equal power distribution of the radio frequency input signal in a ratio of 1:2, and the non-equal power distribution ratio corresponds to the port output impedance ratio of the main path and the auxiliary path.

[0059] In this preferred embodiment, the power split ratio (PSR) of the power divider 100 has an important influence on the linearity of DEPA. Fig. 9 , Fig.10 , Fig. 9The figure shows the gain and power added efficiency of DEPA under different power split ratios. When the PSR changes from 2dB to 4dB, the gain gradually changes from a compression characteristic to an expansion characteristic. Fig.10 The figure shows the distributed output combining network 900 (G) based on the bandpass T structure when PSR = 3dB. R ), the main transistor Q810 internal current source plane (G M ), input network (G V ) and DEPA(G DEPA ) amplitude distortion, when PSR = 3dB, the amplitude distortion of the output network, the main transistor Q810 and each input network can be well offset, thereby showing a relatively flat overall gain characteristic. In order to construct the optimal gain flatness, and considering the difficulty of realizing the actual power divider 100, the present invention preferably uses a Wilkinson unequal power divider with a power distribution ratio of 3dB. And when the application environment changes, the gain compression characteristics of the linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier can be adjusted by the power distribution ratio of the power divider 100. This degree of freedom is used to construct an expanded DEPA gain characteristic and to compensate for the gain compression of the main transistor in the actual design, thereby improving the linearity of the entire DEPA. At the same time, the distributed output combining network based on the bandpass T structure has a gain expansion characteristic. With the increase of the input power, the gain of the entire network shows a gradual increase trend, which is convenient for the design of high-linearity DEPA.

[0060] Please also see Figure 1 and Figure 7The delay network 200 includes: a first delay transmission line TL201, a second delay transmission line TL202, a third delay transmission line TL203, a fourth delay transmission line TL204, a fifth delay transmission line TL205, a sixth delay transmission line TL206, a first delay capacitor C201, a second delay capacitor C202, a third delay capacitor C203, a fourth delay capacitor C204, a fifth delay capacitor C205 and a sixth delay capacitor C206. One end of the first delay transmission line TL201 is connected to the auxiliary output end of the power divider 100, and the other end of the first delay transmission line TL201 is respectively connected to the common end of the second delay capacitor C202 and the second delay transmission line TL202. The other end of the second delay transmission line TL202 is connected to one end of the first delay capacitor C201; the other end of the second delay capacitor C202 is connected to one end of the third delay transmission line TL203, the other end of the third delay transmission line TL203 is connected to the common end of the third delay capacitor C203 and the fourth delay transmission line TL204, and the other end of the fourth delay transmission line TL204 is connected to the common end of the fourth delay capacitor C204 and the fifth delay transmission line TL205. , the other end of the fifth delay transmission line TL205 is connected to one end of the fifth delay capacitor C205, the other end of the fifth delay capacitor C205 is respectively connected to the signal output end and one end of the sixth delay transmission line TL206, the other end of the sixth delay transmission line TL206 is connected to the sixth delay capacitor C206, the other end of the first delay capacitor C201, the other end of the third delay capacitor C203, the other end of the fourth delay capacitor C204 and the other end of the sixth delay capacitor C206 are grounded.

[0061] When the RF input signal flows into the main branch and the auxiliary branch respectively after unequal power signal distribution, since the network structures designed for the main branch and the auxiliary branch are different, the phase difference generated between the networks is also different, so there is a phase difference between the signals from the main branch and the auxiliary branch to the distributed output combining network 900 based on the bandpass T structure. Therefore, the present invention adds the delay network 200 before the auxiliary input matching network 400 to compensate for the phase difference between the main branch and the auxiliary branch, so as to ensure that the main and auxiliary branches have an appropriate phase relationship.

[0062] Further, the delay network 200 is used to compensate for the phase difference between the input ends of the main input matching network 300 and the auxiliary input matching network 400, and the phase difference calculation formula is: P = P1 + P2 + P3 - P4 - P5, where P1, P2, P3, P4 and P5 are the phase changes at all networks except the power divider 100, P1 is the phase difference of the main input matching network 300, P2 is the phase difference of the main intermediate network, P3 is the phase difference of the distributed output combining network 900 based on the bandpass T structure, P4 is the phase difference of the auxiliary intermediate matching network 700, and P5 is the phase difference of the auxiliary input matching network 400. Wherein, when the network is a two-port network, the phase change at the corresponding network is the phase difference at both ends of the two-port network, that is, P1, P2, P4 can be obtained by measuring the phase difference at each network port. When the network is a multi-port network, the phase difference is the phase difference between each first auxiliary branch and the corresponding port in the multi-port network, that is, P3 is the phase difference between the drain of the main transistor Q810 and the drain of the first auxiliary transistor Q801, and P5 is the phase difference between the input end of the auxiliary input matching network 400 and the gate of the first auxiliary driving transistor Q501. Then, the phase difference between the input ends of the main input matching network 300 and the auxiliary input matching network 400 is calculated, and the phase difference is set as the phase difference inside the delay network 200.

[0063] For further information, see Figure 6 The main input matching network 300 includes: a first main input transmission line TL301, a second main input transmission line TL302, a third main input transmission line TL303, a fourth main input resistor R304, a fifth main input transmission line TL305, a sixth main input resistor R305, a first main input capacitor C301, a second main input capacitor C302, a third main input capacitor C303 and a fourth main input capacitor C304. Among them, one end of the first main input transmission line TL301 is connected to the main output end of the power divider, the other end of the first main input transmission line is connected to one end of the first main input capacitor C301, the other end of the first main input capacitor C301 is connected to the common end of the second main input capacitor C302 and the second main input transmission line TL302, the other end of the second main input capacitor C302 is grounded, the other end of the second main input transmission line TL302 is respectively connected to one end of the third main input transmission line TL303 and the fifth main input transmission line TL305; the other end of the third main input transmission line TL303 is connected to the common end of the fourth main input resistor R304 and the third main input capacitor C303, the other end of the fourth main input resistor R304 is connected to the driving voltage V G，M，driveThe input end of the power divider 100 is connected, the other end of the third main input capacitor C303 is grounded, the other end of the fifth main input transmission line TL305 is connected to the common end of the sixth main input resistor R305 and the fourth main input capacitor C304, and the sixth main input resistor R305 and the main input capacitor are connected in parallel to the gate of the main driving transistor Q510. The structure of the main input matching network 300 is used to realize the impedance transformation from the port output impedance of the main output end of the power divider 100 to the source impedance of the connected transistor.

[0064] See also Figure 8 The auxiliary input matching network 400 can be divided into an impedance transformation part IMN A and the traveling wave input matching network part DIMN A The impedance transformation part IMN A It includes: a first auxiliary input capacitor C401, a second auxiliary input capacitor C402, a first auxiliary input transmission line TL401, and the traveling wave input matching network part DIMN AIncluding: a third auxiliary input resistor R403, a third auxiliary input capacitor C403, a second auxiliary input transmission line TL402, a fourth auxiliary input capacitor C404, a fourth auxiliary input transmission line TL404, a fifth auxiliary input resistor R405, a fifth auxiliary input capacitor C405, a sixth auxiliary input transmission line TL406, a sixth auxiliary input capacitor C406, a seventh auxiliary input transmission line TL407, an eighth auxiliary input resistor R408, a seventh auxiliary input capacitor C407, a ninth auxiliary input transmission line TL409, a tenth auxiliary input resistor R410 and an eighth auxiliary input capacitor C408. Among them, one end of the first auxiliary input capacitor C401 is connected to the output end of the delay network, and the other end is connected to the common end of the second auxiliary input capacitor C402 and the first auxiliary input transmission line TL401, and the other end of the second auxiliary input capacitor C402 is grounded for impedance transformation; the other end of the first auxiliary input transmission line TL401 is respectively connected to the common end of the second auxiliary input transmission line TL402, the third auxiliary input resistor R403 and the third auxiliary input capacitor C403; the third auxiliary input resistor and the third auxiliary input capacitor are connected in parallel to the first auxiliary driving transistor Q501; the other end of the second auxiliary input transmission line TL402 is connected to the common end of the fourth auxiliary input capacitor C404 and the fourth auxiliary input transmission line TL404, and the other end of the fourth auxiliary input transmission line TL404 is connected to the common end of the sixth auxiliary input transmission line TL406, the fifth auxiliary input resistor R405 and the fifth auxiliary input capacitor C405; The input resistor R405 and the fifth auxiliary input capacitor C405 are connected in parallel to the second auxiliary drive stage transistor Q502, which is used to output the matched traveling wave signal; the other end of the sixth auxiliary input transmission line TL406 is connected to the common end of the sixth auxiliary input capacitor C406 and the seventh auxiliary input transmission line TL407, and the other end of the seventh auxiliary input transmission line is respectively connected to the common end of the ninth auxiliary input transmission line TL409, the eighth auxiliary input resistor R408 and the seventh auxiliary input capacitor C407. ; The eighth auxiliary input resistor and the seventh auxiliary input capacitor are connected in parallel and connected to the third auxiliary driving stage transistor Q503; the other end of the ninth auxiliary input transmission line TL409 is connected to one end of the tenth auxiliary input resistor R410, and the other end of the tenth auxiliary input resistor R410 is respectively connected to the driving signal and the eighth auxiliary input capacitor C408, and the other end of the fourth auxiliary input capacitor C404, the other end of the sixth auxiliary input capacitor C406, and the other end of the eighth auxiliary input capacitor C408 are grounded.

[0065] The main input matching network 300 and the auxiliary input matching network 400 are designed to match the output impedances of these ports to the source impedances of the corresponding transistors. When the power divider 100 performs a non-equal power distribution of 1:2 on the RF input signal, the non-equal power distribution ratio corresponds to the port output impedance ratio of the main and auxiliary paths of the non-equal Wilkinson power divider 100. For example, according to the designed non-equal Wilkinson power divider 100, the port output impedances of the main and auxiliary paths are 70Ω and 35Ω, respectively. The main input matching network 300 and the auxiliary input matching network 400 are designed to match the output impedances of these ports to the source impedances of the corresponding transistors, respectively, to achieve impedance transformation from the main output end of the power divider 100 to the source impedance of the connected transistor.

[0066] See also Figure 1 The auxiliary road driving stage transistor module 500 includes: a first auxiliary road driving stage transistor Q501, a second auxiliary road driving stage transistor Q502 and a third auxiliary road driving stage transistor Q503. The gate of the first auxiliary road driving stage transistor Q501, the gate of the second auxiliary road driving stage transistor Q502 and the gate of the third auxiliary road driving stage transistor Q503 are respectively connected to the output end of the auxiliary road input matching network 400, the source of the first auxiliary road driving stage transistor Q501, the source of the second auxiliary road driving stage transistor Q502 and the source of the third auxiliary road driving stage transistor Q503 are grounded, and the drain of the first auxiliary road driving stage transistor Q501, the drain of the second auxiliary road driving stage transistor Q502 and the drain of the third auxiliary road driving stage transistor Q503 are respectively connected to the auxiliary road intermediate stage matching network 700.

[0067] Please refer to Figure 1 , Figure 5The main path intermediate stage matching network 600 includes a first intermediate transmission line TL601, a second intermediate transmission line TL602, a third intermediate transmission line TL603, a fourth intermediate transmission line TL604, a fifth intermediate transmission line TL605, a sixth intermediate resistor R606, a seventh intermediate resistor R607, a first intermediate capacitor C601, a second intermediate capacitor C602, a third intermediate capacitor C603, a fourth intermediate capacitor C604, a fifth intermediate capacitor C605 and a sixth intermediate capacitor C606. Among them, one end of the first intermediate capacitor C601 is connected to the drain of the main driving transistor Q510, the other end of the first intermediate capacitor is respectively connected to the common end of the second intermediate transmission line TL602, the third intermediate transmission line TL603 and the second intermediate capacitor C602, the other end of the second intermediate transmission line TL602 is connected to one end of the first intermediate capacitor C601, and the other end of the first intermediate capacitor C601 is grounded; the other end of the second intermediate capacitor C602 is connected to the fourth intermediate transmission line TL604 and the fifth intermediate transmission line TL605 The sixth intermediate resistor R606 and the fifth intermediate capacitor C605 are connected in parallel to the gate of the main transistor Q810; the other end of the fifth intermediate transmission line TL605 is respectively connected to the common end of the sixth intermediate capacitor C606 and the seventh intermediate resistor R607, the other end of the fourth intermediate transmission line TL604 is connected to one end of the fourth intermediate capacitor C604, the other end of the third intermediate transmission line TL603 is connected to one end of the third intermediate capacitor C603, and the other end of the third intermediate capacitor and the other end of the fourth intermediate capacitor C604 are grounded.

[0068] The auxiliary path intermediate stage matching network 700 includes: a first auxiliary path intermediate stage matching network 710, a second auxiliary path intermediate stage matching network 720 and a third auxiliary path intermediate stage matching network 730. The input end of the first auxiliary path intermediate stage matching network 710 is connected to the drain of the first auxiliary path driving stage transistor Q501, the input end of the second auxiliary path intermediate stage matching network 720 is connected to the drain of the second auxiliary path driving stage transistor Q502, and the third auxiliary path intermediate stage matching network 730 is connected to the drain of the third auxiliary path driving stage transistor Q503. The first auxiliary path intermediate stage matching network 710, the second auxiliary path intermediate stage matching network 720 and the third auxiliary path intermediate stage matching network 730 are cascaded with each other so that the three auxiliary paths share the gate bias and drain bias.

[0069] Furthermore, the first auxiliary intermediate-stage matching network 710, the second auxiliary intermediate-stage matching network 720, the third auxiliary intermediate-stage matching network 730 and the main intermediate-stage matching network 600 have the same circuit structure and size, and are used for impedance transformation. Figure 5 As shown, no further elaboration is given here.

[0070] The auxiliary transistor module 800 includes: a first auxiliary transistor Q801, a third auxiliary transistor Q802 and a third auxiliary transistor Q803, the gate of the first auxiliary transistor Q801, the gate of the third auxiliary transistor Q802 and the gate of the third auxiliary transistor Q803 are respectively connected to the auxiliary intermediate stage matching network 700, the source of the first auxiliary transistor Q801, the source of the third auxiliary transistor Q802 and the source of the third auxiliary transistor Q803 are grounded, and the drain of the first auxiliary transistor Q801, the drain of the third auxiliary transistor Q802 and the drain of the third auxiliary transistor Q803 are respectively connected to the distributed output combining network 900 based on the bandpass T structure.

[0071] The main transistor Q810, the first auxiliary transistor Q801, the third auxiliary transistor Q802 and the third auxiliary transistor Q803 are transistors of the same size. Since the transistors used in the main and auxiliary driving stages and power stages are of the same size, the four intermediate-stage matching networks used in the circuit of the present invention all adopt the same circuit structure and size, thereby facilitating industrial design and drawing and reducing material loss in the production process.

[0072] In this embodiment, the linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier is divided into a main branch and an auxiliary branch after unequal power distribution, and the auxiliary branch is divided into three branches after impedance matching and input into the auxiliary driving stage transistor module 500 respectively, and after amplification, they are respectively input into the first, second and third auxiliary intermediate matching networks 730. Among them, the first auxiliary intermediate matching network 710, the second auxiliary intermediate matching network 720, and the third auxiliary intermediate matching network 730 are cascaded with each other to form a quasi-NDPA structure. Through the cascade structure, the quasi-NDPA structure can achieve better broadband effect than ordinary power amplifiers. On this basis, the present invention is further divided into a main path and an auxiliary path based on the DEPA structure, which can not only achieve broadband effect, but also realize back-off efficiency enhancement through impedance modulation. Furthermore, the auxiliary path branches in the present invention are not less than 3, and the number of the auxiliary path branches is not limited here.

[0073] Please also refer to Figure 4The distributed output combining network 900 based on the bandpass T structure includes: a first bandpass T structure unit 901, a second bandpass T structure unit 902, a third bandpass T structure unit 903, a first output capacitor C901, a second output capacitor Cout2, a third output capacitor C903, a fourth output capacitor C904, a first output resistor Rout and a post-matching network 904. One end of the first bandpass T structure unit 901 is connected to the drain of the main transistor Q810 and one end of the first output capacitor C901, and the other end of the first bandpass T structure unit is connected to the drain of the first auxiliary transistor Q801, the second output capacitor Cout2 and the common end of the second bandpass T structure unit 902. The other end of the second bandpass T structure unit 902 is connected to the drain of the third auxiliary transistor Q802, one end of the third output capacitor C903 and the common end of the third bandpass T structure unit 903. The other end of the third bandpass T structure unit 903 is connected to the drain of the third auxiliary transistor Q803, the fourth output capacitor C904 and the common end of the post-matching network. The other end of the first output capacitor C901, the other end of the second output capacitor C902, the other end of the third output capacitor C903 and the other end of the fourth output capacitor C904 are grounded, and the other end of the post-matching network 904 is connected to the RF output terminal through the first output resistor Rout.

[0074] Specifically, in a further implementation of a preferred embodiment, the first band-pass T structure unit 901 includes a first transmission line TL1, a second transmission line TL2 and a third transmission line TL3, the second band-pass T structure unit 902 includes a fourth transmission line TL4, a fifth transmission line TL5 and a sixth transmission line TL6, the third band-pass T structure unit 903 includes a seventh transmission line TL7 and an eighth transmission line TL8; the post-matching network 904 includes a ninth transmission line TL9, a tenth transmission line TL10 and a DC blocking capacitor C1. The first band-pass T structure unit 901 applies a unit circuit of a band-pass T-type structure, wherein the first transmission line TL1 is respectively connected to the drain of the main transistor Q810 and one end of the first output capacitor Cout1; one end of the second transmission line TL2 is respectively connected to one end of the first transmission line TL1 and one end of the third transmission line TL3, and the other end of the second transmission line is grounded; the other end of the third transmission line TL3 is connected to the common end of the fourth transmission line TL4, the drain of the first auxiliary transistor Q801 and the second output capacitor Cout2. The second band-pass T structure unit 902 has the same structure as the first band-pass T structure unit 901, and the fourth transmission line TL4, the fifth transmission line TL5 and the sixth transmission line TL6 are connected in a band-pass T-shaped structure, the other end of the fourth transmission line TL4 is respectively connected to one end of the fifth transmission line TL5 and one end of the sixth transmission line TL6, the other end of the fifth transmission line TL5 is grounded, and the other end of the sixth transmission line TL6 is respectively connected to one end of the seventh transmission line TL7, the third output capacitor Cout3 and the common end of the third auxiliary transistor Q802. In the third band-pass T structure unit 903, the other end of the seventh transmission line TL7 is connected to one end of the eighth transmission line TL8, and the other end of the eighth transmission line TL8 is connected to the drain of the third auxiliary transistor Q803, the fourth output capacitor Cout4 and the common end of the ninth transmission line TL9. The post-matching network 904 is an L-type post-matching network, the other end of the ninth transmission line TL9 is respectively connected to one end of the DC blocking capacitor C1 and the tenth transmission line TL10, and the other end of the first output capacitor Cout1, the other end of the second output capacitor Cout2, the other end of the third output capacitor Cout3 and the other end of the fourth output capacitor Cout4 are grounded. In theory, the bandpass T structure unit circuit is a symmetrical network, but in actual design, the transistor capacitances that need to be absorbed at both ends of the T structure unit network at different positions may be inconsistent, so the T structure unit in the circuit is an asymmetric structure in actual application. This structure can better absorb the parasitic capacitance of the transistor output and achieve better matching, thereby significantly improving the matching characteristics of the entire combining network at the back-off point and the saturation point, bringing better bandwidth and efficiency characteristics.

[0075] Please also refer to Figures 2 to 4, Figure 2 The figure shows a method of using a capacitor-loaded transmission line to equalize an ideal traveling wave structure 90° transmission line in the prior art. One end of the transmission line is connected to the signal input end and the first output capacitor C901, and the other end is connected to the signal output end and the second output capacitor Cout2. The equivalent process calculation formula is:

[0076]

[0077] Among them, Z1a and θ1a are the characteristic impedance and electrical length of the capacitor-loaded transmission line corresponding to the ideal traveling wave structure 90° transmission line, and Cout is the parasitic capacitance of the transistor that needs to be absorbed by the unit circuit. The optimal impedance value of the transistor is Qopt (=ωCoutRoptM), that is, the traditional method of capacitor-loaded transmission line only has a reasonable solution when Qopt < 2. However, in the millimeter wave band, due to the high bias voltage characteristics of gallium nitride transistors, the value of Qopt is usually higher, usually greater than 2. Therefore, the traditional method cannot be used to achieve the absorption of Cout in the millimeter wave band.

[0078] On the basis of the prior art, the present invention applies Figure 3 The unit circuits of the bandpass T-type structure shown constitute a distributed network, wherein Z1b, Z2b, Z3b and θ1a, θ2a, θ3a are the characteristic impedances and electrical lengths of the corresponding first transmission line, second transmission line, and third transmission line TL3, and Cout is the transistor parasitic capacitance that needs to be absorbed by the unit circuit. One end of the first transmission line TL1 is connected to the signal input end and the first output capacitor C901 respectively, and the other end is connected to the common end of the second transmission line TL2 and the third transmission line TL3. The other end of the second transmission line TL2 is grounded, and the other end of the third transmission line TL3 is connected to the signal output end and the second output capacitor Cout2. The first, second and third transmission lines TL3 are connected in a bandpass T-type structure. The equivalent process solution of the bandpass T-type structure is not unique. Therefore, the unit circuits of the bandpass T-type structure constitute a distributed network with more degrees of freedom, and can achieve better equivalent processes in a wider frequency band. And the unit circuit of the bandpass T-type structure can provide drain bias for the power amplifier while absorbing Cout.

[0079] Fig.13 FIG. 1 shows the gain variation of the distributed output combining network 900 based on the bandpass T structure, the internal current source plane of the main transistor Q810, the input network and the DEPA as the input power increases. The gain of the distributed output combining network 900 based on the bandpass T structure is shown in FIG. RAs shown, it can be obtained that as the input power increases, after the auxiliary transistor is turned on, the gain of the distributed output combining network 900 based on the bandpass T structure shows a gradually increasing trend, and the distributed output combining network 900 based on the bandpass T structure has a certain gain expansion characteristic, which lays the foundation for the design of high-linearity DEPA. At the same time, in this preferred embodiment, the distributed output combining network 900 based on the bandpass T structure is used to realize a broadband traveling wave network and absorb the parasitic parameters of the output ends of the main and auxiliary transistors. Because the sizes of the main transistor Q810, the first auxiliary transistor Q801, the third auxiliary transistor Q802 and the third auxiliary transistor Q803 are the same, each transistor has the same output parasitic parameter Cout, and the distributed output combining network 900 based on the bandpass T structure is used to absorb the parasitic parameters of each transistor, so that the output impedance of the transistor is a pure real number, which is convenient for designing the network for impedance matching.

[0080] Since in the present invention, the working state of DEPA at the saturation point is close to that of the conventional NDPA, when all auxiliary transistors work in the Class C mode and the gate bias voltage of the auxiliary transistors is set to -2.2V, the power amplifier will provide a higher back-off efficiency, and this mode is a high back-off efficiency mode.

[0081] like Fig.11 The diagram shows the large signal test results when the present invention is in high back-off efficiency enhancement mode. Psat is the saturated output power; PAE@SAT is the power added efficiency corresponding to the saturated output power point (0dB back-off point), that is, the power output by the power amplifier in the saturated state; PAE@6dB-OBO and PAE@7.5dB-OBO are the power added efficiencies at 6dB and 7.5dB back-off of the saturated output power, respectively. It can be seen from the large signal test result diagram that in the high back-off efficiency mode, the power amplifier can provide a saturated output power of 36.4-37.6dBm between 24GHz and 29GHz, and the PAEs at the 7.5dB, 6dB and 0dB back-off points are 21.5-30.2%, 24.5-31.1% and 32.1-38.7%, respectively.

[0082] In another preferred embodiment of the present invention, when the bias condition of the auxiliary transistor is adjusted from Class C to Class AB, that is, when the gate bias voltage of the auxiliary transistor is set to -1.8V, the power amplifier will operate in a non-uniform traveling wave power amplifier (NDPA) mode, which can provide a wider bandwidth, and is therefore called a bandwidth enhancement mode, thereby improving the compatibility of the linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier of the present invention for different application environments. At this time, the linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier operates in a bandwidth enhancement mode. Fig.12The large signal test results of the present invention in the bandwidth enhancement mode are shown. In the bandwidth enhancement mode, the entire power amplifier can maintain a saturated output power and efficiency of 35.8-37.1dBm and 31.6-38.9% respectively within 24-30.5GHz.

[0083] In some preferred embodiments, the present invention provides a linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier chip, which includes the electrical components of each module of the linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier described above, and the chip adopts a commercial 150nm GaN-on-SiC HEMT process.

[0084] In some embodiments, the present invention further provides a radio frequency module, including the linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier as described above. Specifically, as described in an embodiment of a linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier, it will not be repeated here.

[0085] In some embodiments, the present invention further provides a wireless communication module or wireless communication device, including the linear broadband GaN millimeter wave integrated distributed high-efficiency power amplifier as described above. Specifically, as described in an embodiment of a linear broadband GaN millimeter wave integrated distributed high-efficiency power amplifier, it will not be repeated here.

[0086] In summary, the linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier provided by the present invention has the following beneficial effects:

[0087] The distributed output combining network based on the bandpass T structure must have certain gain expansion characteristics, which lays the foundation for the design of high-linearity DEPA;

[0088] The gain compression characteristics of the input network can be adjusted by the power division ratio of the power divider. This degree of freedom is used to construct an expanded DEPA gain characteristic and to compensate for the gain compression of the main transistor in the actual design, thereby improving the linearity of the entire DEPA.

[0089] When implementing the distributed output combining network, a distributed unit circuit based on a bandpass T structure is used to replace the traditional capacitor-loaded transmission line network, which significantly improves the matching bandwidth of the distributed output combining network at the optimal impedance value Qopt of the large transistor;

[0090] In addition to supporting high back-off efficiency mode, the amplifier can also be re-modulated to non-uniform traveling wave amplifier mode by adjusting the auxiliary amplifier gate bias voltage. This mode supports better bandwidth, thereby improving the compatibility of the power amplifier for different applications.

[0091] By adopting a distributed unit circuit based on a bandpass T structure to replace the traditional capacitor-loaded transmission line network, the matching bandwidth of the distributed output combining network based on the bandpass T structure can be significantly improved at the optimal impedance value Qopt value of the transistor. Compared with the prior art, the distributed output combining network based on the bandpass T structure of the present invention has certain gain expansion characteristics, which improves the design expansion performance of high-linearity DEPA.

[0092] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier, characterized in that: include: Power divider, delay network, main input matching network, auxiliary input matching network, main driver transistor, auxiliary driver transistor module, main intermediate matching network, auxiliary intermediate matching network, main transistor, auxiliary transistor module and distributed output combining network based on bandpass T structure; wherein, The output end of the power divider is connected to the input end of the main input matching network and the input end of the delay network respectively, so as to perform unequal power distribution on the connected RF input signal; The output end of the delay network is connected to the input end of the auxiliary input matching network, and is used to adjust the phase difference between the signal at the input end of the auxiliary input matching network and the main signal; The output end of the main input matching network is connected to the gate of the main driving stage transistor, and the main input matching network is used to match the port output impedance of the main input matching network to the source impedance of the main driving stage transistor; The input end of the auxiliary input matching network is connected to the output end of the delay network, and the output end of the auxiliary input matching network is connected to the auxiliary driving stage transistor module, so as to match the port output impedance of the auxiliary input matching network to the source impedance of the auxiliary driving stage transistor module; The input end of the main intermediate-stage matching network is connected to the drain of the main driving-stage transistor, the output end of the main intermediate-stage matching network is connected to the gate of the main transistor, and the main intermediate-stage matching network is used to perform impedance transformation on the RF input signal; The input end of the auxiliary circuit intermediate stage matching network is connected to the auxiliary circuit driving stage transistor module, and the output end of the auxiliary circuit intermediate stage matching network is connected to the auxiliary circuit driving stage transistor module, for performing impedance transformation on the RF input signal; The input end of the distributed output combining network based on the bandpass T structure is respectively connected to the drain of the main transistor and the output end of the auxiliary transistor module, and the distributed output combining network based on the bandpass T structure is used to realize a broadband traveling wave network and absorb the parasitic parameters of the main transistor and the auxiliary transistor module.

2. The linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier according to claim 1, characterized in that: The distributed output combining network based on the bandpass T structure includes: a first bandpass T structure unit, a second bandpass T structure unit, a third bandpass T structure unit, a first output capacitor, a second output capacitor, a third output capacitor, a fourth output capacitor, a first output resistor and a post-matching network; One end of the first band-pass T structure unit is connected to the drain of the main transistor and one end of the first output capacitor respectively, and the other end of the first band-pass T structure unit is connected to the first output end of the auxiliary transistor module, the second output capacitor and the common end of the second band-pass T structure unit; The other end of the second band-pass T structure unit is connected to the second output end of the auxiliary transistor module, one end of the third output capacitor and the common end of the third band-pass T structure unit; The other end of the third band-pass T structure unit is connected to the third output end of the auxiliary transistor module, the fourth output capacitor and the common end of the post-matching network; The other end of the first output capacitor, the other end of the second output capacitor, the other end of the third output capacitor and the other end of the fourth output capacitor are grounded; The other end of the post-matching network is connected to the RF output end through the first output resistor.

3. The linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier according to claim 2, characterized in that: In the distributed output combining network based on the bandpass T structure, the first bandpass T structure unit includes a first transmission line, a second transmission line and a third transmission line; the second bandpass T structure unit includes a fourth transmission line, a fifth transmission line and a sixth transmission line; the third bandpass T structure unit includes a seventh transmission line and an eighth transmission line; the post-matching network includes a ninth transmission line, a tenth transmission line and a DC blocking capacitor; The first transmission line is respectively connected to the drain of the main transistor and one end of the first output capacitor; one end of the second transmission line is respectively connected to one end of the first transmission line and one end of the third transmission line, and the other end of the second transmission line is grounded; the other end of the third transmission line is connected to the fourth transmission line, the first output end of the auxiliary transistor module and the common end of the second output capacitor; The other end of the fourth transmission line is respectively connected to one end of the fifth transmission line and one end of the sixth transmission line, the other end of the fifth transmission line is grounded, and the other end of the sixth transmission line is respectively connected to one end of the seventh transmission line and the second output end of the auxiliary transistor module; The other end of the seventh transmission line is connected to one end of the eighth transmission line, and the other end of the eighth transmission line is connected to a common end of the third output end of the auxiliary transistor module, the fourth output capacitor and one end of the ninth transmission line; The other end of the ninth transmission line is respectively connected to one end of the DC blocking capacitor and the tenth transmission line, and the other end of the first output capacitor, the other end of the second output capacitor, the other end of the third output capacitor and the other end of the fourth output capacitor are grounded.

4. The linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier according to claim 1, characterized in that: The auxiliary path driving stage transistor module comprises: a first auxiliary path driving stage transistor, a second auxiliary path driving stage transistor and a third auxiliary path driving stage transistor; The gate of the first auxiliary path driver stage transistor, the gate of the second auxiliary path driver stage transistor and the gate of the third auxiliary path driver stage transistor are respectively connected to the output end of the auxiliary path input matching network, the source of the first auxiliary path driver stage transistor, the second auxiliary path driver stage transistor and the third auxiliary path driver stage transistor are grounded, and the drain of the first auxiliary path driver stage transistor, the second auxiliary path driver stage transistor and the third auxiliary path driver stage transistor are respectively connected to the auxiliary path intermediate stage matching network.

5. The linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier according to claim 1, characterized in that: The auxiliary transistor module includes: a first auxiliary transistor, a second auxiliary transistor and a third auxiliary transistor; the gate of the first auxiliary transistor, the gate of the second auxiliary transistor and the gate of the third auxiliary transistor are respectively connected to the auxiliary intermediate stage matching network, the source of the first auxiliary transistor, the source of the second auxiliary transistor and the source of the third auxiliary transistor are grounded, and the drain of the first auxiliary transistor, the drain of the second auxiliary transistor and the drain of the third auxiliary transistor are respectively connected to the distributed output combining network based on the bandpass T structure.

6. The linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier according to claim 4, characterized in that: The auxiliary intermediate-stage matching network includes: a first auxiliary intermediate-stage matching network, a second auxiliary intermediate-stage matching network and a third auxiliary intermediate-stage matching network; the input end of the first auxiliary intermediate-stage matching network is connected to the drain of the first auxiliary driving-stage transistor, the input end of the second auxiliary intermediate-stage matching network is connected to the drain of the second auxiliary driving-stage transistor, the third auxiliary intermediate-stage matching network is connected to the drain of the third auxiliary driving-stage transistor, the first auxiliary intermediate-stage matching network, the second auxiliary intermediate-stage matching network and the third auxiliary intermediate-stage matching network are cascaded with each other, and are used to absorb parasitic parameters in the first auxiliary driving-stage transistor, the second auxiliary driving-stage transistor and the third auxiliary driving-stage transistor respectively.

7. The linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier according to claim 6, characterized in that: The circuit structure and size of the main intermediate-stage matching network and the first auxiliary intermediate-stage matching network, the second auxiliary intermediate-stage matching network and the third auxiliary intermediate-stage matching network are the same; the main intermediate-stage matching network includes: a first intermediate transmission line, a second intermediate transmission line, a third intermediate transmission line, a fourth intermediate transmission line, a fifth intermediate transmission line, a sixth intermediate resistor, a seventh intermediate resistor, a first intermediate capacitor, a second intermediate capacitor, a third intermediate capacitor, a fourth intermediate capacitor, a fifth intermediate capacitor and a sixth intermediate capacitor; wherein, One end of the first intermediate capacitor is connected to the drain of the main driving stage transistor, the other end of the first intermediate capacitor is respectively connected to one end of the second intermediate transmission line, the common end of the third intermediate transmission line and the second intermediate capacitor, the other end of the second intermediate transmission line is connected to one end of the first intermediate capacitor, and the other end of the first intermediate capacitor is grounded; the other end of the second intermediate capacitor is connected to the common end of the fourth intermediate transmission line and the fifth intermediate transmission line, the sixth intermediate resistor and the fifth intermediate capacitor are connected in parallel to the gate of the main transistor; the other end of the fifth intermediate transmission line is respectively connected to the common end of the sixth intermediate capacitor and the seventh intermediate resistor, the other end of the fourth intermediate transmission line is connected to one end of the fourth intermediate capacitor, the other end of the third intermediate transmission line is connected to one end of the third intermediate capacitor, and the other end of the third intermediate capacitor and the other end of the fourth intermediate capacitor are grounded.

8. The linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier according to claim 1, characterized in that: The main input matching network includes: a first main input transmission line, a second main input transmission line, a third main input transmission line, a fourth main input resistor, a fifth main input transmission line, a sixth main input resistor, a first main input capacitor, a second main input capacitor, a third main input capacitor and a fourth main input capacitor; wherein, One end of the first main input transmission line is connected to the main output end of the power divider, the other end of the first main input transmission line is connected to one end of the first main input capacitor, the other end of the first main input capacitor is connected to the common end of the second main input capacitor and the second main input transmission line, the other end of the second main input capacitor is grounded, and the other end of the second main input transmission line is respectively connected to one end of the third main input transmission line and one end of the fifth main input transmission line; the other end of the third main input transmission line is connected to the common end of the fourth main input resistor and the third main input capacitor, the other end of the fourth main input resistor is connected to the input end of the driving voltage, the other end of the third main input capacitor is grounded, the other end of the fifth main input transmission line is connected to the common end of the sixth main input resistor and one end of the fourth main input capacitor, and the sixth main input resistor and the fourth main input capacitor are connected in parallel to the gate of the main driving stage transistor.

9. The linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier according to claim 1, characterized in that: The delay network includes: a first delay transmission line, a second delay transmission line, a third delay transmission line, a fourth delay transmission line, a fifth delay transmission line, a sixth delay transmission line, a first delay capacitor, a second delay capacitor, a third delay capacitor, a fourth delay capacitor, a fifth delay capacitor and a sixth delay capacitor; wherein, One end of the first delay transmission line is connected to the auxiliary output end of the power divider, and the other end of the first delay transmission line is respectively connected to the second delay capacitor and the common end of the second delay transmission line; The other end of the second delay transmission line is connected to one end of the first delay capacitor; the other end of the second delay capacitor is connected to one end of the third delay transmission line, the other end of the third delay transmission line is connected to the common end of the third delay capacitor and the fourth delay transmission line, the other end of the fourth delay transmission line is connected to the common end of the fourth delay capacitor and the fifth delay transmission line, the other end of the fifth delay transmission line is connected to one end of the fifth delay capacitor, the other end of the fifth delay capacitor is respectively connected to the input end of the auxiliary input matching network and one end of the sixth delay transmission line, the other end of the sixth delay transmission line is connected to the sixth delay capacitor, and the other end of the first delay capacitor, the other end of the third delay capacitor, the other end of the fourth delay capacitor and the other end of the sixth delay capacitor are grounded.

10. The linear broadband gallium nitride millimeter wave integrated distributed high-efficiency power amplifier according to claim 4, characterized in that: The auxiliary input matching network includes: a first auxiliary input capacitor, a second auxiliary input capacitor, a first auxiliary input transmission line, a third auxiliary input resistor, a third auxiliary input capacitor, a second auxiliary input transmission line, a fourth auxiliary input capacitor, a fourth auxiliary input transmission line, a fifth auxiliary input resistor, a fifth auxiliary input capacitor, a sixth auxiliary input transmission line, a sixth auxiliary input capacitor, a seventh auxiliary input transmission line, an eighth auxiliary input resistor, a seventh auxiliary input capacitor, a ninth auxiliary input transmission line, a tenth auxiliary input resistor and an eighth auxiliary input capacitor; wherein, One end of the first auxiliary input capacitor is connected to the output end of the delay network, the other end of the first auxiliary input capacitor is connected to the common end of the second auxiliary input capacitor and the first auxiliary input transmission line, and the other end of the second auxiliary input capacitor is grounded; the other end of the first auxiliary input transmission line is respectively connected to the common end of the second auxiliary input transmission line, the third auxiliary input resistor and the third auxiliary input capacitor; the third auxiliary input resistor and the third auxiliary input capacitor are connected in parallel to the first auxiliary driving stage transistor; the other end of the second auxiliary input transmission line is connected to the common end of the fourth auxiliary input capacitor and the fourth auxiliary input transmission line, and the other end of the fourth auxiliary input transmission line is connected to the common end of the sixth auxiliary input transmission line, the fifth auxiliary input resistor and the fifth auxiliary input capacitor; The input resistor and the fifth auxiliary input capacitor are connected in parallel and then connected to the second auxiliary drive-stage transistor for outputting a matched traveling wave signal; the other end of the sixth auxiliary input transmission line is connected to the common end of the sixth auxiliary input capacitor and the seventh auxiliary input transmission line, and the other end of the seventh auxiliary input transmission line is respectively connected to the common end of the ninth auxiliary input transmission line, the eighth auxiliary input resistor and the seventh auxiliary input capacitor; the eighth auxiliary input resistor and the seventh auxiliary input capacitor are connected in parallel and then connected to the third auxiliary drive-stage transistor; the other end of the ninth auxiliary input transmission line is connected to one end of the tenth auxiliary input resistor, and the other end of the tenth auxiliary input resistor is respectively connected to the drive signal and the eighth auxiliary input capacitor, and the other end of the fourth auxiliary input capacitor, the other end of the sixth auxiliary input capacitor and the other end of the eighth auxiliary input capacitor are grounded.

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