Level shift circuit with hybrid structure
By designing a level shift circuit with a hybrid structure in an integrated circuit, combining cross-coupling and current mirror level shift sub-circuit, the problems of long delay time and high power consumption during level conversion are solved, and picosecond-level delay and nanoampere level static power consumption are achieved.
Patent Information
- Application Number
- CN202411515256.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2025-02-25
AI Technical Summary
The level shift circuit in the prior art has a long delay time and high power consumption during conversion between the low voltage domain and the high voltage domain, which cannot meet the strict requirements of high voltage systems for low dynamic and static power consumption and delay.
A mixed-structure level shift circuit is designed, combining the cross-coupled level shift sub-circuit and the two current mirror level shift sub-circuits. By adjusting the pull-up intensity of the pull-up network, the quiescent current path is cut off, and the level conversion between the low voltage domain and the high voltage domain is realized.
The picosecond-level delay and nanoamper-level static power consumption are realized, solving the problem of long delay and high power consumption of level shift circuits in the conversion between low voltage and high voltage domains in the prior art.
Smart Images
Figure CN119519691A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of integrated circuits, and in particular to a level shift circuit with a hybrid structure. Background Art
[0002] With the advancement of automotive electronics and the continuous improvement of integration, in order to obtain higher energy density, stronger power output and lower energy loss, the power supply voltage (VDD) of automotive electronics has increased from 12V to 48V. Therefore, the high-voltage system has put forward strict requirements on the low dynamic and static power consumption and delay of the electronic system. In the prior art, the common electronic system adopts a multi-VDD power supply architecture to reduce the dynamic and static power consumption of the electronic system. Its timing-critical parts or analog circuits work at a high power supply voltage (VDDH), while other non-critical parts are powered by a low power supply voltage (VDDL) to maximize energy efficiency; in integrated circuits with multiple voltage domains, level shift circuits (LSs) are used for stable conversion from a low voltage domain (VDDL) to a high voltage domain (VDDH), but during the conversion process of the voltage domain, its static power consumption is high and the delay is long, which has seriously affected the development of integrated circuits.
[0003] Therefore, it is urgent to design a level shift circuit that can improve the conversion delay and power consumption between the low voltage domain and the high voltage domain in the integrated circuit, so as to solve the problem of long conversion delay and high power consumption of the level shift circuit in the prior art. Summary of the invention
[0004] The purpose of the present invention is to provide a level shift circuit with a hybrid structure, which hybridly designs a cross-coupled level shift circuit and two current mirror level shift circuits, not only realizing the level conversion between the low voltage domain and the high voltage domain in the integrated circuit, but also having picosecond level delay and nanoampere level static power consumption; it solves the problem of long delay and high power consumption when converting between the low voltage domain and the high voltage domain in the level shift circuit in the prior art.
[0005] In order to achieve the above object, the present invention provides the following technical solutions:
[0006] The present invention provides a hybrid structure level shift circuit, which may include at least: a cross-coupling level shift subcircuit, a first current mirror level shift subcircuit and a second current mirror level shift subcircuit;
[0007] The first current mirror level shift subcircuit is connected to the cross-coupling level shift subcircuit, and the second current mirror level shift subcircuit is connected to the cross-coupling level shift subcircuit;
[0008] The output signal of the first current mirror level shift subcircuit is used to reduce the pull-up strength of the first pull-up network in the cross-coupling level shift subcircuit; the first pull-up network is a pull-up network including a third PMOS tube;
[0009] The output signal of the second current mirror level shift subcircuit is used to reduce the pull-up strength of the second pull-up network in the cross-coupling level shift subcircuit; the second pull-up network is a pull-up network including a fourth PMOS tube;
[0010] The cross-coupling level shift subcircuit is used to cut off the static current path in the first current mirror level shift subcircuit and the second current mirror level shift subcircuit, and to realize the conversion between the low voltage domain and the high voltage domain of the level shift circuit.
[0011] Preferably, the first current mirror level shift subcircuit may include a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a third high-voltage NMOS transistor and a first variable resistor;
[0012] The source of the first PMOS tube is connected to the power supply terminal, the drain of the first PMOS tube is connected to the fifth terminal, and the gate of the first PMOS tube is connected to the fifth terminal; the source of the second PMOS tube is connected to the power supply terminal, the drain of the second PMOS tube is connected to the second terminal, and the gate of the second PMOS tube is connected to the fifth terminal;
[0013] The drain of the first NMOS tube is connected to the fifth terminal, the source of the first NMOS tube is connected to the drain of the third high-voltage NMOS tube, and the gate of the first NMOS tube is connected to the first terminal; one end of the first variable resistor is connected to the source of the third high-voltage NMOS tube, and the other end of the first variable resistor is grounded; the gate of the third high-voltage NMOS tube is connected to the circuit input signal terminal.
[0014] Preferably, the first variable resistor can be used to dynamically adjust the pull-up strength of the third PMOS tube on the fourth terminal, and match the pull-up strength with the pull-down strength of the fourth terminal to weaken the current competition between the third PMOS tube and the first high-voltage PMOS tube and the first high-voltage NMOS tube for the fourth terminal point; wherein the first high-voltage PMOS tube and the first high-voltage NMOS tube power tube are used to generate the pull-down strength for the fourth terminal.
[0015] Preferably, the second current mirror level shift subcircuit may include a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, a fourth high-voltage NMOS transistor and a second variable resistor;
[0016] The source of the fifth PMOS tube is connected to the power supply terminal, the drain of the fifth PMOS tube is connected to the fourth terminal, and the gate of the fifth PMOS tube is connected to the sixth terminal; the source of the sixth PMOS tube is connected to the power supply terminal, the drain of the sixth PMOS tube is connected to the sixth terminal, and the gate of the sixth PMOS tube is connected to the sixth terminal;
[0017] The drain of the fifth NMOS tube is connected to the sixth terminal, the source of the fifth NMOS tube is connected to the drain of the fourth high-voltage NMOS tube, and the gate of the fifth NMOS tube is connected to the third terminal; one end of the second variable resistor is connected to the source of the fourth high-voltage NMOS tube, and the other end of the second variable resistor is grounded; the gate of the fourth high-voltage NMOS tube is connected to the circuit input inverted signal terminal.
[0018] Preferably, the second variable resistor can be used to dynamically adjust the pull-up strength of the fourth PMOS tube on the second terminal, and match the pull-up strength of the second terminal with the pull-down strength of the second terminal to weaken the current competition between the fourth PMOS tube and the second high-voltage PMOS tube and the second high-voltage NMOS tube for the second terminal; wherein the second high-voltage PMOS tube and the second high-voltage NMOS tube are used to generate pull-down strength for the second terminal.
[0019] Preferably, the cross-coupled level shift subcircuit may include a third PMOS transistor, a fourth PMOS transistor, a first high-voltage PMOS transistor, a second high-voltage PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first high-voltage NMOS transistor, a second high-voltage NMOS transistor, an inverter, and a buffer;
[0020] The source of the third PMOS tube is connected to the power supply terminal, the drain of the third PMOS tube is connected to the fourth terminal, and the gate of the third PMOS tube is connected to the second terminal; the source of the fourth PMOS tube is connected to the power supply terminal, the drain of the fourth PMOS tube is connected to the second terminal, and the gate of the fourth PMOS tube is connected to the fourth terminal; the source of the first high-voltage PMOS tube is connected to the fourth terminal, the drain of the first high-voltage PMOS tube is connected to the first terminal, and the gate of the first high-voltage PMOS tube is connected to the floating grounding electrode; the source of the second high-voltage PMOS tube is connected to the second terminal, the drain of the second high-voltage PMOS tube is connected to the third terminal, and the gate of the second high-voltage PMOS tube is connected to the floating grounding electrode;
[0021] The drain of the third NMOS tube is connected to the fourth terminal, the source of the third NMOS tube is connected to the floating grounding electrode, and the gate of the third NMOS tube is connected to the second terminal; the drain of the fourth NMOS tube is connected to the second terminal, the source of the fourth NMOS tube is connected to the floating grounding electrode, and the gate of the fourth NMOS tube is connected to the fourth terminal; the drain of the first high-voltage NMOS tube is connected to the first terminal, the source of the first high-voltage NMOS tube is grounded, and the gate of the first high-voltage NMOS tube is connected to the circuit input signal terminal; the drain of the second high-voltage NMOS tube is connected to the third terminal, the source of the second high-voltage NMOS tube is grounded, and the gate of the second high-voltage NMOS tube is connected to the circuit input anti-signal terminal;
[0022] The input end of the inverter is connected to the circuit input signal end, and the output end of the inverter is connected to the circuit input inverted signal end; the input end of the buffer is connected to the second terminal, and the output end of the buffer is connected to the circuit output signal end.
[0023] Preferably, when the level of the circuit input signal terminal is converted from low to high, it may include: the first current mirror level shift subcircuit generates a first mirror current, and the first mirror current is used to suppress current competition between the third PMOS tube, the first high-voltage PMOS tube and the first high-voltage NMOS tube.
[0024] Preferably, when the circuit input signal terminal is at a high level, it may include: a first NMOS tube used to cut off the static current path of the first current mirror level shift subcircuit, and a fourth high-voltage NMOS tube used to cut off the static current path of the second current mirror level shift subcircuit.
[0025] Preferably, when the level of the circuit input signal terminal is converted from high to low, it can include: a second current mirror level shift subcircuit generates a second mirror current flowing through the fifth PMOS tube, and the second mirror current is used to suppress current competition between the fourth PMOS tube, the second high-voltage PMOS tube and the second high-voltage NMOS tube.
[0026] Preferably, when the circuit input signal terminal is at a low level, it may include: a third high-voltage NMOS tube is used to cut off the static current path of the first current mirror level shift subcircuit; a fifth NMOS tube is used to cut off the static current path of the second current mirror level shift subcircuit; and the third PMOS tube in the cross-coupling level shift subcircuit is fully turned on.
[0027] Compared with the prior art, the present invention provides a hybrid structure level shift circuit, which at least provides a cross-coupled level shift subcircuit, a first current mirror level shift subcircuit and a second current mirror level shift subcircuit; the first current mirror level shift subcircuit is connected to the cross-coupled level shift subcircuit, and the second current mirror level shift subcircuit is connected to the cross-coupled level shift subcircuit; the output signal of the first current mirror level shift subcircuit is used to reduce the pull-up strength of the first pull-up network in the cross-coupled level shift subcircuit; the output signal of the second current mirror level shift subcircuit is used to reduce the pull-up strength of the second pull-up network in the cross-coupled level shift subcircuit. degree; wherein, the first pull-up network is a pull-up network including a third PMOS tube; the second pull-up network is a pull-up network including a fourth PMOS tube; the cross-coupled level shift subcircuit is used to cut off the static current path in the first current mirror level shift subcircuit and the second current mirror level shift subcircuit, and to realize the conversion between the low voltage domain and the high voltage domain of the level shift circuit; based on this, the level conversion between the low voltage domain and the high voltage domain in the integrated circuit of multiple voltage domains is realized, and the technical effects of picosecond level delay and nanoampere level static power consumption are achieved; thereby solving the problem of long delay and high power consumption when the level shift circuit in the prior art is converted between the low voltage domain and the high voltage domain. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:
[0029] Figure 1 It is a structural schematic diagram of a first level shift circuit in the prior art;
[0030] Figure 2 is a structural schematic diagram of a second level shift circuit in the prior art;
[0031] Figure 3 A schematic structural diagram of a hybrid level shift circuit provided by the present invention;
[0032] Figure 4 A schematic diagram of a first working principle of a hybrid structure level shift circuit provided by the present invention;
[0033] Figure 5 A schematic diagram of a second working principle of a hybrid structure level shift circuit provided by the present invention;
[0034] Figure 6 A schematic diagram of a third working principle of a hybrid structure level shift circuit provided by the present invention;
[0035] Figure 7A schematic diagram of a fourth working principle of a hybrid structure level shift circuit provided by the present invention;
[0036] Figure 8 A schematic diagram of a start-up delay simulation waveform effect of a hybrid structure level shift circuit provided by the present invention;
[0037] Fig. 9 A schematic diagram of a turn-off delay simulation waveform effect of a hybrid structure level shift circuit provided by the present invention.
[0038] Reference numerals: 300 - level shift circuit, 310 - cross-coupled level shift sub-circuit, 320 - first current mirror level shift sub-circuit, 330 - second current mirror level shift sub-circuit, IN - circuit input signal terminal, INB - circuit input negative signal terminal, OUT - circuit output signal terminal, Q1 - first terminal, Q1 U -Second terminal, Q2 -Third terminal, Q2 U -fourth terminal, Q3-fifth terminal, Q4-sixth terminal, VSSH-floating ground electrode, PL1-first high-voltage PMOS tube, PL2-second high-voltage PMOS tube, NL1-first high-voltage NMOS tube, NL2-second high-voltage NMOS tube, NL3-third high-voltage NMOS tube, NL4-fourth high-voltage NMOS tube. DETAILED DESCRIPTION
[0039] In order to facilitate the clear description of the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit their order of precedence. Those skilled in the art can understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit them to be different.
[0040] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.
[0041] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects in the previous time are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.
[0042] First, some English abbreviations involved in the specification of the present invention are explained as follows:
[0043]
[0044] When the level shift circuit (LSs) in the prior art is used for the conversion process from a stable low voltage domain (VDDL) to a high voltage domain (VDDH), its delay is poor and the power consumption is high, which cannot meet the needs of integrated circuits with multiple voltage domains. Therefore, there is an urgent need for a level shift circuit that improves circuit delay and static power consumption.
[0045] The commonly used cross-coupled LS (CCLS) and current mirror LS (CMLS) are classic level shift structures. Figure 1 to Figure 2 , Figure 1 It is a structural schematic diagram of a first level shift circuit in the prior art; Figure 2 It is a schematic diagram of the structure of a second level shift circuit in the prior art.
[0046] exist Figure 1 In the cross-coupled circuit shown in (a) on the left, when the input signal IN is a high level V in the low voltage domain DDL When the gate voltage of P2 is pulled down to GND, its source terminal is the high level V in the high voltage domain. DDH , so P2 is turned on, and the OUT output is V DDH When the input signal IN is low level GND, INb is high level V in the low voltage domain. DDL At this time, N2 tube is turned on, N1 tube is turned off, and OUT output is GND.
[0047] like Figure 1 In the current mirror circuit shown in (b) on the right, when the input signal IN is a high level V in the low voltage domain DDLWhen N1 is turned on, N2 is turned off, and point X is pulled down to GND. P1 and P2 are turned on at the same time, and OUT output is V DDH When the input signal IN is GND, INb is the high level V in the low voltage domain. DDL At this time, N2 tube is turned on, N1 tube is turned off, and OUT output is GND.
[0048] Based on this, Figure 1 In the circuit structure shown, CCLS achieves near-zero static power consumption with the complementary pull-up network (PUN) and pull-down network (PDN). However, there is a strong current competition problem at the X point of CCLS during the transition from low to high and from high to low. DDL The PDN driver must overcome the V DDH The PUN driven by the LS can perform level conversion. This will cause the delay and energy consumption of LSs to increase with V DDL Although CMLS eliminates the current competition problem that only exists in CCLS, when IN is kept at logic "1", N1 and P1 are turned on, and CMLS has a V DDH The current path to GND causes a higher quiescent current.
[0049] It should be noted that in a static CMOS circuit, the pull-up network (PUN) is composed of PMOS transistors, which are used to charge the load capacitor to logic "1", while the pull-down network (PDN) is composed of NMOS transistors, which are used to discharge the load capacitor to logic "0". The internal structures of these two networks are symmetrical and complementary, that is, the pull-down network is all NMOS, and the pull-up network is all PMOS, and the number of the two is the same.
[0050] exist Figure 2 in Figure 2 Hanwool Jeong et al. proposed a CMLS with logic error detection (CMLS-LED), which mainly consists of two parts: level shift circuit and logic error detection circuit. Its main working principle is: by connecting the gate of P1 to the drain of N1, positive feedback accelerates the transition of OUT and ensures that OUT goes from GND to V DDH The LS circuit is composed of a CMLS with two additional PMOS. The feedback tube P3 controlled by the OUT signal is connected in series with N1 to cut off the static current of this path. Figure 1 The connection point X between the gate of P1 and P1 in (b) is optimized to Figure 2This optimization allows the X node to be fully pulled down during the rise of IN, even after OUT rises. Therefore, OUT can be driven by the fully turned-on P2, preventing the performance of the CMLS-LED from degrading when OUT rises.
[0051] In addition, when INb is high, N2 is turned on and OUT is pulled down to GND. P4 is controlled by the ERR signal. When OUT is pulled down to GND, the ERR signal is high, thereby turning off P4. When P4 is turned off, OUT can be easily pulled down to GND by INb. The ERR signal is generated by the logic error detection circuit, which can be regarded as a level shift AND2 based on a current mirror. Its two input ports are INB and OUT, and the output is ERR. When both INB and OUT are high, the ERR signal is high.
[0052] Based on this, Figure 2 In the circuit structure shown, during the high-to-low transition, the low-level signal INb may not be able to completely pull down ERRb, and competition between P5 and N3 and between P4 and N2 cannot be avoided (if ERR does not rise), resulting in limited conversion range and high energy consumption.
[0053] In view of this, in order to solve the problems of long delay and high power consumption in the conversion from low voltage domain to high voltage domain caused by current competition, static current and speed limitation in the existing LS, the present invention proposes a hybrid level shift circuit based on CCLS / CMLS. The new LS is named HVC 3 MLS. This circuit can not only realize the level conversion between the low-voltage domain and the high-voltage domain, but also has picosecond delay and nanoampere level static power consumption.
[0054] Next, the technical solution of the present invention is described in detail with reference to the accompanying drawings:
[0055] See also Figure 3 , Figure 3 A schematic diagram of a hybrid structure level shift circuit provided by the present invention; the execution subject thereof is a digital circuit or digital product equipped with the technical solution disclosed in the embodiment of the present invention.
[0056] exist Figure 3 In the embodiment, the level shift circuit 300 may at least include: a cross-coupled level shift sub-circuit 310, a first current mirror level shift sub-circuit 320, and a second current mirror level shift sub-circuit 330. The first current mirror level shift sub-circuit 320 is connected to the cross-coupled level shift sub-circuit 310, and the second current mirror level shift sub-circuit 330 is connected to the cross-coupled level shift sub-circuit 310.
[0057] The output signal of the first current mirror level shift subcircuit 320 is used to reduce the pull-up strength of the first pull-up network in the cross-coupling level shift subcircuit 310; the first pull-up network is a pull-up network that may include a third PMOS tube. The output signal of the second current mirror level shift subcircuit 330 is used to reduce the pull-up strength of the second pull-up network in the cross-coupling level shift subcircuit 310; the second pull-up network is a pull-up network that may include a fourth PMOS tube.
[0058] The cross-coupling level shift subcircuit 310 is used to cut off the static current path in the first current mirror level shift subcircuit 320 and the second current mirror level shift subcircuit 330 and to implement the conversion between the low voltage domain and the high voltage domain of the level shift circuit.
[0059] Based on this, the present invention provides a hybrid structure level shift circuit, which at least provides a cross-coupled level shift subcircuit, a first current mirror level shift subcircuit and a second current mirror level shift subcircuit; the first current mirror level shift subcircuit is connected to the cross-coupled level shift subcircuit, and the second current mirror level shift subcircuit is connected to the cross-coupled level shift subcircuit; the output signal of the first current mirror level shift subcircuit is used to reduce the pull-up strength of the first pull-up network in the cross-coupled level shift subcircuit; the output signal of the second current mirror level shift subcircuit is used to reduce the cross-coupled level shift subcircuit. The pull-up strength of the second pull-up network in the cross-coupled level shift subcircuit; wherein, the first pull-up network is a pull-up network including a third PMOS tube; the second pull-up network is a pull-up network including a fourth PMOS tube; the cross-coupled level shift subcircuit is used to cut off the static current path in the first current mirror level shift subcircuit and the second current mirror level shift subcircuit, and realize the conversion between the low voltage domain and the high voltage domain of the level shift circuit; realizes the level conversion between the low voltage domain and the high voltage domain in an integrated circuit of multiple voltage domains, and has the technical effects of picosecond level delay and nanoampere level static power consumption.
[0060] Please continue reading Figure 3 Preferably, the first current mirror level shift sub-circuit 320 may include a first PMOS tube, a second PMOS tube, a first NMOS tube, a third high-voltage NMOS tube and a first variable resistor.
[0061] The source of the first PMOS tube is connected to the power supply end, the drain of the first PMOS tube is connected to the fifth terminal, and the gate of the first PMOS tube is connected to the fifth terminal; the source of the second PMOS tube is connected to the power supply end, the drain of the second PMOS tube is connected to the second terminal, and the gate of the second PMOS tube is connected to the fifth terminal.
[0062] The drain of the first NMOS tube is further connected to the fifth terminal, the source of the first NMOS tube is connected to the drain of the third high-voltage NMOS tube, and the gate of the first NMOS tube is connected to the first terminal Q1; one end of the first variable resistor is connected to the source of the third high-voltage NMOS tube, and the other end of the first variable resistor is grounded; the gate of the third high-voltage NMOS tube is connected to the circuit input signal terminal IN.
[0063] Based on this, the circuit structure of the first current mirror level shift sub-circuit 320 is constructed, that is, the CMLS circuit structure on the left side of the cross-coupled level shift sub-circuit 310 is constructed; thereby, the output signal of the first current mirror level shift sub-circuit 320 can be used to reduce the pull-up strength of the first pull-up network of the cross-coupled level shift sub-circuit 310 including the third PMOS tube.
[0064] Preferably, the first variable resistor can be used to dynamically adjust the pull-up strength of the third PMOS tube on the fourth terminal, and match the pull-up strength with the pull-down strength of the fourth terminal to weaken the current competition between the third PMOS tube and the first high-voltage PMOS tube and the first high-voltage NMOS tube for the fourth terminal point; wherein the first high-voltage PMOS tube and the first high-voltage NMOS tube power tube are used to generate pull-down strength for the fourth terminal.
[0065] Preferably, the second current mirror level shift sub-circuit 330 may include a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, a fourth high-voltage NMOS transistor and a second variable resistor.
[0066] The source of the fifth PMOS tube is connected to the power supply end, the drain of the fifth PMOS tube is connected to the fourth terminal, and the gate of the fifth PMOS tube is connected to the sixth terminal; the source of the sixth PMOS tube is connected to the power supply end, the drain of the sixth PMOS tube is connected to the sixth terminal, and the gate of the sixth PMOS tube is connected to the sixth terminal.
[0067] The drain of the fifth NMOS tube is further connected to the sixth terminal, the source of the fifth NMOS tube is connected to the drain of the fourth high-voltage NMOS tube, and the gate of the fifth NMOS tube is connected to the third terminal; one end of the second variable resistor is connected to the source of the fourth high-voltage NMOS tube, and the other end of the second variable resistor is grounded; the gate of the fourth high-voltage NMOS tube is connected to the circuit input inverted signal terminal INB.
[0068] Based on this, the circuit structure of the second current mirror level shift sub-circuit 330 is constructed, that is, the CMLS circuit structure is constructed on the right side of the cross-coupled level shift sub-circuit 310; thereby, the output signal of the second current mirror level shift sub-circuit 330 can be used to reduce the pull-up strength of the second pull-up network of the cross-coupled level shift sub-circuit 310 including the fourth PMOS tube.
[0069] Preferably, the second adjustable resistor can be used to dynamically adjust the fourth PMOS transistor to the second terminal Q1 U The pull-up strength of the second terminal Q1 U The pull-up strength of the second terminal Q1 U The pull-down strength is matched to weaken the current competition between the fourth PMOS tube and the second high-voltage PMOS tube and the second high-voltage NMOS tube for the second terminal; wherein the second high-voltage PMOS tube and the second high-voltage NMOS tube are used to generate a pull-down strength for the second terminal.
[0070] Preferably, the cross-coupled level shift subcircuit 310 may include a third PMOS transistor, a fourth PMOS transistor, a first high-voltage PMOS transistor, a second high-voltage PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first high-voltage NMOS transistor, a second high-voltage NMOS transistor, an inverter, and a buffer. The buffer Buffer is a circuit structure of two inverters connected in sequence.
[0071] The source of the third PMOS tube is connected to the power supply end, the drain of the third PMOS tube is connected to the fourth terminal, and the gate of the third PMOS tube is connected to the second terminal; the source of the fourth PMOS tube is connected to the power supply end, the drain of the fourth PMOS tube is connected to the second terminal, and the gate of the fourth PMOS tube is connected to the fourth terminal; the source of the first high-voltage PMOS tube is connected to the fourth terminal, the drain of the first high-voltage PMOS tube is connected to the first terminal, and the gate of the first high-voltage PMOS tube is connected to the floating grounding electrode VSSH; the source of the second high-voltage PMOS tube is connected to the second terminal, the drain of the second high-voltage PMOS tube is connected to the third terminal Q2, and the gate of the second high-voltage PMOS tube is connected to the floating grounding electrode VSSH.
[0072] It should be noted that the floating ground electrode refers to the isolation of the circuit or equipment from the common wire that may cause circulating current from the public ground wire, making it easier for circuits with different potentials to cooperate. The characteristic of this grounding method is that the ground of the circuit or equipment has no direct electrical connection with the earth or other public ground wires and is in a suspended state. The advantage of floating grounding is that it can reduce the interference between the circuit and the earth and avoid electromagnetic interference problems caused by common ground impedance. In addition, the floating ground electrode VSSH end can also improve the safety of the circuit. For example, in an isolation transformer, by floating the ground on the low-voltage side, the ground current path from the main power supply can be avoided, thereby improving electrical safety.
[0073] Further connect the drain of the third NMOS tube to the fourth terminal Q2 U The source of the third NMOS tube is connected to the floating ground electrode, and the gate of the third NMOS tube is connected to the second terminal Q1 U Connect the drain of the fourth NMOS tube to the second terminal Q1 UThe source of the fourth NMOS tube is connected to the floating ground electrode, and the gate of the fourth NMOS tube is connected to the fourth terminal Q2 U Connection; the drain of the first high-voltage NMOS tube is connected to the first terminal Q1, the source of the first high-voltage NMOS tube is grounded, and the gate of the first high-voltage NMOS tube is connected to the circuit input signal terminal; the drain of the second high-voltage NMOS tube is connected to the third terminal Q2, the source of the second high-voltage NMOS tube is grounded, and the gate of the second high-voltage NMOS tube is connected to the circuit input anti-signal terminal.
[0074] The input end of the inverter is connected to the circuit input signal end, and the output end of the inverter is connected to the circuit input inverted signal end; the input end of the buffer is connected to the second terminal, and the output end of the buffer is connected to the circuit output signal end OUT.
[0075] It should be noted that the hybrid level shift circuit provided by the present invention, which is composed of a CCLS structure and two CMLS structures, is named HVC in practical applications. 3 MLS. Among them, NL1, NL2, NL3 and NL4 are NLDOM tubes, that is, high-voltage NMOS tubes. In the present invention, NL1 is used to represent the first high-voltage NMOS tube, NL2 is used to represent the second high-voltage NMOS tube, NL3 is used to represent the third high-voltage NMOS tube, and NL4 is used to represent the fourth high-voltage NMOS tube; PL1 and PL2 are PLDMOS tubes, that is, high-voltage PMOS tubes; in the present invention, PL1 is used to represent the first high-voltage PMOS tube, and PL2 is used to represent the second high-voltage PMOS tube; the remaining MOS tubes all use 5V MOSFET. The VSSH terminal is connected to the gates of PL1 and PL2 to isolate the signals between the HV region and the LV region. The magnitude of the mirror current I can be controlled by setting the resistance values of the variable resistors R1 and R2. VDDL-GND and VDDH-VSSH are the power rails of the LV and HV regions, respectively, where the HV and LV regions have the same power rail voltage.
[0076] In the present invention, the power rail voltage is set to 5V, V DDH The voltage of the CMLS is determined by the source-drain breakdown voltage of the high-voltage power tubes NL1-NL4 and PL1-PL2. The CMLS is controlled by the input signal of the CCLS (IN or INB) and the signal generated by the CCLS (Q1 or Q2). Only when the logic level of IN and OUT starts at the transition of the input signal from low to high and from high to low, one of the two CMLS stages on the left and right will be turned on. The output Q1 of the CMLS stage U and Q2 U Connected to the gates of P3 and P4 in the CCLS structure PUN network to dynamically adjust the pull-up strength to eliminate the current contention problem in the CCLS structure. Output Q1 of the level shift circuit U Reshaping and enhancement of HVC by buffer module3 MLS driving capability after output.
[0077] Specifically, the working principle of a hybrid structure level shift circuit provided by the present invention is described in detail below. Figures 4 to 7 , Figure 4 A schematic diagram of a first working principle of a hybrid structure level shift circuit provided by the present invention; Figure 5 A schematic diagram of a second working principle of a hybrid structure level shift circuit provided by the present invention; Figure 6 A schematic diagram of a third working principle of a hybrid structure level shift circuit provided by the present invention; Figure 7 A fourth working principle schematic diagram of a hybrid structure level shift circuit provided by the present invention; it should be noted that, in order to show the accompanying drawings more clearly and more beautifully, Figures 4 to 7 Simplified with Figure 3 The corresponding MOS tube marks and the connections between the terminals; for example, P1 represents MP1, P2 represents PM2, N1 represents MN1, and N2 represents MN2.
[0078] like Figure 4 As shown, Figure 4 The schematic diagram shows the working principle of the conversion from low level to high level at the IN terminal; Figure 4 In the figure, the circuit portion with black lines represents the on state, and the circuit portion with gray lines represents the off state.
[0079] exist Figure 4 In the present invention, the working principle of the IN terminal of a hybrid structure level shift circuit provided by the present invention when converting from a low level to a high level is as follows: when the level of the circuit input signal terminal is converted from low to high, the first current mirror level shift subcircuit generates a first mirror current, and the first mirror current is used to suppress the current competition between the third PMOS tube, the first high-voltage PMOS tube and the first high-voltage NMOS tube.
[0080] Specifically, initially IN = "0", Q1 is at V DDH When IN changes from low level to high level, N1 and NL3 are both turned on, pulling down Q3 and generating a mirror current I through the current mirror composed of P1 and P2. The mirror current I has an effect on Q1. U Charge. Q1 U Connected to the gate of P3, when the gate of P3 is charged, the driving strength of P3 becomes weaker and weaker. So by using the mirror current I from the left CMLS, the P3 and PL1 and NL1 about Q2 are significantly suppressed. U The current competition problem of the point; the magnitude of the mirror current can be controlled by the resistance value of the variable resistor R1. And the resistance of the P3 power tube to Q2 can be dynamically adjusted by setting the resistance value of R1. UThe pull-up strength of the power tubes PL1 and NL1 is U The pull-down strength is matched, weakening P3 with PL1 and NL1 for Q2 U OUT finally turns high and then Q1 discharges, so with the help of the left CMLS stage, the current competition problem in the traditional CCLS is basically alleviated.
[0081] like Figure 5 As shown, Figure 5 The schematic diagram shows the working principle when the IN terminal is "1". Figure 5 In the figure, the circuit portion with black lines represents the on state, and the circuit portion with gray lines represents the off state.
[0082] exist Figure 5 In the present invention, the working principle of a hybrid structure level shift circuit when the IN terminal is "1" is: when the circuit input signal terminal is at a high level, the first NMOS tube is used to cut off the static current path of the first current mirror level shift subcircuit, and the fourth high-voltage NMOS tube is used to cut off the static current path of the second current mirror level shift subcircuit.
[0083] Specifically, after IN and OUT are both turned high, the voltages at Q1 and Q2 are 0 and V respectively. DDH At this time, N1 and NL4 will cut off the static current paths of the left and right CMLS structures respectively. 3 MLS avoids the high quiescent current problem in CCLS.
[0084] like Figure 6 As shown, Figure 6 The schematic diagram shows the working principle of the conversion from high level to low level at the IN terminal; Figure 6 In the figure, the circuit portion with black lines represents the on state, and the circuit portion with gray lines represents the off state.
[0085] exist Figure 6 In the present invention, the working principle of the conversion of the IN terminal of a hybrid structure level shift circuit from high level to low level is: when the level of the circuit input signal terminal is converted from high to low, the second current mirror level shift sub-circuit generates a second mirror current flowing through the fifth PMOS tube, and the second mirror current is used to suppress the current competition between the fourth PMOS tube, the second high-voltage PMOS tube and the second high-voltage NMOS tube.
[0086] Specifically, before the high-to-low transition, IN = "1", INB = "0". Q2 remains at logic "1". When the IN transition begins, after IN becomes low, INB becomes high, thereby temporarily generating a mirror current I flowing through P5. The mirror current I has an effect on Q2.U Charge. Q2 U Connected to the gate of P4, when the gate of P4 is charged, the driving strength of P4 will weaken with the amount of charge. Therefore, by using the mirror current I from the left CMLS, the relationship between P4 and PL2 and NL2 about Q1 can be significantly suppressed. U The magnitude of the mirror current can be controlled by the resistance value of resistor R2, so as to dynamically adjust the current of P4 to Q1. U The pull-up strength of the PL2 and NL2 power tubes is U The pull-down strength is matched, weakening P4 with PL2 and NL2 for Q1 U In this case, with the help of the CMLS stage on the right, the current competition problem in the traditional CCLS is significantly alleviated.
[0087] like Figure 7 As shown, Figure 7 The schematic diagram shows the working principle when the IN terminal is "0". Figure 7 In the figure, the circuit portion with black lines represents the on state, and the circuit portion with gray lines represents the off state.
[0088] exist Figure 7 In the present invention, the working principle of a hybrid structure level shift circuit when the IN terminal is "0" is: when the circuit input signal terminal is at a low level, the third high-voltage NMOS tube is used to cut off the static current path of the first current mirror level shift subcircuit; the fifth NMOS tube is used to cut off the static current path of the second current mirror level shift subcircuit; the third PMOS tube in the cross-coupled level shift subcircuit is fully turned on.
[0089] Specifically, after the high-to-low transition, the voltages at IN and Q2 are both at 0 potential, and NL3 and N5 cut off the quiescent current paths in the left CMLS structure and the right CMLS structure, respectively. P3 of the CCLS stage is fully turned on to achieve Q2 U To maintain full swing, there is no static current path in the CCLS structure and buffer module; therefore, in this case, the proposed HVC 3 MLS also avoids the high quiescent current problem in CCLS-based systems.
[0090] Based on this, the present invention provides a hybrid structure level shift circuit consisting of a CCLS structure and two CMLS structures. The CMLS in the hybrid structure can weaken the pull-up strength of PUN in CCLS, thereby weakening the current contention problem caused by the fact that the PUN strength is much higher than PDN in CCLS, thereby reducing the circuit delay to achieve picosecond level delay. The output signals Q1, Q2 and the input signals IN, INB in CCLS can control the shutdown of the MOSFET of CMLS, thereby cutting off the static current path in CMLS and achieving ultra-low power consumption. The structure proposed by the present invention can realize level conversion from a low voltage domain to any high voltage domain, which only needs to change HVC 3 The NL1, NL2, NL3, NL4, PL1 and PL2 transistors in MLS are made to meet the design rules for source-drain breakdown. The changes of NL1, NL2, NL3, NL4, PL1 and PL2 transistors will affect HVC 3 The PDN of CCLS in the MLS structure only needs to reasonably set the resistance values of R1 and R2 in CMLS to freely adjust the PUN strength to match the change of PDN strength, thereby achieving ultra-low latency.
[0091] Further, in order to verify the superiority of the hybrid structure level shift circuit provided by the present invention, the HVC 3 MLS simulation waveform; see Figures 8 to 9 , Figure 8 A schematic diagram of a start-up delay simulation waveform effect of a hybrid structure level shift circuit provided by the present invention; Fig. 9 A schematic diagram of a turn-off delay simulation waveform effect of a hybrid structure level shift circuit provided by the present invention.
[0092] exist Figure 8 and Fig. 9 The waveform diagrams include three waveform diagrams, which can be the first diagram, the second diagram, and the third diagram from top to bottom; the horizontal axes in the three diagrams all represent time in microseconds; the vertical axis in the first diagram represents voltage in volts; the vertical axis in the second diagram represents voltage in volts; and the vertical axis in the third diagram represents current in milliamperes. The waveform in the first diagram represents the input voltage signal at the IN end, the waveform in the second diagram represents the output voltage signal at the OUT end after the hybrid structure level shift circuit provided by the present invention; the waveform in the third diagram is the current signal output after the hybrid structure level shift circuit provided by the present invention, and dx in the second diagram represents the time difference between the waveforms in the first diagram and the second diagram.
[0093] from Figures 8 to 9 The simulation results shown in FIG. 1 can undoubtedly be obtained that: the level shift circuit (HVC) of the hybrid structure provided by the present invention 3MLS), achieved a turn-on delay of about 276ps when turned on, and a turn-off delay of about 16ps when turned off, and the static current of the circuit was about 3.2nA. The simulation results fully prove that the hybrid structure level shift circuit provided by the present invention combines the advantages of CCLS and CMLS, realizes the level conversion between the low voltage domain and the high voltage domain, and also has picosecond level delay and nanoampere level static power consumption, solves the problem of long delay and high power consumption when converting between the low voltage domain and the high voltage domain in the level shift circuit in the prior art; and promotes the development of integrated circuits.
[0094] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.
[0095] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.
Claims
1. A hybrid structure level shift circuit, characterized in that: The level shift circuit at least comprises: a cross-coupled level shift subcircuit, a first current mirror level shift subcircuit and a second current mirror level shift subcircuit; The first current mirror level shift subcircuit is connected to the cross-coupling level shift subcircuit, and the second current mirror level shift subcircuit is connected to the cross-coupling level shift subcircuit; The output signal of the first current mirror level shift subcircuit is used to reduce the pull-up strength of the first pull-up network in the cross-coupling level shift subcircuit; the first pull-up network is a pull-up network including a third PMOS tube; The output signal of the second current mirror level shift subcircuit is used to reduce the pull-up strength of the second pull-up network in the cross-coupling level shift subcircuit; the second pull-up network is a pull-up network including a fourth PMOS tube; The cross-coupling level shift subcircuit is used to cut off the static current path in the first current mirror level shift subcircuit and the second current mirror level shift subcircuit, and to realize the conversion between the low voltage domain and the high voltage domain of the level shift circuit.
2. The circuit according to claim 1, characterized in that The first current mirror level shift subcircuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a third high-voltage NMOS transistor and a first variable resistor; The source of the first PMOS tube is connected to the power supply terminal, the drain of the first PMOS tube is connected to the fifth terminal Q3, and the gate of the first PMOS tube is connected to the fifth terminal Q3; the source of the second PMOS tube is connected to the power supply terminal, the drain of the second PMOS tube is connected to the second terminal, and the gate of the second PMOS tube is connected to the fifth terminal; The drain of the first NMOS tube is connected to the fifth terminal, the source of the first NMOS tube is connected to the drain of the third high-voltage NMOS tube, and the gate of the first NMOS tube is connected to the first terminal; one end of the first variable resistor is connected to the source of the third high-voltage NMOS tube, and the other end of the first variable resistor is grounded; the gate of the third high-voltage NMOS tube is connected to the circuit input signal terminal.
3. The circuit according to claim 2, characterized in that The first variable resistor is used to dynamically adjust the pull-up strength of the third PMOS tube on the fourth terminal, and match the pull-up strength of the fourth terminal with the pull-down strength to weaken the current competition between the third PMOS tube and the first high-voltage PMOS tube and the first high-voltage NMOS tube for the fourth terminal point; wherein the first high-voltage PMOS tube and the first high-voltage NMOS tube power tube are used to generate pull-down strength for the fourth terminal.
4. The circuit according to claim 1, characterized in that The second current mirror level shift subcircuit includes a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, a fourth high-voltage NMOS transistor and a second variable resistor; The source of the fifth PMOS tube is connected to the power supply terminal, the drain of the fifth PMOS tube is connected to the fourth terminal, and the gate of the fifth PMOS tube is connected to the sixth terminal Q4; the source of the sixth PMOS tube is connected to the power supply terminal, the drain of the sixth PMOS tube is connected to the sixth terminal Q4, and the gate of the sixth PMOS tube is connected to the sixth terminal; The drain of the fifth NMOS tube is connected to the sixth terminal, the source of the fifth NMOS tube is connected to the drain of the fourth high-voltage NMOS tube, and the gate of the fifth NMOS tube is connected to the third terminal; one end of the second variable resistor is connected to the source of the fourth high-voltage NMOS tube, and the other end of the second variable resistor is grounded; the gate of the fourth high-voltage NMOS tube is connected to the circuit input inverted signal terminal.
5. The circuit according to claim 3, characterized in that The second resistor is used to dynamically adjust the pull-up strength of the fourth PMOS tube on the second terminal, and match the pull-up strength of the second terminal with the pull-down strength of the second terminal to weaken the current competition between the fourth PMOS tube and the second high-voltage PMOS tube and the second high-voltage NMOS tube for the second terminal; wherein the second high-voltage PMOS tube and the second high-voltage NMOS tube are used to generate pull-down strength for the second terminal.
6. The circuit according to claim 1, characterized in that The cross-coupled level shift subcircuit includes a third PMOS tube, a fourth PMOS tube, a first high-voltage PMOS tube, a second high-voltage PMOS tube, a third NMOS tube, a fourth NMOS tube, a first high-voltage NMOS tube, a second high-voltage NMOS tube, an inverter and a buffer; The source of the third PMOS tube is connected to the power supply terminal, the drain of the third PMOS tube is connected to the fourth terminal, and the gate of the third PMOS tube is connected to the second terminal; the source of the fourth PMOS tube is connected to the power supply terminal, the drain of the fourth PMOS tube is connected to the second terminal, and the gate of the fourth PMOS tube is connected to the fourth terminal; the source of the first high-voltage PMOS tube is connected to the fourth terminal, the drain of the first high-voltage PMOS tube is connected to the first terminal, and the gate of the first high-voltage PMOS tube is connected to the floating grounding electrode; the source of the second high-voltage PMOS tube is connected to the second terminal, the drain of the second high-voltage PMOS tube is connected to the third terminal, and the gate of the second high-voltage PMOS tube is connected to the floating grounding electrode; The drain of the third NMOS tube is connected to the fourth terminal, the source of the third NMOS tube is connected to the floating grounding electrode, and the gate of the third NMOS tube is connected to the second terminal; the drain of the fourth NMOS tube is connected to the second terminal, the source of the fourth NMOS tube is connected to the floating grounding electrode, and the gate of the fourth NMOS tube is connected to the fourth terminal; the drain of the first high-voltage NMOS tube is connected to the first terminal, the source of the first high-voltage NMOS tube is grounded, and the gate of the first high-voltage NMOS tube is connected to the circuit input signal terminal; the drain of the second high-voltage NMOS tube is connected to the third terminal, the source of the second high-voltage NMOS tube is grounded, and the gate of the second high-voltage NMOS tube is connected to the circuit input anti-signal terminal; The input end of the inverter is connected to the circuit input signal end, and the output end of the inverter is connected to the circuit input inverted signal end; the input end of the buffer is connected to the second terminal, and the output end of the buffer is connected to the circuit output signal end.
7. The circuit according to claim 1, characterized in that When the level of the circuit input signal terminal changes from low to high, including: The first current mirror level shift subcircuit generates a first mirror current, and the first mirror current is used to suppress current competition among the third PMOS tube, the first high-voltage PMOS tube and the first high-voltage NMOS tube.
8. The circuit according to claim 1, characterized in that When the circuit input signal terminal is at a high level, it includes: a first NMOS tube for cutting off the static current path of the first current mirror level shift subcircuit, and a fourth high-voltage NMOS tube for cutting off the static current path of the second current mirror level shift subcircuit.
9. The circuit according to claim 1, characterized in that When the level of the circuit input signal terminal changes from high to low, including: The second current mirror level shift subcircuit generates a second mirror current flowing through the fifth PMOS tube, and the second mirror current is used to suppress current competition among the fourth PMOS tube, the second high-voltage PMOS tube and the second high-voltage NMOS tube.
10. The circuit according to claim 1, characterized in that When the circuit input signal terminal is at a low level, it includes: The third high-voltage NMOS tube is used to cut off the static current path of the first current mirror level shift subcircuit; The fifth NMOS tube is used to cut off the static current path of the second current mirror level shift sub-circuit; The third PMOS tube in the cross-coupled level shift sub-circuit is fully turned on.
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