Calibration type high-precision multi-level PipelinedSAR ADC (Analog to Digital Converter) based on block LMS (Least Mean Square)

Abstract

The invention provides a block LMS (Least Mean Square)-based calibration type high-precision multi-stage PipelinedSAR ADC (Analog to Digital Converter). The block LMS-based calibration type high-precision multi-stage PipelinedSAR ADC comprises a first-stage ADC sub-circuit, a second-stage ADC sub-circuit and a third-stage ADC sub-circuit, wherein the first-stage ADC sub-circuit is used for sampling an input signal and The nth-stage ADC sub-circuit performs residual amplification and re-sampling on the voltage signal of the upper electrode plate of the capacitor after the last adjustment of the previous-stage sub-circuit is completed, and performs cyclic comparison adjustment for multiple times according to the sampled signal, so as to output a 9-bit comparison result digital code; and the dither injection calibration algorithm module calibrates all weights according to all comparison result digital codes to obtain correct weights, and then performs normal ADC sampling quantization to obtain digital codes with relatively high linearity. According to the method, the first five DACs are split to generate corresponding capacitor selection bits, the multiple requirement for a residual amplifier is relaxed through inter-stage capacitance scaling, the correct weight is obtained by processing the calibration weight twice, and the linearity can be improved.

Description

Technical Field

[0001] The invention belongs to the technical field of digital-analog hybrid circuit design, and in particular relates to a high-precision multi-stage Pipelined_SAR ADC based on block LMS calibration. Background Art

[0002] Pipelined_SAR ADC has attracted wide attention in recent years because it combines the advantages of Pipelined ADC and SAR ADC. It divides the process of quantizing data into several parallel stages, which can effectively balance the performance requirements of accuracy and speed. Each stage uses SAR ADC as a submodule, with a relatively simple structure and high linearity, and can be applied to medium-speed and medium-precision fields.

[0003] However, when the accuracy of the Pipelined_SAR ADC exceeds 12 bits, the capacitor mismatch limits the linearity of the Pipelined_SAR ADC. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a high-precision multi-stage Pipelined_SAR ADC based on block LMS calibration. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] A high-precision multi-stage Pipelined_SAR ADC based on block LMS calibration includes: an ADC subcircuit connected by N-stage pipelines and a dither injection calibration algorithm module;

[0006] Among them, the first-level ADC subcircuit samples the input signal, and performs multiple cycles of comparison and adjustment according to the sampled signal, thereby outputting a 10-bit comparison result digital code to the dither injection calibration algorithm module; the n-th-level ADC subcircuit performs residual amplification on the capacitor upper plate voltage signal after the last adjustment of the previous-level ADC subcircuit, and then samples the signal obtained after the residual amplification, and performs multiple cycles of comparison and adjustment according to the sampled signal, thereby outputting a 9-bit comparison result digital code to the dither injection calibration algorithm module; the dither injection calibration algorithm module calibrates all weights according to all comparison result digital codes to obtain the calibrated weights.

[0007] Beneficial effects:

[0008] The present invention provides a high-precision multi-stage Pipelined_SAR ADC based on block LMS calibration, including: the first-stage ADC subcircuit samples the input signal, and performs multiple cyclic comparison and adjustment according to the sampled signal, thereby outputting a 10-bit comparison result digital code to the dither injection calibration algorithm module; the n-stage ADC subcircuit performs residual amplification on the capacitor upper plate voltage signal after the last adjustment of the previous-stage ADC subcircuit, and then samples the signal obtained after the residual amplification, and performs multiple cyclic comparison and adjustment according to the sampled signal, thereby outputting a 9-bit comparison result digital code to the dither injection calibration algorithm module; the dither injection calibration algorithm module calibrates all weights according to all comparison result digital codes to obtain the calibrated weights. The present invention selects to split the first 5-bit DAC into 31 DEM unit capacitors, plus a pseudo-random number generator to generate corresponding capacitor selection bits. The inter-stage scaling capacitor relaxes the multiple requirements for the residual amplifier, from the original 256 times (first stage) and 128 times (second stage) to 32 times. The present invention processes the collected data twice in the calibration mode, the first time a dither disturbance component is introduced through a dither injection capacitor, and the second time no dither disturbance component is injected, and the difference between the two processing results is iteratively corrected under the block LMS calibration algorithm, and the correct weight can be obtained after millions of corrections. Normal ADC sampling and quantization are performed with the correct weight to obtain a digital code with relatively high linearity, so the present invention can improve the linearity of Pipelined_SAR ADC.

[0009] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a structural schematic diagram of a high-precision multi-stage Pipelined_SAR ADC based on block LMS calibration provided by the present invention. DETAILED DESCRIPTION

[0011] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0012] refer to Figure 1 , the present invention provides a high-precision multi-stage Pipelined_SAR ADC based on block LMS calibration, including: an ADC subcircuit connected by N-stage pipelines and a dither injection calibration algorithm module;

[0013] Among them, the first-level ADC subcircuit samples the input signal, and performs multiple cycles of comparison and adjustment according to the sampled signal, thereby outputting a 10-bit comparison result digital code to the dither injection calibration algorithm module; the n-th-level ADC subcircuit performs residual amplification on the capacitor upper plate voltage signal after the last adjustment of the previous-level ADC subcircuit, and then samples the signal obtained after the residual amplification, and performs multiple cycles of comparison and adjustment according to the sampled signal, thereby outputting a 9-bit comparison result digital code to the dither injection calibration algorithm module; the dither injection calibration algorithm module calibrates all weights according to all comparison result digital codes to obtain the calibrated weights.

[0014] refer to Figure 1 , Figure 1 It is a three-stage multi-stage Pipelined_SAR ADC. Figure 1 The ADC subcircuit is 10 bits, 9 bits, and 9 bits respectively, and the inter-level redundant bits between each level are 2 bits, so the actual number of bits of each level is 10 bits, 7 bits, and 7 bits respectively. In order to improve the precision of the first few bits and not to over-occupy hardware resources, the present invention selects to split the first 5 bits into 31 DEM unit capacitors, plus a pseudo-random number generator, to produce corresponding capacitor selection bits. The inter-level scaling capacitor relaxes the multiple requirements of the residual amplifier, from the original 256 times (first level) and 128 times (second level), to 32 times. In calibration mode, the collected data is processed twice, the dither disturbance component is introduced by the dither injection capacitor for the first time, and the dither disturbance component is not injected for the second time, and the difference of the two processing results is iteratively corrected under the block LMS calibration algorithm. After millions of corrections, the correct weight can be obtained, and then the correct result is obtained with the correct weight.

[0015] Continue to refer Figure 1 The first-level ADC subcircuit includes a random number generator, a DEM module, a first-level DAC module, a first-level comparator and a first-level SAR logic circuit; the output end of the random number generator is connected to the input of the DEM module, the output end of the DEM module is connected to the first end of the first-level DAC module, the second end of the first-level DAC module is connected to the Vip signal or the Vref signal, the inverting end of the first-level comparator is grounded, the output end is connected to the input end of the first-level SAR logic circuit and the input end of the second-level ADC subcircuit, the output end of the first-level SAR logic circuit is connected to the control end of the first-level DAC module, and is used to control the second end of the first-level DAC module to access the Vip signal or the Vref signal; the output end of the first-level SAR logic circuit is also connected to the input end of the dither injection calibration algorithm module.

[0016] The random number generator is used to generate pseudo-random numbers;

[0017] The DEM module is used to select a capacitor and a corresponding switching mode in the first-level DAC module according to the pseudo-random number;

[0018] The first-stage DAC module is used to sample the input signal to obtain a sampled signal according to the connection method of the capacitor in the sampling stage;

[0019] The first-stage comparator is used to compare the sampling signal with the ground signal and output a comparison result digital code;

[0020] A first-level logic circuit, used for generating control logic according to the comparison result digital code;

[0021] The first-stage DAC module is further used to switch its own capacitance in a corresponding switching manner according to the control logic in each cycle, and output a capacitor upper plate voltage signal after the switching is completed;

[0022] The first-stage comparator is also used to compare the capacitor upper plate voltage signal with the ground signal in each cycle and output a comparison signal to the first-stage logic circuit;

[0023] The first-level logic circuit is also used to output the digital codes of the 10 comparison results to the dither injection calibration algorithm module.

[0024] The first-level DAC module of the present invention comprises: a dynamic unit matching capacitor and a parallel capacitor group;

[0025] The dynamic unit matching capacitor includes 9 parallel capacitors with a capacitance value of 2 5 The upper plates of the 9 capacitors are the first ends of the first-stage DAC module, connected to the in-phase end of the first-stage comparator, and the upper plates are the second ends of the first-stage DAC module; the parallel capacitor group includes 6 parallel capacitors, the upper plates of the capacitors are connected to the upper plates of each capacitor of the dynamic unit matching capacitor, and the lower plates are connected to the lower plates of the dynamic unit matching capacitors. The capacitance of the second capacitor is 2 0 Starting capacitance, 2 1 Increase proportionally; the capacitance of the first capacitor is 2 0 .

[0026] like Figure 1 As shown, Figure 1The LFSR is a pseudo-random number generator for generating a serial number of a DEM capacitor; and the DEM module is a module using a dynamic unit matching (DEM) technology. As shown in the document (esper Steensgaard-Madsen, "Analog-to-digital converter system and method", United States Patent Number 8,810,443), when the present invention performs quantization of the first 5 bits, 16, 8, 4, 2, and 1 times of the DEM unit capacitor will be randomly selected in turn for quantization, so that the product of the first 5 bits of the digital code and the weight has a characteristic similar to that of white noise, and will be averaged and suppressed under a limited noise bandwidth.

[0027] Continue to refer Figure 1 The n-th level ADC subcircuit of the present invention comprises an n-th level residual amplifier, an n-th level scaling capacitor, an n-th level comparator, an n-th level DAC module and an n-th level SAR logic circuit; n ranges from 2 to N;

[0028] Among them, the in-phase end of the n-th stage residual amplifier is connected to the output end of the 1st stage ADC sub-circuit, and the inverting end is grounded; the output end of the n-th stage residual amplifier is connected to the upper plate of the n-th stage scaling capacitor, the first end of the n-th stage DAC module and the in-phase end of the n-th stage comparator; the lower plate of the n-th stage scaling capacitor and the second end of the n-th stage DAC module are connected to the Vcm signal or the Vref signal; the inverting end of the n-th stage comparator is grounded, the output end is connected to the input end of the n-th stage SAR logic circuit and the input end of the n+1-th stage ADC sub-circuit; the output end of the n-th stage SAR logic circuit is connected to the control end of the n-th stage DAC module, which is used to control the second end of the DAC module to access the Vcm signal or the Vref signal; the output end of the n-th stage SAR logic circuit is also connected to the input end of the dither injection calibration algorithm module.

[0029] The nth stage residual amplifier is used to amplify the voltage signal of the capacitor upper plate of the previous stage ADC subcircuit at the 10th time to obtain a residual amplified signal;

[0030] The n-th stage scaling capacitor is used to further amplify the n-th stage residual amplified signal to obtain an amplified signal;

[0031] The n-th stage DAC module is used to sample the n-th stage amplified signal according to the connection mode of the capacitors in the sampling stage to obtain the n-th stage sampling signal;

[0032] An n-th level comparator, used for comparing the n-th level sampling signal with a ground signal and outputting an n-th level comparison signal;

[0033] An n-th level logic circuit, used for generating an n-th level control logic according to the n-th level comparison signal;

[0034] The n-th level DAC module is further used to switch its own capacitance in a corresponding switching manner according to the control logic in each cycle, and output a capacitor upper plate voltage signal after the switching is completed;

[0035] The nth-stage comparator is further used to compare the capacitor upper plate voltage signal with the ground signal in each feedback and output a comparison signal to the nth-stage logic circuit;

[0036] The nth-stage logic circuit is also used to output the digital codes of the comparison results of the nth-stage ADC subcircuit for a total of 9 times to the dither injection calibration algorithm module.

[0037] The nth level DAC module comprises: 9 capacitors connected in parallel, wherein the capacitance of the first capacitor is 2 0 Starting capacitance, 2 1 Increase proportionally until the capacitance of the 9th capacitor is 2 8 ;

[0038] Among them, the upper plates of the 9 capacitors are the first end of the n-th level DAC module, connected to the non-inverting end of the n+1-th level comparator, and the lower plates are the second end of the n-th level DAC module.

[0039] Figure 1 The scaling capacitor in the paper is the same as that in the literature (Rao Chenguang, Xiao Rui, Sang Qinghua, et al. Design of high-performance margin amplifier for Piplined-SAR ADC based on g_(m) / I_(d) method [J]. Microelectronics, 2021, 51(3): 8). Figure 1 Catt_b = 7*Catt_a, Catt_d = 31*Catt_c. Figure 1 For example, the first and second levels in the figure need to be enlarged by 2 8 = 256 times, which is very difficult to achieve. The voltage is divided by capacitors Catt_a, Catt_b and the capacitor array of the second stage 512C0 (where C0 is a unit capacitor). Because 512C0>>Catt_a+Catt_b, we have:

[0040]

[0041] Among them, V ref is the reference voltage of level 1, V ref2 is the reference voltage of the second stage, that is, the reference voltage V ref2 is scaled down to the first level reference voltage V refThen the actual gain of the residual amplifier between the first stage and the second stage is 256 / 8=32.

[0042] Similarly, the voltage between the second and third levels is divided by Catt_c, Catt_d and the capacitor array of the third level 512C0, and the reference voltage V ref3 The compression is small to the first level reference voltage V ref 1 / 32 of the second level reference voltage V ref 1 / 4 of the 2nd and 3rd stages, the magnification between the 2nd and 3rd stages is 128 / 4=32.

[0043] Continue to refer Figure 1 The dither injection calibration algorithm module calibrates all weights according to all comparison result digital codes to obtain calibrated weights including:

[0044] Receive all comparison result digital codes output twice by the ADC subcircuit connected by the N-stage pipeline;

[0045] For all the comparison result digital codes of the two outputs, the same position is set to 0 or 1 according to whether the disturbance is added or not;

[0046] Calculate the difference between all comparison result digital codes with and without adding disturbance;

[0047] Calculating an error function using the difference and an initial weight of the introduced disturbance capacitor;

[0048] The weights are updated and calibrated multiple times using the error function to obtain updated weights.

[0049] Figure 1 The dither injection calibration algorithm module based on the block LMS algorithm is different from the literature (Hongxing Li, Mark Maddox, Michael CWColn, et al. A Signal-Independent Background-Calibrating 20b1MS / s SAR ADC with 0.3ppm INL. ISSCC, 2018) in that: when performing dither injection, the present invention is performed on the same circuit.

[0050] In the calibration mode, the present invention performs two quantizations for each data sampling. A small disturbance dither is injected into the input during the first quantization, while no dither is injected during the second quantization. The difference Δ between the two is a disturbance introduced in the analog domain. Ideally, if there is no capacitor mismatch in the circuit, then only the disturbance needs to be subtracted in the digital domain, and the result will not change. However, in actual situations, if there is a capacitor mismatch in the circuit, nonlinear errors will be introduced, and Δ contains information about this error.

[0051] Δ=D A -D B (2)

[0052] In the above formula, Δ represents the difference between the two quantization results, D A It represents the quantified result after the first injection of dither, D B It shows the result of the second quantification without dither injection.

[0053] e=Δ×W(3)

[0054] e represents the error function, which represents the degree of deviation between the current weight and the true value.

[0055] W (new) =W (old )-μ×Δ T ×e (4)

[0056] Formula (3) is an iterative formula that continuously updates the weights, where W (new) is the updated new weight, W (old) is the old weight before the update, μ is the step size coefficient that controls the iteration speed, Δ T is the transposed matrix of the matrix Δ.

[0057]

[0058] After multiple iterations of the block LMS algorithm, since the calculation amount of LMS is too large for one million times, in order to reduce the amount of calculation, the sum of the error function can be accumulated L times, and then the weight update can be performed again. By continuously adjusting the initial weight, the error is continuously reduced until it is close to the acceptable range, and finally the introduced disturbance dither is subtracted in the digital domain to obtain the weight that meets the accuracy requirements. The following example illustrates the specific process of performing multiple iterations and updating the weights by the block LMS algorithm of the present invention:

[0059] For example, the initial weight W0 = [w1, w2, w3 ... w 28 ] T , introduce the disturbance injection capacitor C_dither, insert it at position w9 and w 10Between, w_dither=w9, then W0'=[w1,w2,w3…w9,w_dither,w 10 …w 28 ] T For example, in standard mode, sample once quantized:

[0060] The quantitative data of C_dither introduced for the first time is:

[0061] D A =[10010101111101011110101100101];

[0062] The second quantitative data without introducing C_dither is:

[0063] D B =[01010101011101011110101100101];

[0064] The difference between the two is: Δ=D A -D B =[010000001000000000000000000000];

[0065] The error function is:

[0066] The error update method is expressed as: block_sum(new)=block_sum(old)+Δ T *e;

[0067] After the error block_sum is accumulated 32 times, that is, L = 32, the weight is updated once, and the update method is: W(new) = W(old)-u*block_sum, where u is the step coefficient that controls the iteration speed. A total of 2 calibrations are required. 20 times, among which, the first 2 14 times, u=2 -5 , the iteration speed is faster. 14 times, u=2 -9 , the iteration speed is slow because,2 20 ÷32=2 15 , 2 15 =2 14 +2 14 .

[0068] It is worth noting that the terms "first" and "second" in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0069] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components or steps.

[0070] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A high-precision multi-stage Pipelined_SAR ADC based on block LMS calibration, characterized in that: include: N-stage pipeline connected ADC sub-circuit and dither injection calibration algorithm module; Among them, the first-level ADC subcircuit samples the input signal, and performs multiple cycles of comparison and adjustment according to the sampled signal, thereby outputting a 10-bit comparison result digital code to the dither injection calibration algorithm module; the n-th-level ADC subcircuit performs residual amplification on the capacitor upper plate voltage signal after the last adjustment of the previous-level ADC subcircuit, and then samples the signal obtained after the residual amplification, and performs multiple cycles of comparison and adjustment according to the sampled signal, thereby outputting a 9-bit comparison result digital code to the dither injection calibration algorithm module; the dither injection calibration algorithm module calibrates all weights according to all comparison result digital codes to obtain the calibrated weights.

2. The high-precision multi-stage Pipelined_SAR ADC based on block LMS calibration according to claim 1, characterized in that: The first-level ADC subcircuit includes a random number generator, a DEM module, a first-level DAC module, a first-level comparator and a first-level SAR logic circuit; the output end of the random number generator is connected to the input of the DEM module, the output end of the DEM module is connected to the first end of the first-level DAC module, the second end of the first-level DAC module is connected to the Vip signal or the Vref signal, the inverting end of the first-level comparator is grounded, the output end is connected to the input end of the first-level SAR logic circuit and the input end of the second-level ADC subcircuit, the output end of the first-level SAR logic circuit is connected to the control end of the first-level DAC module, and is used to control the second end of the first-level DAC module to access the Vip signal or the Vref signal; the output end of the first-level SAR logic circuit is also connected to the input end of the dither injection calibration algorithm module.

3. The high-precision multi-stage Pipelined_SAR ADC based on block LMS calibration according to claim 2, characterized in that: The random number generator is used to generate pseudo-random numbers; The DEM module is used to select a capacitor and a corresponding switching mode in the first-level DAC module according to the pseudo-random number; The first-stage DAC module is used to sample the input signal to obtain a sampled signal according to the connection method of the capacitor in the sampling stage; The first-stage comparator is used to compare the sampling signal with the ground signal and output a comparison result digital code; A first-level logic circuit, used for generating control logic according to the comparison result digital code; The first-stage DAC module is further used to switch its own capacitance in a corresponding switching manner according to the control logic in each cycle, and output a capacitor upper plate voltage signal after the switching is completed; The first-stage comparator is also used to compare the capacitor upper plate voltage signal with the ground signal in each cycle and output a comparison signal to the first-stage logic circuit; The first-level logic circuit is also used to output the digital codes of the 10 comparison results to the dither injection calibration algorithm module.

4. The high-precision multi-stage Pipelined-SAR ADC based on block LMS calibration according to claim 3, characterized in that: The first-stage DAC module includes: a dynamic unit matching capacitor and a parallel capacitor group; The dynamic unit matching capacitor includes 9 parallel capacitors with a capacitance value of 2 5 The upper plates of the 9 capacitors are the first ends of the first-stage DAC module, connected to the in-phase end of the first-stage comparator, and the upper plates are the second ends of the first-stage DAC module; the parallel capacitor group includes 6 parallel capacitors, the upper plates of the capacitors are connected to the upper plates of each capacitor of the dynamic unit matching capacitor, and the lower plates are connected to the lower plates of the dynamic unit matching capacitors. The capacitance of the second capacitor is 2 0 Starting capacitance, 2 1 Increase proportionally; the capacitance of the first capacitor is 2 0 .

5. The high-precision multi-stage Pipelined_SAR ADC based on block LMS calibration according to claim 1, characterized in that: The n-th ADC subcircuit includes an n-th residual amplifier, an n-th scaling capacitor, an n-th comparator, an n-th DAC module and an n-th SAR logic circuit; n ranges from 2 to N; Among them, the in-phase end of the n-th stage residual amplifier is connected to the output end of the 1st stage ADC sub-circuit, and the inverting end is grounded; the output end of the n-th stage residual amplifier is connected to the upper plate of the n-th stage scaling capacitor, the first end of the n-th stage DAC module and the in-phase end of the n-th stage comparator; the lower plate of the n-th stage scaling capacitor and the second end of the n-th stage DAC module are connected to the Vcm signal or the Vref signal; the inverting end of the n-th stage comparator is grounded, the output end is connected to the input end of the n-th stage SAR logic circuit and the input end of the n+1-th stage ADC sub-circuit; the output end of the n-th stage SAR logic circuit is connected to the control end of the n-th stage DAC module, which is used to control the second end of the DAC module to access the Vcm signal or the Vref signal; the output end of the n-th stage SAR logic circuit is also connected to the input end of the dither injection calibration algorithm module.

6. The high-precision multi-stage Pipelined_SAR ADC based on block LMS calibration according to claim 5, characterized in that: The nth stage residual amplifier is used to amplify the voltage signal of the capacitor upper plate of the previous stage ADC subcircuit at the 10th time to obtain a residual amplified signal; The n-th stage scaling capacitor is used to further amplify the n-th stage residual amplified signal to obtain an amplified signal; The n-th stage DAC module is used to sample the n-th stage amplified signal according to the connection mode of the capacitors in the sampling stage to obtain the n-th stage sampling signal; An n-th level comparator, used for comparing the n-th level sampling signal with a ground signal and outputting an n-th level comparison signal; An n-th level logic circuit, used for generating an n-th level control logic according to the n-th level comparison signal; The n-th level DAC module is further used to switch its own capacitance in a corresponding switching manner according to the control logic in each cycle, and output a capacitor upper plate voltage signal after the switching is completed; The nth-stage comparator is further used to compare the capacitor upper plate voltage signal with the ground signal in each feedback and output a comparison signal to the nth-stage logic circuit; The nth-stage logic circuit is also used to output the digital codes of the comparison results of the nth-stage ADC subcircuit for a total of 9 times to the dither injection calibration algorithm module.

7. The high-precision multi-stage Pipelined-SAR ADC based on block LMS calibration according to claim 5, characterized in that: The nth level DAC module comprises: 9 capacitors connected in parallel, wherein the capacitance of the first capacitor is 2 0 Starting capacitance, 2 1 Increase proportionally until the capacitance of the 9th capacitor is 2 8 ; Among them, the upper plates of the 9 capacitors are the first end of the n-th level DAC module, connected to the non-inverting end of the n+1-th level comparator, and the lower plates are the second end of the n-th level DAC module.

8. The high-precision multi-stage Pipelined-SAR ADC based on block LMS calibration according to claim 1, characterized in that: The dither injection calibration algorithm module calibrates all weights according to all comparison result digital codes to obtain calibrated weights including: Receive all comparison result digital codes output twice by the ADC subcircuit connected by the N-stage pipeline; For all the comparison result digital codes of the two outputs, the same position is set to 0 or 1 according to whether the disturbance is added or not; Calculate the difference between all comparison result digital codes with and without adding disturbance; Calculating an error function using the difference and an initial weight of the introduced disturbance capacitor; The weights are updated and calibrated multiple times using the error function to obtain updated weights.

9. The high-precision multi-stage Pipelined_SAR ADC based on block LMS calibration according to claim 8, characterized in that: The weights are updated and calibrated multiple times using the error function to obtain updated weights, including: The error function and each weight are accumulated multiple times, and when a predetermined number of accumulations is reached, the weight is updated once using a step coefficient to obtain an updated weight.

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