Received signal extraction circuit and transmitter

Abstract

The invention provides a received signal extraction circuit and a transmitter. A coupling module couples a superposed signal on an accessed bidirectional transmission port into a corresponding first signal and couples an accessed local signal into a corresponding second signal, the superposed signal is obtained by superposing a transmitting signal and a receiving signal of the bidirectional transmission port, and the second signal is obtained by superposing a transmitting signal and a receiving signal of the bidirectional transmission port. The local signal is obtained by copying the transmitting signal; the input end of the subtraction module is connected with the output end of the coupling module, and subtraction operation is performed on the first signal and the second signal; the input end of the filtering module is connected with the output end of the subtraction module, and receiving signals on the two-way transmission port are extracted through filtering operation on output signals of the subtraction module. According to the received signal extraction circuit and the transmitter, the received signal can be accurately extracted from a bidirectional simultaneous transmission interface without distortion, analysis operation on the quality of data communication and improvement operation on a data communication system are facilitated, and the circuit and the transmitter have wide applicability.

Description

Technical Field

[0001] The present invention relates to the technical field of data communication, and in particular to a received signal extraction circuit and a transmitter. Background Art

[0002] In a unidirectional transmission link, the interfaces at both ends of the transmission line are unidirectional transmission interfaces. If one of them is used as a transmitting interface, the other can only be used as a receiving interface. Therefore, it is difficult to achieve that one interface can simultaneously transmit and receive data. The biggest advantage of a bidirectional simultaneous transmission interface over a unidirectional transmission interface is that it realizes bidirectional simultaneous transmission of data, expands the data bandwidth of the interface, thereby reducing the number of interfaces of the device (if the device is a chip, the interface is represented by the pins of the chip), and further reduces the wiring of the PCB (Printed Circuit Board). However, the bidirectional simultaneous transmission interface superimposes signals in two directions, including: the signal transmitted by itself and the received signal (the signal sent to the bidirectional simultaneous transmission interface by other devices). Therefore, how to accurately and distortion-free extract the received signal is a technical problem that needs to be solved in the bidirectional simultaneous transmission interface.

[0003] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a received signal extraction circuit and a transmitter for solving the problem in the prior art that it is difficult to accurately and distortion-free extract a received signal from a bidirectional simultaneous transmission interface.

[0005] To achieve the above-mentioned object and other related objects, the present invention provides a received signal extraction circuit, which comprises at least: a coupling module, a subtraction module and a filtering module, wherein:

[0006] The coupling module couples the superimposed signal on the connected bidirectional transmission port into a corresponding first signal, and couples the connected local signal into a corresponding second signal, wherein the superimposed signal is obtained by superimposing the transmission signal and the reception signal of the bidirectional transmission port, and the local signal is obtained by duplicating the transmission signal;

[0007] The input end of the subtraction module is connected to the output end of the coupling module, and performs a subtraction operation on the first signal and the second signal;

[0008] The input end of the filtering module is connected to the output end of the subtraction module, and the receiving signal on the bidirectional transmission port is extracted by filtering the output signal of the subtraction module.

[0009] Optionally, the superimposed signal and the local signal both include differential signals and single-ended signals, wherein, when the superimposed signal and the local signal are both differential signals, the first signal and the second signal are both differential signals; when the superimposed signal and the local signal are both single-ended signals, the first signal and the second signal are both single-ended signals.

[0010] Optionally, the coupling module includes a first coupling unit and a second coupling unit, wherein the input end of the first coupling unit is connected to the superimposed signal, and the first signal is generated through the output end of the first coupling unit; the input end of the second coupling unit is connected to the local signal, and the second signal is generated through the output end of the second coupling unit.

[0011] Optionally, when the superimposed signal and the local signal are both differential signals, the first coupling unit includes: a first resistor, a second resistor, a first capacitor and a second capacitor, wherein: the first end of the first capacitor is connected to the first signal in the superimposed signal; the first end of the first resistor is connected to the second end of the first capacitor, and the second end of the first resistor is connected to the bias signal; the first end of the second capacitor is connected to the second signal in the superimposed signal; the first end of the second resistor is connected to the second end of the second capacitor, and the second end of the second resistor is connected to the bias signal.

[0012] Optionally, when the superimposed signal and the local signal are both differential signals, the second coupling unit includes: a third resistor, a fourth resistor, a third capacitor and a fourth capacitor, wherein: the first end of the third capacitor is connected to the first signal in the local signal; the first end of the third resistor is connected to the second end of the third capacitor, and the second end of the third resistor is connected to the bias signal; the first end of the fourth capacitor is connected to the second signal in the local signal; the first end of the fourth resistor is connected to the second end of the fourth capacitor, and the second end of the fourth resistor is connected to the bias signal.

[0013] Optionally, when the superimposed signal and the local signal are both single-ended signals, the first coupling unit includes a fifth resistor and a fifth capacitor, wherein the first end of the fifth capacitor is connected to the superimposed signal; the first end of the fifth resistor is connected to the second end of the fifth capacitor, and the second end of the fifth resistor is connected to the bias signal.

[0014] Optionally, when the superimposed signal and the local signal are both single-ended signals, the second coupling unit includes a sixth resistor and a sixth capacitor, wherein the first end of the sixth capacitor is connected to the local signal; the first end of the sixth resistor is connected to the second end of the sixth capacitor, and the second end of the sixth resistor is connected to the bias signal.

[0015] Optionally, when the superimposed signal and the local signal are both differential signals, the subtraction module includes: a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first current source, a second current source, a third current source, a fourth current source, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a seventh capacitor and an eighth capacitor, wherein: the gate of the first NMOS tube is connected to the first signal in the second signal; the seventh capacitor is connected between the drain of the first NMOS tube and the reference ground; the seventh resistor is connected between the drain of the first NMOS tube and the operating voltage; the first current source is connected between the source of the first NMOS tube and the reference ground; the gate of the third NMOS tube is connected to the second signal in the first signal, and the drain of the third NMOS tube is connected to the drain of the first NMOS tube; Three current sources are connected between the source of the third NMOS tube and the reference ground; the gate of the second NMOS tube is connected to the first signal in the first signal; the eighth capacitor is connected between the drain of the second NMOS tube and the reference ground; the eighth resistor is connected between the drain of the second NMOS tube and the working voltage; the ninth resistor is connected between the source of the first NMOS tube and the source of the second NMOS tube; the second current source is connected between the source of the second NMOS tube and the reference ground; the gate of the fourth NMOS tube is connected to the second signal in the second signal, and the drain of the fourth NMOS tube is connected to the drain of the second NMOS tube; the fourth current source is connected between the source of the fourth NMOS tube and the reference ground; the tenth resistor is connected between the source of the third NMOS tube and the source of the fourth NMOS tube.

[0016] Optionally, when the superimposed signal and the local signal are both single-ended signals, the subtraction module includes: a fifth NMOS tube, a sixth NMOS tube, a fifth current source, a sixth current source, a ninth capacitor, a tenth capacitor, an eleventh resistor, a twelfth resistor and a thirteenth resistor, wherein: the gate of the fifth NMOS tube is connected to the first signal; the ninth capacitor is connected between the drain of the fifth NMOS tube and the reference ground; the eleventh resistor is connected between the drain of the fifth NMOS tube and the working voltage; the fifth current source is connected between the source of the fifth NMOS tube and the reference ground; the gate of the sixth NMOS tube is connected to the second signal; the tenth capacitor is connected between the drain of the sixth NMOS tube and the reference ground; the twelfth resistor is connected between the drain of the sixth NMOS tube and the working voltage; the sixth current source is connected between the source of the sixth NMOS tube and the reference ground; the thirteenth resistor is connected between the source of the fifth NMOS tube and the source of the sixth NMOS tube.

[0017] Optionally, when the superimposed signal and the local signal are both differential signals, the subtraction module further includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a seventh current source, an eighth current source, a ninth current source, a tenth current source, an eleventh capacitor, a twelfth capacitor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor and a seventeenth resistor, wherein: the gate of the first PMOS tube is connected to the first signal in the second signal; the seventh current source is connected between the source of the first PMOS tube and the operating voltage; the eleventh capacitor is connected between the drain of the first PMOS tube and the reference ground; the sixteenth resistor is connected between the drain of the first PMOS tube and the reference ground; the gate of the third PMOS tube is connected to the second signal in the first signal, and the drain of the third PMOS tube is connected to the reference ground. The gate of the second PMOS tube is connected to the drain of the first PMOS tube; the ninth current source is connected between the source of the third PMOS tube and the operating voltage; the gate of the second PMOS tube is connected to the first signal in the first signal; the eighth current source is connected between the source of the second PMOS tube and the operating voltage; the twelfth capacitor is connected between the drain of the second PMOS tube and the reference ground; the fourteenth resistor is connected between the source of the first PMOS tube and the source of the second PMOS tube; the gate of the fourth PMOS tube is connected to the second signal in the second signal, and the drain of the fourth PMOS tube is connected to the drain of the second PMOS tube; the tenth current source is connected between the source of the fourth PMOS tube and the operating voltage; the seventeenth resistor is connected between the source of the fourth PMOS tube and the reference ground.

[0018] Optionally, when the superimposed signal and the local signal are both single-ended signals, the subtraction module further includes: a fifth PMOS tube, a sixth PMOS tube, an eleventh current source, a twelfth current source, a thirteenth capacitor, a fourteenth capacitor, an eighteenth resistor, a nineteenth resistor and a twentieth resistor, wherein: the gate of the fifth PMOS tube is connected to the first signal; the eleventh current source is connected between the source of the fifth PMOS tube and the working voltage; the thirteenth capacitor is connected between the drain of the fifth PMOS tube and the reference ground; the nineteenth resistor is connected between the drain of the fifth PMOS tube and the reference ground; the gate of the sixth PMOS tube is connected to the second signal; the twelfth current source is connected between the source of the sixth PMOS tube and the working voltage; the fourteenth capacitor is connected between the drain of the sixth PMOS tube and the reference ground; the twentieth resistor is connected between the drain of the sixth PMOS tube and the reference ground; the eighteenth resistor is connected between the source of the fifth PMOS tube and the source of the sixth PMOS tube.

[0019] Optionally, the filtering module includes an active filtering circuit and a passive filtering circuit.

[0020] Optionally, when the filter module is an active filter circuit, the filter module includes a primary active filter circuit, a secondary active filter circuit and a tertiary active filter circuit.

[0021] Optionally, when the filtering module is a first-level active filtering circuit, the filtering module includes: a seventh NMOS tube, an eighth NMOS tube, a thirteenth current source, a fifteenth capacitor, a sixteenth capacitor, a twenty-first resistor and a twenty-second resistor, wherein: the gate of the seventh NMOS tube is connected to the first signal in the output signal of the subtraction module; the fifteenth capacitor is connected between the drain of the seventh NMOS tube and the reference ground; the twenty-first resistor is connected between the drain of the seventh NMOS tube and the working voltage; the thirteenth current source is connected between the source of the seventh NMOS tube and the reference ground; the gate of the eighth NMOS tube is connected to the second signal in the output signal of the subtraction module, the source of the eighth NMOS tube is connected to the source of the seventh NMOS tube; the sixteenth capacitor is connected between the drain of the eighth NMOS tube and the reference ground; the twenty-second resistor is connected between the drain of the eighth NMOS tube and the working voltage; wherein the received signal on the bidirectional transmission port is extracted through the drain of the seventh NMOS tube and the drain of the eighth NMOS tube.

[0022] Optionally, when the filtering module is a first-level active filtering circuit, the filtering module further includes: a seventh PMOS tube, an eighth PMOS tube, a fourteenth current source, a seventeenth capacitor, an eighteenth capacitor, a twenty-third resistor and a twenty-fourth resistor, wherein: the gate of the seventh PMOS tube is connected to the first signal in the output signal of the subtraction module; the fourteenth current source is connected between the source of the seventh PMOS tube and the working voltage; the seventeenth capacitor is connected between the drain of the seventh PMOS tube and the reference ground; the twenty-third resistor is connected between the drain of the seventh PMOS tube and the reference ground; the gate of the eighth PMOS tube is connected to the second signal in the output signal of the subtraction module, the source of the eighth PMOS tube is connected to the source of the seventh PMOS tube; the eighteenth capacitor is connected between the drain of the eighth PMOS tube and the reference ground; the twenty-fourth resistor is connected between the drain of the eighth PMOS tube and the reference ground; wherein the received signal on the bidirectional transmission port is extracted through the drain of the seventh PMOS tube and the drain of the eighth PMOS tube.

[0023] Optionally, when the filtering module is a secondary active filtering circuit, the filtering module includes: a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a fifteenth current source, a sixteenth current source, a nineteenth capacitor, a twentieth capacitor, a twenty-first capacitor, a twenty-second capacitor, a twenty-fifth resistor, a twenty-sixth resistor, a twenty-seventh resistor and a twenty-eighth resistor, wherein: the gate of the eleventh NMOS tube is connected to the first signal in the output signal of the subtraction module; the twenty-first capacitor is connected between the drain of the eleventh NMOS tube and the reference ground; the twenty-seventh resistor is connected between the drain of the eleventh NMOS tube and the working voltage; the sixteenth current source is connected between the source of the eleventh NMOS tube and the reference ground; the gate of the twelfth NMOS tube is connected to the second signal in the output signal of the subtraction module, the source of the twelfth NMOS tube is connected to the source of the eleventh NMOS tube; the twenty-second capacitor is connected The 28th resistor is connected between the drain of the 12th NMOS tube and the working voltage; the gate of the 9th NMOS tube is connected to the drain of the 11th NMOS tube; the 19th capacitor is connected between the drain of the 9th NMOS tube and the reference ground; the 25th resistor is connected between the drain of the 9th NMOS tube and the working voltage; the 15th current source is connected between the source of the 9th NMOS tube and the reference ground; the gate of the 10th NMOS tube is connected to the drain of the 12th NMOS tube, and the source of the 10th NMOS tube is connected to the source of the 9th NMOS tube; the 20th capacitor is connected between the drain of the 10th NMOS tube and the reference ground; the 26th resistor is connected between the drain of the 10th NMOS tube and the working voltage; wherein the receiving signal on the bidirectional transmission port is extracted through the drain of the 9th MOS tube and the drain of the 10th MOS tube.

[0024] Optionally, when the filtering module is a secondary active filtering circuit, the filtering module further includes: a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a seventeenth current source, an eighteenth current source, a twenty-third capacitor, a twenty-fourth capacitor, a twenty-fifth capacitor, a twenty-sixth capacitor, a twenty-ninth resistor, a thirtieth resistor, a thirty-first resistor and a thirty-second resistor, wherein: the gate of the ninth PMOS tube is connected to the first signal in the output signal of the subtraction module; the seventeenth current source is connected between the source of the ninth PMOS tube and the operating voltage; the twenty-third capacitor is connected between the drain of the ninth PMOS tube and the reference ground; the twenty-ninth resistor is connected between the drain of the ninth PMOS tube and the reference ground; the gate of the tenth PMOS tube is connected to the second signal in the output signal of the subtraction module, the source of the tenth PMOS tube is connected to the source of the ninth PMOS tube; the twenty-fourth capacitor is connected to the tenth The 30th resistor is connected between the drain of the 10th PMOS tube and the reference ground; the gate of the 11th PMOS tube is connected to the drain of the 9th PMOS tube; the 18th current source is connected between the source of the 11th PMOS tube and the working voltage; the 25th capacitor is connected between the drain of the 11th PMOS tube and the reference ground; the 31st resistor is connected between the drain of the 11th PMOS tube and the reference ground; the gate of the 12th PMOS tube is connected to the drain of the 10th PMOS tube, and the source of the 12th PMOS tube is connected to the source of the 11th PMOS tube; the 26th capacitor is connected between the drain of the 12th PMOS tube and the reference ground; the 32nd resistor is connected between the drain of the 12th PMOS tube and the reference ground; wherein the receiving signal on the bidirectional transmission port is extracted through the drain of the 11th PMOS tube and the drain of the 12th PMOS tube.

[0025] Optionally, when the filtering module is a three-stage active filtering circuit, the filtering module includes: a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a nineteenth current source, a twentieth current source, a twenty-first current source, a twenty-seventh capacitor, a twenty-eighth capacitor, a twenty-ninth capacitor, a thirtieth capacitor, a thirty-first capacitor, a thirty-second capacitor, a thirty-third resistor, a thirty-fourth resistor, a thirty-fifth resistor, a thirty-sixth resistor, a thirty-seventh resistor and a thirty-eighth resistor, wherein: the gate of the seventeenth NMOS tube is connected to the first signal in the output signal of the subtraction module; the thirty-first capacitor is connected to the gate of the seventeenth NMOS tube between the drain of the 17th NMOS tube and the reference ground; the 37th resistor is connected between the drain of the 17th NMOS tube and the working voltage; the 21st current source is connected between the source of the 17th NMOS tube and the reference ground; the gate of the 18th NMOS tube is connected to the second signal in the output signal of the subtraction module, and the source of the 18th NMOS tube is connected to the source of the 17th NMOS tube; the 32nd capacitor is connected between the drain of the 18th NMOS tube and the reference ground; the 38th resistor is connected between the drain of the 18th NMOS tube and the working voltage; the gate of the 15th NMOS tube is connected to the drain of the 17th NMOS tube; the 29th capacitor is connected to the 15th NMOS tube; The 35th resistor is connected between the drain of the 15th NMOS tube and the working voltage; the 20th current source is connected between the source of the 15th NMOS tube and the reference ground; the gate of the 16th NMOS tube is connected to the drain of the 18th NMOS tube, and the source of the 16th NMOS tube is connected to the source of the 15th NMOS tube; the 30th capacitor is connected between the drain of the 16th NMOS tube and the reference ground; the 36th resistor is connected between the drain of the 16th NMOS tube and the working voltage; the gate of the 13th NMOS tube is connected to the drain of the 15th NMOS tube; the 19th current source is connected to the 13th NMOS tube; The twenty-seventh capacitor is connected between the drain of the thirteenth NMOS tube and the reference ground; the thirty-third resistor is connected between the drain of the thirteenth NMOS tube and the operating voltage; the gate of the fourteenth NMOS tube is connected to the drain of the sixteenth NMOS tube, and the source of the fourteenth NMOS tube is connected to the source of the thirteenth NMOS tube; the twenty-eighth capacitor is connected between the drain of the fourteenth NMOS tube and the reference ground; the thirty-fourth resistor is connected between the drain of the fourteenth NMOS tube and the operating voltage; wherein the receiving signal on the bidirectional transmission port is extracted through the drain of the thirteenth NMOS tube and the drain of the fourteenth NMOS tube.

[0026] Optionally, when the filtering module is a three-stage active filtering circuit, the filtering module further includes: a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a twenty-second current source, a twenty-third current source, a twenty-fourth current source, a thirty-third capacitor, a thirty-fourth capacitor, a thirty-fifth capacitor, a thirty-sixth capacitor, a thirty-seventh capacitor, a thirty-eighth capacitor, a thirty-ninth resistor, a fortieth resistor, a forty-first resistor, a forty-second resistor, a forty-third resistor and a forty-fourth resistor, wherein: the gate of the thirteenth PMOS tube is connected to the first signal in the output signal of the subtraction module; the twenty-second current source is connected to the thirteenth PMOS tube; The 33rd capacitor is connected between the drain of the 13th PMOS tube and the reference ground; the 39th resistor is connected between the drain of the 13th PMOS tube and the reference ground; the gate of the 14th PMOS tube is connected to the second signal in the output signal of the subtraction module, and the source of the 14th PMOS tube is connected to the source of the 13th PMOS tube; the 34th capacitor is connected between the drain of the 14th PMOS tube and the reference ground; the 40th resistor is connected between the drain of the 14th PMOS tube and the reference ground; the gate of the 15th PMOS tube is connected to the drain of the 13th PMOS tube; the 23rd current source is connected to the 24th PMOS tube; the 25th PMOS tube is connected to the drain of the 15th PMOS tube; the 26th PMOS tube is connected to the drain of the 15th PMOS tube; the 27th PMOS tube is connected to the drain of the 15th PMOS tube; the 28th PMOS tube is connected to the drain of the 15th PMOS tube; the 29th PMOS tube is connected to the drain of the 16th PMOS tube; the 30th PMOS tube is connected to the drain of the 16th PMOS tube; the 31st PMOS tube is connected to the drain of the 16th PMOS tube; the 32nd PMOS tube is connected to the drain of the 16th PMOS tube; the 33rd PMOS tube is connected to the drain of the 16th PMOS tube; the 34th PMOS tube is connected to the drain of the 16th PMOS tube; the 35th PMOS tube is connected to the drain of the 16th PMOS tube; the 36th PMOS tube is connected to the drain of the 16th PMOS tube; the 37th PMOS tube is connected to the drain of the 16th PMOS tube; the 38th PMOS tube is connected to the drain The thirty-fifth capacitor is connected between the drain of the fifteenth PMOS tube and the reference ground; the forty-first resistor is connected between the drain of the fifteenth PMOS tube and the reference ground; the gate of the sixteenth PMOS tube is connected to the drain of the fourteenth PMOS tube, and the source of the sixteenth PMOS tube is connected to the source of the fifteenth PMOS tube; the thirty-sixth capacitor is connected between the drain of the sixteenth PMOS tube and the reference ground; the forty-second resistor is connected between the drain of the sixteenth PMOS tube and the reference ground; the gate of the seventeenth PMOS tube is connected to the drain of the fifteenth PMOS tube; the twenty-fourth current source is connected to the seventeenth PMOS tube; The thirty-seventh capacitor is connected between the drain of the seventeenth PMOS tube and the reference ground; the forty-third resistor is connected between the drain of the seventeenth PMOS tube and the reference ground; the gate of the eighteenth PMOS tube is connected to the drain of the sixteenth PMOS tube, and the source of the eighteenth PMOS tube is connected to the source of the seventeenth PMOS tube; the thirty-eighth capacitor is connected between the drain of the eighteenth PMOS tube and the reference ground; the forty-fourth resistor is connected between the drain of the eighteenth PMOS tube and the reference ground; wherein the receiving signal on the bidirectional transmission port is extracted through the drain of the seventeenth PMOS tube and the drain of the eighteenth PMOS tube.

[0027] Optionally, when the filtering module is a passive filtering circuit, the filtering module further includes: a thirty-ninth capacitor, a forty-first capacitor, a forty-second capacitor, a forty-third capacitor, a forty-fourth capacitor, a forty-fifth resistor, a forty-sixth resistor, a forty-seventh resistor, a forty-eighth resistor, a forty-ninth resistor and a fiftieth resistor, wherein: the first end of the forty-fifth resistor is connected to the first signal in the output signal of the subtraction module; the thirty-ninth capacitor is connected between the second end of the forty-fifth resistor and the reference ground; the first end of the forty-sixth resistor is connected to the second end of the forty-fifth resistor; the forty-third capacitor is connected between the second end of the forty-sixth resistor and the reference ground; the first end of the forty-seventh resistor is connected to the first end of the forty-sixth resistor The two ends are connected; the forty-first capacitor is connected between the second end of the forty-seventh resistor and the reference ground; the first end of the forty-eighth resistor is connected to the second signal in the output signal of the subtraction module; the forty-second capacitor is connected between the second end of the forty-eighth resistor and the reference ground; the first end of the forty-ninth resistor is connected to the second end of the forty-eighth resistor; the forty-third capacitor is connected between the second end of the forty-ninth resistor and the reference ground; the first end of the fiftieth resistor is connected to the second end of the forty-ninth resistor; the forty-fourth capacitor is connected between the second end of the fiftieth resistor and the reference ground; wherein the received signal on the bidirectional transmission port is extracted through the second end of the forty-seventh resistor and the second end of the fiftieth resistor.

[0028] To achieve the above objective and other related objectives, the present invention provides a transmitter, which includes the received signal extraction circuit.

[0029] As described above, a received signal extraction circuit and a transmitter of the present invention have the following beneficial effects:

[0030] The received signal extraction circuit and transmitter of the present invention can extract the received signal from the bidirectional simultaneous transmission interface accurately and without distortion, and is convenient for analyzing the quality of data communication and improving the data communication system, and has wide applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a first schematic diagram of the received signal extraction circuit of the present invention.

[0032] Figure 2 It is a second schematic diagram of the received signal extraction circuit of the present invention.

[0033] Figure 3 Shown is a first schematic diagram of a coupling module of the present invention.

[0034] Figure 4 A second schematic diagram of a coupling module according to the present invention is shown.

[0035] Figure 5 Shown is a first schematic diagram of a subtraction module of the present invention.

[0036] Figure 6 Shown is a second schematic diagram of a subtraction module of the present invention.

[0037] Figure 7 Shown is a third schematic diagram of a subtraction module of the present invention.

[0038] Figure 8 A fourth schematic diagram of a subtraction module of the present invention is shown.

[0039] Fig. 9 It is a first schematic diagram of the filter module of the present invention.

[0040] Fig.10 It is a second schematic diagram of the filter module of the present invention.

[0041] Fig.11 It is a third schematic diagram of the filter module of the present invention.

[0042] Fig.12 It is a fourth schematic diagram of the filter module of the present invention.

[0043] Fig.13 It is a fifth schematic diagram of the filter module of the present invention.

[0044] Fig.14 It is a sixth schematic diagram of the filter module of the present invention.

[0045] Fig.15 It is a seventh schematic diagram of the filter module of the present invention.

[0046] Fig.16 A schematic diagram showing the status of superimposed signals in a bidirectional transmission port.

[0047] Fig.17 Shown is a schematic diagram of the received signal extracted from the superimposed signal.

[0048] Description of Reference Numerals

[0049] 1 Received signal extraction circuit

[0050] 11 Coupling module

[0051] 111 First coupling unit

[0052] 112 Second coupling unit

[0053] 12 Subtraction module

[0054] 13 Filter module DETAILED DESCRIPTION

[0055] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0056] See also Figures 1 to 17 It should be noted that the illustrations provided in this embodiment are only schematic illustrations of the basic concept of the present invention. The illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0057] like Figure 1 and Figure 2 As shown, this embodiment provides a received signal extraction circuit 1. It should be noted that: Figure 1 The first situation of the received signal extraction circuit is shown, wherein the signal connected to the input end of the received signal extraction circuit is a differential signal; Figure 2 The second situation of the received signal extraction circuit is shown, wherein the signal connected to the input end of the received signal extraction circuit is a single-ended signal; the received signal extraction circuit 1 comprises: a coupling module 11, a subtraction module 12 and a filtering module 13, wherein:

[0058] like Figure 1 and Figure 2 As shown, the coupling module 11 couples the superimposed signal on the connected bidirectional transmission port into a corresponding first signal, and couples the connected local signal into a corresponding second signal, wherein the superimposed signal is obtained by superimposing the transmitting signal and the receiving signal of the bidirectional transmission port, wherein the transmitting signal is output by the bidirectional transmission port itself, and the receiving signal is a signal transmitted to the bidirectional transmission port by other devices; the local signal is obtained by copying the transmitting signal.

[0059] It should be noted that the superimposed signal and the local signal both include differential signals and single-ended signals, wherein when the superimposed signal and the local signal are both differential signals, the first signal and the second signal are both differential signals; when the superimposed signal and the local signal are both single-ended signals, the first signal and the second signal are both single-ended signals. Coupling refers to the transfer of energy from one circuit to another circuit. Coupling is very common in analog circuits and digital circuits. Weak signals can be coupled to the amplifier circuit for amplification, and the amplified signal can also be output through coupling. Therefore, coupling is the connecting bridge between the two functional circuits, which can realize the transmission of signals and energy. Under normal circumstances, the collected signal will not be an ideal waveform. For example, when collecting AC signals, DC components may be mixed in, and when collecting DC signals, AC components may also be mixed in. If you want to filter out the DC part of the signal, you need to use AC coupling. AC coupling refers to adding a capacitor between the signal and the collection point. Since the capacitor has the characteristics of passing AC and blocking DC, the DC component will be easily filtered out. Therefore, AC coupling is also called capacitive coupling. If you want to filter out the AC component in the signal, you can use a filter to achieve it. For example, a low-pass filter can effectively filter out a considerable portion of the AC component. Therefore, the corresponding coupling method should be selected according to specific needs.

[0060] Specifically, as an example, Figure 3 and Figure 4 As shown, the coupling module 11 includes a first coupling unit 111 and a second coupling unit 112, wherein the input end of the first coupling unit 111 is connected to the superimposed signal, and the first signal is generated through the output end of the first coupling unit 111; the input end of the second coupling unit 112 is connected to the local signal, and the second signal is generated through the output end of the second coupling unit 112. Figure 3 The configuration of the coupling module 11 is shown when both the superimposed signal and the local signal are differential signals. The superimposed signal connected to the first coupling unit 111 includes two paths, namely, signal TP and signal TN; the first signal output by the first coupling unit 111 is a differential signal and includes two paths, namely, signal AC_TP and signal AC_TN. The local signal connected to the second coupling unit 112 includes two paths, namely, signal TPR and signal TNR; the second signal output by the second coupling unit 112 is a differential signal and includes two paths, namely, signal AC_TPR and signal AC_TNR.

[0061] Figure 4 The configuration of the coupling module 11 is shown when both the superimposed signal and the local signal are single-ended signals. The superimposed signal connected to the first coupling unit 111 is a single-ended signal (not in Figure 4 ), the first signal output by the first coupling unit 111 is a single-ended signal (not marked in Figure 4The local signal received by the second coupling unit 112 is a single-ended signal (not in Figure 4 ), the second signal output by the second coupling unit 112 is a single-ended signal (not marked in Figure 4 ).

[0062] More specifically, if Figure 3 As shown, when the superimposed signal and the local signal are both differential signals, the first coupling unit 111 includes: a first resistor R1, a second resistor R2, a first capacitor C1 and a second capacitor C2, wherein: the first end of the first capacitor C1 is connected to the first signal in the superimposed signal, that is, the signal TP; the first end of the first resistor R1 is connected to the second end of the first capacitor C1, the second end of the first resistor R1 is connected to the bias signal V_BIAS, and the signal AC_TP is output through the second end of the first capacitor C1; the first end of the second capacitor C2 is connected to the second signal in the superimposed signal, that is, the signal TN; the first end of the second resistor R2 is connected to the second end of the second capacitor C2, the second end of the second resistor R2 is connected to the bias signal V_BIAS, and the signal AC_TN is output through the second end of the second capacitor C2. The second coupling unit 112 includes: a third resistor R3, a fourth resistor R4, a third capacitor C3 and a fourth capacitor C4, wherein: a first end of the third capacitor C3 is connected to a first signal in the local signal, i.e., a signal TPR; a first end of the third resistor R3 is connected to a second end of the third capacitor C3, a second end of the third resistor R3 is connected to a bias signal V_BIAS, and a signal AC_TPR is output through a second end of the third capacitor C3; a first end of the fourth capacitor C4 is connected to a second signal in the local signal, i.e., a signal TNR; a first end of the fourth resistor R4 is connected to a second end of the fourth capacitor C4, a second end of the fourth resistor R4 is connected to a bias signal V_BIAS, and a signal AC_TNR is output through a second end of the fourth capacitor C4.

[0063] More specifically, if Figure 4 As shown, when the superimposed signal and the local signal are both single-ended signals, the first coupling unit 111 includes a fifth resistor R5 and a fifth capacitor C5, wherein the first end of the fifth capacitor C5 is connected to the superimposed signal (not in Figure 4 The first end of the fifth resistor R5 is connected to the second end of the fifth capacitor C5, the second end of the fifth resistor R5 is connected to the bias signal V_BIAS, and the first signal is output through the second end of the fifth capacitor C5 (not in Figure 4 The second coupling unit 112 includes a sixth resistor R6 and a sixth capacitor C6, wherein the first end of the sixth capacitor C6 is connected to the local signal (not in Figure 4The first end of the sixth resistor R6 is connected to the second end of the sixth capacitor C6, the second end of the sixth resistor R6 is connected to the bias signal V_BIAS, and the second signal is output through the second end of the sixth capacitor C6 (not in Figure 4 ).

[0064] It should be noted that the common-mode level of the superimposed signal on the bidirectional transmission port is affected by the output transmission signal of the superimposed signal and the received signal transmitted by other devices, so the common-mode level of the superimposed signal is not a fixed value, and it is difficult to determine the common-mode value of the local signal obtained by replicating the transmission signal, so it is necessary to make the first signal and the second signal have the same common-mode value through the coupling module 11. It should be further noted that the coupling module 11 can also be set by using an AC-coupled common-phase amplifier circuit so that the first signal and the second signal have the same common-mode value, and the specific settings of the AC-coupled common-phase amplifier circuit will not be repeated here.

[0065] like Figure 1 and Figure 2 As shown, the input end of the subtraction module 12 is connected to the output end of the coupling module 11, and a subtraction operation is performed on the first signal and the second signal.

[0066] Specifically, as an example, Figure 5As shown, when the superimposed signal and the local signal are both differential signals, the subtraction module 12 includes: a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a first current source I1, a second current source I2, a third current source I3, a fourth current source I4, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a seventh capacitor C7 and an eighth capacitor C8, wherein: the gate of the first NMOS tube N1 is connected to the first signal in the second signal, that is, the signal AC_TPR; the seventh capacitor C7 is connected between the drain of the first NMOS tube N1 and the reference ground; the seventh resistor R7 is connected between the drain of the first NMOS tube N1 and the working voltage VDD; the first current source I1 is connected between the source of the first NMOS tube N1 and the reference ground; the gate of the third NMOS tube N3 is connected to the second signal in the first signal, that is, the signal AC_TN; the drain of the third NMOS tube N3 is connected to the first NMOS tube N1. The drain of the first NMOS tube N1 is connected; the third current source I3 is connected between the source of the third NMOS tube N3 and the reference ground; the gate of the second NMOS tube N2 is connected to the first signal in the first signal, that is, the signal AC_TP; the eighth capacitor C8 is connected between the drain of the second NMOS tube N2 and the reference ground; the eighth resistor R8 is connected between the drain of the second NMOS tube N2 and the working voltage VDD; the ninth resistor R9 is connected between the source of the first NMOS tube N1 and the source of the second NMOS tube N2; the second current source I2 is connected between the source of the second NMOS tube N2 and the reference ground; the gate of the fourth NMOS tube N4 is connected to the second signal in the second signal, that is, the signal AC_TNR; the drain of the fourth NMOS tube N4 is connected to the drain of the second NMOS tube N2; the fourth current source I4 is connected between the source of the fourth NMOS tube N4 and the reference ground; the tenth resistor R10 is connected between the source of the third NMOS tube N3 and the source of the fourth NMOS tube N4. It should be noted that the first signal is obtained by coupling the superimposed signal, and the second signal is obtained by coupling the local signal, then the signal AC_TP and the signal AC_TN as well as the signal AC_TPR and the signal AC_TNR have the same common mode value, and the subtraction module 12 establishes a suitable current operating point based on the same common mode value. The first NMOS tube N1 and the second NMOS tube N2 and the third NMOS tube N3 and the fourth NMOS tube N4 respectively form a differential pair, and the signal VOP output by the drain of the first NMOS tube N1 and the drain of the third NMOS tube N3 is a difference signal between the signal AC_TP and the signal AC_TPR, and the signal VON output by the drain of the second NMOS tube N2 and the drain of the fourth NMOS tube N4 is a difference signal between the signal AC_TN and the signal AC_TNR, thereby completing the separation of the transmission signal and the reception signal in the superimposed signal.

[0067] As an example, Figure 7As shown, when the superimposed signal and the local signal are both differential signals, the subtraction module 12 also includes: a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a seventh current source I7, an eighth current source I8, a ninth current source I9, a tenth current source I10, an eleventh capacitor C11, a twelfth capacitor C12, a fourteenth resistor R14, a fifteenth resistor R15, a sixteenth resistor R16 and a seventeenth resistor R17, wherein: the gate of the first PMOS tube P1 is connected to the first signal in the second signal, that is, the signal AC_TPR; the seventh current source I7 is connected between the source of the first PMOS tube P1 and the working voltage VDD; the eleventh capacitor C11 is connected between the drain of the first PMOS tube P1 and the reference ground; the sixteenth resistor R16 is connected between the drain of the first PMOS tube P1 and the reference ground; the gate of the third PMOS tube P3 is connected to the second signal in the first signal, that is, the signal AC_TN; The drain of the third PMOS tube P3 is connected to the drain of the first PMOS tube P1; the ninth current source I9 is ​​connected between the source of the third PMOS tube P3 and the working voltage VDD; the gate of the second PMOS tube P2 is connected to the first signal in the first signal, that is, the signal AC_TP; the eighth current source I8 is connected between the source of the second PMOS tube P2 and the working voltage VDD; the twelfth capacitor C12 is connected between the drain of the second PMOS tube P2 and the reference ground; the fourteenth resistor R14 is connected between the source of the first PMOS tube P1 and the source of the second PMOS tube P2; the gate of the fourth PMOS tube P4 is connected to the second signal in the second signal, that is, the signal AC_TNR; the drain of the fourth PMOS tube P4 is connected to the drain of the second PMOS tube P2; the tenth current source I10 is connected between the source of the fourth PMOS tube P4 and the working voltage VDD; the seventeenth resistor R17 is connected between the source of the fourth PMOS tube P4 and the reference ground. It should be noted that the first PMOS tube P1 and the second PMOS tube P2 and the third PMOS tube P3 and the fourth PMOS tube P4 respectively form a differential pair, the signal VOP output by the drain of the first PMOS tube P1 and the drain of the third PMOS tube P3 is a difference signal between the signal AC_TP and the signal AC_TPR, and the signal VON output by the drain of the second PMOS tube P2 and the drain of the fourth PMOS tube P4 is a difference signal between the signal AC_TN and the signal AC_TNR, thereby completing the separation of the transmission signal and the reception signal in the superimposed signal.

[0068] As an example, Figure 6As shown, when the superimposed signal and the local signal are both single-ended signals, the subtraction module 12 includes: a fifth NMOS transistor N5, a sixth NMOS transistor N6, a fifth current source I5, a sixth current source I6, a ninth capacitor C9, a tenth capacitor C10, an eleventh resistor R11, a twelfth resistor R12 and a thirteenth resistor R13, wherein: the gate of the fifth NMOS transistor N5 is connected to the first signal (not in Figure 6 The ninth capacitor C9 is connected between the drain of the fifth NMOS transistor N5 and the reference ground; the eleventh resistor R11 is connected between the drain of the fifth NMOS transistor N5 and the working voltage VDD; the fifth current source I5 is connected between the source of the fifth NMOS transistor N5 and the reference ground; the gate of the sixth NMOS transistor N6 is connected to the second signal (not in Figure 6 ); the tenth capacitor C10 is connected between the drain of the sixth NMOS tube N6 and the reference ground; the twelfth resistor R12 is connected between the drain of the sixth NMOS tube N6 and the working voltage VDD; the sixth current source I6 is connected between the source of the sixth NMOS tube N6 and the reference ground; the thirteenth resistor R13 is connected between the source of the fifth NMOS tube N5 and the source of the sixth NMOS tube N6. It should be noted that the fifth NMOS tube N5 and the sixth NMOS tube N6 form a differential pair, the first signal is connected to the gate of the fifth NMOS tube N5, and the second signal is connected to the gate of the sixth NMOS tube N6. After the subtraction operation of the first signal and the second signal, the signal output by the drain of the fifth NMOS tube N5 and the signal output by the drain of the sixth NMOS tube N6 have the same common mode value. Therefore, one of the signal output by the drain of the fifth NMOS tube N5 and the signal output by the drain of the sixth NMOS tube N6 can be selected as the difference signal after the subtraction operation.

[0069] As an example, Figure 8 As shown, when the superimposed signal and the local signal are both single-ended signals, the subtraction module 12 further includes: a fifth PMOS tube P5, a sixth PMOS tube P6, an eleventh current source I11, a twelfth current source I12, a thirteenth capacitor C13, a fourteenth capacitor C14, an eighteenth resistor R18, a nineteenth resistor R19 and a twentieth resistor R20, wherein: the gate of the fifth PMOS tube P5 is connected to the first signal (not in Figure 8 The eleventh current source I11 is connected between the source of the fifth PMOS transistor P5 and the working voltage VDD; the thirteenth capacitor C13 is connected between the drain of the fifth PMOS transistor P5 and the reference ground; the nineteenth resistor R19 is connected between the drain of the fifth PMOS transistor P5 and the reference ground; the gate of the sixth PMOS transistor P6 is connected to the second signal (not shown in FIG. Figure 8); the twelfth current source I12 is connected between the source of the sixth PMOS tube P6 and the working voltage VDD; the fourteenth capacitor C14 is connected between the drain of the sixth PMOS tube P6 and the reference ground; the twentieth resistor R20 is connected between the drain of the sixth PMOS tube P6 and the reference ground; the eighteenth resistor R18 is connected between the source of the fifth PMOS tube P5 and the source of the sixth PMOS tube P6. It should be noted that the fifth PMOS tube P5 and the sixth PMOS tube P6 form a differential pair, the first signal is connected to the gate of the fifth PMOS tube P5, and the second signal is connected to the gate of the sixth PMOS tube P6. After the subtraction operation of the first signal and the second signal, the signal output by the drain of the fifth PMOS tube P5 and the signal output by the drain of the sixth PMOS tube P6 have the same common mode value. Therefore, one of the signal output by the drain of the fifth PMOS tube P5 and the signal output by the drain of the sixth PMOS tube P6 can be selected as the difference signal after the subtraction operation.

[0070] It should be further explained that the subtraction module can also be set up using a gate-level circuit or a field programmable logic gate array. The specific settings of the gate-level circuit or the field programmable logic gate array will not be described here one by one. As long as the first signal and the second signal can be subtracted, any setting form of the subtraction module is applicable and is not limited to this embodiment.

[0071] like Figure 1 and Figure 2 As shown, the input end of the filter module 13 is connected to the output end of the subtraction module 12, and the receiving signal on the bidirectional transmission port is extracted by filtering the output signal of the subtraction module 12. It should be noted that the signal output by the subtraction module 12 includes, in addition to the receiving signal, high-frequency jitter interference, which is caused by the phase difference that may exist between the transmission signal and the local signal in the superimposed signal. The high-frequency jitter interference is eliminated by the filter module to obtain an accurate and distortion-free receiving signal. Specifically, as an example, the filter module 13 includes an active filter circuit and a passive filter circuit. When the filter module is an active filter circuit, the filter module includes a primary active filter circuit, a secondary active filter circuit and a tertiary active filter circuit.

[0072] More specifically, if Fig. 9As shown, when the filter module 13 is a primary active filter circuit, the filter module 13 includes: a seventh NMOS tube N7, an eighth NMOS tube N8, a thirteenth current source I13, a fifteenth capacitor C15, a sixteenth capacitor C16, a twenty-first resistor R21 and a twenty-second resistor R22, wherein: the gate of the seventh NMOS tube N7 is connected to the first signal in the output signal of the subtraction module 12; the fifteenth capacitor C15 is connected between the drain of the seventh NMOS tube N7 and the reference ground; the twenty-first resistor R21 is connected between the drain of the seventh NMOS tube N7 and the working voltage VDD; The thirteenth current source I13 is connected between the source of the seventh NMOS tube N7 and the reference ground; the gate of the eighth NMOS tube N8 is connected to the second signal in the output signal of the subtraction module 12, and the source of the eighth NMOS tube N8 is connected to the source of the seventh NMOS tube N7; the sixteenth capacitor C16 is connected between the drain of the eighth NMOS tube N8 and the reference ground; the twenty-second resistor R22 is connected between the drain of the eighth NMOS tube N8 and the working voltage VDD; wherein, the receiving signal on the bidirectional transmission port is extracted through the drain of the seventh NMOS tube N7 and the drain of the eighth NMOS tube N8. It should be noted that if the superimposed signal and the local signal are both differential signals, then after the first signal and the second signal in the output signal of the subtraction module 12 are filtered, the signal output by the filtering module 13 (that is, the signal output by the drain of the seventh NMOS tube N7 and the signal output by the drain of the eighth NMOS tube N8) are both received signals that need to be extracted; if the superimposed signal and the local signal are both single-ended signals, it is only necessary to select one of the signals output by the filtering module 13 (that is, the signal output by the drain of the seventh NMOS tube N7 and the signal output by the drain of the eighth NMOS tube N8) as the received signal that needs to be extracted after the first signal and the second signal in the output signal of the subtraction module 12 are filtered.

[0073] More specifically, if Fig.10As shown, when the filter module 13 is a primary active filter circuit, the filter module 13 also includes: a seventh PMOS tube P7, an eighth PMOS tube P8, a fourteenth current source I14, a seventeenth capacitor C17, an eighteenth capacitor C18, a twenty-third resistor R23 and a twenty-fourth resistor R24, wherein: the gate of the seventh PMOS tube P7 is connected to the first signal in the output signal of the subtraction module 12; the fourteenth current source I14 is connected between the source of the seventh PMOS tube P7 and the working voltage VDD; the seventeenth capacitor C17 is connected between the drain of the seventh PMOS tube P7 and the reference ground. The twenty-third resistor R23 is connected between the drain of the seventh PMOS tube P7 and the reference ground; the gate of the eighth PMOS tube P8 is connected to the second signal in the output signal of the subtraction module 12, and the source of the eighth PMOS tube P8 is connected to the source of the seventh PMOS tube P7; the eighteenth capacitor C18 is connected between the drain of the seventh PMOS tube P7 and the reference ground; the twenty-fourth resistor R24 ​​is connected between the drain of the eighth PMOS tube P8 and the reference ground; wherein, the receiving signal on the bidirectional transmission port is extracted through the drain of the seventh PMOS tube P7 and the drain of the seventh PMOS tube P7. It should be noted that if the superimposed signal and the local signal are both differential signals, then after the first signal and the second signal in the output signal of the subtraction module 12 are filtered, the signal output by the filtering module 13 (i.e., the signal output by the drain of the seventh PMOS tube P7 and the signal output by the drain of the eighth PMOS tube P8) are both received signals that need to be extracted; if the superimposed signal and the local signal are both single-ended signals, it is only necessary to select one of the signals output by the filtering module 13 (i.e., the signal output by the drain of the seventh PMOS tube P7 and the signal output by the drain of the eighth PMOS tube P8) as the received signal that needs to be extracted after the first signal and the second signal in the output signal of the subtraction module 12 are filtered.

[0074] More specifically, if Fig.11As shown, when the filter module 13 is a two-stage active filter circuit, the filter module 13 includes: a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a fifteenth current source I15, a sixteenth current source I16, a nineteenth capacitor C19, a twentieth capacitor C20, a twenty-first capacitor C21, a twenty-second capacitor C22, a twenty-fifth resistor R25, a twenty-sixth resistor R26, a twenty-seventh resistor R27 and a twenty-eighth resistor R28, wherein: the eleventh NMOS transistor N11 The gate of the twelfth NMOS tube N12 is connected to the first signal of the output signal of the subtraction module 12; the twenty-first capacitor C21 is connected between the drain of the eleventh NMOS tube N11 and the reference ground; the twenty-seventh resistor R27 is connected between the drain of the eleventh NMOS tube N11 and the working voltage VDD; the sixteenth current source I16 is connected between the source of the eleventh NMOS tube N11 and the reference ground; the gate of the twelfth NMOS tube N12 is connected to the second signal of the output signal of the subtraction module 12, and the source of the twelfth NMOS tube N12 is connected to the eleventh NMOS tube N11. The source of the 12th NMOS tube N12 is connected; the 22nd capacitor C22 is connected between the drain of the 12th NMOS tube N12 and the reference ground; the 28th resistor R28 is connected between the drain of the 12th NMOS tube N12 and the working voltage VDD; the gate of the 9th NMOS tube N9 is connected to the drain of the 11th NMOS tube N11; the 19th capacitor C19 is connected between the drain of the 9th NMOS tube N9 and the reference ground; the 25th resistor R25 is connected between the drain of the 9th NMOS tube N9 and the working voltage VDD; the 15th current source I15 is connected to the 9th NMOS tube N9. between the source of the S tube N9 and the reference ground; the gate of the tenth NMOS tube N10 is connected to the drain of the twelfth NMOS tube N12, and the source of the tenth NMOS tube N10 is connected to the source of the ninth NMOS tube N9; the twentieth capacitor C20 is connected between the drain of the tenth NMOS tube N10 and the reference ground; the twenty-sixth resistor R26 is connected between the drain of the tenth NMOS tube N10 and the working voltage VDD; wherein, the receiving signal on the bidirectional transmission port is extracted through the drain of the ninth NMOS tube N9 and the drain of the tenth NMOS tube N10. It should be noted that if the superimposed signal and the local signal are both differential signals, then after the first signal and the second signal in the output signal of the subtraction module 12 are filtered, the signal output by the filtering module 13 (that is, the signal output by the drain of the ninth NMOS tube N9 and the signal output by the drain of the tenth NMOS tube N10) are both received signals that need to be extracted; if the superimposed signal and the local signal are both single-ended signals, it is only necessary to select one of the signals output by the filtering module 13 (that is, the signal output by the drain of the ninth NMOS tube N9 and the signal output by the drain of the tenth NMOS tube N10) as the received signal that needs to be extracted after the first signal and the second signal in the output signal of the subtraction module 12 are filtered.

[0075] More specifically, if Fig.12As shown, when the filter module 13 is a two-stage active filter circuit, the filter module 13 also includes: a ninth PMOS tube P9, a tenth PMOS tube P10, an eleventh PMOS tube P11, a twelfth PMOS tube P12, a seventeenth current source I17, an eighteenth current source I18, a twenty-third capacitor C23, a twenty-fourth capacitor C24, a twenty-fifth capacitor C25, a twenty-sixth capacitor C26, a twenty-ninth resistor R29, a thirtieth resistor R30, a thirty-first resistor R31 and a thirty-second resistor R32, wherein: the ninth PMOS tube P The gate of the tenth PMOS tube P10 is connected to the first signal of the output signal of the subtraction module 12; the seventeenth current source I17 is connected between the source of the ninth PMOS tube P9 and the working voltage VDD; the twenty-third capacitor C23 is connected between the drain of the ninth PMOS tube P9 and the reference ground; the twenty-ninth resistor R29 is connected between the drain of the ninth PMOS tube P9 and the reference ground; the gate of the tenth PMOS tube P10 is connected to the second signal of the output signal of the subtraction module 12, and the source of the tenth PMOS tube P10 is connected to the source of the ninth PMOS tube P9; The fourth capacitor C24 is connected between the drain of the tenth PMOS tube P10 and the reference ground; the thirtieth resistor R30 is connected between the drain of the tenth PMOS tube P10 and the reference ground; the gate of the eleventh PMOS tube P11 is connected to the drain of the ninth PMOS tube P9; the eighteenth current source I18 is connected between the source of the eleventh PMOS tube P11 and the working voltage VDD; the twenty-fifth capacitor C25 is connected between the drain of the eleventh PMOS tube P11 and the reference ground; the thirty-first resistor R31 is connected to the drain of the eleventh PMOS tube P11 and the reference ground; the gate of the twelfth PMOS tube P12 is connected to the drain of the tenth PMOS tube P10, and the source of the twelfth PMOS tube P12 is connected to the source of the eleventh PMOS tube P11; the twenty-sixth capacitor C26 is connected between the drain of the twelfth PMOS tube P12 and the reference ground; the thirty-second resistor R32 is connected between the drain of the twelfth PMOS tube P12 and the reference ground; wherein the receiving signal on the bidirectional transmission port is extracted through the drain of the eleventh PMOS tube P11 and the drain of the twelfth PMOS tube P12. It should be noted that if the superimposed signal and the local signal are both differential signals, then after the first signal and the second signal in the output signal of the subtraction module 12 are filtered, the signal output by the filtering module 13 (i.e., the signal output by the drain of the eleventh PMOS tube P11 and the signal output by the drain of the twelfth PMOS tube P12) are both received signals that need to be extracted; if the superimposed signal and the local signal are both single-ended signals, it is only necessary to select one of the signals output by the filtering module 13 (i.e., the signal output by the drain of the eleventh PMOS tube P11 and the signal output by the drain of the twelfth PMOS tube P12) as the received signal that needs to be extracted after the first signal and the second signal in the output signal of the subtraction module 12 are filtered.

[0076] More specifically, if Fig.13As shown, when the filter module 13 is a three-stage active filter circuit, the filter module 13 includes: a thirteenth NMOS tube N13, a fourteenth NMOS tube N14, a fifteenth NMOS tube N15, a sixteenth NMOS tube N16, a seventeenth NMOS tube N17, an eighteenth NMOS tube N18, a nineteenth current source I19, a twentieth current source I20, a twenty-first current source I21, a twenty-seventh capacitor C27, a twenty-eighth capacitor C28, a twenty-ninth capacitor C29, a thirtieth capacitor C30, a thirty-first capacitor C31, a thirty-second capacitor C32, a thirty-third resistor R33, a thirty-fourth resistor R34, a thirty-fifth resistor R35, a thirty-sixth resistor R36, a thirty-seventh resistor R37 and a thirty-eighth resistor R 38, wherein: the gate of the seventeenth NMOS tube N17 is connected to the first signal of the output signal of the subtraction module 12; the thirty-first capacitor C31 is connected between the drain of the seventeenth NMOS tube N17 and the reference ground; the thirty-seventh resistor R37 is connected between the drain of the seventeenth NMOS tube N17 and the working voltage VDD; the twenty-first current source I21 is connected between the source of the seventeenth NMOS tube N17 and the reference ground; the gate of the eighteenth NMOS tube N18 is connected to the second signal of the output signal of the subtraction module 12, and the source of the eighteenth NMOS tube N18 is connected to the source of the seventeenth NMOS tube N17; the thirty-second capacitor C32 is connected between the drain of the eighteenth NMOS tube N18 and the reference ground; the thirty-eighth resistor R38 is connected between the drain of the eighteenth NMOS tube N18 and the working voltage VDD; the gate of the fifteenth NMOS tube N15 is connected to the drain of the seventeenth NMOS tube N17; the twenty-ninth capacitor C29 is connected between the drain of the fifteenth NMOS tube N15 and the reference ground; the thirty-fifth resistor R35 is connected between the drain of the fifteenth NMOS tube N15 and the working voltage VDD; the twentieth current source I20 is connected between the source of the fifteenth NMOS tube N15 and the reference ground; the gate of the sixteenth NMOS tube N16 is connected to the drain of the eighteenth NMOS tube N18, and the source of the sixteenth NMOS tube N16 is connected to the source of the fifteenth NMOS tube N15; the thirtieth capacitor C30 is connected between the sixteenth NMOS tube The 36th resistor R36 is connected between the drain of the 16th NMOS tube N16 and the working voltage VDD; the gate of the 13th NMOS tube N13 is connected to the drain of the 15th NMOS tube N15; the 19th current source I19 is connected between the source of the 13th NMOS tube N13 and the reference ground; the 27th capacitor C27 is connected between the drain of the 13th NMOS tube N13 and the reference ground; the 33rd resistor R33 is connected between the drain of the 13th NMOS tube N13 and the working voltage VDD; the gate of the 14th NMOS tube N14 is connected to the drain of the 16th NMOS tube N16, and the source of the 14th NMOS tube N14 is connected to the source of the 13th NMOS tube N13;The twenty-eighth capacitor C28 is connected between the drain of the fourteenth NMOS tube N14 and the reference ground; the thirty-fourth resistor R34 is connected between the drain of the fourteenth NMOS tube N14 and the operating voltage VDD; wherein the receiving signal on the bidirectional transmission port is extracted through the drain of the thirteenth NMOS tube N13 and the drain of the fourteenth NMOS tube N14. It should be noted that if both the superimposed signal and the local signal are differential signals, then after the first signal and the second signal in the output signal of the subtraction module 12 are filtered, the signal output by the filtering module 13 (i.e., the signal output by the drain of the thirteenth NMOS tube N13 and the signal output by the drain of the fourteenth NMOS tube N14) are both received signals to be extracted; if both the superimposed signal and the local signal are single-ended signals, only one of the signals output by the filtering module 13 (i.e., the signal output by the drain of the thirteenth NMOS tube N13 and the signal output by the drain of the fourteenth NMOS tube N14) is selected as the received signal to be extracted after the first signal and the second signal in the output signal of the subtraction module 12 are filtered. ;

[0077] More specifically, if Fig.14As shown, when the filter module 13 is a three-stage active filter circuit, the filter module 13 also includes: a thirteenth PMOS tube P13, a fourteenth PMOS tube P14, a fifteenth PMOS tube P15, a sixteenth PMOS tube P16, a seventeenth PMOS tube P17, an eighteenth PMOS tube P18, a twenty-second current source I22, a twenty-third current source I23, a twenty-fourth current source I24, a thirty-third capacitor C33, a thirty-fourth capacitor C34, a thirty-fifth capacitor C35, a thirty-sixth capacitor C36, a thirty-seventh capacitor C37, a thirty-eighth capacitor C38, a thirty-ninth resistor R39, a fortieth resistor R40, a forty-first resistor R41, a forty-second resistor R42, a forty-third resistor R43 and a forty-third resistor R44. The fourth resistor R44, wherein: the gate of the thirteenth PMOS tube P13 is connected to the first signal of the output signal of the subtraction module 12; the twenty-second current source I22 is connected between the source of the thirteenth PMOS tube P13 and the working voltage VDD; the thirty-third capacitor C33 is connected between the drain of the thirteenth PMOS tube P13 and the reference ground; the thirty-ninth resistor R39 is connected between the drain of the thirteenth PMOS tube P13 and the reference ground; the gate of the fourteenth PMOS tube P14 is connected to the second signal of the output signal of the subtraction module 12, the source of the fourteenth PMOS tube P14 is connected to the source of the thirteenth PMOS tube P13; the thirty-fourth capacitor C34 is connected between the drain of the fourteenth PMOS tube P14 and the reference ground; the The fortieth resistor R40 is connected between the drain of the fourteenth PMOS tube P14 and the reference ground; the gate of the fifteenth PMOS tube P15 is connected to the drain of the thirteenth PMOS tube P13; the twenty-third current source I23 is connected between the source of the fifteenth PMOS tube P15 and the working voltage VDD; the thirty-fifth capacitor C35 is connected between the drain of the fifteenth PMOS tube P15 and the reference ground; the forty-first resistor R41 is connected between the drain of the fifteenth PMOS tube P15 and the reference ground; the gate of the sixteenth PMOS tube P16 is connected to the drain of the fourteenth PMOS tube P14, and the source of the sixteenth PMOS tube P16 is connected to the source of the fifteenth PMOS tube P15; the thirty-sixth capacitor C36 is connected to the sixteenth PMOS tube P16. between the drain of the OS transistor P16 and the reference ground; the forty-second resistor R42 is connected between the drain of the sixteenth PMOS transistor P16 and the reference ground; the gate of the seventeenth PMOS transistor P17 is connected to the drain of the fifteenth PMOS transistor P15; the twenty-fourth current source I24 is connected between the source of the seventeenth PMOS transistor P17 and the working voltage VDD; the thirty-seventh capacitor C37 is connected between the drain of the seventeenth PMOS transistor P17 and the reference ground; the forty-third resistor R43 is connected between the drain of the seventeenth PMOS transistor P17 and the reference ground; the gate of the eighteenth PMOS transistor P18 is connected to the drain of the sixteenth PMOS transistor P16, and the source of the eighteenth PMOS transistor P18 is connected to the source of the seventeenth PMOS transistor P17;The thirty-eighth capacitor C38 is connected between the drain of the eighteenth PMOS tube P18 and the reference ground; the forty-fourth resistor R44 is connected between the drain of the eighteenth PMOS tube P18 and the reference ground; wherein, the receiving signal on the bidirectional transmission port is extracted through the drain of the seventeenth PMOS tube P17 and the drain of the eighteenth PMOS tube P18. It should be noted that if the superimposed signal and the local signal are both differential signals, then after the first signal and the second signal in the output signal of the subtraction module 12 are filtered, the signal output by the filtering module 13 (i.e., the signal output by the drain of the seventeenth PMOS tube P17 and the signal output by the drain of the eighteenth PMOS tube P18) are both the receiving signals to be extracted; if the superimposed signal and the local signal are both single-ended signals, only one of the signals output by the filtering module 13 (i.e., the signal output by the drain of the seventeenth PMOS tube P17 and the signal output by the drain of the eighteenth PMOS tube P18) is selected as the receiving signal to be extracted after the first signal and the second signal in the output signal of the subtraction module 12 are filtered. ;

[0078] More specifically, if Fig.15As shown, when the filter module 13 is a passive filter circuit, the filter module 13 also includes: a thirty-ninth capacitor C39, a fortieth capacitor C40, a forty-first capacitor C41, a forty-second capacitor C42, a forty-third capacitor C43, a forty-fourth capacitor C44, a forty-fifth resistor R45, a forty-sixth resistor R46, a forty-seventh resistor R47, a forty-eighth resistor R48, a forty-ninth resistor R49 and a fiftieth resistor R50, wherein: a first end of the forty-fifth resistor R45 is connected to a first signal in the output signal of the subtraction module 12; the thirty-ninth capacitor C39 is connected between a second end of the forty-fifth resistor R45 and a reference ground; a first end of the forty-sixth resistor R46 is connected to a second end of the forty-fifth resistor R45; the forty-third capacitor C40 is connected between a second end of the forty-sixth resistor R46 and a reference ground; the forty-seventh resistor R47 is connected to a first end of the forty-eighth resistor R48. The first end of the forty-sixth resistor R46 is connected to the second end of the forty-sixth resistor R46; the forty-first capacitor C41 is connected between the second end of the forty-seventh resistor R47 and the reference ground; the first end of the forty-eighth resistor R48 is connected to the second signal in the output signal of the subtraction module 12; the forty-second capacitor C42 is connected between the second end of the forty-eighth resistor R48 and the reference ground; the first end of the forty-ninth resistor R49 is connected to the second end of the forty-eighth resistor R48; the forty-third capacitor C43 is connected between the second end of the forty-ninth resistor R49 and the reference ground; the first end of the fiftieth resistor R50 is connected to the second end of the forty-ninth resistor R49; the forty-fourth capacitor C44 is connected between the second end of the fiftieth resistor R50 and the reference ground; wherein, the receiving signal on the bidirectional transmission port is extracted through the second end of the forty-seventh resistor R47 and the second end of the fiftieth resistor R50. It should be noted that if the superimposed signal and the local signal are both differential signals, then after the first signal and the second signal in the output signal of the subtraction module 12 are filtered, the signal output by the filtering module 13 (that is, the signal output by the second end of the forty-seventh resistor R47 and the signal output by the second end of the fiftieth resistor R50) are both received signals that need to be extracted; if the superimposed signal and the local signal are both single-ended signals, it is only necessary to select one of the signals output by the filtering module 13 (that is, the signal output by the second end of the forty-seventh resistor R47 and the signal output by the second end of the fiftieth resistor R50) as the received signal that needs to be extracted after the first signal and the second signal in the output signal of the subtraction module 12 are filtered.

[0079] It should be further explained that the filter module 13 can also be set up using an operational amplifier or a dedicated filter chip. As long as the filtering operation of the output signal of the subtraction module 12 can extract the received signal on the bidirectional transmission port, any setting form of the filter module 13 is applicable and is not limited to this embodiment.

[0080] As an example, Fig.16The state of the signal transmitted by the bidirectional transmission port, the received signal (the signal sent by other devices to the bidirectional simultaneous transmission interface) and the superimposed signal are shown, and the received signal extraction circuit provided in this embodiment is used to accurately and distortion-free extract the received signal from the superimposed signal, wherein the state of the superimposed signal and the extracted received signal is as shown in FIG. Fig.17 shown.

[0081] This embodiment also provides a transmitter, which includes the received signal extraction circuit provided in this embodiment, which is used to be set on a bidirectional simultaneous transmission interface in a bidirectional transmission link to extract the received signal accurately and without distortion.

[0082] In summary, a received signal extraction circuit and transmitter of the present invention at least include: a coupling module, a subtraction module and a filtering module, wherein: the coupling module couples the superimposed signal on the connected bidirectional transmission port into a corresponding first signal, and couples the connected local signal into a corresponding second signal, wherein the superimposed signal is obtained by superimposing the transmission signal and the received signal of the bidirectional transmission port, and the local signal is obtained by copying the transmission signal; the input end of the subtraction module is connected to the output end of the coupling module, and the first signal and the second signal are subtracted; the input end of the filtering module is connected to the output end of the subtraction module, and the received signal on the bidirectional transmission port is extracted by filtering the output signal of the subtraction module. The received signal extraction circuit and transmitter of the present invention can accurately and distortion-free extract the received signal from the bidirectional simultaneous transmission interface, facilitate the analysis operation of the quality of data communication and the improvement operation of the data communication system, and have wide applicability. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A received signal extraction circuit, characterized in that: The received signal extraction circuit at least includes: a coupling module, a subtraction module and a filtering module, wherein: The coupling module couples the superimposed signal on the connected bidirectional transmission port into a corresponding first signal, and couples the connected local signal into a corresponding second signal, wherein the superimposed signal is obtained by superimposing the transmission signal and the reception signal of the bidirectional transmission port, and the local signal is obtained by duplicating the transmission signal; The input end of the subtraction module is connected to the output end of the coupling module, and performs a subtraction operation on the first signal and the second signal; The input end of the filtering module is connected to the output end of the subtraction module, and the receiving signal on the bidirectional transmission port is extracted by filtering the output signal of the subtraction module.

2. The received signal extraction circuit according to claim 1, characterized in that: The superimposed signal and the local signal both include differential signals and single-ended signals, wherein, when the superimposed signal and the local signal are both differential signals, the first signal and the second signal are both differential signals; when the superimposed signal and the local signal are both single-ended signals, the first signal and the second signal are both single-ended signals.

3. The received signal extraction circuit according to claim 2, characterized in that: The coupling module includes a first coupling unit and a second coupling unit, wherein the input end of the first coupling unit is connected to the superimposed signal, and the first signal is generated through the output end of the first coupling unit; the input end of the second coupling unit is connected to the local signal, and the second signal is generated through the output end of the second coupling unit.

4. The received signal extraction circuit according to claim 3, characterized in that: When the superimposed signal and the local signal are both differential signals, the first coupling unit includes: a first resistor, a second resistor, a first capacitor and a second capacitor, wherein: the first end of the first capacitor is connected to the first signal in the superimposed signal; the first end of the first resistor is connected to the second end of the first capacitor, and the second end of the first resistor is connected to the bias signal; the first end of the second capacitor is connected to the second signal in the superimposed signal; the first end of the second resistor is connected to the second end of the second capacitor, and the second end of the second resistor is connected to the bias signal.

5. The received signal extraction circuit according to claim 3, characterized in that: When the superimposed signal and the local signal are both differential signals, the second coupling unit includes: a third resistor, a fourth resistor, a third capacitor and a fourth capacitor, wherein: the first end of the third capacitor is connected to the first signal in the local signal; the first end of the third resistor is connected to the second end of the third capacitor, and the second end of the third resistor is connected to the bias signal; the first end of the fourth capacitor is connected to the second signal in the local signal; the first end of the fourth resistor is connected to the second end of the fourth capacitor, and the second end of the fourth resistor is connected to the bias signal.

6. The received signal extraction circuit according to claim 3, characterized in that: When the superimposed signal and the local signal are both single-ended signals, the first coupling unit includes a fifth resistor and a fifth capacitor, wherein the first end of the fifth capacitor is connected to the superimposed signal; the first end of the fifth resistor is connected to the second end of the fifth capacitor, and the second end of the fifth resistor is connected to the bias signal.

7. The received signal extraction circuit according to claim 3, characterized in that: When the superimposed signal and the local signal are both single-ended signals, the second coupling unit includes a sixth resistor and a sixth capacitor, wherein the first end of the sixth capacitor is connected to the local signal; the first end of the sixth resistor is connected to the second end of the sixth capacitor, and the second end of the sixth resistor is connected to the bias signal.

8. The received signal extraction circuit according to claim 2, characterized in that: When the superimposed signal and the local signal are both differential signals, the subtraction module includes: a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first current source, a second current source, a third current source, a fourth current source, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a seventh capacitor and an eighth capacitor, wherein: the gate of the first NMOS tube is connected to the first signal in the second signal; the seventh capacitor is connected between the drain of the first NMOS tube and the reference ground; the seventh resistor is connected between the drain of the first NMOS tube and the working voltage; the first current source is connected between the source of the first NMOS tube and the reference ground; the gate of the third NMOS tube is connected to the second signal in the first signal, and the drain of the third NMOS tube is connected to the drain of the first NMOS tube; the third capacitor is connected to the drain of the first NMOS tube; The current source is connected between the source of the third NMOS tube and the reference ground; the gate of the second NMOS tube is connected to the first signal in the first signal; the eighth capacitor is connected between the drain of the second NMOS tube and the reference ground; the eighth resistor is connected between the drain of the second NMOS tube and the working voltage; the ninth resistor is connected between the source of the first NMOS tube and the source of the second NMOS tube; the second current source is connected between the source of the second NMOS tube and the reference ground; the gate of the fourth NMOS tube is connected to the second signal in the second signal, and the drain of the fourth NMOS tube is connected to the drain of the second NMOS tube; the fourth current source is connected between the source of the fourth NMOS tube and the reference ground; the tenth resistor is connected between the source of the third NMOS tube and the source of the fourth NMOS tube.

9. The received signal extraction circuit according to claim 2, characterized in that: When the superimposed signal and the local signal are both single-ended signals, the subtraction module includes: a fifth NMOS tube, a sixth NMOS tube, a fifth current source, a sixth current source, a ninth capacitor, a tenth capacitor, an eleventh resistor, a twelfth resistor and a thirteenth resistor, wherein: the gate of the fifth NMOS tube is connected to the first signal; the ninth capacitor is connected between the drain of the fifth NMOS tube and the reference ground; the eleventh resistor is connected between the drain of the fifth NMOS tube and the working voltage; the fifth current source is connected between the source of the fifth NMOS tube and the reference ground; the gate of the sixth NMOS tube is connected to the second signal; the tenth capacitor is connected between the drain of the sixth NMOS tube and the reference ground; the twelfth resistor is connected between the drain of the sixth NMOS tube and the working voltage; the sixth current source is connected between the source of the sixth NMOS tube and the reference ground; the thirteenth resistor is connected between the source of the fifth NMOS tube and the source of the sixth NMOS tube.

10. The received signal extraction circuit according to claim 2, characterized in that: When the superimposed signal and the local signal are both differential signals, the subtraction module further includes: a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a seventh current source, an eighth current source, a ninth current source, a tenth current source, an eleventh capacitor, a twelfth capacitor, a fourteenth resistor, a fifteenth resistor, a sixteenth resistor and a seventeenth resistor, wherein: the gate of the first PMOS tube is connected to the first signal in the second signal; the seventh current source is connected between the source of the first PMOS tube and the operating voltage; the eleventh capacitor is connected between the drain of the first PMOS tube and the reference ground; the sixteenth resistor is connected between the drain of the first PMOS tube and the reference ground; the gate of the third PMOS tube is connected to the second signal in the first signal, and the drain of the third PMOS tube is connected to the reference ground. The drain of the first PMOS tube is connected; the ninth current source is connected between the source of the third PMOS tube and the operating voltage; the gate of the second PMOS tube is connected to the first signal in the first signal; the eighth current source is connected between the source of the second PMOS tube and the operating voltage; the twelfth capacitor is connected between the drain of the second PMOS tube and the reference ground; the fourteenth resistor is connected between the source of the first PMOS tube and the source of the second PMOS tube; the gate of the fourth PMOS tube is connected to the second signal in the second signal, and the drain of the fourth PMOS tube is connected to the drain of the second PMOS tube; the tenth current source is connected between the source of the fourth PMOS tube and the operating voltage; the seventeenth resistor is connected between the source of the fourth PMOS tube and the reference ground.

11. The received signal extraction circuit according to claim 2, characterized in that: When the superimposed signal and the local signal are both single-ended signals, the subtraction module further includes: a fifth PMOS tube, a sixth PMOS tube, an eleventh current source, a twelfth current source, a thirteenth capacitor, a fourteenth capacitor, an eighteenth resistor, a nineteenth resistor and a twentieth resistor, wherein: the gate of the fifth PMOS tube is connected to the first signal; the eleventh current source is connected between the source of the fifth PMOS tube and the working voltage; the thirteenth capacitor is connected between the drain of the fifth PMOS tube and the reference ground; the nineteenth resistor is connected between the drain of the fifth PMOS tube and the reference ground; the gate of the sixth PMOS tube is connected to the second signal; the twelfth current source is connected between the source of the sixth PMOS tube and the working voltage; the fourteenth capacitor is connected between the drain of the sixth PMOS tube and the reference ground; the twentieth resistor is connected between the drain of the sixth PMOS tube and the reference ground; the eighteenth resistor is connected between the source of the fifth PMOS tube and the source of the sixth PMOS tube.

12. The received signal extraction circuit according to claim 2, characterized in that: The filtering module includes an active filtering circuit and a passive filtering circuit.

13. The received signal extraction circuit according to claim 12, characterized in that: When the filter module is an active filter circuit, the filter module includes a primary active filter circuit, a secondary active filter circuit and a tertiary active filter circuit.

14. The received signal extraction circuit according to claim 13, characterized in that: When the filtering module is a primary active filtering circuit, the filtering module includes: a seventh NMOS tube, an eighth NMOS tube, a thirteenth current source, a fifteenth capacitor, a sixteenth capacitor, a twenty-first resistor and a twenty-second resistor, wherein: the gate of the seventh NMOS tube is connected to the first signal in the output signal of the subtraction module; the fifteenth capacitor is connected between the drain of the seventh NMOS tube and the reference ground; the twenty-first resistor is connected between the drain of the seventh NMOS tube and the working voltage; the thirteenth current source is connected between the source of the seventh NMOS tube and the reference ground; the gate of the eighth NMOS tube is connected to the second signal in the output signal of the subtraction module, the source of the eighth NMOS tube is connected to the source of the seventh NMOS tube; the sixteenth capacitor is connected between the drain of the eighth NMOS tube and the reference ground; the twenty-second resistor is connected between the drain of the eighth NMOS tube and the working voltage; wherein the receiving signal on the bidirectional transmission port is extracted through the drain of the seventh NMOS tube and the drain of the eighth NMOS tube.

15. The received signal extraction circuit according to claim 13, characterized in that: When the filtering module is a primary active filtering circuit, the filtering module further includes: a seventh PMOS tube, an eighth PMOS tube, a fourteenth current source, a seventeenth capacitor, an eighteenth capacitor, a twenty-third resistor and a twenty-fourth resistor, wherein: the gate of the seventh PMOS tube is connected to the first signal in the output signal of the subtraction module; the fourteenth current source is connected between the source of the seventh PMOS tube and the working voltage; the seventeenth capacitor is connected between the drain of the seventh PMOS tube and the reference ground; the twenty-third resistor is connected between the drain of the seventh PMOS tube and the reference ground; the gate of the eighth PMOS tube is connected to the second signal in the output signal of the subtraction module, the source of the eighth PMOS tube is connected to the source of the seventh PMOS tube; the eighteenth capacitor is connected between the drain of the eighth PMOS tube and the reference ground; the twenty-fourth resistor is connected between the drain of the eighth PMOS tube and the reference ground; wherein the receiving signal on the bidirectional transmission port is extracted through the drain of the seventh PMOS tube and the drain of the eighth PMOS tube.

16. The received signal extraction circuit according to claim 13, characterized in that: When the filtering module is a secondary active filtering circuit, the filtering module includes: a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a fifteenth current source, a sixteenth current source, a nineteenth capacitor, a twentieth capacitor, a twenty-first capacitor, a twenty-second capacitor, a twenty-fifth resistor, a twenty-sixth resistor, a twenty-seventh resistor and a twenty-eighth resistor, wherein: the gate of the eleventh NMOS tube is connected to the first signal in the output signal of the subtraction module; the twenty-first capacitor is connected between the drain of the eleventh NMOS tube and the reference ground; the twenty-seventh resistor is connected between the drain of the eleventh NMOS tube and the working voltage; the sixteenth current source is connected between the source of the eleventh NMOS tube and the reference ground; the gate of the twelfth NMOS tube is connected to the second signal in the output signal of the subtraction module, the source of the twelfth NMOS tube is connected to the source of the eleventh NMOS tube; the twenty-second capacitor is connected to between the drain of the twelfth NMOS tube and the reference ground; the twenty-eighth resistor is connected between the drain of the twelfth NMOS tube and the working voltage; the gate of the ninth NMOS tube is connected to the drain of the eleventh NMOS tube; the nineteenth capacitor is connected between the drain of the ninth NMOS tube and the reference ground; the twenty-fifth resistor is connected between the drain of the ninth NMOS tube and the working voltage; the fifteenth current source is connected between the source of the ninth NMOS tube and the reference ground; the gate of the tenth NMOS tube is connected to the drain of the twelfth NMOS tube, and the source of the tenth NMOS tube is connected to the source of the ninth NMOS tube; the twenty-tenth capacitor is connected between the drain of the tenth NMOS tube and the reference ground; the twenty-sixth resistor is connected between the drain of the tenth NMOS tube and the working voltage; wherein the receiving signal on the bidirectional transmission port is extracted through the drain of the ninth MOS tube and the drain of the tenth MOS tube.

17. The received signal extraction circuit according to claim 13, characterized in that: When the filtering module is a secondary active filtering circuit, the filtering module further includes: a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a seventeenth current source, an eighteenth current source, a twenty-third capacitor, a twenty-fourth capacitor, a twenty-fifth capacitor, a twenty-sixth capacitor, a twenty-ninth resistor, a thirtieth resistor, a thirty-first resistor and a thirty-second resistor, wherein: the gate of the ninth PMOS tube is connected to the first signal in the output signal of the subtraction module; the seventeenth current source is connected between the source of the ninth PMOS tube and the working voltage; the twenty-third capacitor is connected between the drain of the ninth PMOS tube and the reference ground; the twenty-ninth resistor is connected between the drain of the ninth PMOS tube and the reference ground; the gate of the tenth PMOS tube is connected to the second signal in the output signal of the subtraction module, the source of the tenth PMOS tube is connected to the source of the ninth PMOS tube; the twenty-fourth capacitor is connected to the tenth PM The 30th resistor is connected between the drain of the 10th PMOS tube and the reference ground; the gate of the 11th PMOS tube is connected to the drain of the 9th PMOS tube; the 18th current source is connected between the source of the 11th PMOS tube and the working voltage; the 25th capacitor is connected between the drain of the 11th PMOS tube and the reference ground; the 31st resistor is connected between the drain of the 11th PMOS tube and the reference ground; the gate of the 12th PMOS tube is connected to the drain of the 10th PMOS tube, and the source of the 12th PMOS tube is connected to the source of the 11th PMOS tube; the 26th capacitor is connected between the drain of the 12th PMOS tube and the reference ground; the 32nd resistor is connected between the drain of the 12th PMOS tube and the reference ground; wherein the receiving signal on the bidirectional transmission port is extracted through the drain of the 11th PMOS tube and the drain of the 12th PMOS tube.

18. The received signal extraction circuit according to claim 13, characterized in that: When the filtering module is a three-stage active filtering circuit, the filtering module includes: a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a nineteenth current source, a twentieth current source, a twenty-first current source, a twenty-seventh capacitor, a twenty-eighth capacitor, a twenty-ninth capacitor, a thirtieth capacitor, a thirty-first capacitor, a thirty-second capacitor, a thirty-third resistor, a thirty-fourth resistor, a thirty-fifth resistor, a thirty-sixth resistor, a thirty-seventh resistor and a thirty-eighth resistor, wherein: the gate of the seventeenth NMOS tube is connected to the first signal in the output signal of the subtraction module; the thirty-first capacitor is connected to the drain of the seventeenth NMOS tube and the reference ground; the thirty-seventh resistor is connected between the drain of the seventeenth NMOS tube and the operating voltage; the twenty-first current source is connected between the source of the seventeenth NMOS tube and the reference ground; the gate of the eighteenth NMOS tube is connected to the second signal in the output signal of the subtraction module, and the source of the eighteenth NMOS tube is connected to the source of the seventeenth NMOS tube; the thirty-second capacitor is connected between the drain of the eighteenth NMOS tube and the reference ground; the thirty-eighth resistor is connected between the drain of the eighteenth NMOS tube and the operating voltage; the gate of the fifteenth NMOS tube is connected to the drain of the seventeenth NMOS tube; the twenty-ninth capacitor is connected to the fifteenth NMOS The thirty-fifth resistor is connected between the drain of the fifteenth NMOS tube and the working voltage; the twentieth current source is connected between the source of the fifteenth NMOS tube and the reference ground; the gate of the sixteenth NMOS tube is connected to the drain of the eighteenth NMOS tube, and the source of the sixteenth NMOS tube is connected to the source of the fifteenth NMOS tube; the thirtieth capacitor is connected between the drain of the sixteenth NMOS tube and the reference ground; the thirty-sixth resistor is connected between the drain of the sixteenth NMOS tube and the working voltage; the gate of the thirteenth NMOS tube is connected to the drain of the fifteenth NMOS tube; the nineteenth current source is connected to the thirteenth NMOS tube. The twenty-seventh capacitor is connected between the drain of the thirteenth NMOS tube and the reference ground; the thirty-third resistor is connected between the drain of the thirteenth NMOS tube and the operating voltage; the gate of the fourteenth NMOS tube is connected to the drain of the sixteenth NMOS tube, and the source of the fourteenth NMOS tube is connected to the source of the thirteenth NMOS tube; the twenty-eighth capacitor is connected between the drain of the fourteenth NMOS tube and the reference ground; the thirty-fourth resistor is connected between the drain of the fourteenth NMOS tube and the operating voltage; wherein the receiving signal on the bidirectional transmission port is extracted through the drain of the thirteenth NMOS tube and the drain of the fourteenth NMOS tube.

19. The received signal extraction circuit according to claim 13, characterized in that: When the filtering module is a three-stage active filtering circuit, the filtering module further includes: a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a twenty-second current source, a twenty-third current source, a twenty-fourth current source, a thirty-third capacitor, a thirty-fourth capacitor, a thirty-fifth capacitor, a thirty-sixth capacitor, a thirty-seventh capacitor, a thirty-eighth capacitor, a thirty-ninth resistor, a fortieth resistor, a forty-first resistor, a forty-second resistor, a forty-third resistor and a forty-fourth resistor, wherein: the gate of the thirteenth PMOS tube is connected to the first signal in the output signal of the subtraction module; the twenty-second current source is connected to the thirteenth PMOS The thirty-third capacitor is connected between the drain of the thirteenth PMOS tube and the reference ground; the thirty-ninth resistor is connected between the drain of the thirteenth PMOS tube and the reference ground; the gate of the fourteenth PMOS tube is connected to the second signal in the output signal of the subtraction module, and the source of the fourteenth PMOS tube is connected to the source of the thirteenth PMOS tube; the thirty-fourth capacitor is connected between the drain of the fourteenth PMOS tube and the reference ground; the fortieth resistor is connected between the drain of the fourteenth PMOS tube and the reference ground; the gate of the fifteenth PMOS tube is connected to the drain of the thirteenth PMOS tube; the twenty-third current source is connected to the fifteenth PMOS tube; The 35th capacitor is connected between the drain of the 15th PMOS tube and the reference ground; the 41st resistor is connected between the drain of the 15th PMOS tube and the reference ground; the gate of the 16th PMOS tube is connected to the drain of the 14th PMOS tube, and the source of the 16th PMOS tube is connected to the source of the 15th PMOS tube; the 36th capacitor is connected between the drain of the 16th PMOS tube and the reference ground; the 42nd resistor is connected between the drain of the 16th PMOS tube and the reference ground; the gate of the 17th PMOS tube is connected to the drain of the 15th PMOS tube; the 24th current source is connected to the 17th PMOS tube; between the source of the OS tube and the working voltage; the thirty-seventh capacitor is connected between the drain of the seventeenth PMOS tube and the reference ground; the forty-third resistor is connected between the drain of the seventeenth PMOS tube and the reference ground; the gate of the eighteenth PMOS tube is connected to the drain of the sixteenth PMOS tube, and the source of the eighteenth PMOS tube is connected to the source of the seventeenth PMOS tube; the thirty-eighth capacitor is connected between the drain of the eighteenth PMOS tube and the reference ground; the forty-fourth resistor is connected between the drain of the eighteenth PMOS tube and the reference ground; wherein the receiving signal on the bidirectional transmission port is extracted through the drain of the seventeenth PMOS tube and the drain of the eighteenth PMOS tube.

20. The received signal extraction circuit according to claim 12, characterized in that: When the filtering module is a passive filtering circuit, the filtering module also includes: a thirty-ninth capacitor, a forty-first capacitor, a forty-second capacitor, a forty-third capacitor, a forty-fourth capacitor, a forty-fifth resistor, a forty-sixth resistor, a forty-seventh resistor, a forty-eighth resistor, a forty-ninth resistor and a fiftieth resistor, wherein: the first end of the forty-fifth resistor is connected to the first signal in the output signal of the subtraction module; the thirty-ninth capacitor is connected between the second end of the forty-fifth resistor and the reference ground; the first end of the forty-sixth resistor is connected to the second end of the forty-fifth resistor; the forty-third capacitor is connected between the second end of the forty-sixth resistor and the reference ground; the first end of the forty-seventh resistor is connected to the second end of the forty-sixth resistor connection; the forty-first capacitor is connected between the second end of the forty-seventh resistor and the reference ground; the first end of the forty-eighth resistor is connected to the second signal in the output signal of the subtraction module; the forty-second capacitor is connected between the second end of the forty-eighth resistor and the reference ground; the first end of the forty-ninth resistor is connected to the second end of the forty-eighth resistor; the forty-third capacitor is connected between the second end of the forty-ninth resistor and the reference ground; the first end of the fiftieth resistor is connected to the second end of the forty-ninth resistor; the forty-fourth capacitor is connected between the second end of the fiftieth resistor and the reference ground; wherein the received signal on the bidirectional transmission port is extracted through the second end of the forty-seventh resistor and the second end of the fiftieth resistor.

21. A transmitter, characterized in that: The transmitter comprises a received signal extraction circuit as described in any one of claims 1-20.

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