Video transcoding method and device, electronic equipment, storage medium and program product

Abstract

The invention provides a video transcoding method and device, electronic equipment, a storage medium and a program product, and relates to the technical field of video transcoding. The method comprises the steps that a video transcoding card receives a transcoding request and a video to be transcoded sent by a server, the transcoding request comprises a first video parameter and a second video parameter, and the first video parameter and the second video parameter are video parameters before and after transcoding of the video to be transcoded; determining a configuration parameter according to the first video parameter and the second video parameter, the configuration parameter being used for controlling a transcoding speed; transcoding the to-be-transcoded video according to the configuration parameters to obtain a target video; and sending the target video to the server. According to the invention, transcoding is carried out through the external video transcoding card instead of being carried out on a CPU (Central Processing Unit) of the server, the computing resources of the server are not occupied, and transcoding is carried out without using a GPU (Graphic Processing Unit), so that the power consumption and the cost are reduced on the premise of improving the transcoding speed.

Description

Background Art

[0002] With the increasing popularity of urban surveillance, live broadcasting, video conferencing and other services, massive amounts of video data are generated every day. The processing, distribution and storage of this data has brought tremendous pressure to the data centers that support video services, especially in terms of the consumption of computing, network and storage resources, facing severe challenges.

[0003] In related technologies, using CPU (central processing unit) to transcode and compress videos can meet certain needs, but due to low transcoding efficiency, it often occupies most of the server's computing resources, resulting in limited overall performance. Using GPU (graphics processing unit) for transcoding can greatly improve efficiency, but it is accompanied by higher hardware costs and power consumption, further increasing the burden of equipment investment and operation.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The present disclosure provides a video transcoding method, device, electronic device, storage medium and program product, which at least to a certain extent improve the transcoding speed and reduce power consumption and cost.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a video transcoding method is provided, which is applied to a video transcoding card, and includes: receiving a transcoding request and a video to be transcoded sent by a server, the transcoding request including a first video parameter and a second video parameter, the first video parameter and the second video parameter being video parameters of the video to be transcoded before and after transcoding, respectively; determining configuration parameters according to the first video parameter and the second video parameter, the configuration parameters being used to control the transcoding speed; transcoding the video to be transcoded according to the configuration parameters to obtain a target video; and sending the target video to the server.

[0008] In one embodiment of the present disclosure, the configuration parameters include decoder parameters, scaler parameters and encoder parameters, the decoder parameters are configured through decoder instructions, the scaler parameters are configured through scaler instructions, the encoder parameters are configured through encoder instructions, and the decoder instructions, the scaler instructions and the encoder instructions are all custom instructions.

[0009] In one embodiment of the present disclosure, the video to be transcoded is transcoded according to the configuration parameters to obtain a target video, including: decoding the video to be transcoded according to the decoder parameters; transforming the decoded video to be transcoded according to the scaler parameters; encoding the transformed video to be transcoded according to the encoder parameters to obtain the target video; wherein the transforming process includes scaling processing and / or watermark superimposition processing.

[0010] In one embodiment of the present disclosure, the transformed video to be transcoded is encoded according to encoder parameters to obtain the target video, including: inputting the video to be transcoded into a first model for feature extraction to obtain temporal features and spatial features; inputting the temporal features and spatial features into a second model for feature fusion to obtain complexity parameters and a control strategy; encoding the transformed video to be transcoded according to the encoder parameters, and dynamically adjusting the encoding parameters according to the complexity parameters and the control strategy to obtain the target video; wherein the encoding parameters include one or more of a bit rate, a quantization parameter, and a frame type.

[0011] In one embodiment of the present disclosure, the decoder parameters include inverse quantization calculation parameters, inverse discrete cosine transform parameters and arithmetic decoding parameters; the scaler parameters include nearest neighbor interpolation parameters and hybrid algorithm parameters; the encoder parameters include quantization calculation parameters, discrete cosine transform parameters and arithmetic coding parameters.

[0012] In one embodiment of the present disclosure, the custom instruction is a RISC-V fifth-generation reduced instruction set instruction.

[0013] According to another aspect of the present disclosure, a video transcoding device is provided, which is applied to a video transcoding card, including: a receiving module, used to receive a transcoding request and a video to be transcoded sent by a server, the transcoding request including a first video parameter and a second video parameter, the first video parameter and the second video parameter being respectively video parameters of the video to be transcoded before and after transcoding; a determining module, used to determine configuration parameters according to the first video parameter and the second video parameter, the configuration parameters being used to control the transcoding speed; a transcoding module, used to transcode the video to be transcoded according to the configuration parameters to obtain a target video; and a sending module, used to send the target video to the server.

[0014] According to another aspect of the present disclosure, a video transcoding card is provided, comprising: a plurality of video transcoding units, an extension interface and a controller, wherein the plurality of video transcoding units are connected to a server via the extension interface, and the plurality of video transcoding units are connected to the controller, and the controller is used for out-of-band monitoring and management; the video transcoding unit comprises: a control unit, used for instruction extension and transcoding control, the controller and the extension interface are both connected to the control unit; a decoder, used for decoding a video to be transcoded according to decoder parameters; a scaler, used for transforming the decoded video to be transcoded according to the scaler parameters; an encoder, used for encoding the transformed video to be transcoded according to the encoder parameters to obtain a target video; wherein the transforming process comprises a scaling process and / or a watermark superimposing process.

[0015] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform any of the above-mentioned video transcoding methods by executing the executable instructions.

[0016] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any of the above-mentioned video transcoding methods is implemented.

[0017] According to another aspect of the present disclosure, a computer program product is provided, wherein the computer program product comprises a computer program or computer instructions, wherein the computer program or the computer instructions are loaded and executed by a processor so as to enable a computer to implement any of the above-mentioned video transcoding methods.

[0018] In an embodiment of the present disclosure, a video transcoding card receives a transcoding request and a video to be transcoded sent by a server, the transcoding request includes a first video parameter and a second video parameter, the first video parameter and the second video parameter are respectively video parameters of the video to be transcoded before and after transcoding; according to the first video parameter and the second video parameter, a configuration parameter is determined, the configuration parameter is used to control the transcoding speed; according to the configuration parameter, the video to be transcoded is transcoded to obtain a target video; and the target video is sent to the server. The present disclosure performs transcoding through an external video transcoding card instead of on the CPU of the server, does not occupy the computing resources of the server, and does not use a GPU for transcoding, thereby reducing power consumption and cost while increasing the transcoding speed.

[0019] In addition, the present disclosure controls the transcoding speed by configuring parameters, thereby increasing the flexibility of transcoding speed control.

[0020] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0022] Figure 1 A schematic diagram of a video transcoding card in an embodiment of the present disclosure is shown.

[0023] Figure 2 A flow chart of a video transcoding method in an embodiment of the present disclosure is shown.

[0024] Figure 3 A flow chart of a video transcoding method in another embodiment of the present disclosure is shown.

[0025] Figure 4 A schematic diagram of decoder instructions according to an embodiment of the present disclosure is shown.

[0026] Figure 5 A schematic diagram of a scaler instruction according to an embodiment of the present disclosure is shown.

[0027] Figure 6 A schematic diagram of encoder instructions according to an embodiment of the present disclosure is shown.

[0028] Figure 7 A schematic diagram of a video transcoding device in an embodiment of the present disclosure is shown.

[0029] Figure 8 A structural block diagram of an electronic device in an embodiment of the present disclosure is shown.

[0030] Fig. 9 A schematic diagram of a computer-readable storage medium provided in an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0031] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0032] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0033] It should be understood that the various steps described in the method embodiments of the present disclosure may be performed in different orders and / or in parallel. In addition, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present disclosure is not limited in this respect.

[0034] It should be noted that the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0035] It should be noted that the modifications of "one" and "plurality" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0036] For ease of understanding, several terms involved in the present disclosure are explained below:

[0037] DCT (Discrete Cosine Transform): Similar to discrete Fourier transform, but only uses real numbers and is often used in signal processing and image processing.

[0038] IDCT (Inverse Discrete Cosine Transform): The inverse operation of discrete cosine transform.

[0039] BMC (Baseboard Management Controller): A dedicated service processor that uses sensors to monitor the status of a computer, network server, or other hardware drive device.

[0040] ASIC (Application-Specific Integrated Circuit) refers to a device or system that uses this dedicated chip model to perform efficient task processing.

[0041] RISC-V (Reduced Instruction Set Computer Five, the fifth-generation reduced instruction set computer architecture) is an instruction set architecture.

[0042] BMC (Baseboard Management Controller) is an embedded microcontroller used for server and computer hardware management. It runs independently of the main operating system and is specifically used to monitor and manage server hardware and supports remote management functions. It is used to communicate with management personnel through various management protocols (such as IPMI).

[0043] PCIE Switch (Peripheral Component Interconnect Express Switch, referred to as PCIe switch) refers to a network device that can forward data between multiple ports.

[0044] Video services generate massive amounts of video data every day. If the video data is not transcoded and compressed, it will consume a huge amount of network bandwidth and storage resources in the data center during video distribution and storage. If the CPU is used to transcode the video, the CPU will be in a high-load state for a long time and the transcoding efficiency will be low.

[0045] The inventors have found that the hardware transcoding solutions in the related art, such as the AMD Alveo MA35D transcoding card (a transcoding card), are ASIC models, and both the hardware and the dedicated software library rely on AMD, which has low flexibility and scalability. If a GPU is used for video transcoding, the hardware cost is high and the power consumption is high during operation.

[0046] Based on this, the present disclosure proposes a video transcoding method, which is applied to the scenario of video transcoding, for example, the video transcoding card of the present disclosure is connected to the server carrying the video service, and cooperates in the scenario of video transcoding. The video transcoding card of the present disclosure receives the transcoding request and the video to be transcoded sent by the server, the transcoding request includes the first video parameter and the second video parameter, the first video parameter and the second video parameter are respectively the video parameters before and after the transcoding of the video to be transcoded; according to the first video parameter and the second video parameter, the configuration parameters are determined, and the configuration parameters are used to control the transcoding speed; according to the configuration parameters, the video to be transcoded is transcoded to obtain the target video; and the target video is sent to the server. The present disclosure performs transcoding through an external video transcoding card instead of on the CPU of the server, which does not occupy the computing resources of the server, and does not use the GPU for transcoding, thereby reducing power consumption and cost while improving the transcoding speed. In other words, the cost of video services is reduced.

[0047] It should be pointed out that, in the absence of conflict, the embodiments of the present disclosure and the technical features therein may be combined with each other.

[0048] The specific implementation of the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0049] Figure 1 A schematic diagram of a video transcoding card in an embodiment of the present disclosure is shown, and the video transcoding method or video transcoding device in each embodiment of the present disclosure can be applied. A video transcoding card 100 provided by the present disclosure includes: multiple video transcoding units 110, an extension interface 120 and a controller 130, multiple video transcoding units 110 are connected to a server through the extension interface 120, multiple video transcoding units 110 are connected to the controller 130, and the controller 130 is used for out-of-band monitoring management; the video transcoding unit 110 may include: a control unit for instruction extension and transcoding control, the controller and the extension interface are connected to the control unit; a decoder for decoding a video to be transcoded according to decoder parameters; a scaler for transforming the decoded video to be transcoded according to the scaler parameters; an encoder for encoding the transformed video to be transcoded according to the encoder parameters to obtain a target video; wherein the transformation process includes scaling and / or watermark superposition.

[0050] For example, the video transcoding card 100 may be a RISC-V video transcoding card, which is a hardware acceleration card based on the RISC-V architecture for converting video files from one format to another format; the expansion interface 120 may be a PCIe switch; and the controller 130 may be a BMC, which is not specifically limited in the embodiments of the present disclosure. Figure 1 As shown, the RISC-V video transcoding card may include multiple video transcoding units 110, each of which is controlled by the RISC-V instruction set, and the video transcoding unit 110 may include a control unit, a decoder, a scaler, and an encoder. A single video transcoding unit 110 can transcode multiple channels of video at the same time, and different video transcoding units 110 do not affect each other. BMC is used for out-of-band monitoring management, and the video transcoding card 100 is connected to the server via a PCIe switch. For example, the video service platform of the server is connected to the expansion interface 120 of the video transcoding card 100 through an interface library and a hardware driver in turn.

[0051] It should be noted that the control unit can implement standard RV64GC (an instruction set based on RISC-V architecture) instruction extension, which is only used to control a single video transcoding unit 110. The control unit is connected to the BMC and also to the PCIE switch.

[0052] It should be noted that the decoder decodes the input video to be transcoded, and during the decoding process, custom instructions (such as encoder instructions) can be used to accelerate high-frequency calculations such as inverse quantization and IDCT.

[0053] It should be noted that the scaler can provide functions such as hardware scaling and watermark overlay, and these processes can be accelerated using custom instructions (such as scaler instructions).

[0054] It should be noted that the encoder can encode and compress the video stream, and has a built-in neural network (such as the first model, the second model, and the third model), which can assist in video compression. At the same time, custom instructions (such as encoder instructions) are used to accelerate high-frequency calculations such as quantization and DCT. Exemplarily, the decoder can decode the input video to be transcoded through a circuit, and custom instructions can be used to accelerate inverse quantization, inverse discrete cosine transform (IDCT), and arithmetic decoding during the calculation process.

[0055] In addition, the hardware driver and interface library of the video transcoding card 100 need to be implemented at the software level, and the video service platform uses the video transcoding card 100 to process the video by calling the interface.

[0056] The present disclosure proposes a video transcoding method based on RISC-V. A hardware architecture based on RISC-V is designed, and a software library is designed to provide an interface for the video service platform to call and offload the video transcoding task on the server. At the same time, the present disclosure customizes the RISC-V instruction extension for video transcoding to improve the efficiency of video transcoding.

[0057] The present exemplary implementation is described in detail below with reference to the accompanying drawings and embodiments.

[0058] First, a video transcoding method is provided in an embodiment of the present disclosure, and the method can be executed by a video transcoding card.

[0059] Figure 2 A flow chart of a video transcoding method in an embodiment of the present disclosure is shown as follows: Figure 2 As shown, the video transcoding method provided in the embodiment of the present disclosure includes the following S201 to S204.

[0060] S201, receiving a transcoding request and a video to be transcoded sent by a server, wherein the transcoding request includes a first video parameter and a second video parameter, and the first video parameter and the second video parameter are respectively video parameters of the video to be transcoded before and after transcoding.

[0061] In the disclosed embodiment, the video transcoding card receives a transcoding request and a video to be transcoded sent by a server. The transcoding request is a request for requesting the video transcoding card to transcode the video to be transcoded. It should be noted that, in addition to the first video parameter and the second video parameter, the transcoding request may also include selection information for the transcoding speed level. For example, the selection information for the transcoding speed level may include the first level, the second level, and the third level. The higher the level, the faster the transcoding speed. The selection information included in the transcoding request is the third level.

[0062] In the embodiment of the present disclosure, the first video parameter is the video parameter of the video to be transcoded before transcoding, and the second video parameter is the video parameter of the video to be transcoded after transcoding. For example, the video parameter may be one or more of resolution, bit rate, and frame rate.

[0063] S202: Determine configuration parameters according to the first video parameter and the second video parameter, where the configuration parameters are used to control the transcoding speed.

[0064] In the disclosed embodiment, the configuration parameters are parameters that can control the transcoding speed. For example, the configuration parameters may include decoder parameters, scaler parameters, and encoder parameters, the decoder parameters are configured by decoder instructions, the scaler parameters are configured by scaler instructions, and the encoder parameters are configured by encoder instructions, and the decoder instructions, scaler instructions, and encoder instructions are all custom instructions.

[0065] It should be noted that the configuration of mathematical operation parameters in the transcoding process can be achieved through decoder instructions, scaler instructions and encoder instructions. The transcoding speed can be improved by changing the parameters, which can provide flexibility in transcoding control.

[0066] Exemplarily, the configuration parameters may include parameters for configuration at multiple levels, and the parameters for configuration at each level include decoder parameters, scaler parameters, and encoder parameters. The configuration parameters of the corresponding level may be selected according to the transcoding speed level. For example, the selection information included in the transcoding request is the third level, and the configuration parameters include parameters for configuration at 3 levels, and the parameters for configuration at the third level corresponding to the third level are selected to control the transcoding speed.

[0067] In the embodiments of the present disclosure, there is no limitation on how to determine the configuration parameters based on the first video parameters and the second video parameters. For example, according to a preset relationship correspondence table, the configuration parameters corresponding to the first video parameters and the second video parameters are selected. For another example, according to a machine learning model, the first video parameters and the second video parameters are input into the machine learning model, and the configuration parameters are output. It should be noted that if the transcoding request includes selection information, the configuration parameters corresponding to the first video parameters and the second video parameters also include multiple levels of parameters for configuration. After the configuration parameters are determined according to the first video parameters and the second video parameters, the corresponding parameters for configuration are selected according to the selection information. The embodiments of the present disclosure increase the flexibility of control by selecting the configuration parameters of the corresponding level through the selection information, and the configuration parameters are configured through custom instructions, which can improve the efficiency of video transcoding. In addition, the transcoding compression of the transcoded video can reduce the cost of data center network and storage.

[0068] S203, transcoding the video to be transcoded according to the configuration parameters to obtain a target video;

[0069] In the embodiment of the present disclosure, the video to be transcoded is decoded, scaled and encoded in sequence according to the configuration parameters to obtain a target video, which is a transcoded video.

[0070] S204: Send the target video to the server.

[0071] The embodiment of the present disclosure performs transcoding through an external video transcoding card instead of on the CPU of the server, which does not occupy the computing resources of the server and does not use the GPU for transcoding, thereby reducing power consumption and cost while increasing the transcoding speed. In addition, the present disclosure controls the transcoding speed through configuration parameters, which increases the flexibility of transcoding speed control.

[0072] The present disclosure is described below by means of two exemplary embodiments.

[0073] In an exemplary embodiment, if Figure 3 As shown, in the video transcoding method provided by the embodiment of the present disclosure, transcoding the video to be transcoded according to the configuration parameters to obtain the target video may include S2031 to S2033.

[0074] S2031, decode the video to be transcoded according to decoder parameters.

[0075] In the embodiment of the present disclosure, the decoder parameters may include inverse quantization calculation parameters, inverse discrete cosine transform parameters and arithmetic decoding parameters.

[0076] Exemplarily, the decoder decodes the input video stream to be transcoded, and during the calculation process, custom decoder instructions can be used to accelerate inverse quantization, inverse discrete cosine transform, and arithmetic decoding.

[0077] like Figure 4 As shown, the DEQUANT instruction, MACC instruction, COS instruction and ARITHDEC instruction are all decoder instructions, among which the DEQUANT instruction is used to configure the inverse quantization calculation parameters, the MACC instruction and the COS instruction are used to configure the inverse discrete cosine transform parameters, and the ARITHDEC instruction is used to configure the arithmetic decoding parameters.

[0078] In one embodiment, the custom instructions (such as decoder instructions) are RISC-V fifth generation reduced instruction set instructions.

[0079] The two source registers of the DEQUANT instruction are used to store the quantization value Q(u,v) and the quantization step size Q Step , the target register stores the calculation result C ′ (u,v). For example, source register 1 is used to store the quantization value Q(u,v), and source register 2 is used to store the quantization step size Q Step .

[0080] The inverse quantization formula is shown in Formula 1 below.

[0081] C ′ (u,v)=Q(u,v)·Q Step (1)

[0082] Among them, C ′ (u, v) is the transform coefficient after inverse quantization, u is the row index in the transform coefficient matrix, v is the column index in the transform coefficient matrix, Q(u, v) is the quantized coefficient (quantization value), Q Step is the quantization step size.

[0083] The MACC instruction and the COS instruction can be used for the two high-frequency calculation processes of multiplication accumulation and cosine calculation in DCT and IDCT. The source registers rs1 and rs2 of the MACC instruction store the numbers used for multiplication, and rs3 stores the numbers used for addition. The COS instruction source register stores the input value of the cosine function. Exemplary: The MACC instruction assembly format is MACC rd, rs1, rs2, rs3. This instruction and its corresponding hardware circuit are used to implement the calculation process of multiplication accumulation rd = rs1*rs2+rs3.

[0084] The IDCT formula is shown in Formula 2 below.

[0085]

[0086] Among them, f(x,y) is the output pixel value, x is the row coordinate, y is the column coordinate, N is the size of the image block, α is the normalization coefficient, F(k,l) is the value in the input transformation coefficient matrix, k is the row index, and l is the column index.

[0087] For example, Figure 4 As shown, the source registers rs1 and rs2 of the COS instruction can store (x, k) and (y, l). In the MACC instruction, the accumulation starts from 0. The source register rs3 stores the result of the previous operation. The source register rs1 can store the output values ​​of the two COS operations. The source register rs2 can store F(k,l), and the destination register rd is used to store f(x,y).

[0088] It should be noted that the MACC instruction and the COS instruction are part of the IDCT operation. The formula cannot be calculated using only these two instructions. The source register rs1 of the MACC instruction can also store the output values ​​of the two cos.

[0089] The ARITHDEC instruction is used for arithmetic decoding. The two source registers rs1 and rs2 are used to store the storage address of the bit stream S and the probability model p(s j )'s storage address.

[0090] The formulas involved in arithmetic decoding are shown below.

[0091] S={s1,s2,s3....s n} (3)

[0092] Among them, S is the input symbol set (bit stream), s i is the i-th symbol in the symbol set, n is the total number of symbols in the symbol set, and i is a positive integer less than or equal to n.

[0093] Each symbol s i There is a corresponding probability p(s i ), define the cumulative probability C(s i ) is shown in Formula 4 below.

[0094]

[0095] Among them, C(s i ) is the cumulative probability, p(s j ) is the probability model of the j-th symbol, and j is a positive integer less than i-1.

[0096] E is the encoding value, and the current symbol update interval is [L,U), where L is the minimum encoding value and U is the maximum encoding value. The conditions that need to be met are shown in the following formula 5.

[0097]

[0098] Among them, C(s i ) is the cumulative probability, p(s i ) is the probability model of the ith symbol, i is a positive integer less than or equal to n, L is the minimum value of the encoded value, and U is the maximum value of the encoded value.

[0099] Update value L of the minimum value of the coded value new As shown in Formula 6. The updated value U of the maximum value of the encoded value new As shown in Formula 7.

[0100] L new =L+(UL)·C(s i ) (6)

[0101] U new =L+(UL)·(C(s i )+p(s i )) (7)

[0102] Among them, L new is the updated value of the minimum value of the coded value, U new is the updated value of the maximum value of the encoded value, C(s i ) is the cumulative probability, p(s i ) is the probability model of the ith symbol, i is a positive integer less than or equal to n, L is the minimum value of the encoded value, and U is the maximum value of the encoded value.

[0103] It should be noted that the decoder parameters may be configured in advance or during the decoding process, and the embodiments of the present disclosure do not limit this.

[0104] S2032: Perform transformation processing on the decoded video to be transcoded according to the scaler parameters.

[0105] In the disclosed embodiment, the scaler parameters include nearest neighbor interpolation parameters and hybrid algorithm parameters.

[0106] Exemplarily, the scaler is used to implement functions such as video scaling and watermark overlay. Both the NEAREST instruction and the ALPHA instruction are scaler instructions. The NEAREST instruction is used to configure the nearest neighbor interpolation parameters, and the ALPHA instruction is used to configure the mixing algorithm parameters, wherein the mixing algorithm parameters are the parameters of the Alpha mixing algorithm in the watermark overlay.

[0107] In one embodiment, the custom instructions (such as scaler instructions) are RISC-V fifth generation reduced instruction set instructions.

[0108] The NEAREST instruction is used for nearest neighbor interpolation and can be used to scale the video frames of the decoded video to be transcoded. Figure 5 As shown, the source register rs1 stores the storage address of the original video frame, the source register rs2 stores the scaling factor S, and the source register rs3 stores the coordinates of the current pixel of the target frame.

[0109] The nearest neighbor interpolation formula is shown in Figure 8.

[0110]

[0111] Among them, (x out ,y out ) is the coordinate of a pixel in the target image, (x in ,y in ) is the coordinate of a pixel in the original image, S x is the scaling factor of the row coordinates, S y is the scaling factor for column coordinates.

[0112] The ALPHA instruction is used for the Alpha blending algorithm in watermark overlay, such as Figure 5 As shown, the source register rs1 stores the original video pixel value P video , the pixel value P of the source register rs2 watermark watermark , the source register rs3 stores the transparency α, and the destination register stores the color value of the output pixel.

[0113] The Alpha blending algorithm formula is shown in 9 below.

[0114] P out =α·P watermark +(1-α)·P video (9)

[0115] Among them, P out is the color value of the output pixel, P watermark is the color value of the watermark pixel, P video is the color value of the original video frame pixel, and α is the transparency of the watermark.

[0116] It should be noted that the scaler parameters may be configured in advance or during the scaling process or the watermark overlay process, and the embodiments of the present disclosure do not limit this.

[0117] S2033, encoding the transformed video to be transcoded according to the encoder parameters to obtain a target video, wherein the transformation process includes scaling and / or watermark superimposition.

[0118] In the disclosed embodiment, the encoder parameters include quantization calculation parameters, discrete cosine transform parameters and arithmetic coding parameters.

[0119] Exemplarily, the encoder encodes the video to be transcoded after the transformation process, and during the calculation process, a custom encoder instruction can be used to accelerate quantization, discrete cosine transform, and arithmetic coding.

[0120] like Figure 6 As shown, the QUANT instruction and the ARITHENC instruction are both encoder instructions, wherein the QUANT instruction is used to configure quantization calculation parameters, and the ARITHENC instruction is used to configure arithmetic coding parameters.

[0121] In one embodiment, the custom instructions (such as encoder instructions) are RISC-V fifth generation reduced instruction set instructions.

[0122] The QUANT instruction is used for quantization calculation. The source registers rs1 and rs2 are used to store the quantization value C(u,v) and the quantization step size Q respectively. Step , the destination register stores the calculation result Q(u,v).

[0123] The quantization formula is shown in Formula 10 below.

[0124]

[0125] Among them, C(u,v) is the original transform coefficient, u is the row index in the transform coefficient matrix, v is the column index in the transform coefficient matrix, Q(u,v) is the quantized coefficient (quantization value), Q Step is the quantization step size.

[0126] The MACC and COS instructions defined in the decoder can also be used in the DCT calculation of the encoder.

[0127] The DCT formula is shown in the following formula 11.

[0128]

[0129] Among them, f(x,y) is the input pixel value, x is the row coordinate, y is the column coordinate, N is the size of the image block, α is the normalization coefficient, F(k,l) is the value in the output transformation coefficient matrix, k is the row index, and l is the column index.

[0130] The ARITHENC instruction is used for arithmetic coding. The source registers rs1 and rs2 are used to store the storage address of the bit stream S and the probability model p(s j )'s storage address.

[0131] The formulas involved in arithmetic coding are shown below.

[0132] S={s1,s2,s3....s n}

[0133] Among them, S is the input symbol set (bit stream), s i is the i-th symbol in the symbol set, n is the total number of symbols in the symbol set, and i is a positive integer less than or equal to n.

[0134] Each symbol s i There is a corresponding probability p(s i ), define the cumulative probability C(s i ) is shown in the following formula.

[0135]

[0136] Among them, C(s i ) is the cumulative probability, p(s j ) is the probability model of the j-th symbol, and j is a positive integer less than i-1.

[0137] The current symbol update interval is [L, U), where L is the minimum value of the code value, U is the maximum value of the code value, and the update value L of the minimum code value new The updated value U of the maximum value of the coded value new As shown in the following formula.

[0138] L new =L+(UL)·C(s i )

[0139] U new =L+(UL)·(C(s i )+p(s i ))

[0140] Among them, L new is the updated value of the minimum value of the coded value, U new is the updated value of the maximum value of the encoded value, C(s i ) is the cumulative probability, p(s i ) is the probability model of the ith symbol, i is a positive integer less than or equal to n, L is the minimum value of the encoded value, and U is the maximum value of the encoded value.

[0141] The final encoding result is any small value in the final interval, usually the midpoint of the interval, as shown in Formula 12 below.

[0142]

[0143] Among them, Encoded Value is the encoding result, L is the minimum value of the encoded value, and U is the maximum value of the encoded value.

[0144] In another exemplary embodiment, in the video transcoding method provided in the embodiment of the present disclosure, encoding the transformed video to be transcoded according to encoder parameters to obtain the target video may include the following steps A1 to A3.

[0145] Step A1: input the video to be transcoded into the first model for feature extraction to obtain temporal features and spatial features.

[0146] In the embodiment of the present disclosure, the first model is used to extract features in the video frame of the video to be transcoded. The embodiment of the present disclosure does not limit what kind of model the first model is. For example, the first model can be a CNN (Convolutional Neural Network) model.

[0147] In the disclosed embodiment, time features and spatial features are features of two dimensions. Among them, the time feature focuses on the dynamic changes and motion information in the video. For example, the time feature can be one or more of motion vectors (MV), optical flow, motion, temporal correlation, and sequential patterns. The spatial feature focuses on the spatial information of each frame of the video, especially the details and surface structures in the image. Texture is the visual manifestation of repeated or regular patterns in an image. For example, the spatial feature can be one or more of local texture patterns, edge information, frequency domain features, and gray level co-occurrence matrix (GLCM).

[0148] Step A2: input the time feature and the space feature into the second model for feature fusion to obtain the complexity parameter and the control strategy.

[0149] In the embodiment of the present disclosure, the second model is used to fuse the temporal features and the spatial features. The embodiment of the present disclosure does not limit what kind of model the second model is. For example, the second model may be a CNN model or an adaptive model.

[0150] In the disclosed embodiment, the complexity parameter is a parameter that affects the computational complexity of the video encoding process. The complexity parameter can adjust the encoding strategy according to different video contents to ensure the best compression effect and video quality. For example, the complexity parameter can be parameters such as coding block size, motion estimation accuracy, transformation and quantization. The control strategy is used to dynamically adjust various parameters in the encoding process in order to ensure the best visual quality and encoding performance in different input video scenarios. The control strategy can achieve automatic dynamic adjustment under the guidance of the second model (such as a pre-trained network), thereby improving the overall efficiency of video compression.

[0151] The disclosed embodiment fuses the temporal features and the spatial features through the second model, and obtains the complexity parameters and the control strategy according to the fused features, so that the dynamic adjustment of the control strategy is more accurate and the complexity parameters are more precise, thereby ensuring the best compression effect and video quality while ensuring the encoding speed.

[0152] It should be noted that the first model and the second model are combined into a reference AI (artificial intelligence) model, which is used to obtain complexity parameters and control strategies, so as to dynamically adjust the encoding parameters according to the complexity parameters and control strategies to generate a video stream with better compression efficiency.

[0153] Step A3, encoding the transformed video to be transcoded according to encoder parameters, and dynamically adjusting the encoding parameters according to complexity parameters and control strategies to obtain a target video; wherein the encoding parameters include one or more of bit rate, quantization parameter and frame type.

[0154] In addition to the above-mentioned embodiments of the invention that use custom instructions to accelerate the encoding process, the encoder also includes a neural network accelerator (a first model and a second model). The first model performs preliminary feature extraction on the input video, including temporal features such as MV and spatial features such as detail textures, and then uses the second model to fuse the temporal features and spatial features to derive complexity parameters and control strategies that conform to the visual model. When the encoder is encoding, it dynamically adjusts parameters such as the bit rate and QP (quantization parameter) value according to the input video to generate a video stream with better compression efficiency.

[0155] The disclosed embodiment integrates temporal features and spatial features to significantly improve the effect of video processing tasks. By simultaneously capturing the dynamic changes (temporal features) and spatial details (spatial features) of the video, it is possible to more fully understand the video content, enhance the recognition of complex actions and behaviors, improve robustness, and effectively capture temporal and spatial dependencies, making it easier to encode according to precise control encoders.

[0156] In summary, the present disclosure utilizes the customizable characteristics of RISC-V, uses RISC-V-based hardware to offload the video transcoding tasks of the CPU on the server, and accelerates the video transcoding process through custom instructions and corresponding hardware circuits. The present disclosure designs custom instructions for video decoding, which can accelerate the inverse quantization, IDCT, and arithmetic decoding operations in the decoding process. In addition, the present disclosure designs custom instructions to accelerate video scaling and watermark overlay functions. Custom instructions for video encoding are also designed, which can accelerate the quantization, DCT, and arithmetic coding operations in the encoding process, and at the same time provide a first module and a second model to assist the encoding process to generate a video stream with better compression efficiency.

[0157] It should be noted that the present disclosure is based on the open source and free RISC-V instruction set, which has lower hardware cost than GPU-based solutions. The RISC-V instructions for custom video transcoding have faster video transcoding capabilities than general-purpose CPUs.

[0158] The present disclosure is described in detail below through examples.

[0159] In one embodiment, the video transcoding method provided by the present disclosure includes the following steps B1 to B6.

[0160] Step B1: The video service platform starts processing a video transcoding request, for example, transcoding an input H.264 format video into an H.265 format video.

[0161] In step B2, the video service platform calls the interface library of the video transcoding card (such as a video transcoding card based on the RISC-V architecture) and starts scheduling the video to be transcoded to the video transcoding card for video transcoding.

[0162] Step B3, the video transcoding unit of the video transcoding card decodes the input video to be transcoded (H.264 video stream). When performing IDCT calculation in the decoding process, the calculation circuit is called according to the formula by using the MACC instruction and the COS command to accelerate the two processes of accumulation multiplication and cosine calculation. When performing inverse quantization calculation, the DEQUANT instruction is used to accelerate, and when performing arithmetic decoding, the ARITHDEC instruction is called to accelerate.

[0163] Step B4, when performing operations such as video scaling and watermark overlay on the decoded video stream, the computing circuit is called for acceleration through the NEAREST instruction and the ALPHA instruction.

[0164] Step B5, input the scaled video stream into the encoder for encoding, dynamically adjust the bit rate and QP and other parameters in combination with the reference AI encoder in the encoder, encode according to the above parameters, and use QUANT instructions, MACC instructions, COS instructions, ARITHENC instructions and their circuits to accelerate the quantization, DCT, and arithmetic coding processes.

[0165] Step B6: Return the encoded H.265 video stream to the video service platform for subsequent storage or distribution.

[0166] Based on the same inventive concept, the present disclosure also provides a video transcoding device, such as the following embodiment. Since the principle of solving the problem in the device embodiment is similar to that in the above method embodiment, the implementation of the device embodiment can refer to the implementation of the above method embodiment, and the repeated parts will not be repeated.

[0167] Figure 7 A schematic diagram of a video transcoding device in an embodiment of the present disclosure is shown. Figure 7 As shown, the video transcoding device is applied to a video transcoding card, and includes a receiving module 71, a determining module 72, a transcoding module 73 and a sending module 74. The receiving module 71 can be used to receive a transcoding request and a video to be transcoded sent by a server, the transcoding request includes a first video parameter and a second video parameter, and the first video parameter and the second video parameter are respectively video parameters of the video to be transcoded before and after transcoding; the determining module 72 can be used to determine configuration parameters according to the first video parameter and the second video parameter, and the configuration parameters are used to control the transcoding speed; the transcoding module 73 can be used to transcode the video to be transcoded according to the configuration parameters to obtain a target video; the sending module 74 can be used to send the target video to the server.

[0168] In one embodiment, the configuration parameters include decoder parameters, scaler parameters and encoder parameters. The decoder parameters are configured through decoder instructions, the scaler parameters are configured through scaler instructions, and the encoder parameters are configured through encoder instructions. The decoder instructions, scaler instructions and encoder instructions are all custom instructions.

[0169] In one embodiment, the transcoding module 73 can also be used to decode the video to be transcoded according to the decoder parameters; transform the decoded video to be transcoded according to the scaler parameters; encode the transformed video to be transcoded according to the encoder parameters to obtain the target video; wherein the transformation processing includes scaling processing and / or watermark superimposition processing.

[0170] In one embodiment, the transcoding module 73 can also be used to input the video to be transcoded into the first model for feature extraction to obtain temporal features and spatial features; input the temporal features and spatial features into the second model for feature fusion to obtain complexity parameters and control strategies; encode the transformed video to be transcoded according to the encoder parameters, and dynamically adjust the encoding parameters according to the complexity parameters and control strategies to obtain the target video; wherein the encoding parameters include one or more of the bit rate, quantization parameters and frame type.

[0171] In one embodiment, the decoder parameters include inverse quantization calculation parameters, inverse discrete cosine transform parameters and arithmetic decoding parameters; the scaler parameters include nearest neighbor interpolation parameters and hybrid algorithm parameters; the encoder parameters include quantization calculation parameters, discrete cosine transform parameters and arithmetic coding parameters.

[0172] In one embodiment, the custom instruction is a RISC-V fifth generation reduced instruction set instruction.

[0173] The video transcoding device disclosed in the embodiment of the present disclosure performs transcoding through an external video transcoding card instead of on the CPU of the server, which does not occupy the computing resources of the server and does not use the GPU for transcoding, thereby reducing power consumption and cost while increasing the transcoding speed. In addition, the present disclosure controls the transcoding speed through configuration parameters, which increases the flexibility of transcoding speed control.

[0174] Those skilled in the art will appreciate that various aspects of the present disclosure may be implemented as systems, methods or program products. Therefore, various aspects of the present disclosure may be specifically implemented in the following forms, namely: complete hardware implementation, complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to herein as "circuits", "modules" or "systems".

[0175] Refer to the following Figure 8 The electronic device 800 according to this embodiment of the present disclosure is described. Figure 8 The electronic device 800 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0176] like Figure 8 As shown, the electronic device 800 is in the form of a general computing device. The components of the electronic device 800 may include but are not limited to: at least one processing unit 810, at least one storage unit 820, and a bus 830 connecting different system components (including the storage unit 820 and the processing unit 810).

[0177] The storage unit stores a program code, and the program code can be executed by the processing unit 810, so that the processing unit 810 executes the steps described in the "Exemplary Method" section of the specification according to various exemplary embodiments of the present disclosure. For example, the processing unit 810 can execute the following steps of the above method embodiment: receiving a transcoding request and a video to be transcoded sent by a server, the transcoding request including a first video parameter and a second video parameter, the first video parameter and the second video parameter being the video parameters before and after transcoding of the video to be transcoded, respectively; determining configuration parameters according to the first video parameter and the second video parameter, the configuration parameters being used to control the transcoding speed; transcoding the video to be transcoded according to the configuration parameters to obtain a target video; and sending the target video to the server.

[0178] The storage unit 820 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 8201 and / or a cache memory unit 8202 , and may further include a read-only memory unit (ROM) 8203 .

[0179] The storage unit 820 may also include a program / utility 8204 having a set (at least one) of program modules 8205, such program modules 8205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0180] Bus 830 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0181] The electronic device 800 may also communicate with one or more external devices 840 (e.g., keyboards, pointing devices, Bluetooth devices, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 800, and / or communicate with any device that enables the electronic device 800 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed via an input / output (I / O) interface 850. Furthermore, the electronic device 800 may also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via a network adapter 860. As shown, the network adapter 860 communicates with other modules of the electronic device 800 via a bus 830. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 800, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0182] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0183] In the disclosed exemplary embodiments, a computer-readable storage medium is also provided, which may be a readable signal medium or a readable storage medium. Fig. 9 A schematic diagram of a computer-readable storage medium in an embodiment of the present disclosure is shown. Fig. 9 As shown, the computer-readable storage medium 900 stores a program product capable of implementing the above method of the present disclosure.

[0184] In some possible implementations, various aspects of the present disclosure may also be implemented in the form of a program product, which includes program code. When the program product is run on a terminal device, the program code is used to enable the terminal device to execute the steps of various exemplary implementations of the present disclosure described in the above "Specific Implementation Methods" section of this specification.

[0185] More specific examples of computer-readable storage media in the present disclosure may include, but are not limited to, an electrical connection having one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0186] In the present disclosure, a computer readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, wherein a readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A readable signal medium may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0187] Alternatively, the program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the foregoing.

[0188] In a specific implementation, the program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., using an Internet service provider to connect through the Internet).

[0189] The embodiments of the present disclosure provide a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the video transcoding method provided in various optional ways in any embodiment of the present disclosure.

[0190] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0191] In addition, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0192] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0193] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The description and examples are to be regarded as exemplary only, and the true scope of the present disclosure is indicated by the appended claims.

Claims

1. A video transcoding method, characterized in that: Applicable to video transcoding cards, including: Receiving a transcoding request and a video to be transcoded sent by a server, wherein the transcoding request includes a first video parameter and a second video parameter, wherein the first video parameter and the second video parameter are respectively video parameters of the video to be transcoded before and after transcoding; Determining configuration parameters according to the first video parameter and the second video parameter, wherein the configuration parameters are used to control a transcoding speed; Transcode the video to be transcoded according to the configuration parameters to obtain a target video; The target video is sent to the server.

2. The method according to claim 1, characterized in that The configuration parameters include decoder parameters, scaler parameters and encoder parameters. The decoder parameters are configured through decoder instructions, the scaler parameters are configured through scaler instructions, and the encoder parameters are configured through encoder instructions. The decoder instructions, the scaler instructions and the encoder instructions are all custom instructions.

3. The method according to claim 2, characterized in that Transcoding the video to be transcoded according to the configuration parameters to obtain a target video, including: Decoding the video to be transcoded according to the decoder parameters; Performing transformation processing on the decoded video to be transcoded according to the scaler parameters; Encoding the transformed video to be transcoded according to the encoder parameters to obtain the target video; The transformation process includes scaling process and / or watermark superposition process.

4. The method according to claim 2, characterized in that: Encoding the transformed video to be transcoded according to the encoder parameters to obtain the target video, including: Inputting the video to be transcoded into the first model for feature extraction to obtain temporal features and spatial features; Inputting the time feature and the space feature into the second model for feature fusion to obtain complexity parameters and control strategies; Encoding the transformed video to be transcoded according to the encoder parameters, and dynamically adjusting the encoding parameters according to the complexity parameters and the control strategy to obtain the target video; The encoding parameters include one or more of a bit rate, a quantization parameter and a frame type.

5. The method according to claim 2, characterized in that: The decoder parameters include inverse quantization calculation parameters, inverse discrete cosine transform parameters and arithmetic decoding parameters; the scaler parameters include nearest neighbor interpolation parameters and hybrid algorithm parameters; the encoder parameters include quantization calculation parameters, discrete cosine transform parameters and arithmetic coding parameters.

6. The method according to claim 2, characterized in that The custom instructions are RISC-V fifth generation reduced instruction set instructions.

7. A video transcoding device, characterized in that: Applicable to video transcoding cards, including: A receiving module, configured to receive a transcoding request and a video to be transcoded sent by a server, wherein the transcoding request includes a first video parameter and a second video parameter, wherein the first video parameter and the second video parameter are respectively video parameters of the video to be transcoded before and after transcoding; A determination module, configured to determine a configuration parameter according to the first video parameter and the second video parameter, wherein the configuration parameter is used to control a transcoding speed; A transcoding module, used for transcoding the video to be transcoded according to the configuration parameters to obtain a target video; A sending module is used to send the target video to the server.

8. An electronic device, characterized in that: include: processor; as well as A memory, configured to store executable instructions of the processor; The processor is configured to execute the video transcoding method according to any one of claims 1 to 6 by executing the executable instructions.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the video transcoding method according to any one of claims 1 to 6 is implemented.

10. A computer program product, comprising computer instructions, wherein the computer instructions are stored in a computer-readable storage medium, and when the computer instructions are executed by a processor, they implement the operation instructions of the video transcoding method according to any one of claims 1 to 6.

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