Film layer structure for improving UV attenuation of TOPcon battery

Abstract

The invention relates to the technical field of solar cells, in particular to a film layer structure for improving UV attenuation of a TOPcon cell. In order to improve the passivation effect of the front face of the TOPCon cell, an aluminum oxide passivation layer is generally arranged on the surface of a BSG layer on the front face of the TOPCon cell, but the aluminum oxide passivation layer is poor in ultraviolet resistance and prone to being damaged by ultraviolet light, and then the service life of the cell is affected. Aiming at the problem, the invention provides the film layer structure for improving UV attenuation of the TOPcon battery, the second silicon oxide layer and the first silicon oxide layer are respectively arranged above and below the aluminum oxide layer, and the silicon nitride layer is arranged on the surface of the second silicon oxide layer, so that the passivation effect of the front surface of the obtained TOPcon battery is remarkably improved, the attenuation speed of the battery is effectively reduced, and the service life of the battery is prolonged. And the service life of the battery is prolonged.

Description

Technical Field

[0001] The invention relates to the technical field of solar cells, and in particular to a film layer structure for improving UV attenuation of a TOPcon cell. Background Art

[0002] Tunneling oxide passivation contact (TOPCon) is a high-efficiency solar cell structure. Its structure is composed of an ultra-thin layer of silicon oxide (1-2nm) and a layer of phosphorus-doped polysilicon (90-120nm) on the back. The front side of the N-type topcon cell uses boron diffusion, which is different from the traditional P-type cell that uses phosphorus diffusion. The solid solubility of boron is not increased, resulting in poor passivation effect on the front side. Therefore, aluminum oxide will be deposited on the front side for further passivation. However, since aluminum oxide is easily damaged by ultraviolet light, it damages some silicon-hydrogen bonds, which in turn causes the cell to decay. According to a study published by the Renewable Energy Test Center (RETC) in the United States, cells manufactured using TOPCon technology may be at risk of premature degradation due to the influence of ultraviolet (UV) radiation. Actual experimental data also confirms this theory, so it is more critical to improve UV attenuation through optimization of the process end, especially the ALD deposition of aluminum oxide. Summary of the invention

[0003] The problem in the prior art is that, in order to increase the passivation effect of the front side of the TOPCon cell, an aluminum oxide passivation layer is generally provided on the surface of the borosilicate glass (BSG) layer on the front side, but the aluminum oxide passivation layer has poor UV resistance and is easily damaged by ultraviolet light, which in turn affects the service life of the cell. In view of the above problems, the present invention provides a film layer structure for improving the UV attenuation of a TOPcon cell, which includes an N-type silicon wafer;

[0004] The front side of the N-type silicon wafer is provided with a BSG layer, a first silicon oxide layer, an aluminum oxide layer, and a second silicon oxide layer in sequence from bottom to top;

[0005] The back side of the N-type silicon wafer is provided with a silicon oxide tunneling layer, a phosphorus-doped polysilicon layer, a first silicon oxide layer, an aluminum oxide layer, and a second silicon oxide layer in sequence from top to bottom.

[0006] Preferably, a silicon nitride layer is disposed on the surface of the second silicon oxide layer.

[0007] Preferably, the thickness of the silicon nitride layer is 75-80 nm.

[0008] Preferably, the thickness of the BSG layer is 20-30 nm.

[0009] Preferably, the N-type silicon wafer is a double-sided texturing N-type silicon wafer, and after the texturing, the reflectivity of the front and back sides of the silicon wafer is 9.5-10.5%.

[0010] Preferably, the thickness of the first silicon oxide layer is 4-6 nm.

[0011] Preferably, the thickness of the second silicon oxide layer is 4-6 nm.

[0012] Preferably, the thickness of the silicon oxide tunneling layer is 0.5-2.5 nm.

[0013] Preferably, the thickness of the phosphorus-doped polysilicon (p-poly) layer is 70-120 nm.

[0014] Preferably, the preparation method of the film structure for improving UV attenuation of TOPcon cells comprises the following steps:

[0015] S1: Select an N-type silicon wafer and perform texturing on the front and back sides of the N-type silicon wafer so that the reflectivity of the front and back sides of the silicon wafer reaches 9.5-10.5%;

[0016] S2: The silicon wafer obtained in step S1 is placed in a high-temperature quartz furnace tube with the front side facing upwards, and boron chloride and oxygen are introduced into the high-temperature quartz furnace tube by boron diffusion. In the high-temperature environment, boron chloride and oxygen react with Si atoms on the surface of the silicon wafer to form a BSG layer on the front side of the N-type silicon wafer obtained in step S1;

[0017] S3: Then the silicon wafer obtained in step S2 is placed with the front side facing upward in a high-temperature diffusion furnace, oxygen is introduced, and a silicon oxide protective layer is formed on the surface of the BSG layer in a high-temperature environment;

[0018] S4: using a hydrofluoric acid aqueous solution to etch away the BSG layer formed by plating on the back and edge of the silicon wafer obtained in step S3, and polishing the back and edge of the silicon wafer, wherein the reflectivity after polishing reaches 43-46%;

[0019] S5: The back side of the silicon wafer obtained in step S4 is facing upwards, and the silicon wafer is subjected to the pecvd method using N 2 O radio frequency decomposition reaction, forming a silicon oxide tunneling layer on the back side of the silicon wafer obtained in step S4;

[0020] S6: The back side of the silicon wafer obtained in step S5 is facing upward, and the silicon wafer is oxidized by SiH 4 , PH 3 Radio frequency decomposition reaction forms a p-poly layer on the surface of the silicon oxide tunneling layer on the back of the silicon wafer;

[0021] S7: The back side of the silicon wafer obtained in step S6 is facing upward, and the silicon wafer is subjected to the pecvd method using N 2 O、SiH 4 Radio frequency decomposition reaction, depositing a silicon oxide mask layer on the surface of the phosphorus-doped polysilicon layer on the back of the silicon wafer;

[0022] S8: placing the silicon wafer obtained in step S7 at a high temperature of more than 900° C. and performing high temperature annealing treatment under nitrogen protection;

[0023] S9: using a hydrofluoric acid aqueous solution (using the double decomposition reaction between HF and PSG) to etch away the PSG layer formed by plating on the front and edge of the silicon wafer obtained in step S8, then placing the silicon wafer in an alkaline solution to remove the p-poly layer formed by plating on the front and edge of the silicon wafer, and then placing the silicon wafer in a mixed solution formed by hydrofluoric acid and hydrochloric acid to etch away the silicon oxide protective layer on the front of the silicon wafer and the silicon oxide mask layer on the back of the silicon wafer, and then taking out the silicon wafer, washing it with water, and drying it for later use;

[0024] S10: depositing a first silicon oxide layer on the surface of the silicon wafer obtained in step S9 by ALD deposition;

[0025] S11: depositing a single atomic layer of aluminum oxide on the surface of the first silicon oxide layer by ALD deposition;

[0026] S12: depositing a second silicon oxide layer on the surface of the aluminum oxide layer by an ALD deposition method;

[0027] S13: By using the PECVD method, a silicon nitride layer is first deposited on the front side of the silicon wafer, and then a silicon nitride layer is deposited on the back side of the silicon wafer.

[0028] Preferably, the step S3 is specifically as follows:

[0029] The silicon wafer is placed in a high-temperature diffusion furnace and oxygen is introduced. At 900-1100°C, the oxygen reacts with the Si atoms on the surface of the silicon wafer to form a silicon oxide protective layer.

[0030] Preferably, step S4 is specifically as follows:

[0031] The front side of the silicon wafer obtained in step S3 faces upward, and the BSG formed by plating on the back side and the front edge of the silicon wafer is removed by etching with a hydrofluoric acid solution in a chain etcher. Then, the boron-doped silicon oxide layer formed by plating on the back side and the front and back edges of the silicon wafer is polished in an alkaline solution tank. After the polishing is completed, hydrochloric acid is added to the alkaline solution tank for neutralization, and the silicon wafer is taken out, washed with water, and dried for standby use.

[0032] Preferably, in step S8, the high temperature annealing temperature is 900-1000° C., and the annealing time is 50-70 min.

[0033] Preferably, the specific steps of step S10 are as follows:

[0034] The silicon wafer obtained in step S9 is placed in an ALD deposition furnace, and after heating, vacuuming, and leak detection, ozone is introduced to deposit a first silicon oxide layer on the surface of the silicon wafer by utilizing the strong oxidizing reaction of ozone.

[0035] Preferably, the specific steps of step S11 are as follows:

[0036] The silicon wafer obtained in step S10 is placed in an ALD deposition furnace. After heating, vacuuming, and leak detection, trimethylaluminum (TMA) is first introduced into the deposition furnace. TMA is adsorbed on the surface of the silicon wafer to form a trimethylaluminum adsorption layer. Water vapor is then introduced into the deposition furnace to react with the trimethylaluminum adsorption layer on the surface of the silicon wafer to form a single atomic layer of aluminum oxide.

[0037] Preferably, the specific steps of step S12 are as follows:

[0038] The silicon wafer obtained in step S11 is placed in an ALD deposition furnace, and ozone is introduced after heating, vacuuming, and leak detection. Under high temperature conditions, some silicon atoms in the silicon substrate pass through the film layer to reach the surface of the silicon wafer and react with ozone to produce a strong oxidizing reaction, and react on the surface of the aluminum oxide layer to obtain a second silicon oxide layer.

[0039] Preferably, the specific steps of step S13 are as follows:

[0040] The silicon wafer obtained in step S12 is placed in a PECVD precipitation furnace, and after heating, vacuuming, and leak detection, SiH 4 NH 3 , SiH in high temperature environment 4 With NH 3 A reaction occurs, firstly a silicon nitride layer is deposited on the front side of the silicon wafer, and then a silicon nitride layer is deposited on the back side of the silicon wafer.

[0041] The present invention has the following beneficial effects:

[0042] In order to solve the problem that the aluminum oxide layer on the front of the TOPCon battery is not resistant to ultraviolet light, the present invention arranges a second silicon oxide layer and a first silicon oxide layer above and below the aluminum oxide layer respectively, and arranges a silicon nitride layer on the surface of the second silicon oxide layer. The first silicon oxide layer below the aluminum oxide and close to the N-type silicon wafer enhances the passivation, so that under the same conditions, the electrical performance attenuation of the aluminum oxide layer after being damaged by UV radiation is reduced. The second silicon oxide layer above the aluminum oxide layer can protect the aluminum oxide and reduce the influence of UV radiation, thereby improving UV attenuation. The silicon nitride layer above the second silicon oxide layer has three main functions: one is a protective film layer to prevent the thinner silicon oxide layer below from being scratched and worn; the second is that silicon nitride is used as an anti-reflection film layer to reduce light reflection; the third is SIH during silicon nitride deposition. 4 With NH 3Reaction, some of the H ions produced in the reaction enter the interior of the silicon wafer, which can effectively reduce the recombination of the positive charge of the silicon wafer itself and the carriers, thereby reducing the internal defects of the silicon wafer, increasing the life of the photogenerated carriers, and further playing a passivation role, thereby improving the efficiency of the battery cell. Under the joint action of the aluminum oxide layer, the first silicon oxide layer and the second silicon oxide layer, the passivation effect of the front side of the TOPCon battery is significantly improved, the battery attenuation rate is effectively reduced, and the battery life is extended. DETAILED DESCRIPTION

[0043] The present invention is described in detail below with reference to the examples. However, it should be understood that the following examples are only illustrative of the embodiments of the present invention, and are not intended to limit the scope of the present invention.

[0044] The N-type silicon wafers in the following embodiments of the present invention are N-type M10 silicon wafers purchased from LONGi Green Energy.

[0045] Example 1

[0046] A film structure for improving UV attenuation of a TOPcon cell, and a preparation method thereof is as follows:

[0047] S1: Select an N-type silicon wafer and perform texturing on the front and back sides of the N-type silicon wafer so that the reflectivity of the front and back sides of the silicon wafer reaches 9.5%;

[0048] S2: The silicon wafer obtained in step S1 is placed in a high-temperature quartz furnace tube with the front side facing upwards. Boron chloride and oxygen are introduced into the high-temperature quartz furnace tube by boron diffusion. The boron chloride, oxygen and Si atoms on the surface of the silicon wafer react at 860° C. The reaction time is 77 minutes. A BSG layer is formed on the front side of the N-type silicon wafer obtained in step S1. The thickness of the BSG layer is 20 nm. The volume flow rate of boron chloride is 230 sccm, and the volume flow rate of oxygen is 800 sccm.

[0049] S3: Then the silicon wafer obtained in step S2 is placed in a high-temperature diffusion furnace with the front side facing upwards, and oxygen is introduced to form a silicon oxide protective layer on the surface of the BSG layer at 1045°C. The reaction time is 50 minutes, the thickness of the silicon oxide protective layer is 70 nm, and the volume flow rate of oxygen is 25000 sccm;

[0050] S4: using a hydrofluoric acid aqueous solution to etch away the BSG layer formed by plating on the back and edge of the silicon wafer obtained in step S3, and polishing the back and edge of the silicon wafer, wherein the reflectivity after polishing reaches 43%;

[0051] S5: The back side of the silicon wafer obtained in step S4 is facing upwards, and the silicon wafer is subjected to the pecvd method using N 2 O radio frequency decomposition reaction, forming a silicon oxide tunneling layer on the back of the silicon wafer obtained in step S4, wherein the thickness of the silicon oxide tunneling layer is 0.5 nm;

[0052] S6: The back side of the silicon wafer obtained in step S5 is facing upward, and the silicon wafer is oxidized by SiH 4 , PH 3 Radio frequency decomposition reaction forms a p-poly layer on the surface of the silicon oxide tunneling layer on the back of the silicon wafer, and the thickness of the p-poly layer is 70nm;

[0053] S7: The back side of the silicon wafer obtained in step S6 is facing upward, and the silicon wafer is subjected to the pecvd method using N 2 O、SiH 4 A silicon oxide mask layer is deposited on the surface of the p-poly layer on the back of the silicon wafer by radio frequency decomposition reaction, wherein the thickness of the silicon oxide mask layer is 30 nm;

[0054] S8: placing the silicon wafer obtained in step S7 at a high temperature of 900° C. and performing high temperature annealing treatment for 50 minutes under nitrogen protection;

[0055] S9: using a hydrofluoric acid aqueous solution to etch away the PSG layer formed by plating on the front and edge of the silicon wafer obtained in step S8, then placing the silicon wafer in an alkaline solution to remove the p-poly layer formed by plating on the front and edge of the silicon wafer, then placing the silicon wafer in a mixed solution of hydrofluoric acid and hydrochloric acid to etch away the silicon oxide protective layer on the front of the silicon wafer and the silicon oxide mask layer on the back of the silicon wafer, then taking out the silicon wafer, washing it with water, and drying it for later use;

[0056] S10: placing the silicon wafer obtained in step S9 in an ALD deposition furnace, introducing ozone after heating, vacuuming, and leak detection, and utilizing the strong oxidizing reaction of ozone to deposit a first silicon oxide layer on both sides of the silicon wafer surface, wherein the thickness of the first silicon oxide layer is 4 nm;

[0057] S11: placing the silicon wafer obtained in step S10 in an ALD deposition furnace, and after heating, vacuuming, and leak detection, first introducing TMA into the deposition furnace, and TMA is adsorbed on the surface of the silicon wafer to form a trimethylaluminum adsorption layer, and then introducing water vapor into the deposition furnace to react with the trimethylaluminum adsorption layer on the surface of the silicon wafer to form a single atomic layer of aluminum oxide on both sides of the silicon wafer;

[0058] S12: placing the silicon wafer obtained in step S11 in an ALD deposition furnace, introducing ozone after heating, vacuuming, and leak detection. Under the high temperature environment, part of the silicon atoms in the silicon substrate pass through the film layer to reach the surface of the silicon wafer and react with the ozone to react on both sides of the aluminum oxide layer to obtain a second silicon oxide layer. The thickness of the second silicon oxide layer is 4 nm.

[0059] S13: The silicon wafer obtained in step S12 is placed in a PECVD precipitation furnace, and after heating, vacuuming, and leak detection, SiH 4 NH 3 , SiH in high temperature environment4 With NH 3 A reaction occurs, and a silicon nitride layer with a thickness of 75 nm is first deposited on the front side of the silicon wafer, and then a silicon nitride layer with a thickness of 75 nm is deposited on the back side of the silicon wafer.

[0060] Example 2

[0061] A film structure for improving UV attenuation of a TOPcon cell, and a preparation method thereof is as follows:

[0062] S1: Select an N-type silicon wafer and perform texturing on the front and back sides of the N-type silicon wafer so that the reflectivity of the front and back sides of the silicon wafer reaches 10.5%;

[0063] S2: Place the silicon wafer obtained in step S1 with the front side facing upward in a high-temperature quartz furnace tube, introduce boron chloride and oxygen into the high-temperature quartz furnace tube by boron diffusion, and react boron chloride, oxygen and Si atoms on the surface of the silicon wafer at 860° C. The reaction time is 100 min, and a BSG layer is formed on the front side of the N-type silicon wafer obtained in step S1. The thickness of the BSG layer is 30 nm, the volume flow rate of boron chloride is 230 sccm, and the volume flow rate of oxygen is 800 sccm;

[0064] S3: Then the silicon wafer obtained in step S2 is placed in a high-temperature diffusion furnace with the front side facing upward, and oxygen is introduced to form a silicon oxide protective layer on the surface of the BSG layer at 1045° C. The reaction time is 3800 s, the thickness of the silicon oxide protective layer is 90 nm, and the volume flow rate of oxygen is 25000 sccm;

[0065] S4: using a hydrofluoric acid aqueous solution to etch away the BSG layer formed by plating on the back and edge of the silicon wafer obtained in step S3, and polishing the back and edge of the silicon wafer, wherein the reflectivity after polishing reaches 46%;

[0066] S5: The back side of the silicon wafer obtained in step S4 is facing upwards, and the silicon wafer is subjected to the pecvd method using N 2 O radio frequency decomposition reaction, forming a silicon oxide tunneling layer on the back of the silicon wafer obtained in step S4, wherein the thickness of the silicon oxide tunneling layer is 2.5 nm;

[0067] S6: The back side of the silicon wafer obtained in step S5 is facing upward, and the silicon wafer is oxidized by SiH 4 , PH 3 Radio frequency decomposition reaction forms a p-poly layer on the surface of the silicon oxide tunneling layer on the back of the silicon wafer, wherein the thickness of the p-poly layer is 120 nm;

[0068] S7: The back side of the silicon wafer obtained in step S6 is facing upward, and the silicon wafer is subjected to the pecvd method using N 2 O、SiH 4A silicon oxide mask layer is deposited on the surface of the p-poly layer on the back of the silicon wafer by radio frequency decomposition reaction, wherein the thickness of the silicon oxide mask layer is 30 nm;

[0069] S8: placing the silicon wafer obtained in step S7 at a high temperature of 1000° C. and performing high temperature annealing treatment for 70 minutes under nitrogen protection;

[0070] S9: using a hydrofluoric acid aqueous solution to etch away the PSG layer formed by plating on the front and edge of the silicon wafer obtained in step S8, then placing the silicon wafer in an alkaline solution to remove the p-poly layer formed by plating on the front and edge of the silicon wafer, then placing the silicon wafer in a mixed solution of hydrofluoric acid and hydrochloric acid to etch away the silicon oxide protective layer on the front of the silicon wafer and the silicon oxide mask layer on the back of the silicon wafer, then taking out the silicon wafer, washing it with water, and drying it for later use;

[0071] S10: placing the silicon wafer obtained in step S9 in an ALD deposition furnace, introducing ozone after heating, vacuuming, and leak detection, and utilizing the strong oxidizing reaction of ozone to deposit a first silicon oxide layer on both sides of the silicon wafer, wherein the thickness of the first silicon oxide layer is 6 nm;

[0072] S11: placing the silicon wafer obtained in step S10 in an ALD deposition furnace, and after heating, vacuuming, and leak detection, first introducing TMA into the deposition furnace, and TMA is adsorbed on the surface of the silicon wafer to form a trimethylaluminum adsorption layer, and then introducing water vapor into the deposition furnace to react with the trimethylaluminum adsorption layer on the surface of the silicon wafer to form a single atomic layer of aluminum oxide on both sides of the silicon wafer;

[0073] S12: placing the silicon wafer obtained in step S11 in an ALD deposition furnace, and introducing ozone after heating, vacuuming, and leak detection. Under the high temperature environment, part of the silicon atoms in the silicon substrate passes through the film layer to reach the surface of the silicon wafer and react with the ozone to react on both sides of the aluminum oxide layer to obtain a second silicon oxide layer. The thickness of the second silicon oxide layer is 6nm.

[0074] S13: The silicon wafer obtained in step S12 is placed in a PECVD precipitation furnace, and after heating, vacuuming, and leak detection, SiH 4 NH 3 , SiH in high temperature environment 4 With NH 3 A reaction occurs, and a silicon nitride layer with a thickness of 80 nm is first deposited on the front side of the silicon wafer, and then a silicon nitride layer with a thickness of 80 nm is deposited on the back side of the silicon wafer.

[0075] Example 3

[0076] A film structure for improving UV attenuation of a TOPcon cell, and a preparation method thereof is as follows:

[0077] S1: Select an N-type silicon wafer and perform texturing on the front and back sides of the N-type silicon wafer so that the reflectivity of the front and back sides of the silicon wafer reaches 10%;

[0078] S2: The silicon wafer obtained in step S1 is placed in a high-temperature quartz furnace tube with the front side facing upwards. Boron chloride and oxygen are introduced into the high-temperature quartz furnace tube by boron diffusion. The boron chloride, oxygen and Si atoms on the surface of the silicon wafer react at 860° C. The reaction time is 77 minutes. A BSG layer is formed on the front side of the N-type silicon wafer obtained in step S1. The thickness of the BSG layer is 20 nm. The volume flow rate of boron chloride is 230 sccm, and the volume flow rate of oxygen is 800 sccm.

[0079] S3: Then the silicon wafer obtained in step S2 is placed in a high-temperature diffusion furnace with the front side facing upward, and oxygen is introduced to form a silicon oxide protective layer on the surface of the BSG layer at 1045°C. The reaction time is 3400s, the thickness of the silicon oxide protective layer is 80nm, and the volume flow rate of oxygen is 25000sccm;

[0080] S4: using a hydrofluoric acid aqueous solution to etch away the BSG layer formed by plating on the back and edge of the silicon wafer obtained in step S3, and polishing the back and edge of the silicon wafer, wherein the reflectivity after polishing reaches 45%;

[0081] S5: The back side of the silicon wafer obtained in step S4 is facing upwards, and the silicon wafer is subjected to the pecvd method using N 2 O radio frequency decomposition reaction, forming a silicon oxide tunneling layer on the back of the silicon wafer obtained in step S4, wherein the thickness of the silicon oxide tunneling layer is 1.5 nm;

[0082] S6: The back side of the silicon wafer obtained in step S5 is facing upward, and the silicon wafer is oxidized by SiH 4 , PH 3 Radio frequency decomposition reaction forms a p-poly layer on the surface of the silicon oxide tunneling layer on the back of the silicon wafer, and the thickness of the p-poly layer is 90nm;

[0083] S7: The back side of the silicon wafer obtained in step S6 is facing upward, and the silicon wafer is subjected to the pecvd method using N 2 O、SiH 4 A silicon oxide mask layer is deposited on the surface of the p-poly layer on the back of the silicon wafer by radio frequency decomposition reaction, wherein the thickness of the silicon oxide mask layer is 30 nm;

[0084] S8: placing the silicon wafer obtained in step S7 at a high temperature of 950° C. and performing high temperature annealing treatment for 60 minutes under nitrogen protection;

[0085] S9: using a hydrofluoric acid aqueous solution to etch away the PSG layer formed by plating on the front and edge of the silicon wafer obtained in step S8, then placing the silicon wafer in an alkaline solution to remove the p-poly layer formed by plating on the front and edge of the silicon wafer, then placing the silicon wafer in a mixed solution of hydrofluoric acid and hydrochloric acid to etch away the silicon oxide protective layer on the front of the silicon wafer and the silicon oxide mask layer on the back of the silicon wafer, then taking out the silicon wafer, washing it with water, and drying it for later use;

[0086] S10: placing the silicon wafer obtained in step S9 in an ALD deposition furnace, introducing ozone after heating, vacuuming, and leak detection, and utilizing the strong oxidizing reaction of ozone to deposit a first silicon oxide layer on both sides of the silicon wafer surface, wherein the thickness of the first silicon oxide layer is 5 nm;

[0087] S11: placing the silicon wafer obtained in step S10 in an ALD deposition furnace, and after heating, vacuuming, and leak detection, first introducing TMA into the deposition furnace, and TMA is adsorbed on the surface of the silicon wafer to form a trimethylaluminum adsorption layer, and then introducing water vapor into the deposition furnace to react with the trimethylaluminum adsorption layer on the surface of the silicon wafer to form a single atomic layer of aluminum oxide on both sides of the silicon wafer;

[0088] S12: placing the silicon wafer obtained in step S11 in an ALD deposition furnace, and introducing ozone after heating, vacuuming, and leak detection. Under the high temperature environment, part of the silicon atoms in the silicon substrate passes through the film layer to reach the surface of the silicon wafer and react with the ozone to react on both sides of the aluminum oxide layer to obtain a second silicon oxide layer. The thickness of the second silicon oxide layer is 5 nm.

[0089] S13: The silicon wafer obtained in step S12 is placed in a PECVD precipitation furnace, and after heating, vacuuming, and leak detection, SiH 4 NH 3 , SiH in high temperature environment 4 With NH 3 A reaction occurs, and a silicon nitride layer with a thickness of 75 nm is first deposited on the front side of the silicon wafer, and then a silicon nitride layer with a thickness of 75 nm is deposited on the back side of the silicon wafer.

[0090] Comparative Example 1 is the same as Example 1, except that step S10 is omitted in Comparative Example 1.

[0091] Comparative Example 2 is the same as Example 1, except that step S12 is omitted in Comparative Example 2.

[0092] Comparative Example 3 is the same as Example 1, except that step S13 is omitted in Comparative Example 3.

[0093] Comparative Example 4 is the same as Example 1, except that step S10 and step S12 are omitted in Comparative Example 4.

[0094] Comparative Example 5 is the same as Example 1, except that step S10, step S12 and step S13 are omitted in Comparative Example 5.

[0095] Performance Testing

[0096] The membrane structures obtained in the embodiments of the present invention and the comparative examples were connected with corresponding circuits to form TOPcon battery modules, and open circuit voltage attenuation performance tests and Eta efficiency attenuation tests were performed respectively. The specific test results are shown in Table 1.

[0097] Open circuit voltage attenuation: TOPcon battery modules are tested for open circuit voltage using the IEC61646 standard before and after UV irradiation in accordance with the IEC 61215 standard, confirming the open circuit voltage before and after and calculating the attenuation ratio.

[0098] Eta efficiency decay: TOPcon battery modules are tested for efficiency using the IEC61646 standard before and after UV irradiation in accordance with the IEC 61215 standard to confirm the efficiency before and after and calculate the decay ratio.

[0099] Table 1

[0100] Test items Open circuit voltage attenuation ratio (%) Eta efficiency attenuation ratio (%) Example 1 0.73％ 1.55％ Example 2 0.65％ 1.37％ Example 3 0.68％ 1.47％ Comparative Example 1 1.74％ 3.05％ Comparative Example 2 1.42％ 2.51％ Comparative Example 3 1.88％ 3.05％ Comparative Example 4 1.96％ 3.47％ Comparative Example 5 2.32％ 4.11％

[0101] As shown in Table 1, adding silicon oxide layers before and after the aluminum oxide layer can significantly improve the voltage and efficiency attenuation of the TOPcon battery module after UV irradiation. When the thickness of the silicon oxide layer is 4nm, 5nm, and 6nm, the voltage and efficiency attenuation ratios are similar. This shows that when the thickness of the silicon oxide layer is 4nm, the UV attenuation of the TOPcon battery module can be significantly reduced. The silicon oxide layer set outside the aluminum oxide layer is particularly important for reducing the attenuation of the TOPcon battery module after UV irradiation.

[0102] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A film structure for improving UV attenuation of TOPcon cells, characterized in that: Including N-type silicon wafer; The front side of the N-type silicon wafer is provided with a BSG layer, a first silicon oxide layer, an aluminum oxide layer, and a second silicon oxide layer in sequence from bottom to top; The back side of the N-type silicon wafer is provided with a silicon oxide tunneling layer, a phosphorus-doped polysilicon layer, a first silicon oxide layer, an aluminum oxide layer, and a second silicon oxide layer in sequence from top to bottom.

2. The film structure for improving UV attenuation of TOPcon cells according to claim 1, characterized in that: A silicon nitride layer is disposed on the surface of the second silicon oxide layer.

3. The film structure for improving UV attenuation of TOPcon cells according to claim 2, characterized in that: The thickness of the silicon nitride layer is 75-80 nm.

4. The film structure for improving UV attenuation of TOPcon cells according to claim 1, characterized in that: The thickness of the BSG layer is 20-30 nm.

5. The film structure for improving UV attenuation of TOPcon cells according to claim 1, characterized in that: The N-type silicon wafer is a double-sided texturing-treated N-type silicon wafer. After the texturing treatment, the reflectivity of the front and back sides of the silicon wafer is 9.5-10.5%.

6. The film structure for improving UV attenuation of TOPcon cells according to claim 1, characterized in that: The thickness of the first silicon oxide layer is 4-6 nm.

7. The film structure for improving UV attenuation of TOPcon cells according to claim 1, characterized in that: The thickness of the second silicon oxide layer is 4-6 nm.

8. The film structure for improving UV attenuation of TOPcon cells according to claim 1, characterized in that: The thickness of the silicon oxide tunneling layer is 0.5-2.5 nm.

9. The film structure for improving UV attenuation of TOPcon cells according to claim 1, characterized in that: The thickness of the p-poly layer is 70-120nm.

10. A film structure for improving UV attenuation of TOPcon cells according to any one of claims 1 to 9, characterized in that: The preparation method comprises the following steps: S1: Select an N-type silicon wafer and perform texturing on the front and back sides of the N-type silicon wafer so that the reflectivity of the front and back sides of the silicon wafer reaches 9.5-10.5%; S2: The silicon wafer obtained in step S1 is placed in a high-temperature quartz furnace tube with the front side facing upwards, and boron chloride and oxygen are introduced into the high-temperature quartz furnace tube by boron diffusion. In the high-temperature environment, boron chloride and oxygen react with Si atoms on the surface of the silicon wafer to form a BSG layer on the front side of the N-type silicon wafer obtained in step S1; S3: Then the silicon wafer obtained in step S2 is placed with the front side facing upward in a high-temperature diffusion furnace, oxygen is introduced, and a silicon oxide protective layer is formed on the surface of the BSG layer in a high-temperature environment; S4: using a hydrofluoric acid aqueous solution to etch away the BSG layer formed by plating on the back and edge of the silicon wafer obtained in step S3, and polishing the back and edge of the silicon wafer, wherein the reflectivity after polishing reaches 43-46%; S5: With the back side of the silicon wafer obtained in step S4 facing upward, a silicon oxide tunneling layer is formed on the back side of the silicon wafer obtained in step S4 by using a pecvd method and a radio frequency decomposition reaction of N2O; S6: With the back side of the silicon wafer obtained in step S5 facing upward, a p-poly layer is formed on the surface of the silicon oxide tunneling layer on the back side of the silicon wafer by using a pecvd method and a radio frequency decomposition reaction of SiH4 and PH3; S7: With the back side of the silicon wafer obtained in step S6 facing upward, a silicon oxide mask layer is deposited on the surface of the phosphorus-doped polysilicon layer on the back side of the silicon wafer by a pecvd method using a radio frequency decomposition reaction of N2O and SiH4; S8: placing the silicon wafer obtained in step S7 at a high temperature of more than 900° C. and performing high temperature annealing treatment under nitrogen protection; S9: using a hydrofluoric acid aqueous solution to etch away the PSG layer formed by plating on the front and edge of the silicon wafer obtained in step S8, then placing the silicon wafer in an alkaline solution to remove the p-poly layer formed by plating on the front and edge of the silicon wafer, then placing the silicon wafer in a mixed solution of hydrofluoric acid and hydrochloric acid to etch away the silicon oxide protective layer on the front of the silicon wafer and the silicon oxide mask layer on the back of the silicon wafer, then taking out the silicon wafer, washing it with water, and drying it for later use; S10: depositing a first silicon oxide layer on the surface of the silicon wafer obtained in step S9 by ALD deposition; S11: depositing a single atomic layer of aluminum oxide on the surface of the first silicon oxide layer by ALD deposition; S12: depositing a second silicon oxide layer on the surface of the aluminum oxide layer by an ALD deposition method; S13: By PECVD, a silicon nitride layer is first deposited on the front side of the silicon wafer, and then a silicon nitride layer is deposited on the back side of the silicon wafer.