Register for registering predicates

Abstract

Embodiments are provided for converting a bit mask from a compressed format to an extended format. The bit mask is stored in a storage register in a compressed format. The compressed format does not include placeholder bits. The compressed format includes a single bit defining each element of a vector. The sizes of the elements can vary according to data types, for example, each element has 4, 8 and 16 bytes. In a single microoperation, the bitmask of the compressed format is converted to an extended format. The extended bit mask may be written to a predicate register. The extended bit mask includes a plurality of placeholder bits (the placeholder bits are not used in computation). The size of the extended bit mask corresponds to the size of the definition vector, including a plurality of elements of the data type. The extended bit mask may be used to execute an instruction. For example, a vector processor multiplies a sparse matrix with the vector using the extended bit mask.

Description

Background Art

[0001] In some embodiments of the present disclosure, the present disclosure relates to processors, and more particularly, but not exclusively, to microinstructions for vector processors.

[0002] Some processor architectures are designed to execute a single instruction multiple data (SIMD) instruction set architecture (ISA). Such processor architectures designed to execute a SIMD ISA are sometimes referred to as vector processors. Vector processors are designed to reduce code size and / or the number of micro-operations executed while still operating on multiple data. Examples of vector processors include ARM Scalable Vector Extension (SVE) and Intel Advanced Vector eXtension (AVX). Summary of the invention

[0003] The object of the present invention is to provide a processor, a method, a computer program and a computer program product for converting a compressed bit mask into an extended bit mask.

[0004] According to a first aspect, a processor is used to: obtain a bit mask in a compressed format from a storage register, convert the bit mask from the compressed format to an extended format in a single micro-operation, and write the bit mask in the extended format to a predicate register for use as a predicate for executing an instruction.

[0005] According to a second aspect, a method performed by a processor comprises obtaining a bit mask in a compressed format from a storage register, converting the bit mask from a compressed format to an extended format in a single micro-operation, and writing the bit mask in the extended format into a predicate register for use as a predicate for executing an instruction.

[0006] According to a third aspect, a computer program comprises program instructions which, when executed by a processor, cause the processor to: retrieve a bit mask in a compressed format from a storage register, convert the bit mask from the compressed format to an extended format in a single micro-operation, and write the bit mask in the extended format into a predicate register for use as a predicate for executing an instruction.

[0007] According to a fourth aspect, a non-transitory medium stores program instructions which, when executed by a processor, cause the processor to: retrieve a bit mask in a compressed format from a storage register, convert the bit mask from a compressed format to an extended format in a single micro-operation, and write the bit mask in the extended format to a predicate register for use as a predicate for executing instructions.

[0008] Storing the bit mask in a compressed format and expanding the compressed bit mask when needed reduces the amount of memory used to store the bit mask. The amount of compression varies depending on the size of the elements of the expanded bit mask. For example, if a single bit of the compressed bit mask corresponds to an element of 8 bits of the expanded bit mask, the compression ratio is 8 times (8x).

[0009] Compared to using several lines of software code, a single micro-operation improves the computational efficiency of the processor by reducing overhead and / or improving hardware performance. For example, converting the bit mask in the compressed format to the bit mask in the extended format in a single micro-operation simplifies the conversion process and / or reduces errors compared to other methods where the programmer defines multiple complex bit operations.

[0010] In another implementation of the first aspect, the second aspect, the third aspect and the fourth aspect, the processor includes a vector processor, which is used to execute instructions defined by a single instruction multiple data (SIMD) instruction set architecture (ISA), and the processor is also used to obtain the bit mask in the extended format from the predicate register to execute instructions defined by the SIMD ISA.

[0011] The single micro-operation reduces the amount of memory used by the vector processor and / or increases the efficiency with which the vector processor executes the SIMD ISA.

[0012] In another implementation of the first aspect, the second aspect, the third aspect and the fourth aspect, the bit mask in the extended format includes multiple elements, wherein each element has some bits, and the some bits are defined by the data type represented by the element, and the element corresponds to the data type of the vector processed according to the bit mask; wherein the bit mask in the extended format includes a single bit and multiple placeholder bits for each element in a fixed position; wherein the bit mask in the compressed format includes multiple bits corresponding to the multiple elements, excluding placeholder bits.

[0013] The amount of memory saved by the bit mask in the compressed format is determined based on the data type. For example, for a vector array where each bit of the bit mask corresponds to a byte of data, the bit mask in the extended format uses eight times more memory than the bit mask in the compressed format.

[0014] In another implementation of the first aspect, the second aspect, the third aspect and the fourth aspect, the conversion includes: for each corresponding bit of the multiple bits of the bit mask in the compressed format: copying the corresponding bit to a fixed position within a corresponding element of the multiple elements of the bit mask in the extended format, and adding a placeholder bit for the corresponding element.

[0015] Such conversion may be computationally efficient and / or easily adaptable to different data types of the elements depending on the location of the fixed positions.

[0016] In another implementation of the first aspect, the second aspect, the third aspect and the fourth aspect, the predicate register is dynamically overwritten for each new bit mask.

[0017] The same predicate register into which the bit mask in the extended format is written can be reused for a newly calculated extended bit mask, rather than storing the extended bit mask in memory. For example, reusing the predicate register for a different extended bit mask (while storing the compressed bit mask in the storage register) can reduce the amount of memory required compared to storing the extended bit mask in memory.

[0018] In another implementation of the first aspect, the second aspect, the third aspect and the fourth aspect, the bit mask in the storage register is retained without being overwritten for each new bit mask, wherein different storage registers are used for new and different bit masks.

[0019] Multiple different bit masks can be stored in a storage register in a compressed format. The compressed format takes up less register memory than the expanded format.

[0020] In another implementation of the first aspect, the second aspect, the third aspect and the fourth aspect, the size of the predicate register is fixed relative to the size of the vector being processed by executing the instruction.

[0021] Fixing the size of the predicate register relative to the size of the vector may optimize the amount of memory allocated to the predicate register.

[0022] In another implementation of the first aspect, the second aspect, the third aspect and the fourth aspect, each single bit of the multiple single bits of the bit mask in the extended format corresponds to a single element of the multiple elements of the vector being processed by the processor, wherein the placeholder bits that do not include the multiple single bits of the bit mask in the extended format are written to the predicate register and are not used when processing the vector; the bit mask in the compressed format includes the multiple single bits and does not include the placeholder bits; some bits in each of the multiple elements are defined based on the data type represented by each element.

[0023] The amount of memory saved by the compressed format compared to the expanded format depends on the size of the vector and the data type of the elements of the vector.

[0024] In another implementation of the first aspect, the second aspect, the third aspect and the fourth aspect, it also includes: dynamically adjusting the size of the bit mask in the extended format and dynamically adjusting the size of each single element based on the size and data type of the current vector being processed.

[0025] Dynamically adjusting the size of the bit mask can efficiently allocate the required amount of memory.

[0026] In another implementation of the first aspect, the second aspect, the third aspect and the fourth aspect, the processor is further configured to multiply the sparse matrix by the vector according to the bit mask in the extended format.

[0027] A single micro-operation to obtain the bitmask in the extended format improves the efficiency of processors that use bitmasks to multiply sparse matrices with vectors.

[0028] In another implementation of the first aspect, the second aspect, the third aspect, and the fourth aspect, the bit mask includes a predicate.

[0029] The single micro-operation used to fetch the predicate in the extended format improves the efficiency of processors that execute instructions using the predicate.

[0030] Unless otherwise defined, the meaning of all technical and / or scientific terms used herein is the same as that known to those of ordinary skill in the art to which the present invention belongs. Although methods and materials similar or equivalent to the methods and materials described herein can be used in the practice or testing of embodiments of the present invention, exemplary methods and / or materials are described below. In the event of a conflict, this patent specification (including definitions) shall prevail. In addition, these materials, methods and examples are illustrative only and are not necessarily restrictive. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Some embodiments of the present invention are described herein by way of example only in conjunction with the accompanying drawings. Now specifically with reference to the accompanying drawings, it should be emphasized that the details shown are only for the purpose of illustration and for illustrative discussion of the embodiments of the present invention. In this regard, it will be apparent to those skilled in the art how to practice the embodiments of the present invention based on the accompanying drawings.

[0032] In the attached picture:

[0033] Figure 1 is a flow chart of a method of converting a compressed bit mask to an extended bit mask according to some embodiments;

[0034] Figure 2 is a block diagram of components of one or more processors for converting a compressed bit mask to an extended bit mask according to some embodiments;

[0035] Figure 3 are examples of compressed bit masks and expanded bit masks according to some embodiments of the present invention;

[0036] Figure 4 is a schematic diagram describing examples of compressed bit masks and extended bit masks according to some embodiments of the present invention;

[0037] Figure 5 is a diagram describing an example of pseudo code for converting a compressed bit mask to an extended bit mask according to some embodiments of the present invention. DETAILED DESCRIPTION

[0038] In some embodiments of the present disclosure, the present disclosure relates to processors, and more particularly, but not exclusively, to microinstructions for vector processors.

[0039] The terms bitmask and predicate are used herein interchangeably.

[0040] As used herein, the phrases compression bitmask and compressed format bitmask are interchangeable.

[0041] As used herein, the phrases extended bitmask and extended format bitmask are interchangeable.

[0042] An aspect of some embodiments relates to a processor, system, computing device, method and / or code instructions (stored on a memory and executed by one or more processors) for converting a bit mask from a compressed format to an extended format. The bit mask is stored in a storage register in a compressed format. The compressed format does not include a placeholder bit. The compressed format may include a single bit for each element of a definition vector. The size of the element may vary depending on the data type, such as 2, 4, 8, or 16 bytes per element. In a single micro-operation, the bit mask in the compressed format is converted to an extended format. The extended bit mask may be written to a predicate register. The extended bit mask includes a plurality of placeholder bits (the placeholder bits are not used in the calculation). The size of the extended bit mask corresponds to the size of the definition vector, including a plurality of elements of the data type. The extended bit mask may be used as a predicate for executing an instruction. For example, a vector processor uses an extended bit mask to multiply a sparse matrix with a definition vector.

[0043] Storing the bitmask in a compressed format and expanding the compressed bitmask when needed reduces the amount of memory used to store and / or write the bitmask. The amount of compression varies depending on the size of the elements of the expanded bitmask, e.g., a single bit of the compressed bitmask corresponding to an element of 8 bits of the expanded bitmask results in an 8-fold (8x) compression ratio.

[0044] A single micro-operation improves the computational efficiency of the processor by reducing overhead and / or improving hardware performance compared to using several lines of software code. For example, converting a bit mask in a compressed format to a bit mask in an extended format in a single micro-operation simplifies the conversion process and / or reduces errors compared to other methods where the programmer defines multiple complex bit operations. The overhead of converting a compressed bit mask to an extended bit mask is negligible.

[0045] A single micro-op executes in no more than two latency cycles, with a throughput of 1 on a single hardware execution unit. Latency is the number of processor (e.g., CPU) cycles (1 / frequency) it takes for the processor to complete a specific task. Throughput is the maximum number of times an instruction can be completed in one cycle. An execution unit is a single hardware block designed to perform a specific function or multiple functions.

[0046] At least some implementations described herein solve the technical problem of improving the efficiency of a processor (e.g., a vector processor) that uses predicates to control the effective elements of a vector (e.g., stored in a vector register) so as to be stored in a memory, executed and / or other operations defined by an ISA (e.g., a SIMD ISA), etc. This technical problem can be a memory that improves processor access. At least some implementations described herein improve the processor that uses predicates to control the effective elements of a vector register, etc. For example, this improvement can be to reduce the amount of memory used to store an extended predicate, and / or improve the operating efficiency of the processor, for example, to reduce the number of microinstructions executed.

[0047] Typically, the size of the predicate register is fixed relative to the SIMD vector length, and reserves 1 bit for each byte of the SIMD vector, so that element-wise predicated expressions can be performed for elements of size 1 byte or more.

[0048] When used to control larger element sizes, the predicate register requires a single bit per element. In some SIMD ISAs, the position of the single bit used to control larger elements is aligned with the least significant byte position of the element, which requires padding of redundant bits between the actual mask bits. For example, in an ARM SVE using predicates for double precision floating point operations (8-byte elements), the predicate byte contains eight bits per element, but the predicate register requires only a single bit per element.

[0049] In some ISAs (e.g., Intel AVX512), predicates are represented with the exact number of bits required, solving the above problem in a different way.

[0050] For ISAs that keep predicates at a fixed size and use the predicate bits in the least significant byte position of an element, there are no direct instructions to unpack the predicate byte or word into the element bit position in the predicate register. This leaves the software developer with one of the following alternatives:

[0051] -Store predicate values ​​in full predicate format (i.e., extended state).

[0052] - Read the predicate in a compressed state from the memory and decompress (ie, expand) the compressed predicate using bit manipulation instructions.

[0053] This operation may require more instructions, resulting in larger code size, longer processing time, and / or room for coding errors.

[0054] In summary, existing methods require higher memory bandwidth, and / or require larger code size and / or more computational overhead, which reduces processor performance compared to the embodiments described herein.

[0055] Before explaining at least one embodiment of the present invention in detail, it should be understood that the present invention is not necessarily limited in its application to the details of the structure and arrangement of the components and / or methods set forth in the following description and / or illustrated in the drawings and / or examples. The present invention may have other embodiments or may be practiced or implemented in various ways.

[0056] The present invention may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions, which cause a processor to perform various aspects of the present invention.

[0057] Computer readable storage media may be tangible devices that can retain and store instructions for use by instruction execution devices. Computer readable storage media may be, for example but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the above devices.

[0058] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network such as the Internet, a local area network, a wide area network, and / or a wireless network.

[0059] The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, partially on the user's computer as a stand-alone software package, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), and may also be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits including programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may be executed to personalize the electronic circuits by utilizing the state information of the computer-readable program instructions to execute computer-readable program instructions to perform various aspects of the present invention.

[0060] Various aspects of the present invention are described herein in conjunction with flowchart illustrations and / or block diagrams of methods, devices (systems) and computer program products provided in accordance with embodiments of the present invention. It should be understood that each block of the flowchart illustration and / or block diagram and the combination of blocks in the flowchart illustration and / or block diagram can be implemented by computer-readable program instructions.

[0061] The flowchart and block diagram in the figure illustrate the architecture, function and operation of the possible implementation of the system, method and computer program product provided by various embodiments of the present invention. In this regard, each block in the flowchart or block diagram can represent a module, a segment or a portion of instructions, including one or more executable instructions for implementing one or more specified logical functions. In some alternative implementations, the functions described in the blocks may not be implemented in the order described in the figure. For example, in fact, two blocks shown in succession can be executed almost simultaneously, or sometimes in the opposite order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart and the combination of blocks in the block diagram and / or flowchart can be implemented by a dedicated hardware-based system that performs specific functions or actions, or performs a combination of dedicated hardware and computer instructions.

[0062] Reference now Figure 1 , which is a flowchart of a method for converting a compressed bit mask to an extended bit mask according to some embodiments. Figure 2 , which is a block diagram of components of one or more processors 202 for converting a compressed bit mask 252 to an extended bit mask 256 according to some embodiments. Figure 3 , which is an example of a compressed bit mask and an expanded bit mask according to some embodiments of the present invention. Figure 4 , which is a schematic diagram describing examples of compression bit masks and expansion bit masks according to some embodiments of the present invention. Figure 5 , which is a schematic diagram describing an example of pseudo code 500 for converting a compressed bit mask into an extended bit mask according to some embodiments of the present invention. The system 200 may be implemented with reference to Figure 1 and / or Figures 3 to 5 The actions of the method are described by executing microcode instructions 206A by one or more processors 202 of computing device 204 .

[0063] One or more processors 202 access storage registers 250 storing compressed bitmasks 252 and predicate registers 254 storing expanded bitmasks 256. There may be multiple storage registers 250, each storing a different bitmask 252. One or more processors 202 may access vector registers 258 storing vector data 260 (e.g., obtained from data 216A), i.e., the actual data being processed.

[0064] In an ISA, such as a SIMD ISA that uses predicates, a bit mask may be referred to as a predicate. Predicate register 254 may be referred to as a predicate register that stores predicates in an extended format (i.e., an extended bit mask). Predicates 256 in predicate register 254 may control the computational behavior of each element, such as controlling and / or selecting valid elements of vector data 260 stored in vector register 258 for use in memory, execution, and / or other types of SIMD ISAs, etc.

[0065] One or more processors 202 may be implemented as vector processors, for example, designed to execute a SIMD ISA.

[0066] For example, the processor 202 may be implemented as one or more central processing units (CPUs), one or more graphics processing units (GPUs), one or more field programmable gate arrays (FPGAs), one or more digital signal processors (DSPs), one or more application specific integrated circuits (ASICs), one or more custom circuits, processors for interfacing with other units, and / or dedicated hardware accelerators. The one or more processors 202 may be implemented as a single processor, a multi-core processor, and / or a processor cluster arranged for parallel processing (which may include homogeneous and / or heterogeneous processor architectures). Other examples of the one or more processors 202 include ARM-based products and X86 from Intel or AMD.

[0067] The one or more processors 202 execute microcode instructions 206A, such as a single microinstruction to convert a compressed bit mask to an extended bit mask, as described herein.

[0068] One or more processors 202 may execute code 206B stored on memory 206 .

[0069] One or more processors 202 may be included within computing device 204 .

[0070] For example, computing device 204 may be implemented as one or more of: a computing cloud, a cloud network, a computer network, one or more virtual machines (e.g., hypervisors, virtual servers), a network node (e.g., a switch, a virtual network, a router, a virtual router), a single computing device (e.g., a user terminal), a group of computing devices arranged in parallel, a network server, a web server, a storage server, a local server, a remote server, a user terminal, a mobile device, a fixed device, an information kiosk, a smartphone, a laptop, a tablet computer, a wearable computing device, an eyeglass computing device, a watch computing device, and a desktop computer.

[0071] One or more processors 202 and / or computing devices 204 may be implemented as a high-performance computer (HPC) (e.g., a processing core and / or a system-on-chip (SoC)) that may perform software applications using sparse matrix-vector (SPMV) multiplication. SPMV is a fundamental and / or useful calculation in HPC applications. SPMV generates a vector result by multiplying a matrix with a vector, typically a highly sparse matrix and a dense vector stored in a compressed format in memory.

[0072] The memory 206 stores code instructions that can be executed by one or more processors 202, such as random access memory (RAM), dynamic random access memory (DRAM) and / or storage class memory (SCM), non-volatile memory, magnetic media, semiconductor storage devices, hard disk drives, removable storage, and optical media (e.g., DVD, CD-ROM). For example, the memory 206 may store one or more of the following: when one or more processors 202 execute, the storage register 250 storing the compressed bit mask 252 and / or the predicate register 254 storing the extended bit mask 256, the microcode instructions 206A and / or the code 206B implement the reference Figure 1 One or more features and / or actions of a described method.

[0073] The computing device 204 may include a data storage device 216 for storing data, such as data 216A processed using the extended bit mask 256, such as a compressed matrix for multiplying a vector (e.g., a dense vector). For example, the data storage device 216 can be implemented as a memory, a local hard drive, a virtual storage, a removable storage unit, an optical disk, a storage device, and / or a remote server and / or a computing cloud (e.g., accessed using a network connection).

[0074] The computing device 204 may include a network interface 218 for connecting to the network 214, such as one or more of a network interface card, a wireless interface for connecting to a wireless network, a physical interface for connecting to a cable to achieve network connectivity, a virtual interface implemented in software, network communication software providing higher-layer network connectivity, and / or other implementations.

[0075] For example, the network 214 may be implemented as the Internet, a local area network, a virtual private network, a wireless network, a cellular network, a local bus, a point-to-point link (eg, wired), and / or a combination of the above.

[0076] The computing device 204 may be connected to one or more servers 210 and / or one or more user terminals 212 using a network 214 (or another communication channel, such as via a direct link (e.g., cable, wireless) and / or an indirect link (e.g., through an intermediate computing unit such as a server and / or through a storage device)).

[0077] The computing device 204 may include and / or be in communication with one or more physical user interfaces 208 (including mechanisms for a user to input data and / or view data). For example, exemplary user interfaces 208 include one or more of a touch screen, a display, a keyboard, a mouse, and voice-activated software using a speaker and a microphone.

[0078] Now refer back to Figure 1 At 102, the processor obtains a bit mask in a compressed format. The compressed bit mask may be obtained from a storage register.

[0079] Optionally, the bitmask represents a predicate, for example, used by a vector processor to control execution of instructions based on individual elements of a vector.As described herein, a single micro-operation for obtaining a predicate in an extended format improves the efficiency of a processor that executes instructions using a predicate.

[0080] At 104, the processor converts the bit mask from a compressed format to an expanded format in a single micro-operation.

[0081] Now refer back to Figure 3 , describing an example of decompressing a bit mask for a vector of length 512 bits and having 8 type elements.

[0082] The total length of the original vector 302 is 512 bits. The vector 302 includes 8 elements, each of which is 8 bytes in size and / or 64 bits in size, for storing numbers of type "double precision". In order to make the explanation simpler and clearer, a single element 302A is marked. For example purposes only, the value of the vector 302 is A0BC00DE, where each letter or zero value is a single element.

[0083] The compression bit mask 304 (and optionally the predicate) associated with the vector 302 has a length of a number of bits corresponding to the number of elements of the vector 302. That is, a single bit of the bit mask is assigned to each element of the vector 302. In this example, the length of the compression bit mask 304 is 8 bits, corresponding to the 8 elements of the vector 302. A bit value of one is assigned to the non-zero values ​​of the vector 302, and a value of zero is assigned to the zero value of the vector 302. Thus, the following bits of the bit mask 304 are assigned to the corresponding elements of the vector 302: 1→A; 0→0; 1→B; 1→C; 0→0; 0→0; 1→D; 1→E. The compression bit mask 304 does not include placeholder bits.

[0084] The compressed bit mask 306 may be stored in a storage register in a single type as 10110011. The compressed bit mask 306 does not include placeholder bits.

[0085] The compressed bit mask 306 may be expanded into the extended bit mask 308 as described herein.

[0086] The extended bit mask 308 includes a plurality of elements (one element 308A is labeled to make the explanation simpler and clearer), for example, representing a complete predicate of double precision used with the SVE instruction. The number of elements corresponds to the number of elements of the vector 302, for example 8 as shown in the example. Some bits of each element of the bit mask 308 are defined by the data type represented by the element, which corresponds to the data type of the vector 302 processed according to the bit mask. In the example shown, each element of the extended bit mask 308 includes 8 bits. Each element of the extended bit mask 308 may include a single valid bit having a value of zero or one (one bit 310 is shown to make the explanation simpler and clearer) and a plurality of placeholder bits (a set of placeholder bits 312 is shown to make the explanation simpler and clearer). Each valid bit of each element of the extended bit mask 308 corresponds to one byte of each element of the vector 302. The placeholder bits are shown as having a value of "x", indicating that the actual value does not matter because the actual value of the placeholder bits is not used for control instructions. For instance, in the example shown, each element 308A of the extended bit mask 308 includes a single bit 310 and seven placeholder bits 312 .

[0087] The amount of memory saved by the bit mask in compressed format is determined according to the data type, i.e., according to the length of each element of the vector associated with the bit mask. In the example shown, for a vector 302 in which each bit of the compressed bit mask corresponds to a byte of data of the extended bit mask, the bit mask in the extended format uses 8 times more memory than the bit mask in the compressed format.

[0088] Each single valid bit 310 of the extended bit mask 308 corresponds to a single element 302A of the vector 302 being processed by the processor. A placeholder bit 312 that does not include the valid single bit 310 of the extended bit mask 308 can be written to the predicate register. The placeholder bit 312 is not used in the processing vector 302. The compressed bit mask 306 includes a valid single bit and does not include a placeholder bit. Some bits in each element 308A of the extended bit mask 308 are defined based on the data type represented by each element, for example, the double-precision number shown in the example is 8 bytes (64 bits). Compared with the extended format, the amount of memory saved by the compressed format depends on the size of the vector and the data type of the elements of the vector.

[0089] Now refer back to Figure 4 , the compressed bit mask 404 stored in the storage register is converted to an extended bit mask 408, as described herein. Each element in the compressed bit mask 404 is 8 bits. The compressed bit mask 404 is 64 bits in total. The data element itself is 64 bits, but this is in the data vector. The compressed bit mask 404 includes 8 elements, each of which is 64 bits in size, i.e., 8 bytes, such as for representing double-precision numbers. The values ​​from the most significant bit (MSB) to the least significant bit (LSB) are shown in hexadecimal notation as follows: AF, 54, 77, C2, A5, A0, 21, and 87. In order to make the explanation simpler and clearer, an extension of the compressed element 404A with the value A5 is shown. The compressed element 404A is shown as an index value 3, i.e., Imm4=3. An extended bit mask 408 for the compressed element 404A is shown. The extended bit mask 408 for the compressed element 404A includes 8 elements represented in hexadecimal notation, where the LSB indicates a valid bit and the bits to the left of the valid bit are placeholder bits set to zero. Therefore, the compressed element 404A having a binary value of 10100101, i.e., A5, expands to 0100010000010001 in hexadecimal or: 000000010000000000000001000000000000000000000010000000000000000001 in binary.

[0090] This process is iterated (using different index values) for each element of the compressed bitmask 404 to obtain the fully expanded bitmask. The expansion may be performed using the pseudocode function R2DEP (ie, Register to Predicate) described herein, optionally as a single microinstruction.

[0091] Now refer back to Figure 5 , the pseudocode 500 is described in a vector agnostic manner and in the ARM assembly style, but it should be understood that the pseudocode can be applied to any different assembly and vector specific ISA.

[0092] Line 502 defines a pseudo-code function called R2PDEP (register to predicate) for converting a compressed bit mask stored in a storage register denoted as Xn to an extended bit mask for writing to a predicate register denoted as Pd. An index called Imm4 may be set to define the size of the elements of the extended bit mask.

[0093] Line 504 sets the size of each element. The size of each element can be set according to the data type represented by the element, for example, a double precision number is 64 bits (8 bytes).

[0094] Line 506 sets the number of elements. The number of elements is obtained by dividing the total length of the vector (denoted as VL) by the size of each element.

[0095] Line 508 sets the index of the number of elements.

[0096] Line 510 initializes all bits of the predicate register as placeholder bits, eg, sets all bits to zero.

[0097] Line 512 defines a loop over the number of elements.

[0098] Line 514 copies the compressed predicate bits to fixed positions in the predicate register. The copied bits are used as valid bits. The non-copied bits that were previously set to zero are used as placeholder bits.

[0099] Now refer back to 104, describe another exemplary process for converting the compressed bit mask to the extended bit mask. For each corresponding bit of the compressed bit mask: the processor copies the corresponding bit to a fixed position in the corresponding element of the multiple elements of the extended format bit mask. The copied bit in the corresponding element can be copied to a fixed position. The copied bit in the corresponding element represents a valid bit. A placeholder bit can be added to each corresponding element. Alternatively, the placeholder bit is not actively added, but already exists. The processor can dynamically adjust the size of the extended bit mask and / or dynamically adjust the size of each element of the extended bit mask according to the size and / or data type of the current vector being processed. Dynamically adjusting the size of the bit mask can effectively allocate the required amount of memory.

[0100] This conversion is computationally efficient and / or easily adaptable to different data types of the elements, depending on the position of the fixed position.

[0101] At 106, the extended bit mask may be written to the predicate register. The bit mask of the predicate register may be implemented as a predicate associated with the vector. Each valid bit of the predicate may control the execution of an instruction for a corresponding element of the vector. The size of the predicate register may be fixed relative to the size of the vector. Fixing the size of the predicate register relative to the size of the vector may optimize the amount of memory allocated to the predicate register.

[0102] At 108, the processor uses the extended bit mask in the predicate register as a predicate to control execution of the instruction.

[0103] Optionally, the processor multiplies the sparse matrix with the vector according to the extended format bit mask, for example, using a block or bit mask column row sparse matrix compression. A single micro-operation for obtaining the bit mask of the extended format improves the efficiency of the processor using the bit mask to multiply the sparse matrix with the vector. For example, the processor is implemented as a vector processor that executes instructions defined by the SIMD ISA. The processor obtains the extended format bit mask from the predicate register for executing the instructions defined by the SIMD ISA. The single micro-operation reduces the amount of memory used by the vector processor, and / or improves the efficiency of the vector processor in executing the SIMD ISA.

[0104] At 110 , one or more features described with reference to 102 to 108 are iterated.

[0105] There may be multiple storage registers, each with a different compression bit mask, e.g., for different vectors. The compressed format occupies less memory in the register than the extended format. Optionally, during each iteration, the compression bit mask in the storage register that was extended in the previous iteration is retrained. The compression bit mask in the storage register that was extended in the previous iteration is not overwritten by the new bit mask during the current iteration. The new different bit mask uses a different storage register.

[0106] During each iteration, the relevant compression bitmask is extended into the predicate register without overwriting the compression bitmask stored in the storage register.

[0107] During each iteration, the predicate register may be dynamically overwritten with a new bit mask that is expanded during the current iteration. The same predicate register into which the bit mask in the expanded format is written can be reused for the newly calculated expanded bit mask, rather than storing the expanded bit mask in memory. For example, reusing the predicate register for a different expanded bit mask (while storing the compressed bit mask in a storage register) can reduce the amount of memory required compared to storing the expanded bit mask in memory.

[0108] The inventors have conducted experiments based on the embodiments described herein to evaluate the performance of a processor that executes instructions including converting a compressed bit mask to an extended bit mask. Compared with using other existing methods to solve the same problem, using the embodiments described herein can improve processor performance by about 20-50%.

[0109] Other systems, methods, features and advantages of the present invention will be or become apparent to those skilled in the art after studying the following drawings and detailed description. It is intended that all such other systems, methods, features and advantages be included in this description, within the scope of the present invention, and protected by the accompanying claims.

[0110] The description of the various embodiments of the present invention is for illustrative purposes only, and these descriptions are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles, practical applications, or technological advances of the embodiments, or to enable other persons skilled in the art to understand the embodiments disclosed herein, compared to the technologies available on the market.

[0111] It is expected that during the life of a patent that matures from this application, many related processors will be developed, and the scope of the term "processor" is intended a priori to include all such new technologies.

[0112] As used herein, the term "about" refers to ± 10%.

[0113] The terms "including," "having," and variations thereof mean "including but not limited to." This term encompasses the terms "consisting of" and "consisting essentially of.

[0114] The phrase "consisting essentially of" means that the composition or method may include additional ingredients and / or steps, but only if the additional ingredients and / or steps do not materially alter the basic and novel characteristics of the claimed composition or method.

[0115] As used herein, the singular forms "a", "an" and "the" include plural references unless the context clearly indicates otherwise. For example, the term "a compound" or "at least one compound" may include a plurality of compounds, including mixtures thereof.

[0116] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and / or to exclude the incorporation of features of other embodiments.

[0117] The word “optionally” is used herein to mean “is provided in some embodiments and not provided in other embodiments.” Unless multiple “optional” features conflict, any particular embodiment of the present invention may include those features.

[0118] In the present application, various embodiments of the present invention can be presented in range format. It should be understood that the description of the range format is only for convenience and brevity, and should not be interpreted as a fixed limitation on the scope of the present invention. Therefore, the description of the range should be considered to have specifically disclosed all possible sub-ranges and individual numerical values ​​within the range. For example, the description of a range such as from 1 to 6 should be considered to have specifically disclosed sub-ranges from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc. and individual numbers within the range, such as 1, 2, 3, 4, 5 and 6. No matter how wide the range is, this applies.

[0119] When a numerical range is indicated herein, it is meant to include any listed numerals (fractional or integer) within the indicated range. The phrases "range between a first indicated number and a second indicated number" and "range from a first indicated number to a second indicated number" are used interchangeably herein to include the first indicated number and the second indicated number and all fractions and integers between the two.

[0120] It should be understood that certain features of the present invention described in the context of a separate embodiment for the sake of clarity may also be provided in a single embodiment by combination. Conversely, for the sake of brevity, various features of the present invention described in the context of a single embodiment may also be provided individually or in any suitable sub-combination or as any suitable other embodiment of the present invention. Some features described in the context of various embodiments are not considered to be essential features of these embodiments, unless the embodiment is inoperable without these elements.

[0121] The purpose of the applicant is that all publications, patents and patent applications mentioned in this specification are incorporated into this specification by reference in their entirety, just as each individual publication, patent or patent application is specifically and individually indicated when it is mentioned to be incorporated by reference herein. In addition, the citation or identification of any reference in this application should not be construed as an admission that the reference is available as a prior art of the present invention. With regard to the use of section headings, section headings should not be construed as necessary limitations. In addition, any one or more priority documents of the present application are incorporated into this application by reference in their entirety.

Claims

1. A processor (202), characterized in that: Used for: Obtaining a bit mask (252) in a compressed format from a storage register (250); In a single micro-operation (500), converting the bit mask from the compressed format to an expanded format; The bit mask in the extended format is written into a predicate register (254) for use as a predicate for executing instructions.

2. The processor according to claim 1, characterized in that The processor includes a vector processor, wherein the vector processor is used to execute instructions defined by a single instruction multiple data (SIMD) instruction set architecture (ISA), and the processor is also used to obtain the bit mask in the extended format from the predicate register to execute instructions defined by the SIMD ISA.

3. A processor according to any one of the preceding claims, characterized in that The bit mask in the extended format comprises a plurality of elements (308A), wherein each element has a number of bits defined by a data type represented by the element, the element corresponding to the data type of the vector processed according to the bit mask, The bit mask of the extended format includes a single bit (310) for each element in a fixed position and a plurality of placeholder bits (312); The bit mask in the compressed format includes a plurality of bits corresponding to the plurality of elements, excluding placeholder bits.

4. A processor according to any one of the preceding claims, It is characterized in that The conversion includes: For each corresponding bit in the plurality of bits of the bit mask of the compressed format: copying the corresponding bits to fixed positions within corresponding ones of the plurality of elements of the bit mask in the extended format (514); A placeholder bit for the corresponding element is added (510).

5. A processor according to any one of the preceding claims, characterized in that The predicate register is dynamically overwritten for each new bit mask.

6. A processor according to any one of the preceding claims, characterized in that The bit mask in the storage register is retained without being overwritten for each new bit mask, wherein a different storage register is used for a new, different bit mask.

7. A processor according to any one of the preceding claims, characterized in that The size of the predicate register is fixed relative to the size of the vector being processed by executing the instruction.

8. A processor according to any one of the preceding claims, characterized in that Each of the plurality of single bits of the bit mask in the extended format corresponds to a single element (302A) of a plurality of elements of a vector (302) being processed by the processor, wherein placeholder bits excluding the plurality of single bits of the bit mask in the extended format are written to the predicate register and are not used when processing the vector; the bit mask in the compressed format includes the plurality of single bits excluding the placeholder bits; and some of the bits in each of the plurality of elements are defined based on a data type represented by each element.

9. The processor according to claim 8, characterized in that Also includes: The bit mask in the extended format is dynamically sized, and each individual element is dynamically sized, depending on the size and data type of the current vector being processed.

10. The processor according to claim 8 or 9, characterized in that: The processor is further configured to multiply a sparse matrix and the vector according to the bit mask in the extended format.

11. A processor according to any one of the preceding claims, characterized in that The bitmask includes a predicate.

12. A method executed by a processor, characterized in that: include: Get the bit mask in compressed format from the storage register (102); In a single micro-operation, converting the bit mask from a compressed format to an expanded format (104); The bit mask in the extended format is written into a predicate register (106) for use as a predicate (108) for executing an instruction.

13. A computer program comprising program instructions (206A), characterized in that The program instructions (206A), when executed by a processor (202), cause the processor to: Get the bit mask in packed format from the storage register; converting the bit mask from a compressed format to an expanded format in a single micro-operation; The bit mask in the extended format is written into a predicate register for use as a predicate for executing instructions.

14. A non-transitory medium (206) storing program instructions (206A), characterized in that: The program instructions (206A), when executed by the processor (202), cause the processor (202) to: Get the bit mask in packed format from the storage register; converting the bit mask from the compressed format to an expanded format in a single micro-operation; The bit mask in the extended format is written into a predicate register for use as a predicate for executing instructions.

Images