Light detection device

Abstract

The invention provides a light detection device which is low in cost and has large signal detection capability. The light detection device includes a first semiconductor substrate including a first semiconductor layer and a second semiconductor layer stacked on each other. The first semiconductor layer includes a photoelectric conversion region and a floating diffusion region for accumulating charges generated by photoelectric conversion in the photoelectric conversion region, and the second semiconductor layer includes a capacitor for accumulating charges generated by photoelectric conversion in the photoelectric conversion region.

Description

Technical Field

[0001] The invention relates to a light detection device. Background Art

[0002] In order to improve the sensitivity of complementary metal oxide semiconductor (CMOS) solid-state imaging devices, it is desirable to provide a structure capable of accumulating more signal charges generated in a photoelectric converter (photoreceiver). Based on this background, a structure in which a capacitor for accumulating signal charges is provided in addition to a floating diffusion capacitor (FD) has been proposed (see Patent Document 1).

[0003] The solid-state imaging device disclosed in Patent Document 1 includes: a first substrate including a photoelectric conversion element; and a second substrate located on the side of the first substrate opposite to the light incident surface of the photoelectric conversion element and including a capacitor for accumulating charges transferred from the photoelectric conversion element. Citation List Patent Literature

[0004] Patent Document 1: Japanese Patent Application Publication No. 2020-47734 Summary of the invention Problems to be solved by the present invention

[0005] According to Patent Document 1, by accumulating the charge transferred from the photoelectric conversion element through the capacitor provided in the second substrate, it is possible to increase the signal detection capability and expand the dynamic range.

[0006] However, as disclosed in Patent Document 1, a second substrate including a capacitor needs to be provided separately from a first substrate including a photoelectric conversion element, which complicates the manufacturing process and makes it difficult to reduce the manufacturing cost.

[0007] Therefore, an object of the present invention is to provide a light detection device capable of improving sensitivity without complicating the structure. Solution to the problem

[0008] In order to solve the above problem, the present invention provides a light detection device, which includes a first semiconductor substrate, wherein the first semiconductor substrate includes a first semiconductor layer and a second semiconductor layer stacked on each other, wherein: The first semiconductor layer includes a photoelectric conversion region and a floating diffusion region that accumulates charges generated by photoelectric conversion in the photoelectric conversion region, and The second semiconductor layer includes a capacitor that accumulates charges generated by photoelectric conversion in the photoelectric conversion region.

[0009] The second semiconductor layer may include a gate electrode of a transfer transistor that transfers charges generated by photoelectric conversion in the photoelectric conversion region to the floating diffusion region. The capacitor may include a first electrode, a second electrode arranged facing the first electrode, and a dielectric arranged between the first electrode and the second electrode, and the first electrode and the second electrode may be arranged at a layer height between the same layer height as the gate electrode and the same layer height as a wiring layer connected to the gate electrode through a contact portion.

[0010] The first electrode may be arranged at the same layer height as the gate electrode, and the second electrode may be arranged at the same layer height as the wiring layer.

[0011] The first electrode may be arranged at the same layer height as the gate electrode, and The second electrode may be arranged between the gate electrode and the wiring layer.

[0012] The first electrode may be arranged between the gate electrode and the wiring layer, and The second electrode may be arranged at the same layer height as the wiring layer.

[0013] The first electrode and the second electrode may be arranged between the wiring layer and the gate electrode.

[0014] The first electrode and the second electrode may have concavo-convex portions that mesh with each other, and a gap may be provided between facing surfaces of the first electrode and the second electrode.

[0015] The dielectric may include an insulating material different from an etch stop layer disposed between the wiring layer and the gate electrode.

[0016] The dielectric may include the same insulating material as an etch stop layer disposed between the wiring layer and the gate electrode.

[0017] The gate electrode, the wiring layer, the first electrode, and the second electrode may include polysilicon.

[0018] The first electrode may be set to a predetermined negative potential.

[0019] One of the first electrode or the second electrode may include a columnar member extending in a depth direction of the second semiconductor layer, and The other of the first electrode or the second electrode may include a cylindrical member covering at least a side surface of the one electrode via the dielectric.

[0020] The first electrode and the second electrode may extend in a depth direction of the second semiconductor layer.

[0021] Opposing surfaces of the first electrode and the second electrode may be arranged in a depth direction of the second semiconductor layer.

[0022] The two electrodes of the capacitor may be arranged substantially in parallel in a plan view in the region of the pixel.

[0023] The first semiconductor layer may include: a plurality of pixels, each of the pixels having the photoelectric conversion region, and a pixel boundary region arranged between two pixels adjacent to each other among the plurality of pixels, and The capacitor may be arranged in a region coinciding with each of the pixels in a plan view.

[0024] The first semiconductor layer may include: a plurality of pixels, each of the pixels having the photoelectric conversion region, and a pixel boundary region arranged between two pixels adjacent to each other among the plurality of pixels, and The capacitor may be arranged in a region coinciding with the pixel boundary region in a plan view.

[0025] The second semiconductor layer may include a switching transistor which switches whether to transfer charges accumulated in the floating diffusion region to the capacitor.

[0026] A second semiconductor substrate may be further provided, which is arranged on a side of the first semiconductor substrate opposite to the light incident surface and processes a pixel signal corresponding to the charge generated by photoelectric conversion in the photoelectric conversion region.

[0027] Opposing surfaces of the first semiconductor substrate and the second semiconductor substrate may be bonded to each other through contacts between pads, through-hole interconnections, or bumps. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a block diagram showing a schematic configuration example of an embodiment of a solid-state imaging device to which the present technology is applied. Figure 2 is a circuit diagram showing a schematic configuration example of a unit pixel in an effective pixel area. Figure 3 is a cross-sectional diagram showing an example of a cross-sectional structure of a unit pixel. Figure 4 is a plan view showing the arrangement of capacitors in a pixel. Figure 5 is an enlarged cross-sectional view showing an example of a cross-sectional structure of a unit pixel according to the second embodiment. Figure 6 is a plan view showing the arrangement of capacitors in a pixel according to the second embodiment. Figure 7 is an enlarged cross-sectional view showing an example of a cross-sectional structure of a unit pixel according to the third embodiment. Figure 8 is an enlarged cross-sectional view showing an example of a cross-sectional structure of a unit pixel according to the fourth embodiment. Fig. 9 is a cross-sectional diagram showing an example of a cross-sectional structure of a unit pixel according to the fifth embodiment. Fig.10 is an enlarged cross-sectional view showing an example of a cross-sectional structure of a unit pixel according to the sixth embodiment. Fig.11 is a plan view showing the shape and arrangement of capacitors in a pixel according to the seventh embodiment. Fig.12 is an enlarged cross-sectional diagram showing an example of a cross-sectional structure of a unit pixel according to the eighth embodiment. Fig.13 is an enlarged cross-sectional view showing an example of a cross-sectional structure of a capacitor according to an eighth embodiment. Fig.14 is a plan view showing the arrangement of capacitors in a pixel according to the eighth embodiment. Fig.15 is an enlarged cross-sectional diagram showing an example of a cross-sectional structure of a unit pixel according to the ninth embodiment. Fig.16 is a plan view showing the arrangement of capacitors in a pixel according to the ninth embodiment. Fig.17 is a plan view showing the arrangement of capacitors in a pixel according to the tenth embodiment. Fig.18 is a block diagram showing a schematic configuration example of a vehicle control system. Fig.19 1 is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection section and the imaging section. DETAILED DESCRIPTION

[0029] In the following, embodiments of the light detection device will be described with reference to the accompanying drawings. The main components of the light detection device will be described below, but the light detection device may have components and functions that are not shown or described. The following description is not intended to exclude components and functions that are not shown or described.

[0030] "First Embodiment" <Schematic Configuration Example of Solid-State Imaging Device> Figure 1 : is a block diagram showing a schematic configuration example of an embodiment of a solid-state imaging device to which the present technology is applied. The CMOS solid-state imaging device according to the first embodiment is an electronic device including a light detection device to which the present technology is applied. Note that in the following description, the CMOS solid-state imaging device is referred to as a CMOS image sensor, or simply as an image sensor or a solid-state imaging device. Note that the light detection device to which the present technology is applied may be a sensor other than an image sensor.

[0031] like Figure 1 As shown, the image sensor 10 according to the present embodiment includes a pixel array unit 13 , a signal processing circuit 15 , a reference voltage generator 17 , and an output circuit 19 .

[0032] also, Figure 1 The image sensor 10 in the embodiment includes a driving control unit separated from the pixel array unit 13, which is configured to sequentially read analog pixel signals from each unit pixel 131 and output digital image data. The driving control unit includes, for example, a horizontal transfer circuit 18, a pixel driving circuit 12, a timing control circuit 11, and the like.

[0033] The pixel array unit 13 includes a plurality of unit pixels 131 arranged in a two-dimensional matrix along the row direction and the column direction. Figure 1 In order to simplify the description, although some rows and columns in the pixel array unit 13 are omitted, for example, a plurality of unit pixels 131 may be arranged in each row and each column.

[0034] Each unit pixel 131 is connected to the pixel driving circuit 12 through a pixel driving line LD for pixel selection, and is also connected one-to-one to an AD conversion circuit 15a to be described later through a vertical signal line VSL. Note that in this specification, the pixel driving line LD refers to all wirings extending from the pixel driving circuit 12 to each unit pixel 131. For example, the pixel driving line LD may include a control line for transmitting various pulse signals (e.g., a pixel reset pulse, a transfer pulse, a drain line control pulse, etc.) to drive each unit pixel 131.

[0035] The signal processing circuit 15 includes an analog circuit, for example, an analog-to-digital (AD) conversion circuit 15a that converts an analog pixel signal read from each unit pixel 131 into a digital pixel signal, and a logic circuit that performs digital processing such as correlated double sampling (CDS) processing based on the pixel signal obtained by digital value conversion of the AD conversion circuit 15a. Note that, for example, the AD conversion circuit 15a may be provided one-to-one for each unit pixel 131, may be provided one-to-one for each pixel group including a plurality of unit pixels 131, or may be provided one-to-one for each column of the pixel array unit 13. Note that, Figure 1 A configuration is shown in which the plurality of AD conversion circuits 15 a are arranged in a two-dimensional matrix in the row direction and the column direction, but the present disclosure is not limited to this configuration.

[0036] For example, each AD conversion circuit 15a performs AD conversion to convert a reset level as a reference level of a pixel signal and a signal level corresponding to the amount of received light into digital data. In addition, each AD conversion circuit 15a also performs differential processing (corresponding to correlated double sampling (CDS) processing) to obtain a digital pixel signal representing a signal component corresponding to the amount of received light. During this CDS processing, a process for calculating the difference between the AD conversion result of the reset level and the AD conversion result of the signal level is performed. Note that the AD conversion circuit 15a may be, for example, a single slope AD conversion circuit or a successive approximation register (SAR) AD conversion circuit.

[0037] The reference voltage generator 17 provides the reference voltage REF to the signal processing circuit 15 to convert the analog pixel signal read from each unit pixel 131 through the vertical signal line VSL into a digital pixel signal. For example, in the case where the AD conversion circuit 15a is a single slope type, the reference voltage generator 17 outputs a reference voltage REF having a sawtooth waveform (also referred to as a ramp waveform) that rises or falls linearly or stepwise. On the other hand, in the case where the AD conversion circuit 15a is a successive approximation register type, the reference voltage generator 17 outputs a reference voltage REF having a constant voltage value. In this case, each AD conversion circuit 15a generates a plurality of reference voltages for successive approximation by dividing the reference voltage REF as a constant voltage.

[0038] The timing control circuit 11 outputs an internal clock required for the operation of each unit and a pulse signal for providing a timing for each unit to start operating, etc. In addition, the timing control circuit 11 receives data indicating a main clock and an operation mode, etc. from the outside, and outputs data including information about the image sensor 10.

[0039] For example, the timing control circuit 11 outputs a pulse signal to the pixel driving circuit 12, the pulse signal providing a timing for reading a pixel signal from each unit pixel 131. In addition, the timing control circuit 11 outputs a column address signal to the horizontal transfer circuit 18 so that the horizontal transfer circuit 18 reads pixel signals (digital voltage values) sequentially per column from the signal processing circuit 15, each pixel signal representing a signal component obtained by AD conversion by the AD conversion circuit 15a.

[0040] Furthermore, in the timing control circuit 11, a clock having the same frequency as the main clock input from the outside, a clock obtained by dividing the clock by two, a low-speed clock obtained by further dividing the clock, or the like is supplied as an internal clock to each unit such as the horizontal transfer circuit 18, the pixel driving circuit 12, and the signal processing circuit 15 in the image sensor 10. Hereinafter, clocks including the clock obtained by dividing the clock by two and the clock having a lower frequency are collectively referred to as low-speed clocks.

[0041] The pixel driving circuit 12 selects a row in the pixel array unit 13 and outputs a pulse required to drive the row to the pixel driving line LD. For example, the pixel driving circuit includes a vertical decoder that determines a row to be read from rows arranged in the vertical direction (selects a row of the pixel array unit 13) and a vertical driving unit that supplies a pulse to the pixel driving line LD to drive the unit pixel 131 at the read address (in the row direction) determined by the vertical decoder. Note that the vertical decoder selects not only a row from which a pixel signal is read but also a row for an electronic shutter or the like.

[0042] According to the column address signal input from the timing control circuit 11 , the horizontal transfer circuit 18 performs a shift operation (scanning) to read a digital pixel signal from each AD conversion circuit 15 a of a reading column designated by the column address signal to the horizontal signal line HSL.

[0043] The output circuit 19 outputs the digital pixel signal read by the horizontal transfer circuit 18 to the outside as image data.

[0044] Note that the signal processing circuit 15 may include other circuits, such as an automatic gain control (AGC) circuit having a signal amplification function, as necessary.

[0045] In addition, the image sensor 10 may be provided with a clock converter, which is an example of a high-speed clock generator and generates a pulse having a clock frequency higher than an input clock frequency. In this case, the timing control circuit 11 may generate an internal clock based on an input clock (e.g., a main clock) input from the outside or a high-speed clock generated by the clock converter.

[0046] <Circuit Configuration Example of Unit Pixel> Next, we will explain Figure 1 An example of a circuit configuration of unit pixels 131 arranged in a matrix in the pixel array unit 13 in FIG.

[0047] Figure 2 is a circuit diagram showing a schematic configuration example of a unit pixel in an effective pixel area. Figure 2 As shown, the unit pixel 131 includes a photodiode 101, a transfer transistor 102, a reset transistor 103, a switching transistor 104, an amplifying transistor 105, a selection transistor 106, a node 107 as a first floating diffusion portion, a capacitor 108 as a second floating diffusion portion, a selection transistor drive line 117 as a pixel drive line LD (one end of which is connected to the pixel drive circuit 12), a reset transistor drive line 113, a switching transistor drive line 114, a transfer transistor drive line 112, and a vertical signal line VSL (one end of which is connected to the signal processing circuit 15).

[0048] The photodiode 101 performs photoelectric conversion on incident light. The transfer transistor 102 transfers the charge generated in the photodiode 101. The node 107 and the capacitor 108, which serve as the first and second floating diffusions, accumulate the charge transferred by the transfer transistor 102. The switching transistor 104 controls so that the capacitor 108 accumulates the charge. Therefore, the switching transistor 104 switches whether to transfer the charge accumulated in the node 107 to the capacitor 108.

[0049] The amplifying transistor 105 causes a pixel signal representing a voltage corresponding to the charge accumulated in the node 107 or in the node 107 and the capacitor 108 to appear on the vertical signal line VSL. The resetting transistor 103 releases the charge accumulated in the node 107 or in the node 107 and the capacitor 108. The selecting transistor 106 selects the unit pixel 131 to be read.

[0050] The anode of the photodiode 101 is grounded, and the cathode is connected to the source of the transfer transistor 102. The drain of the transfer transistor 102 is connected to the source of the switching transistor 104 and the gate of the amplification transistor 105, and a node 107 as a connection point serves as a first floating diffusion.

[0051] The reset transistor 103 and the switching transistor 104 are arranged in series with respect to the node 107. Note that the drain of the reset transistor 103 is connected to a vertical reset input line (not shown).

[0052] The source of the amplifier transistor 105 is connected to a vertical current supply line (not shown). The drain of the amplifier transistor 105 is connected to the source of the selection transistor 106, and the drain of the selection transistor 106 is connected to the vertical signal line VSL.

[0053] The gate of the transfer transistor 102 , the gate of the reset transistor 103 , the gate of the switching transistor 104 , and the gate of the selection transistor 106 are connected to the pixel driving circuit 12 through the pixel driving line LD, and receive a pulse as a driving signal.

[0054] The node 107 serving as the first floating diffusion and the capacitor 108 serving as the second floating diffusion each convert the accumulated charge into a voltage corresponding to the amount of charge. Note that the first floating diffusion is, for example, a floating diffusion region, and is a grounding capacitance between the node 107 and the ground. However, the first floating diffusion is not limited to the above configuration, and may be a capacitance intentionally added by connecting a capacitor or the like to the node 107.

[0055] Furthermore, the capacitor 108 serving as the second floating diffusion converts the accumulated charge into a voltage corresponding to the amount of the charge.

[0056] <Example of basic functions per pixel> Next, a basic function of the unit pixel 131 will be described. When the switching signal FDG applied to the gate of the switching transistor 104 is always in a high state, the reset transistor 103 operates to start or stop the discharge of the charge accumulated in the node 107 and the capacitor 108 according to the reset signal RST supplied from the pixel driving circuit 12.

[0057] When a high-level reset signal RST is input to the gate of the reset transistor 103, the node 107 and the capacitor 108 are clamped to the voltage applied through the vertical reset input line. Therefore, the charges accumulated in the node 107 and the capacitor 108 are discharged (reset).

[0058] In addition, when a low-level reset signal RST is input to the gate of the reset transistor 103 , the node 107 and the capacitor 108 are electrically disconnected from the vertical reset input line, thereby becoming a floating state.

[0059] While the reset signal RST is always in a high level state, the switching transistor 104 operates to turn on or off the discharge of the charge accumulated in the node 107 according to the switching signal FDG supplied from the pixel driving circuit 12 .

[0060] When the high-level switching signal FDG is input to the gate of the switching transistor 104, the node 107 is clamped to the voltage applied through the vertical reset input line. Therefore, the charge accumulated in the node 107 is discharged (reset).

[0061] In addition, when a low-level switching signal FDG is input to the gate of the switching transistor 104, the node 107 is electrically disconnected from the vertical reset input line and is brought into a floating state.

[0062] The photodiode 101 performs photoelectric conversion on incident light to generate charges corresponding to the amount of light. The generated charges are accumulated on the cathode side of the photodiode 101. The transfer transistor 102 starts or stops the transfer of charges from the photodiode 101 to the node 107 or to the node 107 and the capacitor 108 according to the transfer control signal TRG provided from the pixel driving circuit 12.

[0063] For example, when a high-level transfer control signal TRG is input to the gate of the transfer transistor 102, the charge accumulated in the photodiode 101 is transferred to the node 107 or to the node 107 and the capacitor 108. On the other hand, when a low-level transfer control signal TRG is supplied to the gate of the transfer transistor 102, the charge transfer from the photodiode 101 is interrupted.

[0064] Note that when the transfer transistor 102 interrupts transfer of charges to the node 107 or to the node 107 and the capacitor 108 , charges generated by photoelectric conversion are accumulated in the photodiode 101 .

[0065] As described above, both the node 107 and the capacitor 108 can accumulate the charge transferred from the photodiode 101 through the transfer transistor 102 and convert the charge into a voltage. Therefore, in a floating state where the reset transistor 103 and / or the switching transistor 104 are turned off, the potential of the node 107 or the potential of the node 107 and the capacitor 108 is modulated according to the amount of accumulated charge.

[0066] The amplifier transistor 105 functions as an amplifier that uses potential fluctuation of a node 107 connected to the gate of the amplifier transistor 105 or potential fluctuation of the node 107 and the capacitor 108 as an input signal and outputs a voltage signal as a pixel signal to the vertical signal line VSL through the selection transistor 106 .

[0067] The selection transistor 106 starts or stops the output of the voltage signal from the amplifier transistor 105 to the vertical signal line VSL according to the selection control signal SEL provided from the pixel driving circuit 12. For example, when the high-level selection control signal SEL is input to the gate of the selection transistor 106, the voltage signal of the amplifier transistor 105 is output to the vertical signal line VSL. On the other hand, when the low-level selection control signal SEL is input to the gate of the selection transistor 106, the output of the voltage signal from the amplifier transistor 105 to the vertical signal line VSL is interrupted. Therefore, only the output of the selected unit pixel 131 can be extracted to the vertical signal line VSL connected to the plurality of unit pixels 131.

[0068] As described above, the unit pixel 131 is driven according to the transfer control signal TRG, the reset signal RST, the switching signal FDG, and the selection control signal SEL supplied from the pixel driving circuit 12 .

[0069] <Increase in capacitance per unit area> For example, in the case of the configuration of the above-described unit pixel 131, it may be considered to adopt a so-called trench capacitor as the capacitor 108 used as the second floating diffusion (FD) to increase the capacitance per unit area. The trench capacitor here refers to a vertical capacitor formed in a trench formed in a semiconductor substrate.

[0070] Here, for example, in the case where the trench capacitor is formed in the same semiconductor substrate as the photodiode 101, it is conceivable to arrange the photodiode 101 and the trench capacitor in the plane direction. In this case, the area of ​​each unit pixel 131 increases, resulting in a decrease in pixel density. On the other hand, in order to maintain the pixel density, the area of ​​each photodiode 101 needs to be relatively reduced, but the saturation charge amount Qs is reduced accordingly.

[0071] Therefore, it is also conceivable to form a trench capacitor on a substrate different from the substrate forming the photodiode 101 and bond these substrates to each other. In the case of this configuration, a wide dynamic range can be achieved by increasing the capacitance per unit area while avoiding problems such as a decrease in pixel density.

[0072] However, since the first semiconductor substrate including the photoelectric conversion element and the second semiconductor substrate including the capacitor are separate, two substrates are required, and a process of bonding the substrates together is also required, so it is difficult to reduce the manufacturing cost.

[0073] Therefore, in the present embodiment, in the first semiconductor substrate having the first semiconductor layer and the second semiconductor layer stacked on each other, the first semiconductor layer has a photoelectric conversion region and a floating diffusion region, and the second semiconductor layer has a capacitor. Hereinafter, the detailed configuration of the light detection device according to the present embodiment will be described.

[0074] <Example of cross-sectional structure of image sensor> Figure 3 1 is a cross-sectional diagram showing an example of a cross-sectional structure of a unit pixel. Note that the figure shows a cross-sectional structure along the normal direction of the light incident surface, where the light incident side is the upper side. In the actual pixel array unit 13, the plurality of unit pixels shown in the figure are arranged in Figure 3 The left and right sides of the page and the front and back of the page. Figure 3 The unit pixel in is back-illuminated, and Figure 3 The upper side is the back side of the unit pixel.

[0075] The image sensor 10 has a multilayer structure including a first semiconductor substrate 140 and a second semiconductor substrate 160 bonded to each other. The first semiconductor substrate 140 includes a first semiconductor layer 141 and a second semiconductor layer 150 stacked on each other. The first semiconductor layer 141 and the second semiconductor layer 150 are formed in a substrate, and the second semiconductor layer 150 is a polysilicon layer. In addition, the first semiconductor substrate 140 also includes an insulating layer 153, the second semiconductor layer 150 is stacked on top of the insulating layer 153, and the insulating layer 153 includes a wiring structure.

[0076] The transfer transistor 102, the reset transistor 103, the switching transistor 104, the amplifying transistor 105, and the selecting transistor 106 are formed in the first semiconductor layer 141 and the second semiconductor layer 150. The gate electrodes of the transistors 102 to 106 are respectively formed in the second semiconductor layer 150. In addition, the channel regions and the source / drain regions of the transistors 102 to 106 are respectively formed in the first semiconductor layer 141. Therefore, the transistors 102 to 106 are formed along the boundary between the first semiconductor layer 141 and the second semiconductor layer 150. In the case of such a multilayer structure, the unit pixel 131 is formed in the first semiconductor substrate 140.

[0077] <Structural Example of First Semiconductor Layer> The first semiconductor layer 141 includes a photodiode 101, a node 107, and a channel region and a source / drain region of each transistor. The photodiode 101 receives incident light incident from the back side (upper surface in the figure) of the first semiconductor layer 141. The photodiode 101 is a photoelectric conversion region that performs photoelectric conversion on the incident light.

[0078] A color filter 122 and an on-chip lens 121 are provided above the photodiode 101. Note that a light shielding film 123 may be provided between adjacent color filters 122 to prevent light crosstalk between adjacent unit pixels 131. In addition, a planarization film (not shown) for planarizing the contact surface of the color filter 122 may be provided between the first semiconductor layer 141 and the color filter 122.

[0079] In the photodiode 101 , for example, an n-type semiconductor region 142 is formed as a charge accumulation region that accumulates charges (electrons). In the photodiode 101 , a p-type semiconductor region 143 is provided around the n-type semiconductor region 142 .

[0080] In the p-type semiconductor region 143, the impurity concentration of the region on the front (lower surface) side of the first semiconductor layer 141 may be higher than the impurity concentration of the region on the back (upper surface) side. That is, the photodiode 101 may have a hole accumulation diode (HAD: hole-accumulation diode) structure. In the case of such a configuration, the generation of dark current at each interface on the upper and lower surface sides of the n-type semiconductor region 142 may be suppressed.

[0081] A pixel separator 144 is provided near the pixel boundary of the first semiconductor layer 141, and the pixel separator 144 optically and electrically isolates adjacent photodiodes 101 to prevent crosstalk between the photodiodes 101. In the case where the image sensor 10 is viewed from the upper surface side of the figure (hereinafter referred to as a "plan view"), for example, the pixel separator 144 is formed in a grid pattern and is interposed between adjacent unit pixels 131.

[0082] In the pixel separation portion 144, an element separation portion 145 as an insulating film is provided at an end opposite to an end at which the light shielding film 123 is provided. The element separation portion 145 covers the end of the pixel separation portion 144. In a manner similar to the pixel separation portion 144, the element separation portion 145 is formed in a grid pattern, is interposed between adjacent unit pixels 131 in a plan view, and electrically isolates the unit pixels 131. In addition, the element separation portion 145 is wider than the pixel separation portion 144. The photodiode 101 is formed in a region defined by the pixel separation portion 144 and the element separation portion 145. Therefore, the first semiconductor layer 141 includes a plurality of pixels 131 each having a photodiode 101 and a pixel boundary region (the pixel separation portion 144 and the element separation portion 145) arranged between two adjacent pixels 131.

[0083] The anode (not shown) of the photodiode 101 is grounded through wiring. The n-type semiconductor region 142 used as the cathode of the photodiode 101 is connected to the n-type semiconductor region 146. The n-type semiconductor region 146 is set to extend through the p-type semiconductor region 143 to the lower interface of the first semiconductor layer 141. In addition, three n-type semiconductor regions 147, 148 and 149 are also provided at the lower interface of the first semiconductor layer 141. These n-type semiconductor regions are formed by implanting high-concentration n-type impurity ions into the surface of the p-type semiconductor region 143.

[0084] The n-type semiconductor region 146 functions as the source of the transfer transistor 102. The n-type semiconductor region 147 functions as the drain of the transfer transistor 102, the source of the switching transistor 104, and the node 107. With this configuration, signal charges (e.g., electrons) accumulated in the photodiode 101 are transferred to the node 107 through the transfer transistor 102 connected to the cathode of the photodiode 101.

[0085] The node 107 serving as a floating diffusion region accumulates the charges generated by the photoelectric conversion of the photodiode 101. Then, the node 107 applies a voltage corresponding to the amount of the transferred charges to the gate of the amplifying transistor 105.

[0086] The n-type semiconductor region 148 functions as a drain of the switching transistor 104 and a source of the reset transistor 103. Furthermore, the n-type semiconductor region 148 is connected to a first electrode 151 of the capacitor 108. The n-type semiconductor region 149 functions as a drain of the reset transistor 103.

[0087] Note that p-type semiconductor regions as channel regions of the amplification transistor 105 and the selection transistor 106 and n-type semiconductor regions as source / drain regions are also provided in the cross section (not shown) of the first semiconductor layer 141 .

[0088] <Structural Example of Second Semiconductor Layer> like Figure 3 As shown, the second semiconductor layer 150 includes the respective gate electrodes G1 to G3 of the transistor and the capacitor 108, which accumulates the charge generated by the photoelectric conversion of the photodiode 101. In addition, the second semiconductor layer 150 is provided with wiring layers 21 to 24 (gate wiring layers) connected to the signal line or the drive line, etc., and the contacts 31 to 34 extending through the second semiconductor layer 150 and connected to the wiring layers 21 to 24, respectively. Note that the respective gate electrodes G1 to G3 of the transistor, the wiring layers 21 to 24, and the contacts 31 to 34 include polysilicon. The first electrode 151 and the second electrode 25 constituting the capacitor 108 also include polysilicon.

[0089] The transfer transistor 102 includes a gate electrode G1. The gate electrode G1 is disposed between the paired n-type semiconductor regions 146 and 147 in a plan view. The wiring layer 21 is electrically connected to the gate electrode G1 through the contact portion 31. The gate electrode G1 is formed by forming a gate insulating film (not shown) including a silicon oxide film on the first semiconductor layer 141 and then patterning the polysilicon layer. As described above, the transfer transistor 102 includes the gate electrode G1 and the n-type semiconductor regions 146 and 147 as its source / drain regions. The transfer transistor 102 transfers the charge generated by the photoelectric conversion of the photodiode 101 to the n-type semiconductor region 147 as the node 107.

[0090] The switching transistor 104 includes a gate electrode G2. The gate electrode G2 is disposed between the paired n-type semiconductor regions 147 and 148 in a plan view. The wiring layer 22 is electrically connected to the gate electrode G2 through the contact portion 32. The switching transistor 104 includes the gate electrode G2 and the n-type semiconductor regions 147 and 148 as source / drain regions thereof. In the case of such a configuration, the switching transistor 104 switches whether to transfer the charge accumulated in the node 107 to the n-type semiconductor region 148 connected to the capacitor 108.

[0091] The reset transistor 103 includes a gate electrode G3. The gate electrode G3 is disposed between the paired n-type semiconductor regions 148 and 149 in a plan view. The wiring layer 23 is electrically connected to the gate electrode G3 through the contact portion 33. In addition, the wiring layer 24 is electrically connected to the n-type semiconductor region 149 through the contact portion 34. The reset transistor 103 includes the gate electrode G3 and the n-type semiconductor regions 148 and 149 as its source / drain regions. In the case of such a configuration, the reset transistor 103 discharges the charge accumulated in the node 107 or the node 107 and the capacitor 108 through the wiring including the contact portion 34 and the wiring layer 24.

[0092] Note that the respective gate electrodes, contacts, and wiring layers of the amplifying transistor 105 and the selecting transistor 106 are also provided in the cross section (not shown) of the second semiconductor layer 150. Therefore, the amplifying transistor 105 and the selecting transistor 106 are also provided in the first semiconductor substrate 140. Therefore, all transistors constituting the pixel 131 are formed in the first semiconductor substrate 140.

[0093] The capacitor 108 includes a first electrode 151, a second electrode 25, and a dielectric 152. The second electrode 25 is arranged to face the first electrode 151. The dielectric 152 is arranged between the first electrode 151 and the second electrode 25.

[0094] The first electrode 151 and the second electrode 25 can be arranged at a layer height between the same layer height as the gate electrode G1 of the transfer transistor 102 and the same layer height as the wiring layer 21. In the present embodiment, the first electrode 151 of the capacitor 108 is arranged at the same layer height as the gate electrode G1. Thus, the first electrode 151 can be formed while forming the respective gate electrodes G1 to G3 of the transistor. On the other hand, the second electrode 25 of the capacitor 108 is arranged at the same layer height as the other wiring layers 21 to 24. Thus, the second electrode 25 can be formed while forming the wiring layers 21 to 24. As described above, in the present embodiment, the capacitor 108 can be formed without the need for an additional process. Note that the capacitance of the capacitor 108 can be maintained by setting the first electrode 151 to a predetermined negative potential.

[0095] The dielectric 152 includes a silicon oxide film (SiO2) or a low-k film (low dielectric constant insulating film), etc. The dielectric 152 according to the present embodiment is an insulating material different from an etching stopper (not shown) disposed between the wiring layer 21 and the gate electrode G1 and used to form each portion.

[0096] Figure 4 1 is a plan view showing the arrangement of the capacitor 108 in the pixel 131. The figure shows a region corresponding to a plurality of pixels 131. Note that, for convenience of explanation, the figure also shows a configuration that does not appear in the same cross section.

[0097] As shown in the figure, the element separation portion 145 as a pixel boundary region is arranged between two adjacent pixels 131. The photodiode 101 includes, for example, an n-type semiconductor region 142 and a p-type semiconductor region 143 surrounding the n-type semiconductor region 142, wherein the n-type semiconductor region 142 is formed at the approximate center of a rectangular region designated for each unit pixel 131 in the first semiconductor layer 141. Then, the capacitor 108 according to the present embodiment is arranged in a region that does not overlap with the element separation portion 145 but overlaps with the pixel 131 in a plan view. As described above, by arranging the capacitor 108 in a region that overlaps with the pixel 131, problems such as a decrease in pixel density or a decrease in the saturation charge amount Qs can be solved while preventing the photodiode 101 from becoming smaller due to the presence of the capacitor 108.

[0098] <Structure example of insulating layer> like Figure 3 As shown, the insulating layer 153 is provided on (the lower surface of) the second semiconductor layer 150. The insulating layer 153 includes a through-hole wiring 154, a wiring 155, and an electrode pad 156. The through-hole wiring 154 is provided on the back side of the insulating layer 153 to be electrically connected to a corresponding one of the wiring layers 21 to 24, that is, to be electrically connected to one of the gate electrodes. The through-hole wiring 154 is connected to the corresponding electrode pad 156 through the corresponding wiring 155. For example, the electrode pad 156 includes copper (Cu) on the front side (lower surface) of the insulating layer 153.

[0099] In the case of such a wiring structure, the gate electrode G1 of the transfer transistor 102 is connected to the transfer transistor drive line 112 through the wiring structure including the contact portion 31, the wiring layer 21, and the through-hole wiring 154. In addition, the gate electrode G2 of the switching transistor 104 is connected to the switching transistor drive line 114 through the wiring structure including the contact portion 32, the wiring layer 22, and the through-hole wiring 154. The gate electrode G3 of the reset transistor 103 is connected to the reset transistor drive line 113 through the wiring structure including the contact portion 33, the wiring layer 23, and the through-hole wiring 154. The drain of the reset transistor 103 is connected to the vertical reset input line (not shown) through the wiring structure including the contact portion 34, the wiring layer 24, and the through-hole wiring 154.

[0100] <Structural Example of Second Semiconductor Substrate> The image sensor 10 includes a second semiconductor substrate 160 disposed on a side opposite to a light incident surface of the first semiconductor substrate 140. The second semiconductor substrate 160 processes a pixel signal corresponding to charges generated by photoelectric conversion of the photodiode 101.

[0101] The second semiconductor substrate 160 is provided with Figure 1 The circuit element 164 includes the signal processing circuit 15 in FIG. 164. In addition to the signal processing circuit 15, the circuit element 164 may include, for example, a timing control circuit 11, a pixel driving circuit 12, a horizontal transfer circuit 18, a reference voltage generator 17, an output circuit 19, and the like.

[0102] The circuit element 164 is formed in the semiconductor substrate 161 and in the insulating film 162 provided on (the upper surface of) the semiconductor substrate 161. An electrode pad 163 including copper (Cu) is formed on the upper surface of the insulating film 162 for electrical and mechanical connection with the electrode pad 156 of the second semiconductor substrate 160. As described above, the pixel 131 is arranged in the first semiconductor substrate 140, and the second semiconductor substrate 160 in which the peripheral circuit of the pixel 131 is arranged can be directly bonded to the first semiconductor substrate 140 without using other components.

[0103] <Bonding between substrates> In the case of the above-mentioned configuration, the opposing surfaces of the first semiconductor substrate 140 and the second semiconductor substrate 160 can be bonded to each other, for example, by contact between pads, through-hole interconnects, or bumps. The first semiconductor substrate 140 and the second semiconductor substrate 160 are bonded to each other by so-called Cu-Cu bonding, in which copper (Cu) electrode pads 156 and 163 formed on the respective bonding surfaces of the first semiconductor substrate 140 and the second semiconductor substrate 160 are directly bonded to each other. In the case of this configuration, the electrode pads 156 and 163 serve as connecting portions that allow the first semiconductor substrate 140 and the second semiconductor substrate 160 to be electrically connected and mechanically bonded to each other. Note that the first semiconductor substrate 140 and the second semiconductor substrate 160 can be bonded to each other by so-called direct bonding, in which the respective bonding surfaces of the first semiconductor substrate 140 and the second semiconductor substrate 160 are flattened and bonded to each other using inter-electron force.

[0104] <Function and Effect> As described above, according to the present embodiment, in the first semiconductor substrate 140 including the first semiconductor layer 141 and the second semiconductor layer 150 stacked on each other, the first semiconductor layer 141 includes the photodiode 101 and the node 107. In addition, the second semiconductor layer 150 includes the capacitor 108. This configuration can reduce the manufacturing cost by reducing the number of required semiconductor substrates and eliminating the need for a bonding process. Therefore, a low-cost image sensor 10 with a large signal detection capability can be provided.

[0105] In addition, the first electrode 151 as a part of the capacitor 108 is arranged at a layer height between the same layer height as the gate electrode G1 of the transfer transistor 102 and the same layer height as the wiring layer 21. Thus, the capacitor 108 can be formed at the same time as the transistors 102 to 106 are formed in the second semiconductor layer 150. In addition, in the present embodiment, since the capacitor 108 is arranged on the back side of the photodiode 101 and can be formed without affecting the region of the photodiode 101, even if the photodiode 101 and the capacitor 108 are formed in the first semiconductor substrate 140, the saturation charge amount does not decrease.

[0106] Furthermore, in the present embodiment, whether or not to use the second floating diffusion (capacitor 108) can be switched by controlling the switching transistor 104. With this configuration, it is also possible to switch between high gain (when the second floating diffusion is not used) and wide dynamic range (when the second floating diffusion is used) depending on situations such as nighttime shooting.

[0107] Second Embodiment Figure 51 is an enlarged cross-sectional view showing an example of a cross-sectional structure of a unit pixel according to the second embodiment. Note that in the figure, for ease of understanding, only the first semiconductor substrate 140 as a part of the pixel 131 is shown in an enlarged manner, and other components (such as the second semiconductor substrate 160) are not shown. Figure 6 2 is a plan view showing the arrangement of capacitors in a pixel according to the second embodiment. Note that in each embodiment to be described below, redundant descriptions of components given in the above-described embodiments will be omitted.

[0108] The capacitor 108 of the present embodiment is different from the capacitor 108 of the first embodiment in that the pixel 131 is arranged in a region that coincides with the element isolation section 145 serving as a pixel boundary region in a plan view.

[0109] In the capacitor 108 of this embodiment, as Figure 5 As shown, the first electrode 151, the dielectric 152, and the second electrode 25 are not arranged in a region that coincides with the n-type semiconductor region 148, but are arranged in a region that coincides with the element isolation portion 145. Therefore, the first electrode 151 is not directly connected to the n-type semiconductor region 148 shared by the source / drain regions of the reset transistor 103 and the switching transistor 104. Therefore, the n-type semiconductor region 148 and the first electrode 151 are electrically connected to each other through the contact portion 36, the wiring layer 26, and the wiring structure (not shown) that are arranged in a region that coincides with the n-type semiconductor region 148 and are electrically connected to the n-type semiconductor region 148. Note that the configuration for electrically connecting these components may be a different configuration.

[0110] As described above, by arranging the capacitor 108 in a region overlapping with the element isolation portion 145, the second semiconductor layer 150 can be effectively used. Note that both the capacitor 108 of this embodiment and the capacitor 108 of the first embodiment can be provided in the pixel 131.

[0111] In addition, if Figure 6 As shown, the capacitor 108 according to the present embodiment can be arranged individually or in multiple numbers between the pixels 131 arranged along the row and column directions. In addition, the capacitor 108 can be arranged between the pixels 131 arranged diagonally along the row and column directions. In other words, an additional capacitor 108 can be arranged between the adjacent capacitors 108 shown in the figure.

[0112] "Third Embodiment" Figure 7 1 is an enlarged cross-sectional view showing an example of a cross-sectional structure of a unit pixel according to the third embodiment. The capacitor 108 of this embodiment is different from the capacitor 108 of the first embodiment in the position of the second electrode 25 in the thickness direction of the second semiconductor layer 150 (hereinafter may be simply referred to as the "thickness direction").

[0113] Specifically, the first electrode 151 is arranged at the same layer height as the gate electrodes G1 to G3, but the second electrode 25 is arranged between the gate electrodes G1 to G3 and the wiring layers 21 to 24. That is, the second electrode 25 is arranged in a layer closer to the first electrode 151 and the gate electrodes G1 to G3 than the wiring layers 21 to 24. Therefore, the distance between the electrodes of the capacitor 108 can be reduced to increase the capacitance of the capacitor 108.

[0114] In this case, in order to form the capacitor 108 of the present embodiment, the second electrode 25 is provided as a new layer by a formation process separate from the formation process of the wiring layers 21 to 24. In addition, in this formation process, as shown in FIG. Figure 7 As shown, a wiring layer 251 or a contact portion (not shown) connecting the second electrode 25 and the via wiring 154 is formed.

[0115] Note that, as in the second embodiment, the capacitor 108 according to the present embodiment can be arranged in a region coinciding with the element isolating portion 145. Furthermore, the capacitance of the capacitor 108 can be maintained by setting the first electrode 151 to a predetermined negative potential.

[0116] "Fourth Embodiment" Figure 8 : is an enlarged cross-sectional diagram showing an example of a cross-sectional structure of a unit pixel according to the fourth embodiment. The capacitor 108 of the present embodiment is different from the capacitor 108 of the first embodiment in the position of the first electrode 151 in the thickness direction.

[0117] Specifically, the second electrode 25 is arranged at the same layer height as the wiring layers 21 to 24, but the first electrode 151 is arranged between the gate electrodes G1 to G3 and the wiring layers 21 to 24. That is, the first electrode 151 is arranged in a layer closer to the second electrode 25 and the wiring layers 21 to 24 than the gate electrodes G1 to G3. Therefore, the distance between the electrodes of the capacitor 108 can be reduced to increase the capacitance of the capacitor 108.

[0118] In this case, in order to form the capacitor 108 of the present embodiment, the first electrode 151 is provided as a new layer by a formation process separate from the formation process of the gate electrodes G1 to G3. Figure 8 As shown, a contact portion 1511 is formed to connect the first electrode 151 and the n-type semiconductor region 148 .

[0119] Note that, as in the second embodiment, the capacitor 108 according to the present embodiment can be arranged in a region coinciding with the element isolating portion 145. Furthermore, the capacitance of the capacitor 108 can be maintained by setting the first electrode 151 to a predetermined negative potential.

[0120] "Fifth Embodiment" Fig. 9 1 is an enlarged cross-sectional view showing an example of a cross-sectional structure of a unit pixel according to the fifth embodiment. The capacitor 108 of the present embodiment is different from the capacitor 108 of the first embodiment in the positions of the first electrode 151 and the second electrode 25 in the thickness direction.

[0121] The first electrode 151 and the second electrode 25 in the present embodiment are both arranged between the gate electrodes G1 to G3 and the wiring layers 21 to 24. Therefore, the first electrode 151 is arranged between the gate electrodes G1 to G3 and the wiring layers 21 to 24, and the second electrode 25 is arranged between the gate electrodes G1 to G3 and the wiring layers 21 to 24. That is, the first electrode 151 is arranged closer to the second electrode M5 and the wiring layers 21 to 24 than the gate electrodes G1 to G3, and the second electrode 25 is arranged closer to the first electrode 151 and the gate electrodes G1 to G3 than the wiring layers 21 to 24. Therefore, the distance between the electrodes of the capacitor 108 can be further reduced to further increase the capacitance of the capacitor 108.

[0122] In this case, the first electrode 151 is provided as a new layer through a formation process separate from the formation process of the gate electrodes G1 to G3. Fig. 9 As shown in FIG. 1 , a contact portion 1511 is formed to connect the first electrode 151 to the n-type semiconductor region 148. In addition, in order to form the capacitor 108 of the present embodiment, the second electrode 25 is provided as a new layer by a formation process separate from the formation process of the wiring layers 21 to 24. In addition, in this formation process, as shown in FIG. Fig. 9 As shown, a wiring layer 251 or a contact portion (not shown) connecting the second electrode 25 and the via wiring 154 is formed.

[0123] Note that, as in the second embodiment, the capacitor 108 according to the present embodiment can be arranged in a region coinciding with the element isolating portion 145. Furthermore, the capacitance of the capacitor 108 can be maintained by setting the first electrode 151 to a predetermined negative potential.

[0124] Sixth Embodiment Fig.10 is an enlarged cross-sectional view showing an example of a cross-sectional structure of a unit pixel according to the sixth embodiment. The capacitor 108 of the present embodiment is different from the capacitor 108 of the first embodiment in the material of the dielectric 152A arranged between the first electrode 151 and the second electrode 25 .

[0125] Specifically, the dielectric 152A according to the present embodiment includes the same insulating material as the etching stop layer arranged between the wiring layer 21 and the gate electrode G1. The etching stop layer includes, for example, a silicon oxide film and an insulating film used as an etching stop portion, which is used in the etching for forming the contact opening in the second semiconductor layer 150. For example, a silicon nitride film (Si3N4) is used as the etching stop layer. Note that the etching stop layer may include a material other than a silicon nitride film as long as the material has a significant etching rate difference compared to the silicon oxide film.

[0126] As described above, by using the dielectric 152A as an etching stopper used in etching for forming the contact opening, the etching stopper temporarily provided for forming the second semiconductor layer 150 can be used intact. Therefore, the need for a process of removing the etching stopper can be eliminated, thereby making the process of forming the second semiconductor layer 150 more efficient. In addition, as shown in the figure, since the dielectric 152A is an insulating film used as an etching stopper, the distance between the first electrode 151 and the second electrode 25 is reduced, so that the capacitance of the capacitor 108 can be increased.

[0127] Note that in order to provide the capacitor 108 having such a configuration, the first electrode 151 is provided as a new layer by a formation process separate from the formation process of the gate electrodes G1 to G3. Fig.10 As shown, a contact portion 1511 is formed to connect the first electrode 151 and the n-type semiconductor region 148 .

[0128] Note that, as in the second embodiment, the capacitor 108 of the present embodiment can be arranged in a region coinciding with the element isolating portion 145. Furthermore, the capacitance of the capacitor 108 can be maintained by setting the first electrode 151 to a predetermined negative potential.

[0129] Seventh Embodiment Fig.11 1 is a plan view showing the shape and arrangement of capacitors in a pixel according to the seventh embodiment. The capacitor 108 of this embodiment is different from the capacitor 108 of the first embodiment in the shape of the first electrode 151 and the second electrode 25 in the plan view. The pixel cross-sectional structure of the seventh embodiment is similar to Figure 3 The structure in .

[0130] The first electrode 151 and the second electrode 25 of this embodiment have concavoconvex parts, which are meshed with each other in a plan view, and there is a gap between their opposite surfaces. In other words, the first electrode 151 and the second electrode 25 have comb-shaped parts that mesh with each other. The dielectric 152 is provided between the first electrode 151 and the second electrode 25.

[0131] Therefore, by widening the electrode facing surface of the first electrode 151 and the second electrode 25, the capacitance of the capacitor 108 can be increased. In addition, the first electrode 151 and the second electrode 25 may be formed to overlap each other in the thickness direction of the second semiconductor layer 150.

[0132] "Eighth Embodiment" Fig.12 is an enlarged cross-sectional diagram showing an example of a cross-sectional structure of a unit pixel according to the eighth embodiment. Fig.13 : is an enlarged cross-sectional view showing an example of a cross-sectional structure of a capacitor according to the eighth embodiment. Note that for ease of understanding, Fig.13 With Fig.12 The opposite orientation is shown. Fig.14 is a plan view showing the arrangement of capacitors in a pixel according to the eighth embodiment.

[0133] like Fig.12 As shown, the capacitor 108 of this embodiment is different from the capacitor 108 of other embodiments in that the capacitor 108 is formed in a plug shape extending from the front surface toward the rear surface of the second semiconductor layer 150. In addition, the capacitor 108 of this embodiment is different from the capacitor 108 of the above-mentioned embodiments in that the capacitor is formed vertically.

[0134] In order to form the capacitor 108 into a plug shape, as Fig.13 As shown, one of the first electrode 151A and the second electrode 252 is a columnar member extending in the depth direction of the second semiconductor layer 150. Then, the other electrode is a cylindrical member that covers at least the side surface of the one electrode via a dielectric 152B. As an example, the capacitor 108 of the present embodiment includes the first electrode 151A as a columnar member and the second electrode 252 as a cylindrical member covering the first electrode 151A. In addition, the capacitor 108 includes a thin dielectric 152B between the first electrode 151A and the second electrode 252.

[0135] Therefore, by providing the plug-shaped capacitor 108, the capacitor 108 can be formed in the vertical direction, thereby making the area in the plan view smaller. In the case of such a configuration, for example, Fig.14 As shown, when the capacitor 108 is arranged in a region overlapping with the photodiode 101, the arrangement region of the capacitor 108 can be reduced. Therefore, the size of the pixel 131 can be reduced or the performance can be improved by adding another transistor or capacitor.

[0136] Ninth Embodiment Fig.15 is an enlarged cross-sectional diagram showing an example of a cross-sectional structure of a unit pixel according to the ninth embodiment. Fig.16is a plan view showing the arrangement of capacitors in a pixel according to the ninth embodiment.

[0137] like Fig.15 As shown, the capacitor 108 of this embodiment is different from the capacitor 108 of the other embodiments in that plug-shaped electrodes extending from each surface of the second semiconductor layer 150 toward the other surface are alternately formed. Note that the capacitor 108 of this embodiment includes a plurality of plug-shaped electrodes extending in the depth direction and formed between two adjacent electrodes. In the eighth embodiment, the capacitor 108 is formed in the depth direction, but in the ninth embodiment, the capacitor 108 is formed in the plane direction. Fig.13 Differently, each plug-shaped electrode includes a conductive material such as polysilicon and does not form a capacitor alone.

[0138] Specifically, in the capacitor 108 of the present embodiment, the plug 1512 extends from the first electrode 151 toward the second electrode 25, and the plug 253 extends from the second electrode 25 toward the first electrode 151. In other words, the first electrode 151 and the second electrode 25 extend in the depth direction of the second semiconductor layer 150. The plug 1512 of the first electrode 151 and the plug 253 of the second electrode 25 are alternately arranged with a gap therebetween. In addition, the dielectric 152 is provided between the plug 1512 of the first electrode 151 and the plug 253 of the second electrode 25. In the case of such a configuration, the opposing surfaces of the first electrode 151 and the second electrode 25 can be widened by increasing the area of ​​the electrodes, thereby increasing the capacitance of the capacitor 108.

[0139] "Tenth Embodiment" Fig.17 1 is a plan view showing the arrangement of capacitors in a pixel according to the tenth embodiment. Fig.17 As shown, the capacitor 108 of this embodiment is different from the capacitor 108 of other embodiments in that fin electrodes extending from each surface toward the other surface of the second semiconductor layer 150 are formed. Note that the capacitor 108 of this embodiment includes a plurality of fin electrodes extending in the depth direction.

[0140] The first electrode 151 and the second electrode 25 are arranged on opposite sides along the depth direction of the second semiconductor layer 150. Fig.17 As shown, in a plan view, two electrodes 151 and M5 included in the capacitor 108 are arranged approximately in parallel in the region of the pixel 131. In other words, the electrodes 151 and M5 are arranged in approximately parallel lines in a plan view. Therefore, the capacitor 108 has a configuration including a dielectric 152 sandwiched between the electrodes 151 and M5.

[0141] In addition, if Fig.17As shown, in two pixels 131 arranged in the diagonal direction, the directions of the two electrodes 151 and M5 in the plan view are the same. On the contrary, in two pixels 131 arranged in the horizontal direction or the vertical direction among the row and column directions as the arrangement direction of the pixels 131, the two electrodes 151 and M5 are arranged so that their orientations are tilted by 90 degrees. By changing the directions of the electrodes of the capacitors 108 in two pixels adjacent in the horizontal direction or the vertical direction, coupling between the two capacitors 108 adjacent in the horizontal direction or the vertical direction can be prevented.

[0142] By arranging the capacitor 108 to form capacitance in the vertical direction as described above, the area in a plan view can be reduced. Therefore, the size of the pixel 131 can be reduced and the performance can be improved by adding another transistor or capacitor or the like.

[0143] <<Application Examples>> The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body, such as an automobile, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, a robot, a construction machine, or an agricultural machine (tractor).

[0144] Fig.18 7000 is a block diagram showing a schematic configuration example of a vehicle control system 7000 as an example of a mobile body control system to which the technology according to the present disclosure can be applied. The vehicle control system 7000 includes a plurality of electronic control units connected to each other via a communication network 7010. Fig.18 In the example shown, the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an external information detection unit 7400, an internal information detection unit 7500, and an integrated control unit 7600. The communication network 7010 that interconnects the plurality of control units may be, for example, an in-vehicle communication network that complies with any standard, such as a controller area network (CAN), a local interconnect network (LIN), a local area network (LAN), or FlexRay (registered trademark), etc.

[0145] Each control unit includes: a microcomputer that performs arithmetic processing according to various programs; a storage unit that stores programs executed by the microcomputer or parameters for various operations, etc.; and a drive circuit that drives various control target devices. Each control unit also includes: a network interface (I / F) for communicating with other control units via the communication network 7010; and a communication I / F for communicating with devices or sensors inside and outside the vehicle via wired communication or wireless communication. Fig.187600, a microcomputer 7610, a general communication I / F 7620, a dedicated communication I / F 7630, a positioning unit 7640, a beacon receiving unit 7650, an onboard device I / F 7660, a sound / image output unit 7670, an onboard network I / F 7680, and a storage unit 7690 are shown. Other control units also similarly include a microcomputer, a communication I / F, a storage unit, and the like.

[0146] The drive system control unit 7100 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 7100 is used as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating the drive force of the vehicle, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating the braking force of the vehicle, etc. The drive system control unit 7100 may have a function as a control device for an anti-lock braking system (ABS) or an electronic stability control device (ESC), etc.

[0147] The drive system control unit 7100 is connected to the vehicle state detection unit 7110. The vehicle state detection unit 7110 includes, for example, a gyro sensor for detecting the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor for detecting the acceleration of the vehicle, and at least one of sensors for detecting the operation amount of the accelerator pedal, the operation amount of the brake pedal, the steering angle of the steering wheel, the engine speed, or the wheel speed. The drive system control unit 7100 performs arithmetic processing using the signal input from the vehicle state detection unit 7110, and controls the internal combustion engine, the drive motor, the electric power steering device, the brake device, and the like.

[0148] The body system control unit 7200 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 7200 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a reverse light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave transmitted from a mobile device as a key substitute or a signal of various switches may be input to the body system control unit 7200. The body system control unit 7200 receives the input of these radio waves or signals, and controls the door lock device, the power window device, or the lights, etc. of the vehicle.

[0149] The battery control unit 7300 controls the secondary battery 7310 as a power source for the driving motor according to various programs. For example, information on battery temperature, battery output voltage, or battery remaining power, etc. is provided to the battery control unit 7300 from a battery device including the secondary battery 7310. The battery control unit 7300 performs arithmetic processing using these signals and performs temperature adjustment control of the secondary battery 7310 or controls a cooling device provided in the battery device, etc.

[0150] The vehicle exterior information detection unit 7400 detects information about the exterior of the vehicle including the vehicle control system 7000. For example, the vehicle exterior information detection unit 7400 is connected to at least one of the imaging unit 7410 and the vehicle exterior information detection unit 7420. The imaging unit 7410 includes at least one of a time of flight (ToF) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The vehicle exterior information detection unit 7420 includes, for example, at least one of an environmental sensor for detecting current atmospheric conditions or weather conditions and a peripheral information detection sensor for detecting other vehicles, obstacles, pedestrians, etc. around the vehicle including the vehicle control system 7000.

[0151] The environmental sensor may be, for example, at least one of a raindrop sensor for detecting rain, a fog sensor for detecting fog, a sunshine sensor for detecting the degree of sunshine, and a snow sensor for detecting snowfall. The peripheral information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR device (a light detection and ranging device, or a laser imaging detection and ranging device). The imaging unit 7410 and the vehicle exterior information detection unit 7420 may be provided as independent sensors or devices, respectively, or may be provided as a device integrating a plurality of sensors or devices.

[0152] Here, Fig.19 An example of the installation position of the imaging unit 7410 and the vehicle exterior information detection unit 7420 is shown. The imaging units 7910, 7912, 7914, 7916 and 7918 are arranged, for example, on the front nose, rearview mirror, rear bumper and rear door of the vehicle 7900 and at least one of the positions on the upper part of the windshield inside the vehicle. The imaging unit 7910 arranged at the front nose and the imaging unit 7918 arranged at the upper part of the windshield inside the vehicle mainly obtain images in front of the vehicle 7900. The imaging units 7912 and 7914 arranged at the rearview mirror mainly obtain images on both sides of the vehicle 7900. The imaging unit 7916 arranged at the rear bumper or rear door mainly obtains images behind the vehicle 7900. The imaging unit 7918 arranged at the upper part of the windshield inside the vehicle is mainly used to detect the front vehicle, pedestrians, obstacles, signal lights, traffic signs or lanes, etc.

[0153] Notice, Fig.19Examples of imaging ranges of the respective imaging units 7910, 7912, 7914, and 7916 are shown. Imaging range a represents the imaging range of the imaging unit 7910 disposed at the front nose. Imaging ranges b and c represent the imaging ranges of the imaging units 7912 and 7914 disposed at the rearview mirror, respectively. Shooting range d represents the shooting range of the imaging unit 7916 disposed at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained by superimposing image data imaged by the imaging units 7910, 7912, 7914, and 7916.

[0154] The vehicle exterior information detection units 7920, 7922, 7924, 7926, 7928, and 7930 disposed at the front, rear, sides, and corners of the vehicle 7900 and the upper portion of the windshield inside the vehicle may be, for example, ultrasonic sensors or radar devices. The vehicle exterior information detection units 7920, 7926, and 7930 disposed at the front nose, rear bumper, rear door of the vehicle 7900, and the upper portion of the windshield inside the vehicle may be, for example, LIDAR devices. These vehicle exterior information detection units 7920 to 7930 are mainly used to detect vehicles ahead, pedestrians, obstacles, and the like.

[0155] Refer again Fig.18 , will continue to explain. The vehicle exterior information detection unit 7400 enables the imaging unit 7410 to image the exterior of the vehicle and receive the imaged image data. In addition, the vehicle exterior information detection unit 7400 receives detection information from the vehicle exterior information detection unit 7420 connected to the vehicle exterior information detection unit 7400. In the case where the vehicle exterior information detection unit 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the vehicle exterior information detection unit 7400 sends ultrasonic waves or electromagnetic waves, etc., and receives information of the received reflected waves. Based on the received information, the vehicle exterior information detection unit 7400 can perform processing for detecting objects such as people, vehicles, obstacles, traffic lights, or characters on the road surface, or perform processing for detecting their distances. The vehicle exterior information detection unit 7400 can perform environmental recognition processing for identifying rainfall, fog, or road conditions, etc. based on the received information. The vehicle exterior information detection unit 7400 can calculate the distance of objects outside the vehicle based on the received information.

[0156] In addition, based on the received image data, the vehicle exterior information detection unit 7400 may perform recognition processing for recognizing a person, a vehicle, an obstacle, a signal light, or characters on the road surface, or perform processing for detecting their distances. The vehicle exterior information detection unit 7400 may perform processing such as distortion correction or alignment on the received image data, and combine image data imaged by a plurality of different imaging units 7410 to generate a bird's-eye view image or a panoramic image. The vehicle exterior information detection unit 7400 may perform viewpoint conversion processing using image data imaged by an imaging unit 7410 including different imaging parts.

[0157] The in-vehicle information detection unit 7500 detects information about the interior of the vehicle. The in-vehicle information detection unit 7500 is connected to, for example, a driver state detection unit 7510 that detects the driver's state. The driver state detection unit 7510 may include a camera that images the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sounds inside the vehicle, etc. The biosensor is, for example, arranged on a seat surface or a steering wheel, and detects the biometric information of an occupant sitting on the seat or a driver holding the steering wheel. Based on the detection information input from the driver state detection unit 7510, the in-vehicle information detection unit 7500 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off. The in-vehicle information detection unit 7500 can perform processing such as noise elimination processing on the audio signal obtained by sound collection.

[0158] The integrated control unit 7600 controls the overall operation within the vehicle control system 7000 according to various programs. The integrated control unit 7600 is connected to the input unit 7800. The input unit 7800 is implemented by a device capable of input operation by the occupant, such as a touch panel, a button, a microphone, a switch or a joystick. The integrated control unit 7600 may be provided with data obtained by voice recognition of the voice input through the microphone. The input unit 7800 may be, for example, a remote control device using infrared or other radio waves, or an external connection device supporting the operation of the vehicle control system 7000, such as a mobile phone or a personal digital assistant (PDA). The input unit 7800 may be, for example, a camera. In this case, the occupant may input information by gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the occupant may be input. In addition, the input unit 7800 may include, for example, an input control circuit, etc., for generating an input signal based on the information input by the occupant, etc. using the above-mentioned input unit 7800, and outputting the generated input signal to the integrated control unit 7600. The occupant or the like inputs various data to the vehicle control system 7000 or gives instructions for processing operations through the operation input unit 7800 .

[0159] The storage unit 7690 may include a read-only memory (ROM) storing various programs executed by the microcomputer and a random access memory (RAM) storing various parameters, operation results, sensor values, etc. In addition, the storage unit 7690 may be implemented by a magnetic storage device such as a hard disk drive (HDD), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.

[0160] The general communication I / F 7620 is a widely used communication I / F that coordinates communication with various devices existing in the external environment 7750. The general communication I / F 7620 can implement a cellular communication protocol such as Global System for Mobile Communications (GSM (registered trademark)), Worldwide Interoperability for Microwave Access (WiMAX (registered trademark)), Long Term Evolution (LTE (registered trademark)), LTE-advanced (LTE-A), etc., or another wireless communication protocol such as a wireless LAN (also known as Wireless Fidelity (Wi-Fi (registered trademark)), Bluetooth (registered trademark), etc. The general communication I / F 7620 can be connected to a device (e.g., an application server or a control server) existing on an external network (e.g., the Internet, a cloud network, or a company-specific network) via a base station or an access point, for example. In addition, the general communication I / F 7620 can be connected to a terminal existing near the vehicle (the terminal is, for example, a terminal of a driver, a pedestrian, or a store, or a machine type communication (MTC) terminal) using, for example, a point-to-point (P2P) technology.

[0161] The dedicated communication I / F 7630 is a communication I / F that supports a communication protocol developed for use in a vehicle. For example, the dedicated communication I / F 7630 may implement a standard protocol such as Wireless Access to Vehicular Environment (WAVE), which is a combination of Institute of Electrical and Electronics Engineers (IEEE) 802.11p as a lower layer and IEEE 1609 as a higher layer, dedicated short range communication (DSRC), or a cellular communication protocol. The dedicated communication I / F 7630 generally performs V2X communication as a concept including one or more of communication between vehicles (vehicle to vehicle), communication between roads and vehicles (vehicle to infrastructure), communication between vehicles and homes (vehicle to home), and communication between pedestrians and vehicles (vehicle to pedestrian).

[0162] The positioning unit 7640 performs positioning, for example, by receiving a global navigation satellite system (GNSS) signal from a GNSS satellite (e.g., a GPS signal from a global positioning system (GPS) satellite), and generates position information including the latitude, longitude, and altitude of the vehicle. The positioning unit 7640 may identify the current position by exchanging signals with a wireless access point, or may obtain position information from a terminal such as a mobile phone, a personal handyphone system (PHS), or a smart phone with a positioning function.

[0163] The beacon receiving unit 7650 receives, for example, radio waves or electromagnetic waves transmitted from a radio station installed on a road or the like, and thereby obtains information on the current position, congestion, closed roads, required time, etc. The function of the beacon receiving unit 7650 may be included in the above-mentioned dedicated communication I / F 7630.

[0164] The vehicle-mounted device I / F 7660 is a communication interface that coordinates the connection between the microcomputer 7610 and various vehicle-mounted devices 7760 present in the vehicle. The vehicle-mounted device I / F 7660 can establish a wireless connection using a wireless communication protocol such as wireless LAN, Bluetooth (registered trademark), near field communication (NFC), or wireless universal serial bus (WUSB). In addition, the vehicle-mounted device I / F 7660 can establish a wired connection through a universal serial bus (USB), a high-definition multimedia interface (HDMI (registered trademark)), or a mobile high-definition link (MHL) via a connection terminal (and a cable if necessary) not shown in the figure. The vehicle-mounted device 7760 may, for example, include at least one of a mobile device and a wearable device owned by an occupant and an information device carried or attached to the vehicle. The vehicle-mounted device 7760 may also include a navigation device that searches for a path to an arbitrary destination. The vehicle-mounted device I / F 7660 exchanges control signals or data signals with these vehicle-mounted devices 7760.

[0165] The in-vehicle network I / F 7680 is an interface that coordinates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network I / F 7680 transmits and receives signals and the like in accordance with a predetermined protocol supported by the communication network 7010.

[0166] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 according to various programs based on information obtained via at least one of the general communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the vehicle-mounted device I / F 7660, and the vehicle-mounted network I / F 7680. For example, the microcomputer 7610 may also calculate a control target value for a driving force generating device, a steering mechanism, or a braking device based on the information obtained about the inside and outside of the vehicle, and output a control command to the drive system control unit 7100. For example, the microcomputer 7610 may perform cooperative control of functions intended to realize an advanced driver assistance system (ADAS), including vehicle collision avoidance or shock absorption, follow-up driving based on a following distance, vehicle speed keeping driving, vehicle collision warning, or vehicle lane departure warning, etc. In addition, microcomputer 7610 can perform coordinated control aimed at automatic driving by controlling a driving force generating device, a steering mechanism, a braking device, etc. based on information obtained about the vehicle's surroundings, which enables the vehicle to travel automatically without relying on the driver's operation, etc.

[0167] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and objects such as surrounding structures or people, and generate local map information including information about the surrounding environment of the current position of the vehicle based on information obtained via at least one of the general communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the vehicle-mounted device I / F 7660, and the vehicle-mounted network I / F 7680. In addition, the microcomputer 7610 may also predict dangers such as a vehicle collision, the approach of a pedestrian, or the entry of a closed road, based on the obtained information, and generate a warning signal. The warning signal may be, for example, a signal for generating a warning sound or lighting a warning lamp.

[0168] The sound / image output unit 7670 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Fig.18In the example of, an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are shown as output devices. The display unit 7720 may, for example, include at least one of an on-board display and a head-up display. The display unit 7720 may have an augmented reality (AR) display function. The output device may be a device other than these devices, and may be another device such as headphones, a wearable device such as a glasses-type display worn by an occupant, a projector, a lamp, etc. In the case where the output device is a display device, the display device visually displays the results obtained by various processes performed by the microcomputer 7610 or information received from another control unit in various forms such as text, images, tables, charts, etc. In addition, in the case where the output device is an audio output device, the audio output device converts an audio signal consisting of reproduced audio data or sound data, etc. into an analog signal, and outputs the analog signal auditorily.

[0169] exist Fig.18 In the example shown, at least two control units interconnected via the communication network 7010 can be integrated into one control unit. Alternatively, each individual control unit can be composed of multiple control units. In addition, the vehicle control system 7000 may include other control units not shown in the figure. In addition, part or all of the functions implemented by any one of the control units in the above description can be assigned to another control unit. That is, as long as information is sent and received via the communication network 7010, predetermined arithmetic processing can be performed by any control unit. Similarly, a sensor or device connected to any one of the control units can be connected to another control unit, and multiple control units can send and receive detection information to each other via the communication network 7010.

[0170] Note that the present technology can have the following configurations. (1) A light detection device includes a first semiconductor substrate, wherein the first semiconductor substrate includes a first semiconductor layer and a second semiconductor layer stacked on each other, wherein: The first semiconductor layer includes a photoelectric conversion region and a floating diffusion region that accumulates charges generated by photoelectric conversion in the photoelectric conversion region, and The second semiconductor layer includes a capacitor that accumulates charges generated by photoelectric conversion in the photoelectric conversion region. (2) The light detection device according to (1), wherein: The second semiconductor layer includes a gate electrode of a transfer transistor that transfers charges generated by photoelectric conversion in the photoelectric conversion region to the floating diffusion region. The capacitor includes a first electrode, a second electrode arranged facing the first electrode, and a dielectric arranged between the first electrode and the second electrode, and The first electrode and the second electrode are arranged at a layer height between the same layer height as the gate electrode and the same layer height as a wiring layer connected to the gate electrode through a contact. (3) The light detection device according to (2), wherein: The first electrode is arranged at the same layer height as the gate electrode, and The second electrode is arranged at the same layer height as the wiring layer. (4) The light detection device according to (2), wherein: The first electrode is arranged at the same layer height as the gate electrode, and The second electrode is arranged between the gate electrode and the wiring layer. (5) The light detection device according to (2), wherein: The first electrode is arranged between the gate electrode and the wiring layer, and The second electrode is arranged at the same layer height as the wiring layer. (6) The light detection device according to (2), wherein the first electrode and the second electrode are arranged between the wiring layer and the gate electrode. (7) The light detecting device according to any one of (2) to (6), wherein the first electrode and the second electrode have concave-convex portions that mesh with each other, and a gap is provided between opposing surfaces of the first electrode and the second electrode. (8) The photodetection device according to any one of (2) to (7), wherein the dielectric includes an insulating material different from an etching stopper layer arranged between the wiring layer and the gate electrode. (9) The photodetection device according to any one of (2) to (7), wherein the dielectric includes the same insulating material as an etching stopper layer arranged between the wiring layer and the gate electrode. (10) The photodetection device according to (2) to (9), wherein the gate electrode, the wiring layer, the first electrode, and the second electrode include polysilicon. (11) The light detection device according to any one of (2) to (10), wherein the first electrode is set to a predetermined negative potential. (12) The light detection device according to (2), wherein: One of the first electrode or the second electrode includes a columnar member extending in a depth direction of the second semiconductor layer, and The other of the first electrode or the second electrode includes a cylindrical member covering at least a side surface of the one electrode via the dielectric. (13) The light detection device according to (2), wherein the first electrode and the second electrode extend in a depth direction of the second semiconductor layer. (14) The light detection device according to (2), wherein opposing surfaces of the first electrode and the second electrode are arranged along a depth direction of the second semiconductor layer. (15) The light detection device according to (14), wherein the two electrodes of the capacitor are arranged substantially in parallel in a region of the pixel in a plan view. (16) The light detection device according to any one of (1) to (15), wherein: The first semiconductor layer comprises: a plurality of pixels, each of the pixels having the photoelectric conversion region, and a pixel boundary region arranged between two pixels adjacent to each other among the plurality of pixels, and The capacitor is arranged in a region overlapping with each of the pixels in a plan view. (17) The light detection device according to any one of (1) to (11), wherein: The first semiconductor layer comprises: a plurality of pixels, each of the pixels having the photoelectric conversion region, and a pixel boundary region arranged between two pixels adjacent to each other among the plurality of pixels, and The capacitor is arranged in a region coinciding with the pixel boundary region in a plan view. (18) The photodetection device according to any one of (1) to (17), wherein the second semiconductor layer includes a switching transistor that switches whether to transfer the charge accumulated in the floating diffusion region to the capacitor. (19) According to any one of (1) to (18), the light detection device further includes a second semiconductor substrate, which is arranged on the side of the first semiconductor substrate opposite to the light incident surface and processes a pixel signal corresponding to the charge generated by photoelectric conversion in the photoelectric conversion area. (20) The light detecting device according to (19), wherein the facing surfaces of the first semiconductor substrate and the second semiconductor substrate are bonded to each other through contact between pads, a through-hole interconnection, or a bump.

[0171] The aspects of the present disclosure are not limited to the above-mentioned embodiments, but include various modifications that can be thought of by those skilled in the art, and the effects of the present disclosure are not limited to the above-mentioned contents. That is, various additions, modifications and partial deletions can be made without departing from the conceptual ideas and spirit of the present disclosure derived from the matters defined in the claims and their equivalents. Reference numerals list

[0172] 10 Image Sensor 11 Timing Control Circuit 12 Pixel driving circuit 13 pixel array unit 15 Signal Processing Circuit 15a AD conversion circuit 17 Reference voltage generator 18 Horizontal transfer circuit 19 Output Circuit 21 to 24, 26 Wiring layer 25 Second electrode 31 to 34, 36 Contact part 101 Photodiode 102 Pass transistor 103 Reset transistor 104 Switching transistor 105 Amplifier transistor 106 Select transistor 107 nodes 108 Capacitor 112 Transistor drive line 113 Reset transistor drive line 114 Switching transistor drive line 117 Select transistor drive line 121 On-chip lens 122 Color Filters 123 shading film 131 pixels 140 first semiconductor substrate 141 First semiconductor layer 142, 146, 147, 148, 149 n-type semiconductor region 143 p-type semiconductor region 144 Pixel separation unit 145 Component separation unit 150 Second semiconductor layer 151, 151A first electrode 152, 152A, 152B Dielectric 153 Insulation layer 154 Through-hole wiring 155 Wiring 156, 163 electrode pad 160 second semiconductor substrate 161 Semiconductor substrate 162 Insulation film 164 Circuit Elements G1 to G3 Gate electrodes.

Claims

1. A light detection device, comprising a first semiconductor substrate, wherein the first semiconductor substrate comprises a first semiconductor layer and a second semiconductor layer stacked on each other, wherein: The first semiconductor layer includes a photoelectric conversion region and a floating diffusion region that accumulates charges generated by photoelectric conversion in the photoelectric conversion region, and The second semiconductor layer includes a capacitor that accumulates charges generated by photoelectric conversion in the photoelectric conversion region.

2. The light detection device according to claim 1, wherein: The second semiconductor layer includes a gate electrode of a transfer transistor that transfers charges generated by photoelectric conversion in the photoelectric conversion region to the floating diffusion region. The capacitor includes a first electrode, a second electrode arranged facing the first electrode, and a dielectric arranged between the first electrode and the second electrode, and The first electrode and the second electrode are arranged at a layer height between the same layer height as the gate electrode and the same layer height as a wiring layer connected to the gate electrode through a contact.

3. The light detection device according to claim 2, wherein: The first electrode is arranged at the same layer height as the gate electrode, and The second electrode is arranged at the same layer height as the wiring layer.

4. The light detection device according to claim 2, wherein: The first electrode is arranged at the same layer height as the gate electrode, and The second electrode is arranged between the gate electrode and the wiring layer.

5. The light detection device according to claim 2, wherein: The first electrode is arranged between the gate electrode and the wiring layer, and The second electrode is arranged at the same layer height as the wiring layer.

6. The light detection device according to claim 2, wherein: The first electrode and the second electrode are arranged between the wiring layer and the gate electrode.

7. The light detection device according to claim 2, wherein: The first electrode and the second electrode have concavo-convex portions that mesh with each other, and a gap is provided between facing surfaces of the first electrode and the second electrode.

8. The light detection device according to claim 2, wherein: The dielectric includes an insulating material different from an etch stop layer disposed between the wiring layer and the gate electrode.

9. The light detection device according to claim 2, wherein: The dielectric includes the same insulating material as an etch stop layer disposed between the wiring layer and the gate electrode.

10. The light detection device according to claim 2, wherein: The gate electrode, the wiring layer, the first electrode, and the second electrode include polysilicon.

11. The light detection device according to claim 2, wherein: The first electrode is set to a predetermined negative potential.

12. The light detection device according to claim 2, wherein: One of the first electrode or the second electrode includes a columnar member extending in a depth direction of the second semiconductor layer, and The other of the first electrode or the second electrode includes a cylindrical member covering at least a side surface of the one electrode via the dielectric.

13. The light detection device according to claim 2, wherein: The first electrode and the second electrode extend in a depth direction of the second semiconductor layer.

14. The light detection device according to claim 2, wherein: Opposing surfaces of the first electrode and the second electrode are arranged along a depth direction of the second semiconductor layer.

15. The light detection device according to claim 14, wherein: The two electrodes of the capacitor are arranged approximately in parallel in a plan view in the region of the pixel.

16. The light detection device according to claim 1, wherein The first semiconductor layer comprises: a plurality of pixels, each of the pixels having the photoelectric conversion region, and a pixel boundary region arranged between two pixels adjacent to each other among the plurality of pixels, and The capacitor is arranged in a region overlapping with each of the pixels in a plan view.

17. The light detection device according to claim 1, wherein The first semiconductor layer comprises: a plurality of pixels, each of the pixels having the photoelectric conversion region, and a pixel boundary region arranged between two pixels adjacent to each other among the plurality of pixels, and The capacitor is arranged in a region coinciding with the pixel boundary region in a plan view.

18. The light detection device according to claim 1, wherein The second semiconductor layer includes a switching transistor that switches whether to transfer charges accumulated in the floating diffusion region to the capacitor.

19. The light detection device according to claim 1, further comprising a second semiconductor substrate which is arranged on a side of the first semiconductor substrate opposite to the light incident surface and processes a pixel signal corresponding to the charge generated by photoelectric conversion in the photoelectric conversion region.

20. The light detection device according to claim 19, wherein Opposing surfaces of the first semiconductor substrate and the second semiconductor substrate are bonded to each other through contacts between pads, through-hole interconnections, or bumps.

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