Testing system and testing method for photoelectric heterogeneous integrated chip

Abstract

The embodiment of the invention discloses a test system and a test method for a photoelectric heterogeneous integrated chip, and relates to the field of semiconductors. The test system for the photoelectric heterogeneous integrated chip comprises a bearing platform used for bearing the photoelectric heterogeneous integrated chip to be tested. The first acquisition device is arranged on one side of the bearing table and is used for acquiring first position information of the conductive bumps in the target area on the first surface; and the probe assembly is used for adjusting the probe to be in contact with the conductive salient point in the target area according to the first position information. The clamping assembly comprises an annular chuck, and the annular chuck is used for connecting the edge of the photoelectric heterogeneous integrated chip to be tested. And the second acquisition device is arranged on one side, far away from the first acquisition device, of the annular chuck and is used for acquiring second position information of the optical interface of the optical chip according to the position information of the target area. The optical coupling module is arranged on the side, away from the first collecting device, of the annular chuck and used for obtaining optical signals transmitted by the optical interface according to the second position information and testing the optical signals.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a testing system and a testing method for an optoelectronic heterogeneous integrated chip. Background Art

[0002] After the chip is manufactured, it needs to be tested, which generally includes chip function testing, performance testing, and reliability testing. In the chip testing process, the chip or a wafer including multiple chips (die) is usually placed in the test system, and the probes are coupled to the various contacts on the chip to achieve electrical signal interconnection. The chip is input with electrical signals, and then the output response of the chip electrical signals is detected. The input value and the output value are compared and analyzed immediately to achieve the purpose of testing various technical indicators of the chip.

[0003] However, in heterogeneous integrated optoelectronic chips that integrate electrical chips and optical chips, different test processes need to be used to test the performance of different types of chips, which is not conducive to large-scale testing of heterogeneous integrated chips. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a test system and a test method for an optoelectronic heterogeneous integrated chip, which can expand the application scenarios of the test system, improve test efficiency and reduce test costs.

[0005] To achieve the above purpose, the technical solution of this application is implemented as follows:

[0006] On the one hand, an embodiment of the present application provides a test system for an optoelectronic heterogeneous integrated chip. The test system for an optoelectronic heterogeneous integrated chip includes: a carrier, a first acquisition device, a probe assembly, a clamping assembly, a second acquisition device and an optical coupling module.

[0007] The carrier is used to carry the optoelectronic heterogeneous integrated chip to be tested. The optoelectronic heterogeneous integrated chip includes a wafer-level chip, a plurality of conductive bumps on the first surface of the two opposite surfaces of the wafer-level chip, and an electrical chip and an optical chip on the second surface and coupled to the conductive bumps. A first acquisition device is arranged on one side of the carrier, and is used to collect first position information of the conductive bumps in the target area on the first surface. The probe assembly is used to adjust the contact between the probe and the conductive bumps in the target area according to the first position information. The clamping assembly includes an annular chuck, and the annular chuck is used to connect the edge of the optoelectronic heterogeneous integrated chip to be tested. The second acquisition device is arranged on the side of the annular chuck away from the first acquisition device, and is used to collect the second position information of the optical interface of the optical chip in the target area according to the position information of the target area. The optical coupling module is arranged on the side of the annular chuck away from the first acquisition device, and is used to obtain the optical signal transmitted by the optical interface according to the second position information and perform a test.

[0008] In some examples, the optical coupling module includes: an optical fiber array and a drive motor assembly. The optical fiber array is used to obtain the optical signal transmitted by the optical interface. The drive motor assembly is coupled to the optical fiber array and is used to adjust the relative position between the optical fiber array and the optical interface according to the power of the optical signal transmitted by the optical interface. The drive motor assembly is used to adjust the movement of the optical fiber array along a first direction, a second direction, and a third direction, and the first direction, the second direction, and the third direction intersect each other.

[0009] In some examples, the probe assembly includes a probe card, and a first position adjustment mechanism connected to the probe card. The first position adjustment mechanism includes a pressure sensor and a first mechanical arm, and the first mechanical arm is used to adjust the distance between the probe card and the optoelectronic heterogeneous integrated chip to be tested according to the pressure value between the probe card and the optoelectronic heterogeneous integrated chip to be tested sensed by the pressure sensor;

[0010] Wherein, at least one probe of the probe card contacts one of the conductive bumps in the target area.

[0011] In some examples, the optoelectronic heterogeneous integrated chip to be tested is divided into a plurality of target areas. The first acquisition device is also used to re-acquire the first position information of the conductive bump in another target area on the first surface. The clamping assembly also includes a second mechanical arm connected to the annular chuck, and the second mechanical arm is used to move the optoelectronic integrated chip to be tested according to the updated target area.

[0012] In some examples, the carrier includes a second position adjustment mechanism and a carrier surface connected to the second position adjustment mechanism, and the second position adjustment mechanism is used to adjust the position of the carrier surface according to the target area. The carrier surface at least covers the portion of the optoelectronic heterogeneous integrated chip corresponding to the target area and exposes the optical interface; the area of ​​the target area is characterized by the area of ​​the probe card board of the probe assembly.

[0013] In some examples, the second acquisition device, the optical coupling module and the carrier are located on the same mobile platform. The second position adjustment mechanism is also used to drive the mobile platform to move.

[0014] In some examples, a plurality of vacuum adsorption holes are disposed on the surface of the carrier platform; and a distribution density of the plurality of vacuum adsorption holes increases as the area of ​​the surface of the carrier platform decreases.

[0015] In the test system of the above-mentioned optoelectronic heterogeneous integrated chip, the first and second surfaces of the optoelectronic heterogeneous integrated chip to be tested are exposed by the annular chuck, the probe is coupled with the conductive bump on the first surface, and the electrical signal is transmitted to the electrical chip and the optical chip; and the optical coupling module can receive the optical signal transmitted by the optical chip on the second surface, and the annular chuck will not block the optical signal emitted by the optical chip on the second surface. In this way, the optical chip and the electrical chip can be tested synchronously by the probe on one side of the optoelectronic heterogeneous integrated chip to be tested and the optical coupling module on the other side, which not only expands the application scenarios of testing different types of integrated chips, but also improves the test efficiency, is conducive to large-scale testing, and reduces the test cost. Moreover, the combined structure and the positional relationship between the carrier, the first acquisition device, the probe assembly, the clamping assembly, the second acquisition device and the optical coupling module used in the test system of the above-mentioned optoelectronic heterogeneous integrated chip are conducive to improving the structural compactness of the test system, and the position of each functional structure is controllably adjustable, which is suitable for the test process of various heterogeneous integrated chips, and improves the scope of application of the test system.

[0016] On the other hand, an embodiment of the present application provides a method for testing an optoelectronic heterogeneous integrated chip. The testing method includes: connecting an annular chuck to the edge of the optoelectronic heterogeneous integrated chip to be tested; determining a target area on the optoelectronic heterogeneous integrated chip to be tested; and providing a plurality of conductive bumps coupled to an optical chip and an electrical chip in the target area. According to the position information of the target area, the carrier table is controlled to contact part of the optoelectronic heterogeneous integrated chip to be tested in the target area, and the optical interface of the optical chip is exposed. The first position information of the conductive bump in the target area is collected, and the probe of the probe assembly is adjusted to contact the conductive bump according to the first position information. An electrical signal is input to the optical chip and the electrical chip through the probe. The electrical chip is tested, and the optical signal transmitted by the optical interface of the optical chip is obtained to test the optical chip.

[0017] In some examples, the testing of the optical chip includes: collecting second position information of the optical interface of the optical chip, and obtaining the optical signal power transmitted by the optical interface, adjusting the relative position of the optical fiber array in the optical coupling module and the optical interface, and testing the optical chip.

[0018] In some examples, the test method further includes: when the probe contacts the conductive bump, obtaining a first distance between the probe card of the probe assembly and the optoelectronic heterogeneous integrated chip to be tested, and a pressure value between the probe and the conductive bump. According to the pressure value between the probe and the conductive bump, adjusting the first distance to a second distance, the second distance being a distance that satisfies a preset pressure value between the probe and the conductive bump. The second distance is less than or equal to the first distance. The electrical chip in the target area is tested by the probe.

[0019] The above-mentioned testing method is a method for driving a testing system for optoelectronic heterogeneous integrated chips to perform chip testing, and has the same beneficial effects as the testing system for optoelectronic heterogeneous integrated chips, which will not be described in detail here.

[0020] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the structure of an optoelectronic heterogeneous integrated chip provided in one embodiment of the present application;

[0022] Figure 2 A schematic diagram of the structure of a test system for an optoelectronic heterogeneous integrated chip provided in one embodiment of the present application;

[0023] Figure 3 A schematic diagram of the structure of a test system for an optoelectronic heterogeneous integrated chip provided in an embodiment of the present application Figure 2 ;

[0024] Figure 4 A schematic diagram of a testing method for an optoelectronic heterogeneous integrated chip provided in an embodiment of the present application Figure 1 ;

[0025] Figure 5 A schematic diagram of a testing method for an optoelectronic heterogeneous integrated chip provided in an embodiment of the present application Figure 2 . DETAILED DESCRIPTION

[0026] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0027] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0028] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0029] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers.

[0030] Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part. When the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has a first element, component, region, layer or part.

[0031] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0032] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0033] With the vigorous development of artificial intelligence and the digital economy, the demand for high-speed data transmission and fiber-optic network equipment is growing. Traditional optical modules and on-chip copper interconnects can no longer meet the rapidly growing data transmission needs. Therefore, optoelectronic heterogeneous integration technology has emerged. The high transmission and low latency characteristics of silicon-based optoelectronic heterogeneous integrated chips have effectively solved the bandwidth bottleneck and power consumption wall problems faced by traditional copper interconnection technology. High-density optoelectronic heterogeneous integrated chips conform to the needs and challenges of technological development in terms of the continuity of Moore's Law, and have broad prospects and potential in applications. In terms of development trends, they show the characteristics of higher integration, higher energy efficiency and lower power consumption. However, they also face challenges such as the complexity of interconnection technology, material and process compatibility, and large-scale testing and screening.

[0034] In the field of large-scale integrated circuit manufacturing, wafer-level testing can determine the quality of process and performance before the chip is cracked, reduce the loss of subsequent chip packaging, and improve the yield of the back-end manufacturing process. It can provide a fast and efficient solution for chip inspection and screening, and is an important guarantee for promoting the large-scale and standardized development of products. However, the functions of silicon-based optoelectronic heterogeneous integrated chips are complex, and they involve optical coupling and the integration of multiple chips. At present, it is impossible to directly obtain the comprehensive parameter performance of the real chip through wafer testing, which hinders the large-scale industrial application of silicon-based optoelectronic heterogeneous integrated chips.

[0035] Therefore, in order to achieve efficient testing and batch screening of silicon-based optoelectronic heterogeneous integrated chips, it is necessary to design a wafer-level testing device that can achieve automated optical coupling and automated needle testing while ensuring that the chip is non-destructive and warped, and ultimately achieve wafer-level comprehensive parameter measurement and screening. The device has a compact structure, reasonable layout, operability, and strong scalability. It effectively solves the screening problem of high-density silicon-based optoelectronic heterogeneous integrated chips, and greatly reduces the cost of large-scale application of silicon-based heterogeneous integrated core particles and optoelectronic fusion chips.

[0036] Based on this, the embodiments of the present application provide a testing system and a testing method for an optoelectronic heterogeneous integrated chip, which can improve the testing efficiency of the optoelectronic heterogeneous integrated chip and reduce the testing cost.

[0037] For example, Figure 1 As shown, the present application provides an optoelectronic heterogeneous integrated chip 100. The optoelectronic heterogeneous integrated chip 100 includes: a wafer-level chip 110, a plurality of electrical chips 120 and at least one optical chip 130.

[0038] It is understandable that the electrical chip 120 is used to implement electrical signal transmission, and the optical chip 130 is used to implement conversion of electrical signals into optical signals.

[0039] The wafer-level chip 110 includes a first semiconductor substrate 111 and a plurality of transfer structures 112 disposed in the first semiconductor substrate 111. The transfer structures 112 extend from one side surface of the wafer-level chip 110 to the other side surface in a direction perpendicular to the plane where the wafer-level chip 110 is located. For example, the wafer-level chip 110 includes a first surface 1101 and a second surface 1102 opposite to each other. The transfer structures 112 form conductive bumps 1121 on a portion of the first surface 1101. The portion of the transfer structures 112 extending to the second surface is coupled to the electrical chip 120 and the optical chip 130.

[0040] A plurality of electrical chips 120 are disposed at intervals on the second surface 1102 of the wafer-level chip 110 and are coupled to the conductive bumps 1121. The electrical chips 120 include a second semiconductor substrate ( Figure 1The material used for the first semiconductor substrate 111 may be different from the material used for the second semiconductor substrate.

[0041] The optical chip 130 and the electrical chip 120 are spaced apart and arranged on the second surface 1102 of the wafer-level chip 110, and are coupled to the conductive bumps 1121. The optical chip 130 includes a third semiconductor substrate ( Figure 1 The material used for the first semiconductor substrate 111 may be different from the material used for the third semiconductor substrate.

[0042] For example, Figure 1 As shown, the optical chip 130 includes at least one optical interface 131 , and the optical interface 131 can transmit optical signals.

[0043] It should be noted that the optoelectronic heterogeneous integrated chip 100 provided in the present application is for the purpose of explaining the testing principle and workflow of the testing system, and does not limit the specific structure of the optoelectronic heterogeneous integrated chip 100 .

[0044] Based on the above exemplary optoelectronic heterogeneous integrated chip 100 , the following example of the present application provides a test system that can synchronously test the optical chip 130 and the electrical chip 120 in the same test system.

[0045] In some embodiments, Figure 2 and Figure 3 As shown, the present application provides a testing system 200 for an optoelectronic heterogeneous integrated chip.

[0046] The test system 200 for optoelectronic heterogeneous integrated chip includes: a carrier 210 , a first acquisition device 220 , a probe assembly 230 , a clamping assembly 240 , a second acquisition device 250 and an optical coupling module 260 .

[0047] The carrier 210 is used to carry the optoelectronic heterogeneous integrated chip 100 to be tested. Figure 1 As shown, the optoelectronic heterogeneous integrated chip 100 includes a wafer-level chip 110 , a plurality of conductive bumps 1121 located on a first surface 1101 of two opposite surfaces of the wafer-level chip 110 , and an electrical chip 120 and an optical chip 130 located on a second surface 1102 and coupled to the conductive bumps 1121 .

[0048] The first acquisition device 220 is disposed on one side of the carrier 210, and is used to collect the first position information of the conductive bump 1121 in the target area M on the first surface 1101. For example, the first acquisition device 220 may include a microscope and a drive motor. The microscope may include a stereo microscope, a mirror microscope, a telephoto microscope or a digital microscope. The motor driving the microscope to move may include at least one of a stepper motor drive, a servo motor drive and a linear motor drive.

[0049] The probe assembly 230 is used to adjust the probe 231 to contact the conductive bump 1121 in the target area M according to the first position information.

[0050] The clamping assembly 240 includes an annular chuck 241, which is used to connect the edge of the optoelectronic heterogeneous integrated chip 100 to be tested. For example, the annular chuck 241 is a hollow structure, and when the edge of the optoelectronic heterogeneous integrated chip 100 to be tested is connected and fixed, the conductive bumps 1121, the electrical chip 120, and the optical chip 130 on the optoelectronic heterogeneous integrated chip 100 to be tested can be exposed.

[0051] The second acquisition device 250 is disposed on a side of the annular chuck 241 away from the first acquisition device 220, and is used to acquire the second position information of the optical interface 131 of the optical chip 130 in the target area M according to the position information of the target area M. For example, the second acquisition device 250 may include a microscope and a drive motor. The microscope may include a stereo microscope, a mirror microscope, a telephoto microscope or a digital microscope. The motor driving the microscope to move may include at least one of a stepper motor drive, a servo motor drive and a linear motor drive.

[0052] The optical coupling module 260 is disposed on a side of the annular chuck 241 away from the first acquisition device 220 , and is used to acquire the optical signal transmitted by the optical interface 131 according to the second position information and perform a test.

[0053] The first surface 1101 and the second surface 1102 of the optoelectronic heterogeneous integrated chip 100 to be tested are exposed by the annular chuck 241 (see Figure 1 ), probe 2311 (see Figure 2 and Figure 3 ) is coupled with the conductive bump 1121 on the first surface 1101 to transmit electrical signals to the electrical chip 120 and the optical chip 130; and the optical coupling module 260 can receive the optical signal transmitted by the optical chip 130 on the second surface 1102. In this way, the optical chip 130 and the electrical chip 120 can be tested synchronously through the probe 2311 on one side of the optoelectronic heterogeneous integrated chip 100 to be tested and the optical coupling module 260 on the other side, which not only expands the application scenarios of testing different types of integrated chips, but also improves the test efficiency, is conducive to large-scale testing, and reduces the test cost.

[0054] Moreover, the combined structure and mutual positional relationship of the carrier 210, the first acquisition device 220, the probe assembly 230, the clamping assembly 240, the second acquisition device 250 and the optical coupling module 260 used in the above-mentioned optoelectronic heterogeneous integrated chip testing system 200 are conducive to improving the structural compactness of the testing system, and the position of each functional structure is controllably adjustable, which is suitable for the testing process of various heterogeneous integrated chips, thereby improving the scope of application of the testing system.

[0055] For example, the material of the annular chuck 241 can be one or more of metal, ceramic or glass.

[0056] In some examples, the annular chuck 241 may be connected to the edge of the optoelectronic heterogeneous integrated chip 100 to be tested by clamping or vacuum adsorption.

[0057] For example, the annular chuck 241 is clamped with the edge of the optoelectronic heterogeneous integrated chip 100 to be tested, and a buffer pad can be provided at the clamping position to improve the tightness of the clamping and reduce the probability of wear on the edge of the optoelectronic heterogeneous integrated chip 100 to be tested by the clamping method.

[0058] Alternatively, the annular chuck 241 is connected to the edge area of ​​the optoelectronic heterogeneous integrated chip 100 to be tested by vacuum adsorption, and a plurality of vacuum adsorption holes can be formed on the front of the annular structure of the annular chuck 241 (i.e., the surface for adsorbing the optoelectronic heterogeneous integrated chip 100 to be tested), and a vacuum adsorption gas source interface connected to the vacuum adsorption holes is formed on the side of the annular structure of the annular chuck 241, and an air flotation groove for blowing away the optoelectronic heterogeneous integrated chip 100 to be tested is formed on the back of the annular structure of the annular chuck 241, and an air flotation gas source interface connected to the air flotation groove is formed on the side of the annular structure of the annular chuck 241. The number and arrangement of the vacuum adsorption holes can be set according to actual needs.

[0059] In some examples, such as Figure 3 As shown, the optical coupling module 260 includes: an optical fiber array 261 and a driving motor assembly 262 .

[0060] The optical fiber array 261 is used to obtain the optical signal transmitted by the optical interface 131. For example, the optical fiber array 261 includes a plurality of optical fibers arranged in an array, the tip of the optical fiber can be a reflective optical fiber or a lens optical fiber, and the optical fiber material can be silicon, glass or polymer material.

[0061] The driving motor assembly 262 is coupled to the optical fiber array 261, and is used to adjust the relative position between the optical fiber array 261 and the optical interface 131 according to the acquired optical signal power transmitted by the optical interface 131. The driving motor assembly 262 is used to adjust the optical fiber array 261 to move along the first direction X, the second direction Y and the third direction Z, and the first direction X, the second direction Y and the third direction Z intersect each other.

[0062] For example, the driving motor assembly 262 may include a piezoelectric ceramic motor with three-axis displacement and a stepper motor with three-axis rotation displacement. The piezoelectric ceramic motor with three-axis displacement can drive the optical fiber array 261 to move linearly along the first direction X, the second direction Y and / or the third direction Z, and the stepper motor with three-axis rotation displacement can adjust the rotation angle of the optical fiber array 261. In this way, the optical fiber end of the optical fiber array 261 can be parallel to the oblique waveguide of the optical chip 130 to improve the optical coupling efficiency, thereby improving the sensitivity and accuracy of the test of the optoelectronic heterogeneous integrated chip 100.

[0063] Furthermore, the driving motor assembly 262 may also include a capacitive height probe or a laser rangefinder to precisely control the distance between the tip of the optical fiber array and the optical chip 130 .

[0064] In some examples, such as Figure 3 As shown, the probe assembly 230 includes a probe card 231 and a first position adjustment mechanism 232 connected to the probe card 231 .

[0065] The first position adjustment mechanism 232 includes a pressure sensor and a first mechanical arm (not shown in the figure), and the first mechanical arm is used to adjust the distance between the probe card 231 and the optoelectronic heterogeneous integrated chip 100 to be tested according to the pressure value between the probe card 231 and the optoelectronic heterogeneous integrated chip 100 to be tested sensed by the pressure sensor.

[0066] At least one probe 2311 of the probe card 231 contacts a conductive bump 1121 in the target area M.

[0067] For example, the driving motor of the first mechanical arm may include at least one of a stepper motor drive, a servo motor drive and a linear motor drive. The present application does not impose any specific restrictions on the structure of the first mechanical arm, as long as it can drive the position of the probe card 231 to change.

[0068] The probe card 231 includes a plurality of probes 2311. When the probe card 231 is aligned with a target area on the optoelectronic heterogeneous integrated chip 100 to be tested, at least one probe 2311 is brought into contact with a conductive bump 1121 in the target area M according to the first position information of the plurality of conductive bumps 1121 and the arrangement of the probes 2311 (e.g., the number of probes 2311, the spacing between adjacent probes 2311, etc.), which is beneficial to improving the transmission yield of electrical signals to the optical chip 130 and the electrical chip 120 and improving the accuracy of the test.

[0069] In some examples, the optoelectronic heterogeneous integrated chip 100 to be tested is divided into a plurality of target regions M. The first acquisition device 220 is further used to re-acquire first position information of the conductive bump 1121 in another target region M on the first surface 1101 .

[0070] The clamping assembly 240 further includes a second mechanical arm (not shown in the figure) connected to the annular chuck 241 , and the second mechanical arm is used to move the optoelectronic heterogeneous integrated chip 100 to be tested according to the updated target area M.

[0071] For example, the optoelectronic heterogeneous integrated chip 100 to be tested can be divided into multiple target areas M. After the optical chip 130 and the electrical chip 120 in one target area M are tested, the first acquisition device 220 can re-determine another target area M. When the first mechanical arm drives the probe card 231 to leave the surface of the optoelectronic heterogeneous integrated chip 100 to be tested, and the optoelectronic heterogeneous integrated chip 100 to be tested is not fixed on the carrier 210, the second mechanical arm of the clamping assembly 240 can move the annular chuck 241 (i.e., the optoelectronic heterogeneous integrated chip 100 to be tested) according to the first position information, and adjust the position of the probe card 231 through the first mechanical arm according to the first position information of the conductive bump 1121 in another target area M, so that the probe card 231 contacts the conductive bump 1121 in the updated target area M. The present application does not impose any specific restrictions on the structure of the second mechanical arm, and it is sufficient that the position of the annular chuck 241 can be driven to change.

[0072] In some examples, such as Figure 3 As shown, the carrying platform 210 includes a second position adjustment mechanism 211 and a carrying platform surface 212 connected to the second position adjustment mechanism 211 .

[0073] The second position adjustment mechanism 211 is used to adjust the position of the carrier table 212 according to the target area M. The carrier table 212 at least covers the portion of the optoelectronic heterogeneous integrated chip 100 corresponding to the target area M and exposes the optical interface 131. The area of ​​the target area M is represented by the area of ​​the probe card board 2310 of the probe assembly 230.

[0074] For example, the second position adjustment mechanism 211 can drive the carrier 210 to move within a range close to the target area M, and can also adjust the distance between the carrier 210 and the optoelectronic heterogeneous integrated chip 100 to be tested, so that the carrier table 212 contacts the part of the optoelectronic heterogeneous integrated chip 100 to be tested corresponding to the target area M, providing support and fixation. At the same time, in order to meet the optical coupling module 260 to obtain the optical interface 131 to collect the optical signal, the carrier table 212 needs to expose the optical interface 131.

[0075] The area of ​​the target region M is represented by the area of ​​the probe card board 2310 of the probe assembly 230. The combined force of the probe 2311 and the carrier table 212 can be considered to reduce the probability of warping of the structure of other regions (regions other than the target region) on the entire optoelectronic heterogeneous integrated chip 100 to be tested due to a small force area. The carrier table 212 can be set to at least cover the portion of the optoelectronic heterogeneous integrated chip 100 corresponding to the target region M to improve the structural stability.

[0076] For example, the driving motor of the second position adjustment mechanism 211 may include at least one of a stepper motor drive, a servo motor drive and a linear motor drive.

[0077] In some examples, such as Figure 2 As shown, the second acquisition device 250, the optical coupling module 260 and the carrier 210 are located on the same mobile platform 270. The second position adjustment mechanism 211 (see Figure 3 ) is also used to drive the mobile platform 270 to move.

[0078] For example, consider a test process in which the second acquisition device 250 is used to determine the second position information of the optical interface 131 in the target area M, the carrier 210 is adjusted to contact the portion of the optoelectronic heterogeneous integrated chip 100 to be tested corresponding to the target area M and expose the optical interface 131, and then the optical coupling module 260 collects the optical signal transmitted by the optical interface 131. The second acquisition device 250, the optical coupling module 260 and the carrier 210 are arranged on the same mobile platform 270, which is conducive to simplifying the operating steps and improving the test efficiency.

[0079] For example, one or more of an air-floating platform, a marble platform and a buffer pad can be provided at the bottom of the mobile platform 270 to achieve a supporting and shock-absorbing effect.

[0080] In some examples, such as Figure 3 As shown, a plurality of vacuum adsorption holes are disposed on the support platform surface 212 ; the distribution density of the plurality of vacuum adsorption holes increases as the area of ​​the support platform surface 212 decreases.

[0081] In this way, when the area of ​​the optoelectronic heterogeneous integrated chip 100 to be tested is relatively large relative to the area of ​​the carrier table 212, for example, the area of ​​the optoelectronic heterogeneous integrated chip 100 to be tested may be 8 inches, 10 inches or 12 inches, and the area of ​​the carrier table 212 may be 1 inch, 2 inches, etc., and not larger than the area of ​​the optoelectronic heterogeneous integrated chip 100 to be tested. The portion of the optoelectronic heterogeneous integrated chip 100 to be tested that is pressed by the probe 2311 (i.e., the target area) is brought into contact with the carrier table 212, and considering the joint force of the probe 2311 and the carrier table 212, the probability of warping of the structure of other areas (areas other than the target area) on the entire optoelectronic heterogeneous integrated chip 100 to be tested due to the small force area can be reduced, thereby improving the structural stability.

[0082] For example, the shape of the arrangement of the multiple vacuum adsorption holes can be circular, rectangular or other polygonal, which can be set according to actual needs.

[0083] In addition, a semiconductor cooler and / or a thermistor may be disposed under the carrier table 212 to adjust the temperature of the optoelectronic heterogeneous integrated chip 100 to be tested, thereby reducing the adverse effects of the number of test operations or the test environment on the accuracy of the test results.

[0084] On the other hand, Figure 4 and Figure 5 As shown, the embodiment of the present application provides a test method for an optoelectronic heterogeneous integrated chip. The test method includes: S100 to S400.

[0085] S100: the annular chuck 241 is connected to the edge of the optoelectronic heterogeneous integrated chip 100 to be tested; a target area M on the optoelectronic heterogeneous integrated chip 100 to be tested is determined. The target area M is provided with a plurality of conductive bumps 1121 coupled to the optical chip 130 and the electrical chip 120 .

[0086] For example, Figure 1 The structure of the optoelectronic heterogeneous integrated chip 100 shown in FIG. 1 can be determined after the optoelectronic heterogeneous integrated chip 100 is placed on the carrier 210. Figure 3 The target area M is shown.

[0087] S200 : According to the position information of the target area M, the table surface 212 of the carrier platform is controlled to contact a portion of the optoelectronic heterogeneous integrated chip 100 to be tested in the target area M, and the optical interface 131 of the optical chip 130 is exposed.

[0088] For example, the controller controls the second position adjustment mechanism to adjust the displacement of the carrier 210 according to the position information of the target area M, and when the carrier 210 is located within the range of the corresponding target area, controls the carrier surface 212 to contact part of the optoelectronic heterogeneous integrated chip 100 to be tested in the target area M, and exposes the optical interface 131 of the optical chip 130.

[0089] S300 : collecting first position information of the conductive bump 1121 in the target area M, and adjusting the probe of the probe assembly 230 to contact the conductive bump 1121 according to the first position information.

[0090] For example, Figure 2 As shown, the first acquisition device 220 acquires the first position information of the conductive bump 1121 in the target area M and transmits it to the controller. The controller adjusts the displacement of the first mechanical arm of the probe assembly 230 according to the first position information, drives the probe card 231 to move, and makes at least one probe 2311 on the probe card 231 contact with a conductive bump 1121.

[0091] S400 : Inputting electrical signals to the optical chip 130 and the electrical chip 120 through the probe 2311 , testing the electrical chip 120 , and acquiring optical signals transmitted by the optical interface 131 of the optical chip 130 , and testing the optical chip 130 .

[0092] For example, when the optoelectronic heterogeneous integrated chip 100 to be tested is stably placed on the carrier table 212 and the probe 2311 is in contact with the conductive bump 1121, an electrical signal is input to the conductive bump 1121 through the probe 2311 and is received by the optical chip 130 and the electrical chip 120 coupled to the conductive bump 1121.

[0093] Then, the signal fed back by the electrical chip 120 can be transmitted through the probe 2311 to test the electrical chip 120 ; and the optical chip 130 converts the received electrical signal into an optical signal and outputs it from the optical interface 131 to test the optical chip 130 .

[0094] During the above test method, the test operations of the optical chip 130 and the electrical chip 120 can be implemented simultaneously, which expands the test application scope of the semiconductor structure integrating different types of chips, improves the test efficiency, and helps to reduce the test cost.

[0095] In some examples, such as Figure 5 As shown, the testing method further includes S500.

[0096] S500: After the optoelectronic heterogeneous integrated chip 100 to be tested contacts the carrier 210, the profile information of the optoelectronic heterogeneous integrated chip 100 to be tested is collected, and the placement angle of the optoelectronic heterogeneous integrated chip 100 to be tested is adjusted by the clamping component 240 so that the optoelectronic heterogeneous integrated chip 100 to be tested does not tilt. In this way, the yield rate and conductive performance of the electrical connection between the probe 2311 and the conductive bump 1121 can be improved.

[0097] In some examples, such as Figure 5 As shown, step S400: testing the optical chip 130 includes S410.

[0098] S410 : collecting second position information of the optical interface 131 of the optical chip 130 , and obtaining the optical signal power transmitted by the optical interface 131 , adjusting the relative position of the optical fiber array 261 in the optical coupling module 260 and the optical interface 131 , and testing the optical chip 130 .

[0099] For example, the second acquisition device 250 may include a microscope and a drive motor. The microscope is used to determine the second position information of the optical interface 131 in the target area M. The drive motor (for example, by controlling the displacement of the mobile platform 270) adjusts the position of the optical coupling module 260 near the target area M. Then, the optical coupling module 260 can receive the optical signal transmitted by the optical chip 130 on the second surface 1102, and adjust the relative position of the optical fiber array 261 and the optical interface 131 according to the power of the optical signal. For example, adjust the rotation angle of the optical fiber array 261, and / or the distance between the optical fiber tip and the optical interface 131. In this way, the optical coupling efficiency can be improved and the accuracy of the test of the optical chip 130 can be improved.

[0100] In some examples, such as Figure 5 As shown, the testing method also includes: S420 to S440.

[0101] S420 : when the probe 2311 is in contact with the conductive bump 1121 , a first distance between the probe card 231 of the probe assembly 230 and the optoelectronic heterogeneous integrated chip 100 to be tested and a pressure value between the probe 2311 and the conductive bump 1121 are obtained.

[0102] For example, the first acquisition device 220 may acquire a first distance between the probe card 231 of the probe assembly 230 and the optoelectronic heterogeneous integrated chip 100 to be tested.

[0103] Furthermore, the probe assembly 230 includes a probe card 231 and a first position adjustment mechanism 232 connected to the probe card 231. The first position adjustment mechanism 232 includes a pressure sensor and a first mechanical arm. The pressure sensor can obtain the pressure value between the probe 2311 and the conductive bump 1121.

[0104] S430: According to the pressure value between the probe 2311 and the conductive bump 1121, the first distance is adjusted to a second distance, where the second distance satisfies a preset pressure value between the probe 2311 and the conductive bump 1121. The second distance is less than or equal to the first distance.

[0105] For example, the controller determines whether the current crimping distance between the probe 2311 and the conductive bump 1121 meets the second distance based on the first distance collected by the first collection device 220 and the pressure value collected by the pressure sensor. The second distance refers to a preset distance that ensures that the probe 2311 does not damage the surface of the optoelectronic heterogeneous integrated chip 100 to be tested and has good electrical connection performance with the conductive bump 1121. In this way, the distance between the probe card 231 of the probe assembly 230 and the optoelectronic heterogeneous integrated chip 100 to be tested is adjusted to the second distance, which can meet the conditions for testing the chip.

[0106] It is understandable that in the process of adjusting the distance between the probe card 231 of the probe assembly 230 and the optoelectronic heterogeneous integrated chip 100 to be tested, a larger spacing will be first satisfied to prevent the probe 2311 from directly contacting the surface of the optoelectronic heterogeneous integrated chip 100 to be tested, resulting in damage or scratches on the surface of the optoelectronic heterogeneous integrated chip 100 to be tested. Then, the distance between the probe card 231 and the optoelectronic heterogeneous integrated chip 100 to be tested is gradually reduced to a second distance.

[0107] S440 : Testing the electrical chip 120 in the target area M through the probe 2311 .

[0108] For example, after the electrical signal is transmitted to the electrical chip 120 through the probe 2311, the electrical signal is processed and fed back inside the electrical chip 120. The controller determines the performance of the electrical chip 120 based on the feedback signal of the electrical chip 120 transmitted by the probe 2311, thereby implementing the test of the electrical chip 120.

[0109] Based on this, Figure 5 As shown, after the above-mentioned step S420 and step S430, electrical signals can be output to the optical chip 130 and the electrical chip 120 through the probe. Then, the time sequence of the test of the optical chip 130 and the test of the electrical chip 120 can be adjusted according to actual needs. The overall testing process is reflected in the synchronous testing of the optical chip 130 and the electrical chip 120.

[0110] It should be noted that the embodiments of the test system for optoelectronic heterogeneous integrated chips provided in the present application and the test method embodiments belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict. However, it should be further noted that the test system for optoelectronic heterogeneous integrated chips provided in the embodiments of the present application, the combination of its various technical features can already solve the technical problems to be solved by the present application; therefore, the signal processing device provided in the embodiments of the present application may not be limited by the test method provided in the embodiments of the present application, and any test system for optoelectronic heterogeneous integrated chips that can apply the test method provided in the embodiments of the present application is within the scope of protection of the present application.

[0111] The above is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A test system for optoelectronic heterogeneous integrated chips, characterized in that: include: A carrier, used for carrying an optoelectronic heterogeneous integrated chip to be tested; the optoelectronic heterogeneous integrated chip comprises a wafer-level chip, a plurality of conductive bumps on a first surface of two opposite sides of the wafer-level chip, and an electrical chip and an optical chip on a second surface and coupled to the conductive bumps; A first acquisition device, disposed on one side of the carrier, for acquiring first position information of the conductive bumps in a target area on the first surface; a probe assembly, used for adjusting the contact between the probe and the conductive bump in the target area according to the first position information; A clamping assembly, comprising an annular chuck, wherein the annular chuck is used to connect to the edge of the optoelectronic heterogeneous integrated chip to be tested; A second acquisition device, disposed on a side of the annular chuck away from the first acquisition device, for acquiring second position information of the optical interface of the optical chip in the target area according to the position information of the target area; The optical coupling module is arranged on a side of the annular chuck away from the first acquisition device, and is used to obtain the optical signal transmitted by the optical interface according to the second position information and perform a test.

2. The test system according to claim 1, characterized in that: The optical coupling module comprises: An optical fiber array, used for acquiring an optical signal transmitted by the optical interface; A drive motor assembly coupled to the optical fiber array, for adjusting the relative position between the optical fiber array and the optical interface according to the acquired optical signal power transmitted by the optical interface; The driving motor assembly is used to adjust the optical fiber array to move along a first direction, a second direction and a third direction, and the first direction, the second direction and the third direction intersect each other.

3. The test system according to claim 1, characterized in that: The probe assembly includes a probe card, and a first position adjustment mechanism connected to the probe card; The first position adjustment mechanism includes a pressure sensor and a first mechanical arm, wherein the first mechanical arm is used to adjust the distance between the probe card and the optoelectronic heterogeneous integrated chip to be tested according to the pressure value between the probe card and the optoelectronic heterogeneous integrated chip to be tested sensed by the pressure sensor; Wherein, at least one probe of the probe card contacts one of the conductive bumps in the target area.

4. The test system according to claim 1, characterized in that: The optoelectronic heterogeneous integrated chip to be tested is divided into a plurality of target areas; The first acquisition device is also used to re-acquire the first position information of the conductive bump in another target area on the first surface; The clamping assembly also includes a second mechanical arm connected to the annular chuck, and the second mechanical arm is used to move the optoelectronic integrated chip to be tested according to the updated target area.

5. The test system according to claim 1, characterized in that: The carrying platform comprises a second position adjustment mechanism and a carrying platform surface connected to the second position adjustment mechanism, wherein the second position adjustment mechanism is used to adjust the position of the carrying platform surface according to the target area; The surface of the carrier platform at least covers a portion of the optoelectronic heterogeneous integrated chip corresponding to the target area and exposes the optical interface; the area of ​​the target area is represented by the area of ​​the probe card board of the probe assembly.

6. The test system according to claim 5, characterized in that: The second acquisition device, the optical coupling module and the carrying platform are located on the same mobile platform; The second position adjustment mechanism is also used to drive the mobile platform to move.

7. The test system according to claim 5, characterized in that: A plurality of vacuum adsorption holes are arranged on the surface of the carrying platform; and the distribution density of the plurality of vacuum adsorption holes increases as the area of ​​the surface of the carrying platform decreases.

8. A method for testing an optoelectronic heterogeneous integrated chip, characterized in that: include: The annular chuck is connected to the edge of the optoelectronic heterogeneous integrated chip to be tested; Determining a target area on the optoelectronic heterogeneous integrated chip to be tested; A plurality of conductive bumps coupled to the optical chip and the electrical chip are provided in the target area; Control the table surface of the carrier to contact the part of the optoelectronic heterogeneous integrated chip to be tested in the target area according to the position information of the target area, and expose the optical interface of the optical chip; Collecting first position information of the conductive bump in the target area, and adjusting the probe of the probe assembly to contact the conductive bump according to the first position information; Inputting electrical signals to the optical chip and the electrical chip through the probe; The electrical chip is tested, and an optical signal transmitted by an optical interface of the optical chip is obtained to test the optical chip.

9. The testing method according to claim 8, characterized in that: The testing of the optical chip includes: collecting second position information of the optical interface of the optical chip, obtaining the optical signal power transmitted by the optical interface, adjusting the relative position of the optical fiber array in the optical coupling module and the optical interface, and testing the optical chip.

10. The testing method according to claim 8, characterized in that: The test method also includes: When the probe is in contact with the conductive bump, obtaining a first distance between the probe card of the probe assembly and the optoelectronic heterogeneous integrated chip to be tested, and a pressure value between the probe and the conductive bump; According to the pressure value between the probe and the conductive bump, the first distance is adjusted to a second distance, the second distance being a distance that satisfies a preset pressure value between the probe and the conductive bump; wherein the second distance is less than or equal to the first distance; The electrical chip in the target area is tested by the probe.

Images