Test method of vertical LED chip
By using open-hole bearing film and micro-cutting technology during the testing of vertical LED chips, the problem of wafers being easily broken during vacuum adsorption and release is solved, and the subsequent processing is smooth and the integrity protection of wafers is achieved.
Patent Information
- Application Number
- CN202411669725.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-21
- Publication Date
- 2025-02-28
AI Technical Summary
During the testing of vertical LED chips, wafers are prone to fragmentation during vacuum adsorption and release, resulting in difficulty in subsequent processing.
The open-hole bearing film is used to carry the wafer, and the risk of wafer breaking is reduced through the steps of micro-cutting on the front, testing and film change back cut.
It effectively reduces the risk of wafer chip breaking, ensures the smooth progress of subsequent processing, and maintains the integrity of the wafer by turning the film, avoiding the scrapping of the entire wafer.
Smart Images
Figure CN119535164A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of semiconductor technology, and in particular to a testing method for a vertical LED chip. Background Art
[0002] The vertical LED chip has a special electrode distribution structure, with its P-type electrode and N-type electrode located on the front and back of the chip body respectively, so that the current almost entirely flows vertically through the chip epitaxial layer, which can be used with large current and has good heat dissipation performance.
[0003] In the testing phase of the vertical LED chip manufacturing process, due to the limitations of the structural characteristics of the vertical LED chip, it is usually necessary to remove the carrier film that supports the wafer, and place the micro-cut wafer with the vertical LED chip test unit on the metal platform of the tester for testing through vacuum adsorption; the metal platform directly contacts the back of the wafer to form an ohmic contact, and then the probe contacts the vertical LED chip test unit on the front of the wafer to form a test path. However, since the wafer has been micro-cut and there is no carrier film attached, the wafer is easily broken during vacuum adsorption and vacuum release, making subsequent processing difficult. Summary of the invention
[0004] The purpose of the present invention is to overcome the shortcomings of the prior art. The present invention provides a testing method for a vertical LED chip. By using a perforated carrier film to support a wafer, and then sequentially performing front micro-cutting, testing, and back-cutting with film replacement, the risk of wafer breakage is effectively reduced, ensuring the smooth progress of subsequent processing.
[0005] The present invention provides a method for testing a vertical LED chip, comprising the following steps:
[0006] S1, attaching a first carrier film to a carrier ring, and opening at least three holes on the first carrier film in the inner region of the carrier ring;
[0007] S2, attaching a wafer to the first carrier film in the inner ring area of the carrier ring, wherein the hole exposes the back side of the wafer;
[0008] S3, cutting the front side of the wafer to form a plurality of vertical LED chip test units on the front side of the wafer;
[0009] S4, attaching the first carrier film to a metal platform of a testing machine, so that the back side of the wafer forms an ohmic contact with the metal platform through the hole;
[0010] S5. The probe of the testing machine performs contact testing on the plurality of vertical LED chip testing units one by one;
[0011] S6, flipping the tested wafer onto the second carrier film to expose the back side of the wafer, and cutting the wafer from the back side to obtain a number of vertical LED chip particles.
[0012] Specifically, in step S2, the center of the wafer coincides with the center of the carrier ring.
[0013] Specifically, the diameter of the wafer ranges from 75 to 300 mm.
[0014] Specifically, the centers of all the holes are located on the same circle, and all the holes are distributed at equal intervals around the center of the carrying ring.
[0015] Specifically, the total number of the holes is N, where N is an integer, 3≤N≤5.
[0016] Specifically, the total area of the N holes is S N , the area of the wafer is S J , the S N and the S J The constraint relationship is: S N =0.4S J .
[0017] Specifically, the radius of any hole is R1, the radius of the wafer is R2, the distance from the center of each hole to the center of the carrying ring is L1, and the constraint relationship among R1, R2 and L1 is:
[0018]
[0019] Specifically, the wafer includes a substrate and a chip structure layer arranged on the substrate, the thickness of the chip structure layer is H, the cutting depth of the front side of the wafer is h, and the constraint relationship between H and h is:
[0020]
[0021] Specifically, the first carrier film is a blue film; and / or the second carrier film is a blue film.
[0022] Specifically, the carrying ring is an iron ring or a stainless steel ring.
[0023] Compared with the prior art, the present invention has the following beneficial effects:
[0024] In the testing method of the present invention, a first carrying film having at least three holes is used in conjunction with a carrying ring to carry a wafer. The wafer can subsequently be tested by forming ohmic contact with the metal platform through the holes. There is no need to remove the film before the test, and there is no need to perform vacuum adsorption during the test, thereby effectively reducing the risk of wafer breakage and ensuring the smooth progress of subsequent processing. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0026] Figure 1 is a schematic flow chart of a method for testing a vertical LED chip in an embodiment of the present invention;
[0027] Figure 2 is a schematic diagram of a first distribution structure of holes in an embodiment of the present invention;
[0028] Figure 3 is a schematic diagram of a second distribution structure of holes in an embodiment of the present invention;
[0029] Figure 4 Schematic diagram of the third distribution structure of holes in an embodiment of the present invention.
[0030] In the accompanying drawings, 1, hole; 2, wafer; 3, first carrier film; 4, carrier ring. DETAILED DESCRIPTION
[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0032] The present invention provides a method for testing a vertical LED chip. Figure 1 A schematic flow chart of a method for testing a vertical LED chip in an embodiment of the present invention is shown, comprising the following steps:
[0033] S1, attaching a first carrier film to a carrier ring, and opening at least three holes on the first carrier film in the inner region of the carrier ring;
[0034] S2, attaching a wafer to the first carrier film in the inner ring area of the carrier ring, wherein the hole exposes the back side of the wafer;
[0035] S3, cutting the front side of the wafer to form a plurality of vertical LED chip test units on the front side of the wafer;
[0036] S4, attaching the first carrier film to a metal platform of a testing machine, so that the back side of the wafer forms an ohmic contact with the metal platform through the hole;
[0037] S5. The probe of the testing machine performs contact testing on the plurality of vertical LED chip testing units one by one;
[0038] S6, flipping the tested wafer onto the second carrier film to expose the back side of the wafer, and cutting the wafer from the back side to obtain a number of vertical LED chip particles.
[0039] In the testing method of the present invention, a first carrying film having at least three holes is used in conjunction with a carrying ring to carry a wafer. The wafer can subsequently be tested by forming ohmic contact with the metal platform through the holes. There is no need to remove the film before the test, and there is no need to perform vacuum adsorption during the test, thereby effectively reducing the risk of wafer breakage and ensuring the smooth progress of subsequent processing.
[0040] Moreover, even if the wafer is broken, the existence of the first carrier film can keep the shape of the wafer intact. The broken wafer can be transferred to a new carrier film by flipping the film and continuing the cutting process on the back. This can avoid the entire wafer from being scrapped and only lose part of the yield, and still harvest a large number of vertical LED chip particles.
[0041] The present invention also provides a method for testing a vertical LED chip. Figure 1 , including the following steps:
[0042] S1, attaching a first carrier film to a carrier ring, and opening at least three holes on the first carrier film in the inner region of the carrier ring;
[0043] Figure 2 shows a schematic diagram of a first distribution structure of holes in an embodiment of the present invention, Figure 3 Schematic diagram of a second distribution structure of holes in an embodiment of the present invention is shown. Figure 4 A schematic diagram of a third distribution structure of holes in an embodiment of the present invention is shown.
[0044] At least three holes 1 are provided to ensure that the subsequent wafer 2 can form an ohmic contact with the metal platform through the holes 1. Specifically, the total number of holes 1 is N, where N is an integer, 3≤N≤5; see Figure 2 , Figure 3 and Figure 4 , that is, the total number of the holes 1 can be 3, 4 or 5, the centers of all the holes 1 are located on the same circle, and all the holes 1 are equally spaced around the center of the carrier ring 4, while ensuring that the wafer 2 can form an ohmic contact with the metal platform through the holes 1, and also ensuring that the first carrier film 3 still has good mechanical strength. Preferably, the total number of the holes 1 is 3, so that the first carrier film 3 has good stability and is easy to process.
[0045] In some specific embodiments, the first carrier film 3 is a blue film, which has a large adhesive peeling degree and can be firmly attached to the carrier ring 4 and can also fix the wafer 2 well later.
[0046] In some specific embodiments, the carrying ring 4 is an iron ring or a stainless steel ring, which is strong and durable.
[0047] S2, attaching a wafer to the first carrier film in the inner ring area of the carrier ring, wherein the hole exposes the back side of the wafer;
[0048] The back side of the wafer 2 can subsequently form an ohmic contact with the metal platform through the hole 1. Figure 2 , Figure 3 or Figure 4 The center of the wafer 2 coincides with the center of the carrying ring 4 , ensuring that the hole 1 can evenly expose the back side of the wafer 2 .
[0049] In some specific embodiments, the diameter of the wafer 2 ranges from 75 to 300 mm, and the diameter of the wafer 2 can specifically be 75 mm, 100 mm, 125 mm, 150 mm, 200 mm or 300 mm, covering common wafers 2 on the market.
[0050] Preferably, the diameter of the wafer 2 is in the range of 150 to 300 mm, which is the size range of mainstream wafers on the market.
[0051] In some specific embodiments, the total area of the N holes 1 is S N , the area of the wafer 2 is S J , the S N and the S J The constraint relationship is: S N =0.4S J If S N Less than 0.4 times S J, the total area of the hole 1 is insufficient, making it difficult for the wafer 2 to form an effective area electrical connection with the metal platform, affecting the subsequent test; if S N Greater than 0.4 times S J , the total area of the holes 1 is too large, which will seriously weaken the mechanical strength of the first carrier film 3 and make it easy to deform, resulting in the inability to provide effective fixing effect for the wafer 2, which will affect subsequent cutting, testing, etc.
[0052] In some specific embodiments, the radius of any of the holes 1 is R1, the radius of the wafer 2 is R2, the distance from the center of each of the holes 1 to the center of the carrier ring 4 is L1, and the constraint relationship among R1, R2 and L1 is:
[0053]
[0054] Since the center of the wafer 2 coincides with the center of the carrying ring 4, L1 is also the distance from the center of each hole 1 to the center of the wafer 2. R1, R2 and L1 satisfy the above-mentioned constraint relationship, which not only enables the wafer 2 to form a good ohmic contact with the metal platform through the hole 1, but also ensures the mechanical strength of the first carrying film 3, avoids the first carrying film 3 from being easily deformed, and thus can provide effective fixing effect for the wafer 2.
[0055] Specifically, by S N =0.4S J It can be seen that NπR1 2 =0.4πR2 2 ,Right now
[0056] The distance between the centers of two adjacent holes 1 is L2; with the center of the wafer 2 as the vertex, the angle between the centers of two adjacent holes 1 is 2π / N, then
[0057] therefore
[0058]
[0059] In order to ensure the mechanical strength of the first carrier film 3, the distance between the centers of two adjacent holes 1 needs to be controlled to be L2=2R1+(R2-R1) / N, then
[0060]
[0061] S3, cutting the front side of the wafer to form a plurality of vertical LED chip test units on the front side of the wafer;
[0062] The wafer includes a substrate and a chip structure layer arranged on the substrate. The front side of the wafer is cut, that is, the chip structure layer is slightly cut, and the chip structure layer is divided into several vertical LED chip test units, which is convenient for subsequent testing of the photoelectric parameters of individual chip particles one by one.
[0063] In some specific embodiments, the thickness of the chip structure layer is H, the cutting depth of the front side of the wafer is h, and the constraint relationship between H and h is:
[0064]
[0065] It is ensured that the chip structure layer can be appropriately divided into a number of vertical LED chip test units.
[0066] Specifically, the thickness of the chip structure layer ranges from 170 to 190 mm, that is, H∈[170, 190], which can be adjusted according to the specific process flow; preferably, the thickness of the chip structure layer is 185 mm, and during the cutting process, the vertical LED chip test unit formed has clear boundaries and is not adhered.
[0067] S4, attaching the first carrier film to a metal platform of a testing machine, so that the back side of the wafer forms an ohmic contact with the metal platform through the hole;
[0068] Through the cooperation of the first carrier film and the carrier ring, after the wafer is attached to the metal platform of the test machine, there is no need for vacuum adsorption, which can reduce the risk of wafer breakage.
[0069] Specifically, the metal platform contacts the N-type electrode on the back side of the wafer. The N-type electrode on the back side of the wafer is now a whole and is electrically connected to all vertical LED chip test units.
[0070] S5. The probe of the testing machine performs contact testing on the plurality of vertical LED chip testing units one by one;
[0071] The probes of the test machine will contact the P-type electrodes on the vertical LED chip test unit one by one. The probes, P-type electrodes, N-type electrodes and metal platform form a test path, thereby realizing the test of photoelectric parameters.
[0072] S6, flipping the tested wafer onto the second carrier film to expose the back side of the wafer, and cutting the wafer from the back side to obtain a number of vertical LED chip particles.
[0073] When cutting from the back side of the wafer, the cutting track needs to be aligned with the cutting mark on the front side of the wafer to ensure that complete vertical LED chip particles are obtained.
[0074] In some specific embodiments, the second carrier film is a blue film, which has good bonding stability and can firmly fix the wafer, which is beneficial to ensure that the wafer can be stably cut and is not easily shifted.
[0075] The testing method of the present invention makes the holes of appropriate size and reasonable distribution by constraining the total area of the holes, the radius of a single hole, the distance from the center of each hole to the center of the supporting ring, etc., so that the wafer and the metal platform form an effective area of electrical connection and obtain a good ohmic contact effect; it also ensures the mechanical strength of the first supporting film and avoids the first supporting film from being easily deformed, thereby providing an effective fixing effect for the wafer.
[0076] In addition, the testing method of the present invention ensures that the chip structure layer can be appropriately divided into a number of vertical LED chip testing units by restricting the cutting depth of the front side of the wafer, thereby facilitating the smooth progress of the test.
[0077] Example 1
[0078] Take a wafer with a diameter of 75 mm as an example: the radius of the wafer R2 = 37.5 mm, and the area of the wafer S J =1406.25π; the total area of N holes S N =0.4S J =562.5π; the relevant parameters of the hole are set as shown in Table 1:
[0079]
[0080] Example 2
[0081] Take a wafer with a diameter of 100 mm as an example: the radius of the wafer R2 = 50 mm, the area of the wafer S J =2500π; the total area of N holes is S N =0.4S J =1000π; the relevant parameters of the hole are set as shown in Table 2:
[0082]
[0083] Example 3
[0084] Take a wafer with a diameter of 125 mm as an example: the radius of the wafer R2 = 62.5 mm, the area of the wafer S J =3906.25π; the total area of N holes S N =0.4S J =1562.5π; the relevant parameters of the hole are set as shown in Table 3:
[0085]
[0086] Example 4
[0087] Take a wafer with a diameter of 150 mm as an example: the radius of the wafer R2 = 75 mm, the area of the wafer S J =5625π; the total area of N holes S N =0.4S J =2250π; the relevant parameters of the hole are set as shown in Table 4:
[0088]
[0089] Example 5
[0090] Take a wafer with a diameter of 200 mm as an example: the radius of the wafer R2 = 100 mm, the area of the wafer S J =10000π; the total area of N holes is S N =0.4S J =4000π; the relevant parameters of the hole are set as shown in Table 5:
[0091]
[0092] Example 6
[0093] Take a wafer with a diameter of 300 mm as an example: the radius of the wafer R2 = 150 mm, the area of the wafer S J =22500π; the total area of N holes is S N =0.4S J =9000π; the relevant parameters of the hole are set as shown in Table 6:
[0094]
[0095] The above is a detailed introduction to a testing method for a vertical LED chip provided in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention.
Claims
1. A method for testing a vertical LED chip, characterized in that: The following steps are involved: S1, attaching a first carrier film to a carrier ring, and opening at least three holes on the first carrier film in the inner region of the carrier ring; S2, attaching a wafer to the first carrier film in the inner ring area of the carrier ring, wherein the hole exposes the back side of the wafer; S3, cutting the front side of the wafer to form a plurality of vertical LED chip test units on the front side of the wafer; S4, attaching the first carrier film to a metal platform of a testing machine, so that the back side of the wafer forms an ohmic contact with the metal platform through the hole; S5. The probe of the testing machine performs contact testing on the plurality of vertical LED chip testing units one by one; S6, flipping the tested wafer onto the second carrier film to expose the back side of the wafer, and cutting the wafer from the back side to obtain a number of vertical LED chip particles.
2. The method for testing a vertical LED chip according to claim 1, wherein: In step S2, the center of the wafer coincides with the center of the carrier ring.
3. The method for testing a vertical LED chip according to claim 1, wherein: The diameter of the wafer ranges from 75 to 300 mm.
4. The method for testing a vertical LED chip according to claim 1, wherein: The centers of all the holes are located on the same circle, and all the holes are distributed at equal intervals around the center of the carrying ring.
5. The method for testing a vertical LED chip according to claim 4, wherein: The total number of the holes is N, where N is an integer, 3≤N≤5.
6. The method for testing a vertical LED chip according to claim 5, wherein: The total area of the N holes is S N , the area of the wafer is S J , the S N and the S J The constraint relationship is: S N =0.4S J .
7. The method for testing a vertical LED chip according to claim 6, wherein: The radius of any of the holes is R1, the radius of the wafer is R2, the distance from the center of each hole to the center of the carrying ring is L1, and the constraint relationship among R1, R2 and L1 is:
8. The method for testing a vertical LED chip according to claim 1, wherein: The wafer comprises a substrate and a chip structure layer arranged on the substrate, the thickness of the chip structure layer is H, the cutting depth of the front side of the wafer is h, and the constraint relationship between H and h is:
9. The method for testing a vertical LED chip according to claim 1, wherein: The first carrier film is a blue film; and / or the second carrier film is a blue film.
10. The method for testing a vertical LED chip according to claim 1, wherein: The carrying ring is an iron ring or a stainless steel ring.