High-density addressable ring oscillator test circuit and method

Abstract

The invention discloses an addressable ring oscillator test circuit. The circuit comprises an addressing circuit, a switching circuit, an excitation circuit, a test RO unit group and a frequency dividing circuit. Wherein the test RO unit group comprises a plurality of test RO units, the addressing circuit comprises a column addressing circuit and a row addressing circuit, the column addressing circuit and the row addressing circuit are respectively connected to the test RO unit group through the switching circuit, and the test RO units in the test RO unit group are gated through addresses. And the output end of each test RO unit is connected with a corresponding frequency divider in the frequency dividing circuit. The test circuit further comprises a sensing circuit connected to the test RO unit group. The test RO unit is composed of a NAND gate, a plurality of phase inverters and a driver, and the NAND gate and the plurality of phase inverters are connected end to end and input to the driver.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor wafer testing, and in particular relates to an addressable ring oscillator testing circuit and method. Background Art

[0002] As the process nodes of CMOS technology continue to shrink, device performance will change randomly due to random fluctuations in dopants, changes in metal gate grain size and line edge roughness, resulting in increasingly significant changes in circuit propagation delay. Ring Oscillator (RO) consists of an odd number of inverters connected end to end to form a closed loop, thus forming a positive feedback path, allowing the circuit to self-oscillate without an external input signal. The oscillation frequency of the ring oscillator is related to the delay of the circuit, and is often used to measure the delay of the circuit, as well as for reliability research, aging feature simulation, in-situ sensors and canary circuits in integrated circuits. Ring oscillators are widely used in integrated circuit design. They can be used as a source of clock signals, and can also be used to test and monitor circuit performance and reliability. Since RO is highly sensitive to process parameters, it is usually used to characterize changes in circuit frequency, leakage current and other performance.

[0003] Since the monitoring of random changes requires a large amount of test data support, the time and area cost of testing ROs one by one is too high. Therefore, when large-scale RO testing is required, the current mainstream test solution is to select the RO to be tested through the addressing circuit to improve the area utilization. However, since each test unit is set with an independent signal output, the number of tests per unit area is limited.

[0004] Here, area cost refers to the relationship between the area occupied by a function on a silicon wafer and the cost required for that area. Area utilization refers to the ratio of the part used to implement the circuit function to the total area within a given silicon wafer area. In large-scale RO testing, improving area utilization means that more test circuits can be integrated on the same silicon wafer area, thereby improving test efficiency and reducing costs. Summary of the invention

[0005] The present disclosure discloses a high-density addressable ring oscillator test circuit, which includes an addressing circuit, a switch circuit, an excitation circuit, a test RO unit group, a frequency division circuit and a sensing circuit.

[0006] The test RO unit group includes a plurality of test RO units.

[0007] The addressing circuit includes a column addressing circuit and a row addressing circuit. The column addressing circuit and the row addressing circuit are respectively connected to the test RO unit group through a switch circuit, and the test RO unit therein is selected by an address.

[0008] The sensing circuit is connected to the test RO unit group.

[0009] The present invention discloses a high-density addressable ring oscillator test circuit, which integrates RO units of different levels and different loads and uses a switching circuit to share all RO power supply signals, thereby performing large-scale, rapid and accurate tests on different RO units, improving the integration of the test circuit and obtaining higher area utilization and accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, in which:

[0011] Figure 1 Schematic diagram of an addressable ring oscillator test circuit according to one embodiment of the present invention.

[0012] Figure 2 A schematic diagram of the composition of a ring oscillator RO unit according to one embodiment of the present invention.

[0013] Figure 3 A schematic diagram of the composition of a frequency divider circuit according to one embodiment of the present invention.

[0014] Figure 4 A schematic diagram of the composition of a sensing circuit according to one embodiment of the present invention.

[0015] Figure 5 Schematic diagram of RO units with different loads according to one embodiment of the present invention.

[0016] Figure 6 Schematic diagram of a switch circuit for sharing an enable signal and a power signal according to one embodiment of the present invention.

[0017] Figure 7 Schematic diagram of an output common divider addressable ring oscillator test circuit according to one embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to meet the requirements of fast, high-density and large-scale testing for monitoring the random changes of integrated circuit devices, the present disclosure provides a high-density addressable ring oscillator test circuit. This addressable ring oscillator test circuit can not only realize the performance measurement of large-scale RO (including frequency, dynamic current, DC current, etc.), but also achieve higher area utilization and accuracy.

[0019] According to one or more embodiments, an addressable ring oscillator test circuit is mainly composed of an addressing circuit, a switching circuit, an excitation circuit, a sensing circuit, a test RO unit and a frequency division circuit. Considering that the measurable frequency range of the test equipment is limited, it is necessary to use a frequency divider to reduce the frequency. The specific technical solution is as follows:

[0020] (1) It includes an addressing circuit, a switching circuit, an excitation circuit, a test RO unit, a frequency division circuit, and a sensing circuit. The row and column addresses can be set to any bit width in the addressing circuit. The following is an introduction using 4-bit row and column addresses. The row and column addresses are RA[0:3] and CA[0:3], respectively, which are converted into 16-bit R[0:15] and C[0:15] by a decoder, so that 16×16=256 RO units can be tested. The excitation circuit inputs Enable and VDD signals, and the switch circuit outputs Enable[0:255] and VDD[0:255] signals under the action of R[0:15] and C[0:15]. It is connected to 256 RO units to control whether the RO units are oscillating. For example Figure 1 As shown in the figure, "Enable" means enable, and "Address" means address.

[0021] The addressable ring oscillator test circuit includes:

[0022] A column addressing circuit is connected to a ring oscillator group composed of a plurality of RO units through a column switch circuit;

[0023] A row addressing circuit, connected to the ring oscillator group composed of multiple RO units through a row switch circuit;

[0024] A switch circuit for controlling connection or disconnection with the ring oscillator;

[0025] An excitation circuit is connected to the column switch circuit and the row switch circuit to provide an excitation signal to the ring oscillator to start the oscillation process;

[0026] The RO group includes a plurality of ring oscillators (such as FO1 RO, FO2 RO, FO3 RO, and FO4 RO), and each ring oscillator is connected to a corresponding frequency divider;

[0027] The sensing circuit is connected to the RO group to monitor and record the output of the ring oscillator.

[0028] Therefore, the test circuit realizes parallel testing of multiple ring oscillators to improve test efficiency and reduce costs. By using the column addressing circuit and the switch circuit, the ring oscillator to be tested can be effectively selected and controlled, while the excitation circuit and the sensing circuit are responsible for providing the necessary excitation and monitoring functions.

[0029] Furthermore, each RO unit is composed of a NAND gate, several inverters and a driver Driver, and the NAND gate and several inverters are connected end to end and input to the driver. The output end of the last inverter connected to the input end of the driver is connected end to end with the NAND gate, connected to one input end of the NAND gate, and the other input end of the NAND gate is the enable signal Enable control end, and the signal at the connection is V OUT0 The NAND gate is used to realize the enable signal Enable control. The NAND gate and the inverter VDD are connected together and controlled by an external signal. At this time, due to the large number of ring oscillators, the influence of the distributed capacitance of the devices will be superimposed, making the output waveform V OUT0 It presents a dome wave and needs to be input into the driver for wave rectification without affecting the signal frequency. Figure 2 shown.

[0030] Furthermore, the frequency divider can have a variety of structures. In this embodiment, it is composed of a plurality of cascaded D flip-flops. The frequency divider reduces the frequency to a measurable range of the test machine. The specific number of levels is determined according to the frequency of the ring oscillator. Figure 3 shown.

[0031] Furthermore, each RO test unit is connected to a sensing circuit to sense the actual VDD SENSE The Enable signal is input to the NAND gate of the RO unit, that is, the gate end of the MOS tube. The gate current is extremely small, and the voltage drop caused by the transmission gate in the switch circuit can be ignored. VDD is connected to the source end of the PMOS, and the current is large. The voltage drop caused by the transmission gate needs to be considered. Therefore, a sensing circuit is set, that is, the transmission gate is connected to the VDD end to obtain the signal VDD SENSE . Figure 4 The connection relationship between the sensing circuit and the RO unit is shown. The VDD signal of the RO is obtained through the sensing circuit. SENSE . Figure 4 The necessity of introducing a sensing circuit is explained. Because the switching circuit will produce a voltage drop, causing the actual VDD value of the RO unit to be tested to be lower than the ideal value, a sensing circuit is needed to sense the voltage drop in real time. The sensing circuit is composed of transmission gates, such as Figure 4 As shown in the figure, when the Address[N] signal is 1, the gate voltage of the transmission gate NMOS is 1, and the gate voltage of the PMOS is 0, so the transmission gate is turned on, and the VDD of the RO unit can be transmitted to the other end to obtain VDD SENSE .

[0032] The sensing circuit is used to monitor and measure the actual voltage VDD of the power supply voltage (VDD) when passing through the transmission gate. SENSEA transmission gate is set on the VDD path to connect and disconnect the power path. The transmission gate consists of an N-channel MOSFET (NMOS) and a P-channel MOSFET (PMOS) connected in parallel, and the power supply can be controlled by address selection. VDD SENSE Used to monitor and adjust the power supply voltage so that the sensing circuit is used to ensure the stability of the power supply voltage and the reliability of the circuit.

[0033] (2) Each RO test unit can be composed of inverters of different levels and loads. In this example, in order to compare the performance of RO, four types of inverters with different loads are designed, namely FO1, FO2, FO3, and FO4, where FO1, FO2, FO3, and FO4 are 4×16 each. Here, load refers to fan-out, that is, load capacitance. The connection structure with the inverter is: Assuming an FO3 type inverter, two identical inverters are connected to the input of one inverter, but the output is left floating, such as Figure 5 shown.

[0034] The RO frequencies of inverters with different loads are different. In order to improve the area utilization, ROs with the same load share a frequency divider, so a total of four frequency dividers are required, V OUT_DIV_FO1 、V OUT_DIV_FO2 、V OUT_DIV_FO3 、V OUT_DIV_FO4 are their respective output signals. Similarly, different levels of ring oscillator frequencies are different, and the number of frequency dividers may be different. It is necessary to divide the modules according to the required number of frequency dividers and determine the number of output signals. Figure 5 As shown. The frequency of RO is inversely proportional to the number of inverters in RO. The smaller the number of levels, the higher the frequency. When the output frequency of RO is higher than the frequency that can be measured by the test machine, it is necessary to connect a frequency divider for frequency division. In this example, a frequency divider composed of D flip-flops is used. N D flip-flops can achieve 2^N times frequency division. For example, if the number of levels of the frequency divider is 3 (that is, it is composed of 3 D flip-flops), 8 times frequency reduction can be achieved. Because RO units of different levels and different loads are integrated in the RO array, the output frequencies of different RO units are different, so it is necessary to connect frequency dividers of different levels. When the number of RO units is smaller, the output frequency is larger, and the number of frequency dividers required is larger.

[0035] (3) The enable signal and power signal of all RO units share a pad contact PAD, and the selection is realized through the addressing circuit and the switch circuit. The switch circuit realizes the control of the enable and power of all ROs to be tested by using one Enable and one VDD, and does not directly control the sensing and RO output. Figure 1As shown in the figure, the input signals are mainly divided into address signals RA, CA and excitation signals Enable and VDD. The function of the switch circuit is to use the address signal to distribute the excitation signal to each unit under test. For example, if the unit under test in the first row and the first column is selected, then Enable[0]=Enable(PAD input), VDD[0]=VDD(PAD input), and Enable[N] and VDD[N] of other units under test are both 0.

[0036] The switch circuit TG_PD is realized by a combination of a transmission gate and a pull-down tube, such as Figure 6 As shown, when Address[N] = 1, the pull-down tube is closed, the transmission gate is opened, and V OUT =V IN Otherwise, the pull-down tube is turned on, V OUT =0. In the addressing circuit, R[0:15] and C[0:15] can generate 256 signals, corresponding to the Enable and VDD signals of the excitation circuit, and can generate 256 groups of Enable[N] and VDD[N], which uniquely correspond to the row and column addresses, and can effectively improve the chip area utilization. This is because, for example, for the embodiment of the present disclosure, 4 bits of row address and column address are set, and the entire circuit only needs one Enable and one VDD PAD. With the help of the addressing circuit and the switching circuit, 256 Enable signals and 256 VDD signals can be generated, and then 256 RO units can be controlled. Therefore, only one group of Enable and VDD PAD is needed to control 256 RO units, which effectively saves the number of PADs, thereby increasing the number of tests per unit area. In addition, modifying the number of bits of the row and column addresses can further increase the number of tests per unit area.

[0037] like Figure 6 As shown. The switch circuit TG_PD includes a transmission gate and a pull-down tube connected to the transmission gate. The transmission gate (TG) is composed of an NMOS and a PMOS in parallel. When the control signal turns on the transmission gate, the input signal can be transmitted to the output without loss; when the transmission gate is closed, there is a high impedance state between the input and the output, and the signal cannot be transmitted. The pull-down tube is an NMOS, and its function is to provide a certain low level state for the output when signal transmission is not required. In CMOS circuits, pull-down tubes are used to achieve the output of logic "0". The pull-down tube ensures that the output terminal will not be suspended when the transmission gate is closed to prevent the circuit state from being uncertain.

[0038] (4) If the outputs of multiple RO units share a frequency divider, that is, if the outputs of multiple RO units are directly connected together, the signals will interfere with each other and affect the oscillation. Therefore, all RO units connected to the same frequency divider can share an output port through a transmission gate, and the RO units that are not selected are turned off. Figure 7 As shown, each RO unit is connected together through a transmission gate. By controlling the opening and closing of the transmission gate, it can be ensured that only one RO unit output is connected to the divider at the same time. This can prevent multiple signals from affecting the input of the divider at the same time. The row and column address switch signals are used to control the transmission gate selection.

[0039] Therefore, the disclosed embodiment integrates RO units of different levels and different loads, and uses a switch circuit to realize the sharing of all RO power supply signals, so as to perform large-scale, fast and accurate testing of different RO units. That is, when using the addressing method to perform RO large-scale testing, all RO units share the power supply signal, and the design of RO units of different levels and different loads can be integrated. Here, the RO unit is composed of an odd number of inverters, and different levels are the number of different inverters. In a large-scale RO array, RO units of different levels and different loads can be integrated at the same time, without being limited to only changing the level or only changing the load, and the integration and usability are stronger.

[0040] In this embodiment, the solution of improving the integration of the test circuit by sharing the signal ports of all RO test units, the number of RO parallel test arrays, the number of row and column address bits, the number of different loads and levels, the principle structure of the divider and the driver, the structure of the switching circuit, and the number of shared signals of the RO units can all be selected and changed according to different needs.

[0041] In summary, the beneficial effects of the present disclosure include:

[0042] 1) In the test circuit disclosed in the present invention, all ROs share one Enable terminal and VDD PAD, which can significantly increase the number of tests per unit area.

[0043] 2) The test circuit disclosed in the present invention provides a circuit that allows testing of RO units with different loads and different levels, and has more application scenarios and is more flexible.

[0044] 3) The test circuit disclosed in the present invention uses a sensing circuit to sense the VDD voltage drop of the RO unit, which can accurately detect the actual operating voltage of the circuit and ensure accurate analysis of subsequent test data.

[0045] The advantage of using a common Enable terminal and VDD PAD for all ROs is that the number of tests per unit area can be significantly increased. Figure 7 As shown, combined Figure 1In the example of this patent, 4 bits are set for the row address and column address respectively. The entire circuit only needs one Enable and one VDD PAD. With the help of the addressing circuit and the switch circuit, 256 Enable signals and 256 VDD signals can be generated, which can then control 256 RO units. Therefore, only one set of Enable and VDD PAD is needed to control 256 RO units, which effectively saves the number of PADs, thereby increasing the number of tests per unit area. In addition, modifying the number of bits of the row and column addresses can further increase the number of tests per unit area.

[0046] It should be understood that in the embodiments of the present invention, the term "and / or" is only a description of the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0047] It is worth noting that, although the foregoing content has described the spirit and principle of the invention with reference to several specific embodiments, it should be understood that the invention is not limited to the disclosed specific embodiments, and the division of various aspects does not mean that the features in these aspects cannot be combined, and such division is only for the convenience of expression. The invention is intended to cover various modifications and equivalent arrangements included in the spirit and scope of the appended claims.

Claims

1. An addressable ring oscillator test circuit, characterized in that: The circuit includes an addressing circuit, a switch circuit, an excitation circuit, a test RO unit group and a frequency division circuit. The test RO unit group includes a plurality of test RO units. The addressing circuit includes a column addressing circuit and a row addressing circuit. The column addressing circuit and the row addressing circuit are respectively connected to the test RO unit group through a switch circuit, and the test RO units therein are selected by the address. The output end of each test RO unit is connected to a corresponding frequency divider in the frequency dividing circuit.

2. The test circuit according to claim 1, characterized in that: It also includes a sensing circuit, which is connected to the test RO unit group.

3. The test circuit according to claim 1, characterized in that: The test RO unit is composed of a NAND gate, several inverters and a driver, in the manner that the NAND gate and several inverters are connected end to end and input to the driver.

4. The test circuit according to claim 1, characterized in that: The inverter of the test RO unit includes various loads.

5. The test circuit according to claim 1, characterized in that: The frequency divider is composed of a plurality of D flip-flops connected in cascade.

6. The test circuit according to claim 2, characterized in that: The sensing circuit includes a plurality of transmission gates, and a group of transmission gates consisting of the plurality of transmission gates is connected to a corresponding test RO unit in the test RO unit group.

7. The test circuit according to claim 1, characterized in that: All the test RO units share the enable signal input terminal, and the enable signal input gating of the selected test RO unit is realized through the addressing circuit combined with the switch circuit.

8. The test circuit according to claim 1, characterized in that: All the test RO units share the power supply VDD input terminal, and the power supply input gating of the selected test RO unit is realized through the addressing circuit combined with the switch circuit.

9. The test circuit according to claim 1, characterized in that: The output end of the test RO unit is connected to the frequency divider through the transmission gates corresponding to the respective rows in series.

10. An integrated circuit testing method, characterized in that: The integrated circuit is tested based on the addressable ring oscillator test circuit as claimed in claim 1.

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