Unibus communication digital control circuit

Abstract

The invention provides a unibus communication digital control circuit which can be applied to the technical field of electronic communication. The digital control circuit comprises a main control module, a mode control module, a synchronous reset module, a single-bus communication module and a burning control module, and the main control module is used for receiving and executing commands, adjusting calibration parameters and storing the adjusted calibration parameters in a register; the mode control module is used for controlling the state of the circuit; the synchronous reset module is used for generating a stable synchronous reset signal; the single bus communication module is used for processing an input signal so as to ensure the accuracy of data transmission and sequential control; and the burning control module is used for controlling the programming and reading functions of the programmable memory. Through precise management of the main control module, high-reliability programming and reading operation of the programmable memory is realized, and through functions of clock calibration, data buffering, instruction scheduling and the like, all the modules are ensured to keep synchronous and efficient operation in different working environments.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic communications, and in particular to a single bus communication digital control circuit. Background Art

[0002] In modern electronic systems, the reference voltage source is a key module that plays a vital role in the overall performance of the system. Especially in applications such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and various sensor interfaces, the stability of the reference voltage directly determines the accuracy and reliability of the system. However, the output of the reference voltage source is often affected by changes in ambient temperature, resulting in voltage drift, which in turn affects the accuracy of the system. This temperature drift effect is particularly significant in high-precision systems. Therefore, the design of a high-precision reference voltage source with low temperature drift has become a technical challenge in modern electronic design.

[0003] Traditional reference voltage sources usually rely on analog circuits to be implemented. Although they have good temperature characteristics, in practical applications, debugging and calibration are relatively complicated and have low flexibility. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] In order to solve the problems existing in the reference voltage source in the prior art, the embodiment of the present invention provides a single bus communication digital control circuit, which can realize the permanent storage and precise control of calibration parameters such as temperature compensation coefficient and voltage compensation coefficient by combining single bus communication (1-WIRE) and programmable memory (EFUSE) with the reference voltage source. When the temperature changes, the system can automatically compensate by reading the calibration parameters stored in EFUSE, thereby maintaining a stable output of the reference voltage. It not only reduces the dependence on external components and simplifies the system structure, but also improves the integration and reduces the power consumption, and is particularly suitable for high-precision measurement and control systems.

[0006] (II) Technical solution

[0007] In view of the above problems, an embodiment of the present invention provides a single bus communication digital control circuit.

[0008] According to a first aspect of the present invention, there is provided a single bus communication digital control circuit, comprising: a main control module, a mode control module, a synchronous reset module, a single bus communication module and a burning control module, wherein the main control module converts between different operation modes through a state machine, receives and executes commands; and is used to parse data to adjust calibration parameters and store the adjusted calibration parameters in registers; the mode control module controls the state of the circuit using a combinational logic circuit based on a single bus input signal and a voltage comparator enable signal; the synchronous reset module is used to synchronize an asynchronous signal to a clock domain to generate a stable synchronous reset signal; the single bus communication module is used to process the input signal to ensure the accuracy and timing control of data transmission; and the burning control module is used to control the programming and reading functions of a programmable memory.

[0009] In some exemplary embodiments, the single bus communication module includes: a de-jitter module, which is used to perform multi-level de-jitter processing on the input single bus input signal, filter out noise or jitter caused by hardware connection or signal instability, so as to obtain a stable input signal, maintain data integrity, and improve the reliability of data transmission; a reset detection module, which detects whether there is a reset signal that meets the preset reset condition on the single bus according to the preset reset condition, and after detecting the reset signal, releases the bus from the current state, restores the default state, and resets other modules, and provides a reset confirmation signal and a reset completion signal to coordinate different stages in the reset process; a rising edge trigger module, which stores and compares the input signal state in each clock cycle, outputs a pulse signal and updates the input when a rising edge is detected signal status; a falling edge trigger module, which updates the register status through the rising edge of the clock or the falling edge of the reset. When not reset, it stores the current input signal status, and outputs a falling edge pulse signal when the signal is detected to change from high to low; a byte control module, which controls the processing of receiving data bytes and sending data bytes through a finite state machine, and performs command parsing and data exchange in the data buffer; a byte sending module, which adds a check bit to the data byte to be sent, sends it out through the single bus, and calls the falling edge trigger module to ensure that the data sending process is synchronized with the single bus communication timing; and a byte receiving module, which receives data from the single bus according to the write 1 and write 0 timing, and shifts it bit by bit into the register, and calls the rising edge trigger module at the same time to ensure that the data receiving process is synchronized with the single bus communication timing.

[0010] In some exemplary embodiments, different operation modes of the state machine include idle, waiting for command, programming and reading of programmable memory, wherein the initial operation mode of the state machine is idle, and in the idle operation mode, the main control module is in a state of waiting for an external command signal; when a valid command signal is detected, the state machine switches to the waiting for command operation mode and continuously monitors the programming or reading operation request of the programmable memory; upon receiving the programming or reading operation request of the programmable memory, the state machine switches to the programming or reading operation mode of the corresponding programmable memory to perform the programmable memory programming or reading operation; and after completing the programmable memory programming or reading operation, the state machine returns to the waiting for command operation mode to receive subsequent commands.

[0011] In some exemplary embodiments, during the programmable memory programming or reading operation, the main control module automatically generates signals for temperature compensation and voltage adjustment by parsing the read programmable memory data to implement the dynamic adjustment function of the control circuit under different temperature and voltage conditions.

[0012] In some exemplary embodiments, when the state machine is in the waiting command state, the main control module monitors the programming or reading operation requests of the programmable memory by listening to the data cache area signal. If the data cache chip select signal and enable signal are valid, the data cache area enters the read-write mode and performs corresponding data write or read operations based on the status of the write enable signal and the read enable signal.

[0013] In some exemplary embodiments, the process by which the main control module stores the adjusted calibration parameters in a register specifically includes: the main control module first writes the data into the register, and then writes it into the programmable memory for permanent storage after debugging and calibration, so as to avoid irreversible consequences caused by directly writing erroneous data; when the clock calibration signal detects a clock change, the main control module automatically starts the correction process to correct the clock error to ensure the stability and accuracy of the control circuit.

[0014] In some exemplary embodiments, the mode control module uses a combinational logic circuit to control the state of the circuit, specifically including: turning on the digital state to output debugging information during the debugging and calibration stages; and turning off the digital state after the calibration is completed to reduce the power consumption of the control circuit while ensuring that the analog state continues to run, wherein the debugging information includes temperature compensation information and voltage adjustment information.

[0015] In some exemplary embodiments, the synchronous reset module synchronizes the asynchronous signal to the clock domain by adopting a two-level register structure to generate a stable synchronous reset signal, specifically including: at each rising edge of the clock or the falling edge of the asynchronous reset signal, if the asynchronous reset signal is detected to be at a low level, the two-level registers are cleared at the same time; when the asynchronous reset signal returns to a high level, the first-level register is set first, and then in the next clock cycle, the second-level register synchronously follows the state change of the first-level register; and the output of the second-level register is used as a synchronous reset signal to ensure the stability of the reset operation in the clock domain and avoid system instability caused by asynchronous reset.

[0016] In some exemplary embodiments, the input signal of the single bus communication module includes: a clock signal, a power-on reset signal, a single bus input signal, and a voltage comparator enable signal.

[0017] In some exemplary embodiments, a burning control module is used to control the programming and reading functions of a programmable memory, including controlling chip select, program enable, serial clock, and read / write selection signals to achieve data storage and reading by responding to programming requests and read requests.

[0018] (III) Beneficial effects

[0019] It can be seen from the above technical solutions that a single bus communication digital control circuit provided by an embodiment of the present invention has at least one of the following beneficial effects:

[0020] (1) Through the precise management of the main control module, high-reliability programming and reading operations of the programmable memory (EFUSE) are achieved. At the same time, through functions such as clock calibration, data buffering and instruction scheduling, it ensures that each module maintains synchronization and efficient operation in a complex and changing working environment.

[0021] (2) The synchronous reset module effectively eliminates the metastable problem introduced by the asynchronous signal and ensures the stability of the reset signal in the clock domain.

[0022] (3) The single bus communication module works closely with the de-jitter module to improve the accuracy and anti-interference ability of signal processing and ensure data integrity in noisy environments.

[0023] (4) Through the temperature compensation mechanism and the two-stage clock calibration module, the system can monitor the changes in ambient temperature in real time and dynamically adjust the clock frequency, thereby maintaining high reliability of programmable memory (EFUSE) operation and data transmission under temperature fluctuations, further enhancing the stability and anti-interference ability of the system.

[0024] (5) This design effectively combines the coordinated optimization of software and hardware resources, improves the overall performance of the system, and meets the requirements for low power consumption and high stability in industrial scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0026] Figure 1 A block diagram schematically shows a composition of a single bus communication digital control circuit according to an embodiment of the present invention;

[0027] Figure 2 A block diagram schematically shows a composition of a single bus communication module according to an embodiment of the present invention; and

[0028] Figure 3 The schematic diagram shows a bidirectional port principle diagram of a single bus communication according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] Figure 1 The block diagram schematically shows a composition of a single bus communication digital control circuit according to an embodiment of the present invention.

[0031] like Figure 1 As shown, a single bus communication digital control circuit according to an embodiment of the invention includes: a main control module, a mode control module, a synchronous reset module, a single bus communication module and a burning control module, wherein the main control module converts between different operation modes through a state machine, receives and executes commands; and is used to parse data to adjust calibration parameters and store the adjusted calibration parameters in registers; the mode control module controls the state of the circuit using a combinational logic circuit based on a single bus input signal and a voltage comparator enable signal; the synchronous reset module is used to synchronize asynchronous signals to the clock domain to generate a stable synchronous reset signal; the single bus communication module is used to process input signals to ensure the accuracy and timing control of data transmission; and the burning control module is used to control the programming and reading functions of the programmable memory.

[0032] In some exemplary embodiments, the main control module is controlled by a finite state machine, which switches between different operation modes, including idle, waiting for command, programmable memory programming and reading operation modes. The initial operation mode is the idle operation mode, in which the module waits for an external command signal. When a valid command signal is detected, the state machine switches to the waiting for command operation mode according to the specific operation type, and continuously monitors the EFUSE programming request (EFUSE_BURN_REQ) or read request (EFUSE_READ_REQ) in this operation mode. Once the corresponding operation request is received, the state machine will switch to the EFUSE programming or reading state to perform the EFUSE programming and reading operations. After completing these operations, the state machine returns to the waiting for command state and is ready to receive subsequent commands. Preferably, in the process of processing the EFUSE programming and reading operations, the module will parse the read EFUSE data and automatically generate signals for temperature compensation and voltage adjustment, thereby realizing the dynamic adjustment function of the system under different temperature and voltage conditions. Optionally, when the state machine is in the waiting for command state, the module will monitor the data buffer signal. If the data cache chip select signal (DBI_SEL) and enable signal (DBI_ENABLE) are valid, the data cache area enters the read-write mode. According to the status of the write enable signal (DBI_WREN) and the read enable signal (DBI_RDEN), the module performs the corresponding data write or read operation to ensure efficient data management and storage. Preferably, when data needs to be written to the register, the module first writes the data to the register, and then writes it to the programmable memory (EFUSE) for permanent storage after debugging and calibration, so as to avoid the irreversible consequences caused by directly writing erroneous data. Preferably, when the clock calibration signal (CK_CAL_VALID) detects a clock change, the system automatically starts the correction process to effectively correct the clock error and ensure the stability and accuracy of the system.

[0033] In some exemplary embodiments, the synchronous reset module adopts a two-level register structure, which ensures the stability and reliability of the reset signal in the clock domain. At each rising edge of the clock or the falling edge of the asynchronous reset signal, if the asynchronous reset signal is detected to be at a low level, the two-level registers will be cleared at the same time; when the asynchronous reset signal returns to a high level, the first-level register is set first, and then in the next clock cycle, the second-level register synchronously follows the state change of the first-level register. Finally, the output of the second-level register is used as a synchronous reset signal to ensure the stability of the reset operation in the clock domain and avoid system instability caused by asynchronous reset.

[0034] In some exemplary embodiments, the mode control module turns on the digital state during the debugging and calibration phase to output key debugging information such as temperature compensation and voltage adjustment through a combinational logic circuit based on a single bus input signal (BUS_DI) and a voltage comparator enable signal (COMP_EN), and turns off the digital state after the calibration is completed to reduce system power consumption while ensuring that the analog state continues to run.

[0035] In some exemplary embodiments, the burn control module accurately implements the programming and reading functions of the EFUSE model through state machine control and counters to ensure that the system can operate stably under various external environmental changes. Specifically, when the module receives a programming request signal (BURN_REQ), the state machine control enters the programming process. The module uses a dedicated programming signal (PGM) and a clock signal (SCLK) to program data bit by bit. During the whole process, the main control module accurately calibrates and synchronizes the clock to ensure that the programming operation can be completed stably and reliably even under the influence of environmental factors such as temperature fluctuations or voltage changes. After all the data is programmed, the module notifies the main control module by sending a programming confirmation signal (BURN_ACK), indicating that the programming process has been successfully completed. When reading the programmable memory (EFUSE) data, when the module receives a read request signal (READ_REQ), the state machine switches to the read mode and starts to perform the data reading operation. The programmable memory (EFUSE) control module gradually reads the stored data from the programmable memory (EFUSE) model by coordinating the read signal (RW) and the clock signal (SCLK), and transmits the read data to the main control module through the data output port (DOUT). During the reading process, the system is still supported by the clock synchronization and calibration of the main control module to ensure that the data reading process can remain highly stable and accurate even under complex environmental conditions. After the reading operation is completed, the module sends a read confirmation signal (READ_ACK) to notify the main control module that the data reading has been successfully executed.

[0036] In some exemplary embodiments, the single bus communication module first uses a de-jitter circuit to stabilize the single bus input signal (BUS_DI). The receiving and sending of data are completed by the byte control module, the byte sending module and the byte receiving module, and the receiving and sending of input and output data bytes are controlled by clock synchronization. At the same time, the module supports EFUSE operation and transmits EFUSE programming instructions through control signals. The module outputs a single bus output signal (BUS_DO) through combinational logic to ensure the accuracy and timing control of data transmission. For the schematic diagram of the single bus communication bidirectional port, see Figure 3(IOBUF is essentially a dynamic array for storing binary data. It can be viewed as a continuous block of memory that contains data and related meta-information. The main features of IOBUF are as follows: dynamic memory allocation, IOBUF can dynamically allocate and release memory as needed, which means that it can adjust memory usage according to the actual data size, avoiding unnecessary memory waste; efficient data operation, IOBUF provides a series of methods to operate data, such as reading, writing, splicing, cutting, etc. These methods can efficiently process binary data and meet the needs of network communication; and data buffering, IOBUF can be used as a data buffer to temporarily store data to be sent or received. By using IOBUF reasonably, the performance and efficiency of network communication can be improved. IOBUF has four pins: O, I, I / O, and T, and the input or output state is switched by the control signal T. When T is 1, the external signal is input into the Field-Programmable Gate Array (FPGA) through the I / O port; when T is 0, the internal signal of the FPGA is output through the I / O port. After Vivado synthesis, the I / O is directly connected to the IOBUF, realizing bidirectional data transmission).

[0037] Figure 2 The block diagram schematically shows a composition of a single bus communication module according to an embodiment of the present invention.

[0038] like Figure 2 As shown, the single bus communication module according to an embodiment of the present invention includes:

[0039] The de-jitter module ensures the stability of the signal state by sampling the input signal and using two counters to time the high level and low level respectively. Specifically, after the single bus input signal (BUS_DI) is synchronized by three levels of registers, its changes before and after are compared to detect the rising and falling edges of the signal. When the falling edge is detected, the low level counter (CNT_LOW) is started. Only when the input signal continues to be at a low level and reaches the preset de-jitter time (CNT_VAL), the module sets the output signal (BUS_AFT_DBC) to a low level. When the rising edge is detected, the high level counter (CNT_HIGH) is started. Only when the input signal continues to be at a high level and reaches the preset de-jitter time (CNT_VAL), the module sets the output signal (BUS_AFT_DBC) to a high level. In this way, the input single bus input signal is subjected to multi-level de-jitter processing, the noise or jitter caused by hardware connection or signal instability is filtered out, a stable input signal is obtained, and the integrity of the data is maintained, thereby improving the reliability of data transmission.

[0040] Single bus reset detection module, when the power-on reset signal (PORB) is valid, the module starts to monitor the input signal through the internal counter. The parameter RST_EFF_VAL is used to determine the effective time of the reset signal. When the counter reaches this value and the input signal is low, the module sets the reset core signal (RST_CORE_N) to a low level, indicating the reset state. Next, the reset confirmation signal is controlled by the second counter (ACK_CNT), and the reset confirmation signal (RST_ACK_N) and reset completion signal (RST_ACK_DONE) are generated after the reset is completed.

[0041] The byte control module uses a finite state machine (FSM) to handle the reception and transmission of data in single bus communication. Specifically, the byte control module manages input and output data through different states, parses command bytes, and performs corresponding operations. The finite state machine of the byte control module starts from reset and enters the idle state (CMD_IDLE). After receiving valid data, it enters the command parsing state (CMD_DEC). According to the command byte, the byte control module can perform write registers, read registers, clock calibration, and EFUSE operations. When writing registers, the module writes the input address and data to the registers; when reading registers, it reads data from the registers and outputs them. When calibrating the clock, the byte control module issues a clock calibration request and completes the operation after waiting for the confirmation signal. The EFUSE operation triggers programming or other operations by checking the command byte. The byte control module confirms and completes the entire process according to the operation type.

[0042] The byte transmission module controls the transmission process of an 8-bit data through clock and reset signals. It sends the input byte data together with the check bit through the shift register bit by bit. When the transmission enable signal (TX_EN) is valid, the module captures the input data, loads it into the shift register, and triggers the shift operation through a negative pulse. The module uses two timing counters to accurately control the transmission time of each bit to 30 microseconds to ensure that the data is sent in the correct timing. After the transmission is completed, the output signal (TX_DONE) is set high, indicating that the byte transmission is completed. In addition, the module also generates a check bit and adds it to the data stream during transmission to ensure data integrity.

[0043] The byte receiving module controls the sampling and reception of data through the clock signal (SCLK) and the reset signal (RST_N). The byte receiving module uses the falling edge (NEG_PULSE) and the rising edge (POS_PULSE) to trigger the byte receiving module to detect the edge change of the input data signal (DIN). When the receive enable signal (RX_EN) is set high, the byte receiving module starts the sampling counter and samples the input data according to the preset 30 microsecond time interval. The sampled data is stored bit by bit in the shift register (RX_SFT_R0), and the data is stored in sequence from the input end through the shift operation. In addition, the byte receiving module will mark the progress of data reception according to the RX_SFT_MARK signal, and after receiving the complete 8-bit data, it will generate a valid signal (DO_VALID) to indicate that the data is ready. When the confirmation signal (DO_ACK) is set high, the byte receiving module clears the flag to wait for the next data reception. Ensure that the input data is sampled and processed in time sequence in each clock cycle, and transfer the data bits to the output end (DO_BYTE0) through the shift register.

[0044] The rising edge trigger module is used to accurately detect the rising edge of the input signal. It stores the input signal state of each clock cycle through a register and compares it with the current input signal in the next cycle. Specifically, if the current signal changes from a low level to a high level (i.e., a rising edge), the module will output a pulse signal. The specific implementation process is to generate logic through a loop. For each bit of the input signal, the clock rising edge (POSEDGE_SCLK) and the reset signal falling edge (NEGEDGE RST_N) are used as sensitive lists. The state of the input signal is updated at the rising edge of the clock, and the rising edge is detected in each cycle by comparing the current and previous signal states. If a rising edge is detected, the corresponding output pulse signal bit will be set high, reflecting that the signal has a rising edge change.

[0045] The falling edge trigger module is used to detect the falling edge of the input signal. Specifically, the state of the input signal in each clock cycle is stored in the register, and the current state is compared with the previous state to detect the falling edge. If the current input signal changes from a high level to a low level, the module outputs a pulse signal. The specific steps are: updating the register at the rising edge of the clock or the falling edge of the reset signal, clearing the register when reset; and storing the current input signal state in the register when not reset. Then, through logical operations, when the current signal is low and the signal in the previous cycle is high, the corresponding falling edge pulse signal is output.

[0046] In summary, the embodiment of the present invention provides a single bus communication digital control circuit, which has the characteristics of low temperature drift and high precision reference, can operate stably in the frequency range of 10MHz to 30MHz, and has good system reliability, data transmission efficiency and cost-effectiveness. The system realizes high reliability programming and reading operations of EFUSE through precise management of the main control module, and ensures that each module maintains synchronization and efficient operation in a complex and changeable working environment through functions such as clock calibration, data buffering and instruction scheduling. The synchronous reset module effectively eliminates the metastable problem introduced by the asynchronous signal and ensures the stability of the reset signal in the clock domain. In addition, the single bus communication module and the de-jitter module work closely together to improve the accuracy and anti-interference ability of signal processing and ensure data integrity in a noisy environment. Through the temperature compensation mechanism and the two-stage clock calibration module, the system can monitor the changes in ambient temperature in real time and dynamically adjust the clock frequency, so as to maintain the high reliability of EFUSE operation and data transmission under temperature fluctuations, and further enhance the stability and anti-interference ability of the system. This design effectively combines the coordinated optimization of software and hardware resources, improves the overall performance of the system, and meets the requirements for low power consumption and high stability in industrial scenarios.

[0047] The embodiments of the present invention are described above. However, these embodiments are only for the purpose of illustration, and are not intended to limit the scope of the present disclosure. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A single bus communication digital control circuit, characterized in that: include: Main control module, mode control module, synchronous reset module, single bus communication module and burning control module, The main control module is used to convert between different operation modes through a state machine, receive and execute commands; and is used to parse data to adjust calibration parameters and store the adjusted calibration parameters in registers; The mode control module controls the state of the circuit using a combinational logic circuit based on a single bus input signal and a voltage comparator enable signal; The synchronous reset module is used to synchronize the asynchronous signal to the clock domain to generate a stable synchronous reset signal; A single bus communication module for processing input signals to ensure accuracy and timing control of data transmission; and The burning control module is used to control the programming and reading functions of the programmable memory.

2. The single bus communication digital control circuit according to claim 1, characterized in that: The single bus communication module comprises: The de-jitter module is used to perform multi-level de-jitter processing on the input single bus input signal, filter out the noise or jitter caused by hardware connection or signal instability, so as to obtain a stable input signal, maintain data integrity, and improve the reliability of data transmission; A reset detection module detects whether there is a reset signal that meets the preset reset condition on the single bus according to the preset reset condition. After detecting the reset signal, the bus is released from the current state, restored to the default state, and resets other modules, and provides a reset confirmation signal and a reset completion signal to coordinate different stages in the reset process; The rising edge trigger module stores and compares the input signal status in each clock cycle, outputs a pulse signal and updates the input signal status when a rising edge is detected; The falling edge trigger module updates the register state through the rising edge of the clock or the falling edge of the reset. When not reset, it stores the current input signal state. When the signal changes from high to low, it outputs a falling edge pulse signal. The byte control module controls the operation of receiving and sending data bytes through a finite state machine, and performs command parsing and data exchange in the data buffer; The byte sending module adds a check bit to the data byte to be sent and sends it out through the single bus, and calls the falling edge trigger module to synchronize the data sending process with the single bus communication timing; and The byte receiving module receives data from the single bus according to the write 1 and write 0 timing, and stores it into the register bit by bit. At the same time, the rising edge trigger module is called to ensure that the data receiving process is synchronized with the single bus communication timing.

3. The single bus communication digital control circuit according to claim 1, characterized in that: The different operation modes of the state machine include idle, waiting for commands, programming and reading programmable memories, Wherein, the initial operation mode of the state machine is idle, and in the idle operation mode, the main control module is in a state of waiting for an external command signal; When a valid command signal is detected, the state machine switches to a waiting command operation mode and continuously monitors the programmable memory for programming or reading operation requests; Upon receiving a program or read operation request of a programmable memory, the state machine switches to a corresponding program or read operation mode of the programmable memory to perform a program or read operation of the programmable memory; and After completing the programmable memory programming or reading operation, the state machine returns to the wait command operation mode to receive subsequent commands.

4. The single bus communication digital control circuit according to claim 3, characterized in that: During the programming or reading operation of the programmable memory, the main control module automatically generates signals for temperature compensation and voltage adjustment by parsing the read programmable memory data, so as to realize the dynamic adjustment function of the control circuit under different temperature and voltage conditions.

5. The single bus communication digital control circuit according to claim 3, characterized in that: When the state machine is in the waiting command state, the main control module monitors the programming or reading operation request of the programmable memory by listening to the data cache area signal. If the data cache chip select signal and enable signal are valid, the data cache area enters the read-write mode and performs the corresponding data write or read operation according to the status of the write enable signal and the read enable signal.

6. The single bus communication digital control circuit according to claim 1, characterized in that: The process in which the main control module stores the adjusted calibration parameters in the register specifically includes: The main control module first writes the data into the register, and then writes it into the programmable memory for permanent storage after debugging and calibration, so as to avoid irreversible consequences caused by directly writing wrong data; When the clock calibration signal detects a clock change, the main control module automatically starts a correction process to correct the clock error to ensure the stability and accuracy of the control circuit.

7. The single bus communication digital control circuit according to claim 1, characterized in that: The mode control module uses a combinational logic circuit to control the state of the circuit, specifically including: Enable digital mode to output debug information during debugging and calibration; and After calibration is completed, the digital state is turned off to reduce the power consumption of the control circuit, while ensuring that the analog state continues to operate. The debugging information includes temperature compensation information and voltage adjustment information.

8. The single bus communication digital control circuit according to claim 1, characterized in that: The synchronous reset module synchronizes the asynchronous signal to the clock domain by adopting a two-level register structure to generate a stable synchronous reset signal, specifically including: At each rising edge of the clock or falling edge of the asynchronous reset signal, if the asynchronous reset signal is detected to be low level, the two-level registers are cleared at the same time; When the asynchronous reset signal returns to a high level, the first-stage register is set first, and then in the next clock cycle, the second-stage register synchronously follows the state change of the first-stage register; and The output of the second-level register is used as a synchronous reset signal to ensure the stability of the reset operation in the clock domain and avoid system instability caused by asynchronous reset.

9. The single bus communication digital control circuit according to claim 1, characterized in that: The input signals of the single bus communication module include: a clock signal, a power-on reset signal, a single bus input signal and a voltage comparator enable signal.

10. The single bus communication digital control circuit according to claim 1, characterized in that: The programming control module is used to control the programming and reading functions of the programmable memory, including controlling chip selection, program enable, serial clock and read / write selection signals by responding to programming requests and read requests to achieve data storage and reading.

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