PWM output circuit, controller, and control system

Abstract

The embodiment of the invention provides a PWM output circuit, a controller and a control system, and the circuit comprises a signal output module, a first register and a data sampling module. And the signal output module is used for outputting the initial PWM signal and triggering the data sampling module to sample the output parameter of the initial PWM signal through the first register after the initial PWM signal is output. By setting the first register, the data sampling module is automatically triggered after the signal output module outputs the PWM signal, automatic detection of the PWM signal is completed according to a hardware structure, the problem caused by software triggering is avoided, and the accuracy of reliability detection of the PWM signal is improved.

Description

Technical Field

[0001] The present application relates to the field of electronic control technology, and in particular to a PWM output circuit, a controller and a control system. Background Art

[0002] PWM signals are widely used in various control systems, such as motor drive, LED dimming and audio signal processing. However, the output reliability of PWM signals directly affects the stability and safety of the system. In some key application scenarios, such as automotive electronic systems and industrial automation systems, the output detection of PWM signals has high requirements. The existing technology mainly implements the detection method based on software control, and the sampling is triggered by the software program to obtain the detection data. Due to the priority problem of the software, the detection program may be preempted by other high-priority programs, resulting in delay problems, resulting in limitations in the real-time detection. Summary of the invention

[0003] The embodiments of the present application provide a PWM output circuit, a controller and a control system to achieve the effect of automatically triggering sampling detection.

[0004] In a first aspect, an embodiment of the present application provides a PWM output circuit, the circuit comprising a signal output module (100), a first register (200) and a data sampling module (300):

[0005] The signal output module (100) is used to output an initial PWM signal and, after the initial PWM signal is output, trigger the data sampling module (300) through the first register (200) to sample the output parameters of the initial PWM signal.

[0006] In a possible implementation, the signal output module (100) comprises a second register (101) and a level control unit (102); an output end of the second register (101) is connected to an input end of the level control unit (102);

[0007] A second register (101) is used to send a data signal to a level control unit (102) based on a setting parameter of an initial PWM signal, and to send a control signal to a first register (200) based on the setting parameter;

[0008] The first register (200) triggers the data sampling module (300) according to the control signal, and the level control unit (102) outputs an initial PWM signal according to the data signal.

[0009] In a possible implementation, the signal output module (100) further comprises a counting unit (103), the counting unit (103) is connected to a clock signal, and the counting unit (103) is used to count according to the clock signal and send the count value to the first register (200) and the second register (101);

[0010] The first register (200) is used to send a trigger signal to a data sampling module (300) according to a count value, and the second register (101) is used to send a data signal to a level control unit (102) according to a count value.

[0011] In a possible implementation, the second register (101) includes a duty cycle register (1011) and a period register (1012);

[0012] A duty cycle register (1011), used for comparing a duty cycle value set in the duty cycle register (1011) with a count value, and sending a first data signal to a level control unit (102) according to a first comparison result;

[0013] The cycle register (1012) is used to compare the cycle value set in the cycle register (1012) with the count value, send a second data signal value level control unit (102) according to a second comparison result, and send a control signal to the first register (200) according to the second comparison result.

[0014] In a possible implementation, the first register (200) is further used to compare the delay value set in the first register (200) with the count value after receiving the control signal, and send a trigger signal to the data sampling module (300) based on a third comparison result.

[0015] In a possible implementation, the circuit further comprises a signal processing module (400), the signal processing module (400) being used to amplify the initial PWM signal and output a target PWM signal;

[0016] The signal processing module (400) is further used to determine the delay value, and the first register (200) is further used to trigger the data sampling module (300) to sample the output parameters of the target PWM signal according to the delay value.

[0017] In a possible implementation, the data sampling module (300) comprises a sampling channel for each parameter, and each parameter sampling channel is used to sample each parameter of the PWM signal.

[0018] In a possible implementation, the signal output module (100) comprises a trigger management unit (104), an input end of the trigger management unit (104) is connected to an output end of the first register (200), and receives a trigger signal sent by the first register (200);

[0019] The trigger management unit (104) is used to trigger each sampling channel of the data sampling module (300) to start according to the trigger signal.

[0020] In a second aspect, an embodiment of the present application provides a controller, wherein the controller (70) includes a clock module (701) and a PWM output circuit as in the first aspect / any one of the embodiments of the first aspect, wherein the clock module (701) is used to provide a clock signal for the PWM output circuit.

[0021] In a possible implementation, the controller (70) further includes an interrupt control module (704), which is connected to the trigger management unit (104), and the trigger management unit (104) is used to send an external interrupt output to the interrupt control module (704) after receiving a trigger signal sent by the first register (200).

[0022] In a third aspect, an embodiment of the present application provides a control system, the control system comprising a PWM management platform and a controller as provided in the second aspect / the second aspect embodiment above;

[0023] The PWM management platform is used to obtain data collected by the data sampling module (300), and judge whether the initial PWM signal or the target PWM signal is normal based on the collected data, and issue an alarm when the initial PWM signal or the target PWM signal is abnormal.

[0024] The PWM output circuit, controller and control system provided by the embodiment of the present application, wherein the circuit includes a signal output module, a first register and a data sampling module; the signal output module is used to output an initial PWM signal, and after the initial PWM signal is output, the data sampling module is triggered by the first register to sample the output parameters of the initial PWM signal. By setting the first register, the data sampling module is automatically triggered after the signal output module outputs the PWM signal, and the automatic detection of the PWM signal is completed according to the hardware structure, avoiding the problems caused by software triggering, and improving the accuracy of the reliability detection of the PWM signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0026] Figure 1The structure of the PWM output circuit provided in one embodiment of the present application is Figure 1 ;

[0027] Figure 2 The structure of the PWM output circuit provided in one embodiment of the present application is Figure 2 ;

[0028] Figure 3 The structure of the PWM output circuit provided in one embodiment of the present application is Figure 3 ;

[0029] Figure 4 The structure of the PWM output circuit provided in one embodiment of the present application is Figure 4 ;

[0030] Figure 5 The structure of the PWM output circuit provided in one embodiment of the present application is Figure 5 ;

[0031] Figure 6 The structure of the PWM output circuit provided in one embodiment of the present application is Figure 6 ;

[0032] Figure 7 This is a structural diagram of a controller provided in one embodiment of the present application.

[0033] Reference numerals:

[0034] 100: signal output module; 101: second register; 1011: duty cycle register; 1012: period register; 102: level control unit; 103: counting unit; 104: trigger management unit; 200: first register; 201: delay register; 300: data sampling module; 400: signal processing module; 70: controller; 701: clock module; 702: PWM output module; 703: ADC module; 704: interrupt control module.

[0035] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0036] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0037] PWM (Pulse Width Modulation) signal, also known as pulse width modulation signal, is a digital signal that simulates or controls a continuous signal by adjusting the pulse width (duty cycle). In a PWM signal, the period of each pulse is fixed, but the pulse width (i.e., the duration of the high level) can be adjusted as needed. In a PWM cycle, the signal changes from high level to low level and then to high level to form a complete rectangular wave. The three main parameters of a PWM signal are period, frequency, and duty cycle:

[0038] (1) Cycle: The time required for a signal to change from a high level to a low level and then to a high level.

[0039] (2) Frequency: The number of times a signal changes from high level to low level and then back to high level per unit time. It is equal to the inverse of the period.

[0040] (3) Duty cycle: The ratio of the pulse width to the signal period within one cycle. It is usually expressed as a percentage and must be between 0 and 1.

[0041] The basic principle of PWM signal is based on the area equivalence principle, that is, when narrow pulses with equal impulses but different shapes are added to the inertial link, the effect is basically the same. The impulse here refers to the area of ​​the narrow pulse, and the effect is basically the same means that the output waveform of the link is basically the same. Therefore, by adjusting the duty cycle of the PWM signal, the equivalent control of the analog signal level can be achieved.

[0042] PWM signals play an important role in many fields. For example, in motor control, by adjusting the duty cycle of the PWM signal, precise control of the motor speed and torque can be achieved. In power management, PWM signals are widely used to control the voltage and current of power output, thereby achieving efficient management of batteries and other power sources. PWM signals are also used to control the brightness and color changes of LED lights. By changing the duty cycle of the PWM signal, the brightness of the LED light can be adjusted steplessly. In addition, in the fields of audio processing, smart home control, etc., PWM signals have broad application prospects.

[0043] However, the output reliability of PWM signals directly affects the stability and safety of the system. In some key application scenarios, such as automotive electronic systems and industrial automation systems, the output detection of PWM signals has high requirements. The existing technology mainly implements the detection method based on software control, and the sampling is triggered by the software program to obtain the detection data. Due to the priority problem of the software, the detection program may be preempted by other high-priority programs, resulting in delay problems, resulting in limitations in the real-time detection.

[0044] In view of the above technical problems, the present application provides a PWM output circuit, such as Figure 1 As shown, the circuit includes a signal output module 100, a first register 200 and a data sampling module 300:

[0045] The signal output module 100 is used to output an initial PWM signal, and after the initial PWM signal is output, trigger the data sampling module 300 to sample the output parameters of the initial PWM signal through the first register 200.

[0046] The initial PWM signal refers to the PWM signal output by the signal output module 100 , which may be a PWM signal directly output by the signal output module 100 without any processing, or a PWM signal generated by the signal output module 100 and then processed and output.

[0047] The signal output module 100 generates the required PWM signal according to the set parameters. When generating the PWM signal, a variety of methods can be used, and the specific structure of the signal output module 100 is determined in combination with the usage scenario of the PWM signal. Among them, the set parameters refer to the parameters of the pre-set PWM signal, including duty cycle, period, frequency and other data.

[0048] For example, a PWM signal can be generated by a waveform generator, but this method is usually suitable for laboratories or test environments, and may not be economical or convenient for actual application scenarios. Microcontrollers or microcontrollers are commonly used control cores in modern electronic systems, and they usually have the function of generating PWM signals. By writing corresponding programs, the control of the PWM generator inside the microcontroller or microcontroller can be realized to generate the required PWM signal. This method has the advantages of strong flexibility, low cost, and easy implementation, so it has been widely used in industrial control, automotive electronics, household appliances and other fields. The basic principle of a microcontroller or microcontroller generating a PWM signal is to generate a fixed frequency clock signal through an internal timer or counter, and then use a comparator or logic circuit to compare the clock signal with a preset threshold to generate a PWM signal with a specific duty cycle.

[0049] In addition, in order to simplify the PWM signal generation process and improve the system integration, a dedicated PWM chip is proposed. The PWM chip integrates key components such as a PWM generator, a comparator, and a drive circuit, and the user can generate the required PWM signal through simple configuration. Regardless of which method the signal output module 100 adopts, in order to ensure the reliability of the output PWM signal in the actual application scenario, it needs to be tested.

[0050] The data sampling module 300 is used to sample and detect the output initial PWM signal, obtain the output parameters of the initial PWM signal, and compare them with the set parameters to determine whether the initial PWM signal is stable and whether it is the required PWM signal. Among them, the parameter type of the output parameter is one or more of the set parameters. For example, in one embodiment, it is necessary to determine the duty cycle of the initial PWM signal, and in another embodiment, it is necessary to simultaneously determine the duty cycle and period of the initial PWM signal. Similarly, the data sampling module 300 can have the function of collecting one parameter, and can also have the function of collecting multiple parameters. Therefore, the parameter type of the output parameter is determined according to the application scenario, and the data sampling module 300 performs data sampling according to the required output parameters. Preferably, the data sampling module 300 can sample multiple parameters of the initial PWM signal.

[0051] It can be understood that the data sampling module 300 needs to sample the initial PWM signal after the initial PWM signal is output, that is, immediately after the output of the signal output module 100. The embodiment of the present application monitors the output of the initial PWM signal through the first register 200, thereby triggering the data sampling module 300 to sample the initial PWM signal after the initial PWM signal is output. In addition, the initial PWM signal is a periodic signal, and its duty cycle and period are both relatively important parameters. Sampling the output parameters of the initial PWM signal includes sampling and monitoring the parameters of the signal in each period of the initial PWM signal. Therefore, after detecting that the initial PWM signal starts to output in each period, the first register 200 triggers the data sampling module 300.

[0052] Specifically, the value of the first register is set by the period of the initial PWM signal. The first register 200 is connected to the signal output module 100 to obtain the starting time of the initial PWM signal, and then start to determine the real-time value. When the real-time value reaches the set value, it represents that a period of the initial PWM signal ends and the next period begins, triggering the data sampling module 300 to sample.

[0053] After completing data sampling, the data sampling module 300 sends the collected data to the monitoring system, which determines whether the data is normal and issues an alarm if the data is abnormal. Specifically, the monitoring system determines whether the sampled data is a value corresponding to the high level of the PWM signal. If so, it is considered that the PWM output is normal; otherwise, if the data is incorrect for three consecutive times, it is determined that the PWM output is abnormal. When it is determined that the PWM output is abnormal, the user is notified through an alarm sound or an alarm icon so that the user can go for inspection and maintenance in time.

[0054] In the circuit provided by the above embodiment, the circuit includes a signal output module, a first register and a data sampling module; the signal output module is used to output an initial PWM signal, and after the initial PWM signal is output, the data sampling module is triggered by the first register to sample the output parameters of the initial PWM signal. By setting the first register, the data sampling module is automatically triggered after the signal output module outputs the PWM signal, and the automatic detection of the PWM signal is completed according to the hardware structure, avoiding the problems caused by software triggering, and improving the accuracy of the reliability detection of the PWM signal.

[0055] In one embodiment, if Figure 2 As shown, the signal output module 100 includes a second register 101 and a level control unit 102; the output end of the second register 101 is connected to the input end of the level control unit 102;

[0056] The second register 101 is used to send a data signal to the level control unit based on the setting parameters of the initial PWM signal, and send a control signal to the first register 200 based on the setting parameters;

[0057] The first register 200 triggers the data sampling module 300 according to the control signal, and the level control unit 102 outputs an initial PWM signal according to the data signal.

[0058] Among them, the level control unit 102 controls the level of the output pin output. The second register 101 stores values ​​related to the duty cycle, period and other parameters of the initial PWM signal. The duty cycle and frequency of the initial PWM signal are calculated through these values, and then output to the level control unit 102 through the data signal. The level control unit 102 adjusts the output of the initial PWM signal according to the data signal. Exemplarily, the second register 101 includes ARR (automatic reload register) and PSC (prescaler register). The value of the ARR register determines the period of the PWM signal, and the value of the PSC register determines the frequency of the clock signal. By adjusting the values ​​of these two registers, the frequency and duty cycle of the PWM wave can be accurately controlled. These adjusted values ​​are output to the level control unit 102 by the register in the form of data signals, thereby realizing accurate control of the PWM signal waveform.

[0059] In combination with the description in the above embodiments, the first register 200 needs to trigger the data sampling module 300 to perform sampling after each cycle of the initial PWM signal is output. Therefore, when the second register 101 sends a data signal to the level control unit 102, a control signal is sent to the first register 200 to control the first register 200 to trigger the data sampling module 300.

[0060] In the circuit provided in the above embodiment, the output of the level control unit is adjusted by setting the second register to output the required PWM signal. Moreover, based on the working principle of the register, the second register that determines the initial PWM signal parameters controls the first register, which can accurately trigger the data sampling module, improve the accuracy and effectiveness of the sampling results, and further improve the accuracy of PWM detection.

[0061] In one embodiment, if Figure 3 As shown, the signal output module further includes a counting unit 103, the counting unit 103 is connected to the clock signal, the counting unit 103 is used to count according to the clock signal, and send the count value to the first register 200 and the second register 101;

[0062] The first register 200 is used to send a trigger signal to the data sampling module 300 according to the count value, and the second register 101 is used to send a data signal to the level control unit 102 according to the count value.

[0063] The clock signal is a stable signal source, usually generated by a crystal oscillator. Its output frequency is fixed and very stable. The clock signal can be used to control the state transition of the trigger, thereby realizing the counting function. The counting unit 103 includes a trigger, and the counting unit 103 relies on the storage function of the trigger and the periodic change of the clock signal to complete the counting.

[0064] The counting unit 103 receives the clock signal and counts based on the clock signal. When the period and frequency of the clock signal are known, the parameter setting of the PWM signal is completed through the count value of the counting unit 103. For example, if the frequency of the clock signal is known to be 1 MHz and the period is 1 μs, when the expected PWM period is 2 ms, the period-related value in the second register 101 is set to (1000) = 1 ms / 1 μs.

[0065] It should be noted that, in order to avoid timing disorder, the count value of the counting unit 103 is sent to the first register 200 and the second register 101 at the same time.

[0066] In the embodiment of the present application, the second register controls the PWM signal and the first register triggers the data sampling module through the counting unit 103, thereby ensuring timing synchronization.

[0067] In one embodiment, if Figure 4 As shown, the second register 101 includes a duty cycle register 1011 and a period register 1012;

[0068] The duty cycle register 1011 is used to compare the duty cycle value set in the duty cycle register 1011 with the count value, and send a first data signal to the level control unit 102 according to a first comparison result;

[0069] The period register 1012 is used to compare the period value set in the period register 1012 with the count value, send the second data signal value level control unit 102 according to the second comparison result, and send the control signal to the first register 200 according to the second comparison result.

[0070] Among them, the duty cycle register 1011 is used to control the duty cycle of the initial PWM signal, and the period register 1012 is used to control the period of the initial PWM signal. For example, it is known that the frequency of the clock signal is 1MHz and the period is 1μs. When the expected PWM duty cycle time is 1ms, the duty cycle register 1011 sets the duty cycle value to (1000) = 1ms / 1μs; by comparing the count value sent by the counting unit 103 with the duty cycle value, when the count value reaches the duty cycle value, the first data signal is sent to the level control unit 102. The level control unit 102 will pull up the output pin at the beginning, and pull down the output pin after receiving the first data signal sent by the duty cycle register 1011.

[0071] When the expected PWM cycle time is 2ms, the cycle register 1012 sets the cycle value (2000) = 2ms / 1μs. By comparing the count value sent by the counting unit 103 with the cycle value, when the count value reaches the cycle value, the second data signal is sent to the level control unit 102. After the level control unit 102 receives the second data signal sent by the cycle register 1012, it pulls up the output pin, so that the level control unit 102 outputs the expected initial PWM signal.

[0072] After the cycle register 1012 determines that the count value sent by the counting unit 103 is equal to the cycle value, it indicates that one cycle of the PWM signal ends. At this time, the cycle register 1012 needs to notify the counting unit 103 to clear the count and restart the count. Combined with the timing when the cycle register 1012 sends a control signal to the first register 200, the control signal can be sent to the counting unit 103 at the same time to complete the count clearing.

[0073] After receiving the control signal, the first register 200 compares the delay value set in the first register 200 with the count value, and sends a trigger signal to the data sampling module 300 according to the third comparison result.

[0074] The delay value represents that the sampling time of the data sampling module 300 in a cycle is later than the start time of a cycle. The delay value can be set randomly by humans or according to the transmission conditions of the PWM signal to be sampled. For example, in one embodiment, Figure 5 As shown, the circuit further includes a signal processing module 400, and the signal processing module 400 is used to amplify the initial PWM signal and output a target PWM signal;

[0075] The signal processing module 400 is further used to determine the delay value, and the first register 200 is further used to trigger the data sampling module 300 to sample the output parameters of the target PWM signal according to the delay value.

[0076] In actual application scenarios, the initial PWM signal output by the signal output module 100 is usually not capable of driving external devices, such as motors, LEDs, etc. Therefore, it is necessary to amplify the initial PWM signal, enhance its driving capability, and then output the target PWM signal to drive the external device. However, due to the processing of the initial PWM signal by the signal processing module 400, there will be a delay between the target PWM signal and the initial PWM signal. When the high level of the PWM signal needs to be sampled and detected, it is necessary to ensure that the sampling is performed at the high level of the PWM signal. Therefore, the delay value is set by the first register 200. After a period of time after the start of each cycle of the initial PWM signal, the first register 200 triggers the data sampling module 300 to perform sampling.

[0077] In the above example, when the expected delay time is 5 μs, the first register 200 sets the delay value to (5)=5 μs / 1 μs. After the first register 200 determines that the count value reaches 5, the data sampling module 300 is triggered.

[0078] In the above embodiment, the counting unit 103 needs to be initialized before counting starts to ensure the accuracy of the count value. When counting according to the clock signal, the counting unit 103 can use a variety of counting methods, for example, counting only on the rising edge of the clock signal, counting only on the falling edge of the clock signal, or counting on both the rising and falling edges of the clock signal.

[0079] In the circuit provided by the above embodiment, the counting unit and the register cooperate with each other to realize automatic detection of the PWM signal after the value of the register is set.

[0080] In one embodiment, if Figure 6 As shown, the signal output module 100 includes a trigger management unit 104, the input end of the trigger management unit 104 is connected to the output end of the first register 200, and receives the trigger signal sent by the first register 200;

[0081] The data sampling module 300 includes a sampling channel for each parameter, and each parameter sampling channel is used to sample each parameter of the PWM signal;

[0082] The trigger management unit 104 is used to trigger each sampling channel of the data sampling module 300 to start according to a trigger signal.

[0083] It can be understood that the time for sampling different parameters of the PWM signal is different. Therefore, if the data sampling module 300 is directly triggered by the first register 200, there may be sampling errors, and some sampled data are invalid. In this embodiment, the trigger management unit 104 is added to complete the sampling of the data sampling module 300 through the trigger management unit 104. Specifically, the trigger management unit 104 contains a linked register, and this register is set by the user to sample the linked channel through the application scenario. When the trigger management unit 104 receives the trigger signal sent by the first register 200, it controls the channel corresponding to the linked register inside the trigger management unit 104 to collect.

[0084] In the circuit provided by the above embodiment, the trigger management unit uniformly manages the triggering of the data sampling module, thereby isolating the first register and the data sampling module, and can better trigger the data sampling module to ensure the accuracy of the sampled data.

[0085] It should be understood that, although the functional modules in the circuit block diagrams of the above embodiments are clearly divided and have certain signal transmission directions between them, the division of these functional modules is not necessarily divided in the manner indicated above. The above functional modules are only limited in function. For example, in some embodiments, the first register 200 may be a part of the signal output module 100, rather than an independent individual. Unless otherwise clearly stated herein, the division of these functional modules and their subordinate levels is not strictly limited.

[0086] Based on the same inventive concept, an embodiment of the present application also provides a controller, and the implementation solution for solving the problem provided by the controller is similar to the implementation solution recorded in the above circuit. Therefore, the specific limitations in one or more controller embodiments provided below can refer to the limitations on the PWM output circuit in the above text and will not be repeated here.

[0087] In one embodiment, a controller is provided. The controller includes a clock module 701 and a PWM output circuit as in any of the above embodiments. The clock module 701 is used to provide a clock signal for the PWM output circuit.

[0088] The controller may be a microcontroller unit (MCU).

[0089] like Figure 7 As shown, the controller 70 includes a clock module 701, a PWM output module 702, an ADC module 703 and an interrupt control module 704;

[0090] The PWM output module 702 includes a counting unit 103, a duty cycle register 1011, a period register 1012, a delay register 201, a level control unit 102 and a trigger management unit 104;

[0091] The initial PWM signal output by the level control unit 102 of the controller 70 is amplified by the peripheral drive circuit, and the target PWM signal is output to control the external device (motor, LED, etc.). The external drive circuit has a delay, and the delay value of the delay register 201 is set according to the delay condition.

[0092] The counting unit 103 receives the clock signal provided by the clock module 701, counts according to the clock signal, and provides the count value to the duty cycle register 1011, the period register 1012 and the delay register 201. The duty cycle register 1011 provides the first data signal to the level control unit 102 according to the set duty cycle value and the count value, and the period register 1012 provides the second data signal to the level control unit 102 according to the set period value and the count value. The level control unit 102 outputs the initial PWM signal according to the first data signal and the second data signal. The duty cycle value and the period value are the PWM signals required by the user according to the application scenario, and are set in advance in the register.

[0093] After determining that the count value reaches the cycle value, the cycle register 1012 sends a control signal to the counting unit 103 to clear the count value, and the counting unit 103 restarts counting. The cycle register also sends a control signal to the delay register 201, and the delay register 201 compares the count value with the delay value, and notifies the trigger management unit 104 after the count value reaches the delay value.

[0094] The trigger management unit 104 contains an ADC (Analog to Digital Converter) link register, which is set by the user through the application scenario. When the trigger management unit 104 receives the notification of the delay register 201, it triggers the external interrupt output notification interrupt control module 704 and triggers the ADC channel acquisition notification corresponding to the ADC link register inside the unit.

[0095] After receiving the ADC channel acquisition notification, the ADC module 703 automatically collects the data of the corresponding channel and notifies the software. The software determines whether the ADC sampling data is a value corresponding to a high level. If so, it is considered that the PWM output is normal; otherwise, if the data is incorrect for three consecutive times, it is determined that the PWM output is abnormal. When it is determined that the PWM output is abnormal, the user is notified through an alarm sound or an alarm icon so that the user can go for inspection and maintenance in time.

[0096] In the controller provided in the above embodiment, through the internal design of the controller, the user only needs to set the registers in the controller to realize the PWM output module and ADC module in the controller to work together and automatically perform detection, and finally the ADC module notifies the software of the sampling results, thereby realizing a high-precision and high-reliability PWM signal detection function.

[0097] In addition, an embodiment of the present application further provides a control system, the control system comprising a PWM management platform and the controller mentioned in the above embodiment;

[0098] The PWM management platform is used to obtain the data collected by the data sampling module, and judge whether the initial PWM signal or the target PWM signal is normal based on the collected data, and issue an alarm if the initial PWM signal or the target PWM signal is abnormal.

[0099] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A PWM output circuit, characterized in that: The circuit comprises a signal output module (100), a first register (200) and a second register (300); The signal output module (100) is used to output an initial PWM signal, and after the initial PWM signal is output, trigger the first register (300) through the first register (200) to sample the output parameters of the initial PWM signal.

2. The circuit according to claim 1, characterized in that The signal output module (100) comprises a second register (101) and a level control unit (102); the output end of the second register (101) is connected to the input end of the level control unit (102); The second register (101) is used to send a data signal to the level control unit (102) based on the setting parameters of the initial PWM signal, and to send a control signal to the first register (200) based on the setting parameters; The first register (200) triggers the first register (300) according to the control signal, and the level control unit (102) outputs the initial PWM signal according to the data signal.

3. The circuit according to claim 2, characterized in that The signal output module (100) further comprises a counting unit (103), wherein the counting unit (103) is connected to a clock signal, and the counting unit (103) is used to count according to the clock signal and send the count value to the first register (200) and the second register (101); The first register (200) is used to send a trigger signal to the first register (300) according to the count value, and the second register (101) is used to send a data signal to the level control unit (102) according to the count value.

4. The circuit according to claim 3, characterized in that The second register (101) includes a duty cycle register (1011) and a period register (1012); The duty cycle register (1011) is used to compare the duty cycle value set in the duty cycle register (1011) with the count value, and send a first data signal to the level control unit (102) according to a first comparison result; The period register (1012) is used to compare the period value set in the period register (1012) with the count value, and send a second data signal value to the level control unit (102) according to a second comparison result, and send a control signal to the first register (200) according to the second comparison result.

5. The circuit according to claim 4, characterized in that The first register (200) is also used to compare the delay value set in the first register (200) with the count value after receiving the control signal, and send a trigger signal to the first register (300) according to a third comparison result.

6. The circuit according to claim 5, characterized in that The circuit further comprises a signal processing module (400), wherein the signal processing module (400) is used to amplify the initial PWM signal and output a target PWM signal; The signal processing module (400) is further used to determine the delay value, and the first register (200) is further used to trigger the first register (300) to sample the output parameter of the target PWM signal according to the delay value.

7. The circuit according to claim 1, characterized in that The first register (300) includes a sampling channel for each parameter, and each parameter sampling channel is used to sample each parameter of the PWM signal.

8. The circuit according to claim 7, characterized in that The signal output module (100) comprises a trigger management unit (104), the input end of the trigger management unit (104) is connected to the output end of the first register (200), and receives a trigger signal sent by the first register (200); The trigger management unit (104) is used to trigger each sampling channel of the first register (300) to start according to the trigger signal.

9. A controller, characterized in that: The controller (70) comprises a clock module (701) and a PWM output circuit according to any one of claims 1 to 8, wherein the clock module (701) is used to provide a clock signal for the PWM output circuit.

10. The controller according to claim 9, characterized in that: The controller (70) further comprises an interrupt control module (704), wherein the interrupt control module (704) is connected to the trigger management unit (104), and the trigger management unit (104) is used to send an external interrupt output to the interrupt control module (704) after receiving a trigger signal sent by the first register (200).

11. A control system, characterized in that: The control system comprises a PWM management platform and a controller according to any one of claims 9 to 10; The PWM management platform is used to obtain data collected by the first register (300), and judge whether an initial PWM signal or a target PWM signal is normal based on the collected data, and to issue an alarm if the initial PWM signal or the target PWM signal is abnormal.

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