Reverse connection prevention circuit, linear voltage regulator and reverse connection prevention method
By designing an anti-reverse circuit in a linear voltage regulator, the induction unit is used to sense the current during reverse connection and control the anti-reverse tube to turn off, the problem of inability to block the reverse current in time during reverse connection is solved, and the effect of effectively blocking the reverse current and preventing the latch-up is achieved.
Patent Information
- Application Number
- CN202411697422.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-25
- Publication Date
- 2025-02-28
AI Technical Summary
Existing linear regulators cannot detect and block the reverse current in time at the moment of reverse connection, resulting in an internal latch-up, which may lead to chip damage and anti-reverse circuit failure.
An anti-reverse circuit is designed, including a biasing unit, a control unit and an induction unit. The N well of the induction unit is close to the N well of the power tube, and is used to induce the current generated during reverse connection. By adjusting the voltage of the biasing unit, the anti-reverse tube is quickly turned off and prevented from reverse current.
Effectively block the reverse current, prevent the latch-up from further intensifying, avoid chip damage and anti-reverse circuit failure, and improve the reverse connection tolerance of the linear regulator.
Smart Images
Figure CN119536445A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an anti-reverse connection circuit, a linear voltage regulator and an anti-reverse connection method. Background Art
[0002] In actual applications, the output cable of the linear regulator LDO may be bound together with a variety of signal / power cables and provided to the subsequent load. Once the cable is damaged, the output of the linear regulator may be short-circuited to other power supply voltages higher than the input voltage of the linear regulator LDO. At the moment of short circuit, a large reverse current will flow from the output end of the linear regulator LDO to the input. In addition, the output end of the linear regulator LDO may also be mistakenly connected to a power supply voltage that is much larger than the input voltage.
[0003] In the above reverse connection scenario, when a large reverse current flows through the linear regulator LDO, the parasitic transistor BJT of the linear regulator LDO will be turned on, causing an internal latch-up effect, chip logic function errors, or even burning; at the same time, a large reverse current flows back to the input end, which may cause damage to the power supply and other devices on the power supply.
[0004] Usually, linear regulators LDOs with this application risk are designed with anti-reverse tubes and anti-reverse circuits. The anti-reverse circuit detects the voltage difference between the input voltage VIN and the output voltage VOUT. When the output voltage VOUT is greater than the input voltage VIN, the anti-reverse tube is turned off to block the current path from the output end to the input end; or the reverse current is detected. When the reverse current is greater than the preset value, the anti-reverse tube is turned off to prevent the reverse current.
[0005] However, at the moment of reverse connection, the power tube of the linear regulator LDO is in the on state, and its on-resistance is usually small, resulting in a large reverse current at the moment of reverse connection, which can be as high as more than ten amperes. The voltage drop on the power tube will cause its body diode to turn on. After the body diode turns on, a large current will also flow through it, causing the parasitic PNP transistor formed between the body diode and the substrate PSUB to turn on, amplifying the current and eventually causing the internal latch effect Latch-up. This series of reactions occurs within microseconds. If the anti-reverse connection circuit fails to detect and shut down the anti-reverse tube in time, the chip may be damaged by the latch effect Latch-up, and the tube may also burn out due to the large current. In addition, after the latch effect Latch-up occurs, it will also cause internal logic confusion and make the anti-reverse connection circuit ineffective.
[0006] Figure 1A conventional LDO circuit with reverse connection protection function is shown. There is a power tube MP2 and an anti-reverse tube MP1 on the power stage path from the input end to the output end. During normal operation, the anti-reverse tube MP1 is in a normally open state and works in the linear region. The LDO adjusts the gate voltage VG2 of the power tube MP2 through the loop regulation circuit to obtain a stable output voltage VOUT. When the conventional anti-reverse connection circuit detects that the power supply is reversely connected, the anti-reverse tube MP1 is turned off to prevent reverse current.
[0007] like Figure 2 and Figure 3 As shown, there is a parasitic PNP transistor Q1 between the body diode of the power tube MP2 and the substrate PSUB. At the moment of reverse connection, when the body diode conducts current, the current will be amplified by the parasitic PNP transistor, causing the substrate PSUB to generate a large current. The substrate PSUB has a parasitic resistance Rpar, and the potential of the substrate PSUB will be higher than the "ground" potential at this time, causing latch-up to occur internally, or interfering with the logic, resulting in abnormal chip function, and the conventional anti-reverse circuit cannot shut down the anti-reverse tube in time.
[0008] like Figure 3 As shown, the parasitic PNP transistor Q1 conducts current, causing the potential of the substrate PSUB to rise. If there is a grounded N-well and a weak pull-up / high-resistance N-well nearby, the parasitic NPN transistor Q2 formed by the substrate PSUB and the N-well will be turned on to generate a large current.
[0009] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention
[0010] The purpose of the present invention is to provide an anti-reverse connection circuit, a linear voltage regulator and an anti-reverse connection method, which can detect the current generated during reverse connection, quickly shut down the anti-reverse connection tube, block the reverse current, and prevent the latch effect from further aggravating, thereby avoiding interference with the conventional anti-reverse connection circuit and thus avoiding chip damage.
[0011] In order to achieve the above-mentioned purpose, a specific embodiment of the present invention provides an anti-reverse connection circuit for a linear voltage regulator, wherein the linear voltage regulator comprises a power tube and an anti-reverse connection tube, wherein the second end of the anti-reverse connection tube is used to receive an input voltage, the first end of the anti-reverse connection tube is connected to the first end of the power tube, and the second end of the power tube generates an output voltage, and the anti-reverse connection circuit comprises: a bias unit, a control unit and a sensing unit; the first end of the bias unit is connected to the first end of the control unit, the first end of the anti-reverse connection tube and the first end of the power tube, the second end of the bias unit is connected to the first end of the sensing unit and the control end of the control unit, and the second end of the control unit is connected to the control end of the anti-reverse connection tube;
[0012] The N-well where the sensing unit is located is arranged close to the N-well where the power tube is located to sense the current generated between the substrate of the power tube and the N-well where the power tube is located when the power tube has a latch effect, and adjust the voltage on the bias unit when the current is sensed. The control unit controls the anti-reverse tube to be turned off based on the voltage on the bias unit.
[0013] In one or more embodiments of the present invention, the bias unit includes a first resistor, a first end of the first resistor is connected to the first end of the anti-reverse tube and the first end of the power tube, and a second end of the first resistor is connected to the control end of the control unit and the first end of the sensing unit.
[0014] In one or more embodiments of the present invention, the control unit includes a first transistor, a first end of the first transistor is connected to a first end of the anti-reverse tube and a first end of the power tube, and a control end of the first transistor is connected to a second end of the bias unit and a first end of the sensing unit.
[0015] In one or more embodiments of the present invention, the sensing unit includes a diode or a second transistor or a triode, the cathode of the diode is connected to the second end of the bias unit and the control end of the control unit, the anode of the diode is connected to the ground voltage, the second end of the second transistor is connected to the second end of the bias unit and the control end of the control unit, the control end of the second transistor is connected to the first end of the second transistor and the ground voltage, the second end of the triode is connected to the second end of the bias unit and the control end of the control unit, and the control end of the triode is connected to the first end of the triode and the ground voltage.
[0016] In one or more embodiments of the present invention, the distance between the N-well where the sensing unit is located and the N-well where the power tube is located is no more than 40 um.
[0017] In one or more embodiments of the present invention, the anti-reverse connection circuit further includes a voltage stabilizing unit, a first end of the voltage stabilizing unit is connected to a first end of the bias unit, and a second end of the voltage stabilizing unit is connected to a second end of the bias unit.
[0018] In one or more embodiments of the present invention, the voltage stabilizing unit includes a third transistor, a first end of the third transistor is connected to a control end of the third transistor and a first end of the bias unit, and a second end of the third transistor is connected to a second end of the bias unit.
[0019] In one or more embodiments of the present invention, the anti-reverse connection circuit also includes a second resistor, a first end of the second resistor is connected to the second end of the bias unit and the control end of the control unit, and a second end of the second resistor is connected to the first end of the sensing unit.
[0020] The invention also discloses a linear voltage stabilizer, comprising the anti-reverse connection circuit.
[0021] The present invention also discloses an anti-reverse connection method for a linear voltage regulator, wherein the linear voltage regulator comprises a power tube and an anti-reverse connection tube, wherein the second end of the anti-reverse connection tube is used to receive an input voltage, the first end of the anti-reverse connection tube is connected to the first end of the power tube, and the second end of the power tube generates an output voltage. Based on the anti-reverse connection circuit, the anti-reverse connection method comprises:
[0022] The N-well where the sensing unit is located is arranged close to the N-well where the power tube is located to sense the current generated between the substrate of the power tube and the N-well where the power tube is located when the latch effect occurs in the power tube;
[0023] When the sensing unit senses the current, the bias unit adjusts its own voltage;
[0024] The control unit controls the anti-reverse tube to be turned off based on the voltage on the bias unit.
[0025] Compared with the prior art, the anti-reverse connection circuit, linear voltage regulator and anti-reverse connection method of the present invention place the N-well of the sensing unit close to the N-well of the power tube, detect the current generated by the latch-up effect at the moment of reverse connection in the detection circuit, and quickly turn off the anti-reverse connection tube after detecting the current, so as to quickly and effectively block the reverse current, avoid further strengthening of the latch-up effect due to reverse connection, and effectively prevent other circuits from being interfered with.
[0026] Compared with conventional detection circuits, the anti-reverse connection circuit, linear voltage regulator and anti-reverse connection method of the present invention will not fail due to the influence of the latch-up effect, but reversely utilize the latch-up effect during reverse connection, and respond more quickly. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0028] Figure 1 The circuit diagram of the linear voltage regulator in the prior art is shown in FIG.
[0029] Figure 2 FIG. 1 is an equivalent schematic diagram of a parasitic PNP transistor of a power tube in the prior art.
[0030] Figure 3 FIG. 4 is an equivalent schematic diagram of a parasitic NPN transistor of a power tube in the prior art.
[0031] Figure 4 4 is a circuit schematic diagram of an anti-reverse connection circuit in an embodiment.
[0032] Figure 5 The figure is a structural cross-sectional view of a part of the circuit of the reverse connection protection circuit in one embodiment.
[0033] Figure 6 It is a structural cross-sectional comparison diagram of a partial circuit of an anti-reverse connection circuit in an embodiment. DETAILED DESCRIPTION
[0034] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0035] "Coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.
[0036] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals refer to like parts throughout, and wherein are shown by way of exemplary embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered in a limiting sense.
[0037] The various operations in the specification may be described in turn as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.
[0038] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
[0039] Various components and devices may be referred to or shown in the singular form herein (e.g., "transistor," "transistor," "switch," etc.), but this is merely for ease of discussion, and any element referred to in the singular form may include multiple such elements in accordance with the teachings herein.
[0040] The specification describes the use of the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of the present disclosure are synonymous.
[0041] like Figure 4 As shown, an anti-reverse connection circuit in an embodiment of the present invention is used for a linear regulator, wherein the linear regulator includes a power tube MP2 and an anti-reverse connection tube MP1, the second end of the anti-reverse connection tube MP1 is used to receive an input voltage VIN, the first end of the anti-reverse connection tube MP1 is connected to the first end of the power tube MP2, and the second end of the power tube MP2 generates an output voltage VOUT.
[0042] like Figure 4As shown, the anti-reverse connection circuit includes: a bias unit 10, a control unit 20, a sensing unit 30, a current limiting unit 40 and a voltage stabilizing unit 50. The first end of the bias unit 10 is connected to the first end of the anti-reverse tube MP1 and the first end of the power tube MP2 to form a node HV, and the second end of the bias unit 10 is connected to the first end of the current limiting unit 40 and the control end of the control unit 20. The first end of the control unit 20 is connected to the first end of the anti-reverse tube MP1 and the first end of the power tube MP2, and the second end of the control unit 20 is connected to the control end of the anti-reverse tube MP1. The second end of the current limiting unit 40 is connected to the first end of the sensing unit 30, and the second end of the sensing unit 30 is connected to the ground voltage. The first end of the voltage stabilizing unit 50 is connected to the first end of the bias unit 10, and the second end of the voltage stabilizing unit 50 is connected to the second end of the bias unit 10.
[0043] The N-well where the sensing unit 30 is located is arranged close to the N-well where the power tube MP2 is located to sense the current generated between the substrate of the power tube MP2 and the N-well where the power tube MP2 is located when the latch effect occurs in the power tube MP2, and adjust the voltage on the bias unit 10 when the current is sensed. The control unit 20 controls the anti-reverse tube MP1 to be turned off based on the voltage on the bias unit 10.
[0044] Among them, the bias unit 10 includes a first resistor R1, a first end of the first resistor R1 is connected to the first end of the anti-reverse tube MP1 and the first end of the power tube MP2 to form a node HV, and a second end of the first resistor R1 is connected to the control end of the control unit 20 and the first end of the current limiting unit 40.
[0045] In one embodiment, the control unit 20 includes a first transistor M1, a first end of the first transistor M1 is connected to a first end of the anti-reverse tube MP1 and a first end of the power tube MP2, and a control end of the first transistor M1 is connected to a second end of the bias unit 10 and a first end of the current limiting unit 40.
[0046] The current limiting unit 40 includes a second resistor R2 , a first end of the second resistor R2 is connected to the second end of the first resistor R1 and the control end of the first transistor M1 , and a second end of the second resistor R2 is connected to the first end of the sensing unit 30 .
[0047] The sensing unit 30 includes a diode D1, a cathode of the diode D1 is connected to the second end of the current limiting unit 40, and an anode of the diode D1 is connected to the ground voltage. In other embodiments, the current limiting unit 40 may not be provided, that is, the cathode of the diode D1 is directly connected to the second end of the first resistor R1 and the control end of the control unit 20.
[0048] In other embodiments, a second transistor M2 may be used instead of the diode D1, wherein the second end of the second transistor M2 is connected to the second end of the bias unit 10 and the control end of the control unit 20, and the control end of the second transistor M2 is connected to the first end of the second transistor M2 and the ground voltage; or a transistor Q may be used instead of the diode D1, wherein the second end of the transistor Q is connected to the second end of the bias unit 10 and the control end of the control unit 20, and the control end of the transistor Q is connected to the first end of the transistor Q and the ground voltage.
[0049] The voltage stabilizing unit 50 includes a third transistor M3 , a first end of the third transistor M3 is connected to a control end of the third transistor M3 and a first end of the bias unit 10 , and a second end of the third transistor M3 is connected to a second end of the bias unit 10 .
[0050] To ensure that the sensing unit 30 can sense the current generated between the substrate of the power tube MP2 and the N-well where the power tube MP2 is located when the latch effect occurs in the power tube MP2, the sensing unit 30 is configured so that the distance between the N-well where the sensing unit 30 is located and the N-well where the power tube MP2 is located is no more than 40um.
[0051] Specifically, taking the sensing unit 30 as a diode D1 as an example, combined with Figure 5 , 4 As shown in , 3, 2, 1, the distance L between the N-well N-Well1 where the diode D1 is located and the N-well N-Well2 where the power tube MP2 is located is not greater than 40um. When the latch-up effect Latch-up occurs and causes current to be generated on the parasitic PNP transistor Q1, that is, the collector of the parasitic PNP transistor Q1 will have current flowing through the parasitic resistor Rpar to the ground, so that there will be a voltage drop on the parasitic resistor Rpar, causing the base-emitter of the parasitic NPN transistor Q2 to be forward biased. Since the node A is at a high potential, the parasitic NPN transistor Q2 is turned on, and the collector of the parasitic NPN transistor Q2, that is, the N-well N-Well1 where the diode D1 corresponding to the node A is located, will also generate current. At this time, it is equivalent to the diode D1 being reversely conducted and pulling down the voltage of the node A.
[0052] The voltage of node A is pulled down, and current will be generated on the first resistor R1 and the second resistor R2. When the voltage drop on the first resistor R1 is greater than the turn-on voltage of the first transistor M1, the first transistor M1 will be turned on. The first transistor M1 is large in size, and the voltage VG1 of the control end of the anti-reverse tube MP1 will be quickly pulled up to the voltage on the node HV, thereby turning off the anti-reverse tube MP1 and preventing the reverse current, that is, preventing the further occurrence of the latch-up effect Latch-up, and ensuring the normal operation of the remaining circuits (including the conventional anti-reverse connection circuit). On the layout, the position of the diode D1, the second transistor M2 or the triode Q is as close to the power tube MP2 as possible while meeting the circuit design requirements, so that it can first sense the current generated by the latch-up effect Latch-up and act quickly before other circuits are affected.
[0053] like Figure 6 As shown, if the distance between the N-well N-Well1 where the diode D1 is located and the N-well N-Well2 where the power tube MP2 is located is too large, the current generated by the collector of the parasitic PNP transistor Q1 will be drawn away by the nearby grounded P+, and then the far-end parasitic resistor Rpar will not have current. Without a voltage drop, the parasitic NPN transistor Q2 will not be turned on, and the anti-reverse connection circuit will not work.
[0054] The present invention also discloses a linear voltage stabilizer, comprising the above-mentioned anti-reverse connection circuit and Figure 1 The circuit shown.
[0055] Combination Figures 1 to 5 As shown, the present invention also discloses an anti-reverse connection method for a linear voltage regulator, the linear voltage regulator includes a power tube MP2 and an anti-reverse connection tube MP1, the second end of the anti-reverse connection tube MP1 is used to receive an input voltage VIN, the first end of the anti-reverse connection tube MP1 is connected to the first end of the power tube MP2, and the second end of the power tube MP2 generates an output voltage VOUT. Based on the above anti-reverse connection circuit, the anti-reverse connection method includes:
[0056] The sensing unit 30 is disposed close to the power transistor MP2 to sense the current generated between the substrate of the power transistor MP2 and the N-well where the power transistor MP2 is located when the power transistor MP2 has a latching effect. In one embodiment, the distance between the N-well where the sensing unit 30 is located and the N-well where the power transistor MP2 is located is not greater than 40 um.
[0057] When the sensing unit 30 senses the current, the bias unit 10 adjusts its own voltage.
[0058] The control unit 20 controls the anti-reverse tube MP1 to be turned off based on the voltage on the bias unit 10 .
[0059] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.
[0060] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
Claims
1. A reverse connection prevention circuit for a linear voltage regulator, the linear voltage regulator comprising a power tube and a reverse connection prevention tube, the second end of the reverse connection prevention tube being used to receive an input voltage, the first end of the reverse connection prevention tube being connected to the first end of the power tube, and the second end of the power tube generating an output voltage, characterized in that: The anti-reverse connection circuit comprises: a bias unit, a control unit and a sensing unit; the first end of the bias unit is connected to the first end of the control unit, the first end of the anti-reverse connection tube and the first end of the power tube, the second end of the bias unit is connected to the first end of the sensing unit and the control end of the control unit, and the second end of the control unit is connected to the control end of the anti-reverse connection tube; The N-well where the sensing unit is located is arranged close to the N-well where the power tube is located to sense the current generated between the substrate of the power tube and the N-well where the power tube is located when the power tube has a latch effect, and adjust the voltage on the bias unit when the current is sensed. The control unit controls the anti-reverse tube to be turned off based on the voltage on the bias unit.
2. The anti-reverse connection circuit according to claim 1, characterized in that: The bias unit includes a first resistor, a first end of the first resistor is connected to the first end of the anti-reverse tube and the first end of the power tube, and a second end of the first resistor is connected to the control end of the control unit and the first end of the sensing unit.
3. The anti-reverse connection circuit according to claim 1, characterized in that: The control unit includes a first transistor, a first end of the first transistor is connected to a first end of the anti-reverse tube and a first end of the power tube, and a control end of the first transistor is connected to a second end of the bias unit and a first end of the sensing unit.
4. The anti-reverse connection circuit according to claim 1, characterized in that: The sensing unit includes a diode or a second transistor or a triode, the cathode of the diode is connected to the second end of the bias unit and the control end of the control unit, the anode of the diode is connected to the ground voltage, the second end of the second transistor is connected to the second end of the bias unit and the control end of the control unit, the control end of the second transistor is connected to the first end of the second transistor and the ground voltage, the second end of the triode is connected to the second end of the bias unit and the control end of the control unit, and the control end of the triode is connected to the first end of the triode and the ground voltage.
5. The anti-reverse connection circuit according to claim 1, characterized in that: The distance between the N-well where the sensing unit is located and the N-well where the power tube is located is not greater than 40 um.
6. The anti-reverse connection circuit according to claim 1, characterized in that: The anti-reverse connection circuit further includes a voltage stabilizing unit, a first end of the voltage stabilizing unit is connected to a first end of the bias unit, and a second end of the voltage stabilizing unit is connected to a second end of the bias unit.
7. The anti-reverse connection circuit according to claim 6, characterized in that: The voltage stabilizing unit includes a third transistor, a first end of the third transistor is connected to a control end of the third transistor and a first end of the bias unit, and a second end of the third transistor is connected to a second end of the bias unit.
8. The anti-reverse connection circuit according to claim 1, characterized in that: The anti-reverse connection circuit also includes a second resistor, a first end of the second resistor is connected to the second end of the bias unit and the control end of the control unit, and a second end of the second resistor is connected to the first end of the sensing unit.
9. A linear regulator, characterized in that: The invention comprises the anti-reverse connection circuit as claimed in any one of claims 1 to 8.
10. A method for preventing reverse connection, characterized in that: Used in a linear voltage regulator, the linear voltage regulator includes a power tube and an anti-reverse tube, the second end of the anti-reverse tube is used to receive an input voltage, the first end of the anti-reverse tube is connected to the first end of the power tube, and the second end of the power tube generates an output voltage. Based on the anti-reverse connection circuit according to any one of claims 1 to 8, the anti-reverse connection method includes: The N-well where the sensing unit is located is arranged close to the N-well where the power tube is located to sense the current generated between the substrate of the power tube and the N-well where the power tube is located when the latch effect occurs in the power tube; When the sensing unit senses the current, the bias unit adjusts its own voltage; The control unit controls the anti-reverse tube to be turned off based on the voltage on the bias unit.