Data reading method and device, controller, AXI host, AHB slave and SOC

Abstract

The invention discloses a data reading method which comprises the steps that a reading instruction from an AXI host is received, when a reading address range corresponding to the reading instruction crosses a preset boundary, the reading instruction is divided into N reading sub-instructions, the preset boundary is an address of bytes which are positive integer multiples with a preset number of bytes as a cardinal number, N is the number of the reading address range crossing the preset boundary plus 1, and N is a positive integer number of bytes; and performing AHB protocol conversion on the N read sub-instructions to obtain N pieces of read operation information, and sending the N pieces of read operation information to the AHB slave so as to return a read result to the AXI host. The embodiment of the invention also provides a data reading device, a controller, an AXI host, an AHB slave, an SOC and a computer storage medium.

Description

Technical Field

[0001] The present invention relates to a digital chip front-end technology in an integrated circuit, and in particular to a data reading method, device, controller, AXI host, AHB slave and SOC. Background Art

[0002] As the scale of integrated circuits increases day by day, the functions and complexity of chips increase, and the requirements for the processing performance of System on Chip (SOC) are getting higher and higher. As the central bridge connecting various modules, the internal bus of the chip has an important impact on the performance of the SOC system, especially in the system with multiple master devices and multiple slave devices.

[0003] Among them, Advanced eXtensible Interface (AXI) is an on-chip bus for high performance, high bandwidth, and low latency in the Advanced Microcontroller Bus Architecture (AMBA) bus system. Its address / control and data phases are separated, and it has five independent channels, namely: write address channel, write data channel, write reply channel, read address channel, and read data channel. Advanced High-preformance Bus (AHB), as the previous generation bus of AXI bus, is used in high-performance, high-clock frequency system modules, supports functions or features such as data burst transmission, split transmission, and pipeline mode. As the core backbone bus of the system, it is widely used in early SOC products. When the new generation of high-performance SOC chooses AXI bus for system interconnection, it will choose to interconnect AXI bus with other types of buses such as AHB and Advanced Peripheral Bus (APB) through a bridge controller to be compatible with early products.

[0004] In the related art, the address and data separation method is used to control the interface timing of read and write access respectively, and the protocol conversion is realized by setting up an address command channel and a data buffer area. However, this method can only meet the access of continuous addresses less than or equal to 1KB, resulting in limited application scenarios of protocol conversion and reduced throughput. It can be seen that the existing AXI to AHB method has a narrow applicability and leads to the technical problem of low throughput. Summary of the invention

[0005] The embodiments of the present invention provide a data reading method, device, controller, AXI host, AHB slave and SOC, which can improve the applicability of AXI to AHB conversion.

[0006] The technical solution of the present invention is achieved in this way:

[0007] An embodiment of the present invention provides a data reading method, which is applied in a controller and includes:

[0008] Receive read command from AXI host;

[0009] When the read address range corresponding to the read instruction crosses a preset boundary, split the read instruction into N read sub-instructions; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes, and N is the number of preset boundaries crossed by the read address range plus 1;

[0010] Performing AHB protocol conversion on the N read sub-instructions to obtain N pieces of read operation information;

[0011] The N pieces of read operation information are sent to the AHB slave to return the read result to the AXI host.

[0012] By splitting the read instruction and converting it when it is determined that the read address range crosses the preset boundary, the N read operation information obtained is made information that can be processed by the AHB slave, thereby obtaining a reading result, so that AXI to AHB can be applicable to the situation of crossing the preset boundary, thereby improving applicability and further improving data throughput.

[0013] Furthermore, the method further comprises:

[0014] Based on the read instruction, determining the number of preset boundaries that the read address range crosses;

[0015] When the number is greater than 0, determining that the read address range crosses a preset boundary;

[0016] When the number is equal to 0, it is determined that the read address range does not cross a preset boundary.

[0017] By determining the number of read address units that cross preset boundaries determined by the read instruction, it is possible to determine whether the read address range corresponding to the read instruction crosses the preset boundary, thereby determining whether to split the read instruction to use reading in more situations, thereby improving applicability.

[0018] Furthermore, the method further comprises:

[0019] When the read address range corresponding to the read instruction does not cross the preset boundary, the read ID and the encoding field 0 in the read address information in the read instruction are re-determined as the read ID in the read address information to obtain the read instruction again;

[0020] Performing AHB protocol conversion on the read instruction to obtain a piece of read operation information;

[0021] The piece of read operation information is sent to the AHB slave to return the read result to the AXI host.

[0022] In the case where the read address range does not cross the preset boundary, only the read ID in the read address information in the read instruction is re-determined, the encoding field is added, and the read address information is reconstructed to obtain the read instruction again and perform AHB protocol conversion to obtain a read operation information to achieve the response reading of the read instruction that does not cross the preset boundary, thereby improving applicability.

[0023] Further, determining the number of preset boundaries that the read address range crosses based on the read instruction includes:

[0024] Determine a read end address based on a read start address, a read transfer length, and a read transfer width in the read instruction;

[0025] The read end address and the read start address are respectively right-shifted by a preset number of bits, and a difference between the shifted read end address and the shifted read start address is calculated; wherein the preset number of bits is equal to the minimum bit width corresponding to a preset number of bytes;

[0026] The difference is determined as the number of preset boundaries crossed by the read address range.

[0027] The read end address is determined by the read address information, and the read end address and the read start address are used for shifting and difference calculation to obtain the number of times the read address range crosses the preset boundary. In this way, it is possible to determine whether the read address range crosses the preset boundary, and if so, the size of N can be determined, which is conducive to completing the splitting of the read instruction.

[0028] Further, when the read address range corresponding to the read instruction crosses a preset boundary, splitting the read instruction into N read sub-instructions includes:

[0029] When the read address range corresponding to the read instruction crosses a preset boundary, the read address information in the read instruction is split into N read sub-instructions; wherein the N read sub-instructions include: N read address sub-information;

[0030] Accordingly, performing AHB protocol conversion on the N read sub-instructions to obtain N pieces of read operation information includes:

[0031] Perform AHB protocol conversion on the N pieces of read address sub-information to obtain N pieces of read operation information.

[0032] By splitting the read address information to obtain N read sub-instructions, and performing AHB protocol conversion on the N read sub-instructions, the converted N read address sub-instructions are obtained, so that the N read operation information meets the requirements of the AHB slave, and the reading of data of the read instruction across the preset boundary is realized, thereby improving the applicability of AXI to AHB reading.

[0033] Further, when the read address range corresponding to the read instruction crosses a preset boundary, splitting the read address information in the read instruction into N read sub-instructions includes:

[0034] When the read address range corresponding to the read instruction crosses a preset boundary, the read ID, the read first address, the read transfer length and the read transfer width in the read address information are respectively split into N pieces of read address sub-information.

[0035] By splitting each parameter in the read address information as above, N pieces of read address sub-information are obtained, so that the obtained N read sub-instructions can read corresponding data from the AHB slave one by one, thereby ensuring correct reading of data.

[0036] Further, when the read address range corresponding to the read instruction crosses a preset boundary, the read ID, the read first address, the read transfer length and the read transfer width in the read address information are split into N pieces of read address sub-information respectively, including:

[0037] When the read address range corresponding to the read instruction crosses a preset boundary, the read ID and the coding field a in the read address information are determined as the read ID of the a-th read address sub-information; wherein a is a positive integer greater than or equal to 1 and less than or equal to N;

[0038] When a is equal to 1, the read start address of the read address information is determined as the read start address of the a-th read address sub-information; when a is greater than or equal to 2 and less than or equal to N, the N-1 boundary addresses starting from the read start address of the read address information are determined, and the j-th boundary address among the N-1 boundary addresses is determined as the read start address of the a-th read address sub-information; wherein j is equal to a-1;

[0039] When a is greater than or equal to 1 and less than or equal to N-1, determine N-1 boundary addresses starting from the read start address of the read address information, and determine the jth boundary address among the N-1 boundary addresses as the read end address of the ath read address sub-information; when a is equal to N, determine the read end address of the read address information as the read end address of the ath read address sub-information;

[0040] When N is equal to 2, the read transfer length in the a-th read address sub-information is determined by using the read end address of the a-th read address sub-information and the read start address of the a-th read address sub-information; when N is greater than 2, the read end address of the 1st read address sub-information and the read start address of the 1st read address sub-information are used to determine the read transfer length in the 1st read address sub-information; the preset read transfer length is determined as the read transfer length in the 2nd to N-1st read address sub-information; the read end address of the N-th read address sub-information and the read start address of the N-th read address sub-information are used to determine the read transfer length in the N-th read address sub-information; wherein the preset read transfer length is obtained by right-shifting the maximum number of the preset number of bytes by the number of digits of the read transfer width;

[0041] The read transfer width of the read address information is determined as the read transfer width in the a-th read address sub-information.

[0042] By determining the parameters in each read address sub-information as described above, each read address sub-information is determined. Then, when the AHB slave receives each read sub-instruction, the content of each read address sub-information can be known, which is conducive to reading the data corresponding to each read address sub-information from the AHB slave, thereby improving the accuracy of data reading.

[0043] Further, sending the N pieces of read operation information to the AHB slave to return the read result to the AXI host includes:

[0044] Send the N pieces of read operation information to the AHB slave to obtain N pieces of read data sub-information and N pieces of read response information of the N pieces of read data sub-information;

[0045] Receiving N pieces of read data sub-information and N pieces of read response information of the N pieces of read data sub-information from the AHB slave;

[0046] Performing AXI protocol conversion on the N pieces of read data sub-information and the N pieces of read response information to obtain converted N pieces of read data sub-information and converted N pieces of read response information; wherein the read result is the converted N pieces of read data sub-information and the converted N pieces of read response information;

[0047] The converted N pieces of read data sub-information and the converted N pieces of read response information are sent to the AXI host.

[0048] After receiving N read data sub-information and N read response information of N read operation information of the AHB slave, AXI protocol conversion is performed on the N read data sub-information and the N read response information, so as to send the converted N read data sub-information and the converted N read response information that meet the protocol requirements to the AXI host, so that the AXI host can obtain the desired data.

[0049] Further, the receiving of a read instruction from the AXI host includes:

[0050] receiving a read request from the AXI host;

[0051] Sending the read request to the AHB slave;

[0052] receiving a response message for the read request from the AHB slave, and sending the response message for the read request to the AXI host;

[0053] When the response information to the read request indicates that the AHB slave is in a read state or a write state, a read instruction from the AXI host is received.

[0054] By receiving a read request from the AXI host before sending a read instruction and forwarding it to the AHB slave to obtain whether the AHB slave is currently in a read state or a write state. If it is, the AXI host will send a read instruction to the controller. In this way, the problem of receiving a write instruction when the AHB slave is in a busy state and failing to read successfully is prevented, thereby ensuring the reading efficiency.

[0055] Further, when the read address range corresponding to the read instruction crosses a preset byte boundary, splitting the read instruction into N read sub-instructions includes:

[0056] When the read address range corresponding to the read instruction is within the preset read address range of the AHB slave, and the read address range corresponding to the read instruction crosses a preset boundary, the read instruction is split into N read sub-instructions.

[0057] By pre-determining whether the read address range corresponding to the read instruction is within the preset read address range of the AHB slave, the read instruction is executed only when it is. When the read address range corresponding to the read instruction crosses the preset boundary, the read instruction is split into N read sub-instructions to prevent the problem that the data to be read by the read instruction is not in the AHB slave, thereby ensuring the reading efficiency.

[0058] Furthermore, the method further comprises:

[0059] Receive write instructions from the AXI host;

[0060] When the write address range corresponding to the write instruction crosses a preset boundary, the write instruction is split into N write sub-instructions; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; and N is the number of preset boundaries that the write address range crosses plus 1;

[0061] Performing AHB protocol conversion on the N write sub-instructions to obtain N write operation information;

[0062] The N pieces of write operation information are sent to the AHB slave to return the write result to the AXI host.

[0063] By splitting the write instruction and converting it when it is determined that the write address range crosses the preset boundary, the N write operation information obtained is made information that can be processed by the AHB slave, thereby obtaining the write result, so that AXI to AHB can be applicable to the situation of crossing the preset boundary, thereby improving the applicability and further improving the data throughput.

[0064] Further, when the write address range corresponding to the write instruction crosses a preset boundary, the write instruction is split into N write sub-instructions, including:

[0065] When the write address range corresponding to the write instruction crosses a preset boundary, the write address information in the write instruction and the write data information in the write instruction are respectively split into N write sub-instructions; wherein the N write sub-instructions include: N write address sub-information and N write data sub-information;

[0066] Accordingly, performing AHB protocol conversion on the N write sub-instructions to obtain N write operation information includes:

[0067] AHB protocol conversion is performed on the N pieces of write address sub-information and the N pieces of write data sub-information respectively to obtain N pieces of write operation information; wherein the N pieces of write operation information include: the converted N pieces of write address sub-information and the converted N pieces of write data sub-information; and the converted N pieces of write address sub-information correspond one-to-one to the converted N pieces of write data sub-information.

[0068] By splitting the write address information and the write data information respectively to obtain N write sub-instructions when writing instructions, and performing AHB protocol conversion on the N write sub-instructions, the converted N write address sub-information and the converted N write data sub-information are obtained, and the converted N write address sub-information and the converted N write data sub-information correspond one to one, so that the N write operation information meets the requirements of the AHB slave, realizes the data writing of the write instruction across the preset boundary, and improves the applicability of AXI to AHB writing.

[0069] Further, when the write address range corresponding to the write instruction crosses a preset boundary, the write address information in the write instruction and the write data information in the write instruction are respectively split into N write sub-instructions, including:

[0070] When the write address range corresponding to the write instruction crosses a preset boundary, the write ID, the write first address, the write transfer length and the write transfer width in the write address information are respectively split into N pieces of write address sub-information;

[0071] Based on the N pieces of write address sub-information, the write data information is split into write data sub-information corresponding to each piece of write address information to obtain N pieces of write data sub-information.

[0072] By splitting each parameter in the write address information as described above, N write address sub-information are obtained. The write data information is split based on the N write address sub-information, so that each write address information corresponds to one write data sub-information, so that the obtained N write sub-instructions can be written into the AHB slave one by one, ensuring the correct writing of data.

[0073] Further, sending the N pieces of write operation information to the AHB slave to return a write result to the AXI host includes:

[0074] Send the N pieces of write operation information to the AHB slave to obtain N pieces of write response information for the N pieces of write operation information;

[0075] Receiving N write response messages of N write operation messages from the AHB slave;

[0076] When the encoding fields in the N pieces of write response information include all integers from 1 to N, and the N pieces of write response information all indicate that the write is successful, generate write success information, perform AXI protocol conversion on the write success information, and send the converted write success information to the AXI host;

[0077] When the encoding fields in the N pieces of write response information do not include all integers from 1 to N, and / or at least one piece of write response information in the N pieces of write response information indicates a write failure, generating write failure information, performing AXI protocol conversion on the write failure information, and sending the converted write failure information to the AXI host;

[0078] The write result includes: converted write success information or converted write failure information.

[0079] After receiving N write response messages of N write operation messages from the AHB slave, the encoding fields of the N write response messages are judged to determine whether the current write is successful, so as to send information indicating successful write or failed write to the AXI host. In this way, the AXI host knows whether the write instruction issued this time has successfully completed the writing of data.

[0080] An embodiment of the present invention provides a data reading method, which is applied to an AXI host and includes:

[0081] Send a read command to the controller;

[0082] receiving a read result of the read instruction from the controller;

[0083] Wherein, when the read address range corresponding to the read instruction crosses a preset boundary, the controller splits the read instruction into N read sub-instructions and performs AHB protocol conversion to obtain N read operation information and send them to the AHB slave, and obtains the read result of the read instruction through the AHB slave and the controller; wherein, the preset boundary is the address of bytes that are a positive integer multiple of a preset number of bytes; and N is the number of read address ranges that cross the preset boundary plus 1.

[0084] By sending a read instruction to the controller, the controller splits the read instruction and converts it when it determines that the read address range crosses the preset boundary, so that the obtained N read operation information is information that the AHB slave can process, thereby obtaining a read result, so that AXI to AHB can be applicable to the situation of crossing the preset boundary, thereby improving applicability and further improving data throughput.

[0085] Further, the reading result is: N converted read data sub-information and N converted read response information; the N converted read data sub-information and the N converted read response information are obtained by the controller converting the N read data sub-information from the AHB slave and the N read response information corresponding to the N read data sub-information.

[0086] For the read instruction, the read instruction corresponds to the converted N pieces of read data sub-information and the converted N pieces of read response information, so that the reading of the data of the read instruction across the preset boundary is realized, and the applicability of data reading is improved.

[0087] An embodiment of the present invention provides a data reading method, which is applied to an AHB slave and includes:

[0088] Receive N pieces of read operation information from the controller; wherein the N pieces of read operation information are obtained by the controller splitting the read instruction from the AXI host into N read sub-instructions when the read address range corresponding to the read instruction crosses a preset boundary, and performing AHB protocol conversion on the N read sub-instructions; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; and N is the number of read address ranges that cross the preset boundary plus 1;

[0089] Based on the N pieces of read operation information, reading is performed to send a read result to the AXI host through the controller.

[0090] By splitting the read instruction and converting it when it is determined that the read address range crosses the preset boundary, the obtained N read operation information are sent to the AHB slave, and the N read operation information are information that the AHB slave can process, thereby obtaining a read result, so that AXI to AHB can be applicable to the situation of crossing the preset boundary, thereby improving the applicability and further improving the data throughput.

[0091] Furthermore, the method further comprises:

[0092] Based on the N pieces of read address sub-information, N pieces of read data sub-information are obtained, and N pieces of read response information corresponding to the N pieces of read data sub-information are generated;

[0093] N pieces of read data sub-information and N pieces of read response information are sent to the controller so that the controller obtains the read result based on the N pieces of read data sub-information and the N pieces of read response information; wherein the read result is: the converted N pieces of read data sub-information and the converted N pieces of read response information.

[0094] By reading out N read data sub-information during a read instruction, generating corresponding N read response information and sending them to the controller, so that the AXI host can receive the read result, and the AXI host can obtain the result of the data reading, thereby realizing the reading of data of the read instruction across the preset boundary from AXI to AHB, and improving the applicability of data reading.

[0095] An embodiment of the present invention provides a data reading method, which is applied to a system-on-chip (SOC), wherein the SOC includes: an AXI host, a controller, and an AHB slave; the method includes:

[0096] The AXI host sends a read instruction to the controller;

[0097] When the read address range corresponding to the read instruction crosses a preset boundary, the controller splits the read instruction into N read sub-instructions, performs AHB protocol conversion on the N read sub-instructions, and obtains N read operation information.

[0098] Send the N read operation information to the AHB slave; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; N is the number of the read address range that crosses the preset boundary plus 1;

[0099] The AHB slave performs reading based on the N pieces of read operation information to send the reading result to the AXI host through the controller.

[0100] The AXI host sends a read instruction to the controller. When the controller determines that the read address range crosses the preset boundary, it splits the read instruction and converts it, so that the obtained N read operation information is sent to the AHB slave. The N read operation information is information that the AHB slave can process, so that the AXI host obtains the read result, making AXI to AHB conversion applicable to the situation that crosses the preset boundary, thereby improving the applicability and further improving the data throughput.

[0101] An embodiment of the present invention provides a data reading device, which is applied to a controller and includes:

[0102] A first receiving module, used for receiving a read instruction from an AXI host;

[0103] A splitting module, used for splitting the read instruction into N read sub-instructions when the read address range corresponding to the read instruction crosses a preset boundary; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; and N is the number of preset boundaries crossed by the read address range plus 1;

[0104] A conversion module, used for performing AHB protocol conversion on the N read sub-instructions to obtain N read operation information;

[0105] The first sending module is used to send the N pieces of read operation information to the AHB slave to return the read result to the AXI host.

[0106] After the first receiving module receives the read instruction, the splitting module splits the read instruction and converts it when it is determined that the read address range crosses the preset boundary, so that the N read operation information obtained by the conversion module is information that can be processed by the AHB slave, and is sent out by the first sending module to obtain a read result, so that AXI to AHB can be applicable to the situation of crossing the preset boundary, thereby improving applicability and further improving data throughput.

[0107] An embodiment of the present invention provides a data reading device, which is applied to an AXI host and includes:

[0108] A second sending module, used for sending a read instruction to the controller;

[0109] A second receiving module, used for receiving a read result of the read instruction from the controller;

[0110] Wherein, when the read address range corresponding to the read instruction crosses a preset boundary, the controller splits the read instruction into N read sub-instructions and performs AHB protocol conversion to obtain N read operation information and send them to the AHB slave, and obtains the read result of the read instruction through the AHB slave and the controller; wherein, the preset boundary is the address of bytes that are a positive integer multiple of a preset number of bytes; and N is the number of read address ranges that cross the preset boundary plus 1.

[0111] A read instruction is sent to the controller through the second sending module, so that when the controller determines that the read address range crosses the preset boundary, the controller splits the read instruction and converts it, so that the obtained N read operation information is information that can be processed by the AHB slave, so that the second receiving module receives the read result, so that AXI to AHB conversion can be applicable to the situation of crossing the preset boundary, thereby improving applicability and further improving data throughput.

[0112] An embodiment of the present invention provides a data reading device, which is applied to an AHB slave and includes:

[0113] A third receiving module is used to receive N pieces of read operation information from the controller; wherein the N pieces of read operation information are obtained by the controller splitting the read instruction from the AXI host into N read sub-instructions when the read address range corresponding to the read instruction crosses a preset boundary, and performing AHB protocol conversion on the N read sub-instructions; wherein the preset boundary is a byte address that is a positive integer multiple of a preset number of bytes as a base; N is the number of read address ranges that cross the preset boundary plus 1, so as to send the read result to the controller through the controller;

[0114] The reading module is used to perform reading based on the N pieces of read operation information, so as to send the reading result to the AXI host through the controller.

[0115] N pieces of read operation information are received through the third receiving module. The N pieces of read operation information are obtained by splitting the read instruction and converting it when the controller determines that the read address range crosses the preset boundary. The reading module reads based on the N pieces of read operation information, so that the obtained N pieces of read operation information are sent to the AHB slave. The N pieces of read operation information are information that the AHB slave can process, thereby obtaining a reading result, so that AXI to AHB conversion can be applicable to the situation of crossing the preset boundary, thereby improving applicability and further improving data throughput.

[0116] The embodiment of the present invention provides a SOC, including: an AXI host, a controller and an AHB slave; wherein:

[0117] The AXI host is used to send a read instruction to the controller;

[0118] The controller is used for splitting the read instruction into N read sub-instructions when the read address range corresponding to the read instruction crosses a preset boundary, performing AHB protocol conversion on the N read sub-instructions to obtain N read operation information, and sending the N read operation information to the AHB slave; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; and N is the number of the read address range crossing the preset boundary plus 1;

[0119] The AHB slave is used to read based on the N pieces of read operation information, and send the read result to the AXI host through the controller.

[0120] The AXI host sends a read instruction to the controller. When the controller determines that the read address range crosses the preset boundary, it splits the read instruction and converts it, so that the obtained N read operation information is sent to the AHB slave. The N read operation information is information that the AHB slave can process, so that the AXI host obtains the read result, making AXI to AHB conversion applicable to the situation that crosses the preset boundary, thereby improving the applicability and further improving the data throughput.

[0121] An embodiment of the present invention provides a controller, comprising: a processor and a storage medium storing instructions executable by the processor, wherein the storage medium relies on the processor to perform operations via a communication bus, and when the instructions are executed by the processor, the data reading method described in one or more of the above embodiments is executed.

[0122] An embodiment of the present invention provides an AXI host, comprising: a processor and a storage medium storing instructions executable by the processor, wherein the storage medium relies on the processor to perform operations through a communication bus, and when the instructions are executed by the processor, the data reading method described in one or more of the above embodiments is executed.

[0123] An embodiment of the present invention provides an AHB slave, comprising: a processor and a storage medium storing instructions executable by the processor, wherein the storage medium relies on the processor to perform operations through a communication bus, and when the instructions are executed by the processor, the data reading method described in one or more of the above embodiments is executed.

[0124] An embodiment of the present invention provides a computer storage medium storing executable instructions. When the executable instructions are executed by one or more processors, the processors execute the data reading method described in one or more embodiments.

[0125] Beneficial effects of the present invention:

[0126] (1) By splitting and converting the read instruction when it is determined that the read address range crosses the preset boundary, the obtained N pieces of read operation information are information that can be processed by the AHB slave, so that the read instruction that crosses the preset boundary can be applicable to the requirements of the AHB slave;

[0127] (2) Based on N read operation information sent to the AHB slave, the read result is returned to the AXI master, so that the AXI to AHB conversion can be applicable to the situation of crossing the preset boundary, thereby improving the applicability and further improving the data throughput. BRIEF DESCRIPTION OF THE DRAWINGS

[0128] Figure 1 A schematic diagram of the structure of an optional SOC provided in an embodiment of the present invention;

[0129] Figure 2 A schematic diagram of the process interaction of an optional data reading and writing method provided by an embodiment of the present invention;

[0130] Figure 3 A schematic diagram of the structure of an optional SOC example provided in an embodiment of the present invention;

[0131] Figure 4 A flowchart of an example 1 of an optional data reading and writing method provided by an embodiment of the present invention;

[0132] Figure 5 A flowchart of Example 2 of an optional data reading and writing method provided in an embodiment of the present invention;

[0133] Figure 6 A schematic diagram of an optional data reading method provided in an embodiment of the present invention Figure 1 ;

[0134] Figure 7 A schematic diagram of an optional data reading method provided in an embodiment of the present invention Figure 2 ;

[0135] Figure 8 A schematic diagram of an optional data reading method provided in an embodiment of the present invention Figure 3 ;

[0136] Fig. 9 A schematic diagram of an optional data reading method provided in an embodiment of the present invention Figure 4 ;

[0137] Fig.10 A schematic diagram of an optional data reading device provided in an embodiment of the present invention Figure 1 ;

[0138] Fig.11A schematic diagram of an optional data reading device provided in an embodiment of the present invention Figure 2 ;

[0139] Fig.12 A schematic diagram of an optional data reading device provided in an embodiment of the present invention Figure 3 ;

[0140] Fig.13 A schematic diagram of the structure of an optional controller provided in an embodiment of the present invention;

[0141] Fig.14 A schematic diagram of the structure of an optional AXI host provided in an embodiment of the present invention;

[0142] Fig.15 A schematic diagram of the structure of an optional AHB slave provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0143] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0144] The embodiment of the present invention provides a data reading and writing method, which is applied in SOC. Figure 1 A schematic diagram of an optional SOC structure provided by an embodiment of the present invention, such as Figure 1 As shown, SOC100 may include: an AXI host 11, a controller 12 and an AHB slave 13; wherein the AXI host 11 is connected to one end of the controller 12, and the other end of the controller 12 is connected to the AHB slave 13; wherein,

[0145] The AXI host 11 is used to send read and write instructions to the controller 12. The controller 12 processes the read and write instructions and finally obtains read and write operation information that can be received by the AHB slave 13. The AHB slave 13 reads and writes data based on the received read and write operation information.

[0146] It should be noted that the above-mentioned AXI host 11 can be a core of a central processing unit (CPU) or a controller of a device, etc., and the above-mentioned AHB slave 13 can be a memory, or a double data rate synchronous dynamic random access memory (DDR) or a flash memory (FLASH), etc., and the embodiment of the present invention does not make specific limitations on this.

[0147] Based on the above Figure 1 SOC, the embodiment of the present invention provides a data reading and writing method, Figure 2A schematic diagram of the process interaction of an optional data reading and writing method provided by an embodiment of the present invention, such as Figure 2 As shown, the data reading and writing method may include:

[0148] S201: The AXI host 11 sends a read / write instruction to the controller 12;

[0149] In the related art, the AXI to AHB method is only applicable to the case of read and write instructions that do not cross the 1KB byte boundary, and is not applicable to the read and write instructions that cross the 1KB byte boundary, resulting in only the reading and writing of data that does not cross the 1KB byte boundary, thus resulting in low throughput of the SOC.

[0150] In order to improve the applicability of AXI to AHB conversion and to improve the throughput of SOC, in an embodiment of the present invention, a controller 12 is arranged between the AXI host 11 and the AHB slave 13, and the AXI host 11 sends a read and write instruction to the controller 12, and the read and write instruction may include: a read instruction or a write instruction; wherein the read instruction may include read address information, and the write instruction may include write address information and write data information, and the AXI host 11 first sends the write address information to the controller 12, and after an address channel is established between the AXI host 11 and the controller 12, the AXI host 11 sends the write data information to the controller 12.

[0151] In this way, the AXI host 11 sends read and write instructions to the controller 12 , so that the controller 12 can read and write data from the AHB slave 13 .

[0152] S202: When the read / write address range corresponding to the read / write instruction crosses a preset boundary, the controller 12 splits the read / write instruction into N read / write sub-instructions;

[0153] Through S201, the AXI host 11 sends a read / write instruction to the controller 12, so that the controller 12 receives the read / write instruction and first determines whether the read / write address range corresponding to the read / write instruction crosses a preset boundary, where the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; here, for AHB, the preset number of bytes is usually 1KB, that is, the controller 12 needs to determine whether the read / write address range crosses an IKB byte boundary, where the preset boundary can be the 1KB byte boundary, the 2KB byte boundary, the 3KB byte boundary, ..., the RKB byte boundary; where R can represent the number of 1KB byte boundaries that the read / write address range crosses.

[0154] Here, only when the controller 12 determines that the read-write address range crosses the preset boundary, the read-write instruction needs to be split. Through the splitting, N read-write sub-instructions are obtained, where N is the number of read-write address ranges that cross the preset boundary plus 1. That is to say, the read-write instruction is split into the number of read-write address ranges that cross the preset boundary plus 1 read-write sub-instruction, that is, each split read-write sub-instruction is sent to the AHB slave 13 for reading and writing one by one after conversion.

[0155] Here, for write instructions, not only the write address information in the write instructions needs to be split, but also the write data information in the write instructions needs to be split. For read instructions, only the read address information in the read instructions needs to be split.

[0156] In this way, the request with AHB can be used through S202.

[0157] S203: The controller 12 performs AHB protocol conversion on the N read and write sub-instructions to obtain N read and write operation information;

[0158] Through S202, the read and write instructions whose read and write address ranges cross the preset boundaries are split into N read and write sub-instructions. In order to be applicable to the AHB protocol, the controller 12 here also performs AHB protocol conversion on the N read and write sub-instructions, thereby obtaining N read and write sub-instructions after protocol conversion, that is, N write operation information, which are sent to the AHB slave 13 for realizing data reading and writing.

[0159] When the read-write instruction is a write instruction, the N pieces of read-write operation information are N pieces of write operation information; when the read-write instruction is a read instruction, the N pieces of read-write operation information are N pieces of read operation information.

[0160] The above S203 may perform the AHB protocol conversion in a serial manner, that is, the AHB protocol conversion is performed one by one by reading and writing sub-instructions, or may perform the AHB protocol conversion in a parallel manner, that is, multiple read and write sub-instructions are simultaneously converted to the AHB protocol. Here, the embodiment of the present invention does not specifically limit this.

[0161] Compared with the serial method, the parallel conversion method can improve the reading and writing speed from AXI to AHB.

[0162] S204 : the controller 12 sends N pieces of read and write operation information to the AHB slave 13 .

[0163] S205: The AHB slave 13 performs reading and writing based on the N pieces of read and write operation information.

[0164] N pieces of read and write operation information are obtained through S203. In order to realize reading and writing, the N pieces of read and write operation information are sent to the AHB slave 13. Here, it should be noted that the controller 12 sends the N pieces of read and write operation information to the AHB slave 13 one by one, so that the AHB slave 13 receives the N pieces of read and write operation information one by one, and reads and writes data one by one to realize the reading and writing of data and obtain the reading result, wherein the write instruction corresponds to the write result, and the read instruction corresponds to the read result.

[0165] In order to determine whether the read / write address range crosses a preset boundary, in an optional embodiment, the method may further include:

[0166] The controller 12 determines the number of preset boundaries that the read / write address range crosses based on the read / write instruction;

[0167] When the number is greater than 0, the controller 12 determines that the read / write address range crosses a preset boundary;

[0168] When the number is equal to 0, the controller 12 determines that the read / write address range does not cross the preset boundary.

[0169] It can be understood that after receiving the read-write instruction, the controller 12 determines the corresponding read-write address range based on the read-write instruction, and determines the number of times the read-write address range crosses the preset boundaries, that is, the above-mentioned R. When the number is 0, it means that the number of times the read-write address range crosses the preset boundaries is 0, that is, it is determined that the read-write address range does not cross the preset boundary. When the number is greater than 0, it means that the read-write address range crosses the preset boundary.

[0170] Then, in case that the read / write address range crosses the preset boundary, the read / write instruction is split into N read / write sub-instructions to meet the requirements of AHB.

[0171] In addition, for the case where the read / write address range does not cross the preset boundary, in an optional embodiment, the above method may further include:

[0172] When the read / write address range corresponding to the read / write instruction does not cross the preset boundary, the controller 12 redefines the read / write ID and the encoding field 0 in the read / write address information in the read / write instruction as the read / write ID in the read / write address information to obtain the read / write instruction again;

[0173] The controller 12 performs AHB protocol conversion on the read and write instructions to obtain a read and write operation information;

[0174] The controller 12 sends a read / write operation message to the AHB slave to implement the read / write operation.

[0175] It can be understood that when the read-write address range does not cross the preset boundary, the read-write instruction does not need to be split. It is only necessary to redefine the read-write ID in the read-write address information in the read-write instruction together with the encoding field 0 as the read-write ID in the read-write address information, thereby redefining the redetermined read-write ID and other information in the read-write instruction as the read-write instruction.

[0176] For example, for a read instruction, the read ID in the read address information of the read instruction is re-determined together with the coding field 0 as the read ID in the read address information, and is determined together with the read starting address, read transfer length and read transfer width in the read address information as the read instruction; for a write instruction, the write ID in the write address information of the write instruction is re-determined together with the coding field 0 as the write ID in the write address information, and is determined together with the write starting address, write transfer length and write transfer width in the write address information as the write address information, and the write address information and the write data information are determined together as the write instruction; in this way, read and write instructions are obtained.

[0177] In order to meet the requirements of AHB, the controller 12 needs to perform AHB protocol conversion on the read and write instructions to obtain the converted read and write instructions, that is, obtain a read and write operation information, and then send it to the AHB slave 13 to realize the reading and writing of data.

[0178] In order to determine whether the read / write address range crosses the number of preset boundaries, in an optional embodiment, the controller 12 determines the number of preset boundaries crossed by the read / write address range based on the read / write instruction, which may include:

[0179] The controller 12 determines the read / write end address based on the read / write start address, the read / write transfer length and the read / write transfer width in the read / write instruction;

[0180] The controller 12 right-shifts the read / write end address and the read / write start address by a preset number of bits, and calculates the difference between the shifted read / write end address and the shifted read / write start address;

[0181] The controller 12 determines the difference as the number of read / write address ranges that cross preset boundaries.

[0182] It can be understood that the controller 12 uses the read / write address information in the read / write instruction to determine the read / write end address, wherein, taking the write address information as an example, the write address information includes: a write start address, a write transfer length, and a write transfer width, wherein the calculation formula of the write end address is as follows:

[0183] Write end address = (AxADDR + AxLEN * 2 AxSIZE )(1)

[0184] Among them, the above AxADDR represents the write start address, AxLEN represents the write transfer length, and AxSIZE represents the write transfer width. That is to say, the write transfer length is shifted left by the read / write transfer width, and the sum of it and the write start address is determined as the write end address.

[0185] After obtaining the write end address, the write end address and the write start address are respectively shifted right by a preset number of bits, wherein the preset number of bits is the minimum bit width corresponding to the preset number of bytes. For example, if the preset number of bytes is 1KB, then the corresponding minimum bit width is 10. Thus, after the shift, the difference between the shifted write end address and the shifted write start address is calculated, and the difference is determined as the number R of the write address range crossing the preset boundary. The calculation formula of R is as follows:

[0186] R=(AxADDR+AxLEN*2 AxSIZE ) / 2 10 -AxADDR / 2 10 (2)

[0187] In this way, shifting and addition and subtraction operations can be performed based on the write start address, write end address, write transfer length and write transfer width to obtain the number of preset boundaries across the write address range, thereby determining whether the write address range crosses the preset boundaries and the number of boundaries, and splitting the read and write instructions that need to be split into N read and write sub-instructions in turn to meet the requirements of AHB.

[0188] It should be noted that in calculating the number of times that the write address range crosses the preset boundary, the read address range is similar to the write address range, and will not be described in detail here.

[0189] For the process of writing data, in an optional embodiment, when the read-write instruction is a write instruction, the write instruction includes: write address information and write data information, and correspondingly, N pieces of read-write operation information are N pieces of write operation information; S202 may include:

[0190] When the write address range corresponding to the write instruction crosses a preset boundary, the controller 12 splits the write address information in the write instruction and the write data information in the write instruction into N write sub-instructions respectively; wherein the N write sub-instructions include: N write address sub-information and N write data sub-information;

[0191] S203 may include:

[0192] The controller 12 performs AHB protocol conversion on the N write address sub-information and the N write data sub-information respectively to obtain N write operation information; wherein the N write operation information includes: the converted N write address sub-information and the converted N write data sub-information; and the converted N write address sub-information corresponds one-to-one to the converted N write data sub-information.

[0193] It can be understood that for write instructions, the controller 12 needs to split the write address information and the write data information respectively, so as to obtain N write address sub-information and N write data sub-information. After the splitting is completed, the controller 12 performs AHB protocol conversion on the N write address sub-information and the N write data sub-information respectively, so as to obtain one-to-one corresponding converted N write address sub-information and N converted write data sub-information. That is to say, through the AHB protocol conversion, not only the converted N write address sub-information and the converted N read data sub-information suitable for the AHB protocol are obtained, but also the two are matched one-to-one, so that the N write address sub-information and the N write data information in the N write operation information correspond to each other, so as to facilitate the correct writing of data.

[0194] Further, with respect to the process of writing data, in an optional embodiment, when the write address range corresponding to the write instruction crosses a preset boundary, the controller 12 splits the write address information and the write data information into N write sub-instructions respectively, including:

[0195] When the write address range corresponding to the write instruction crosses the preset boundary, the controller 12 splits the write ID, the write first address, the write transfer length and the write transfer width in the write address information into N pieces of write address sub-information respectively;

[0196] Based on the N pieces of write address sub-information, the controller 12 splits the write data information into write data sub-information corresponding to each piece of write address sub-information to obtain N pieces of write data sub-information.

[0197] It can be understood that since the write instruction includes write address information and write data information, then, in the process of splitting the write address information and the write data information respectively, the controller 12 needs to split the write ID in the write address information, split the write start address, split the write transfer length, and split the write transfer width, thereby obtaining N pieces of write address information, wherein each piece of write address sub-information includes: write ID, write start address, write transfer length and write transfer width.

[0198] Then, the controller 12 splits the write data information based on the N pieces of write address sub-information to obtain the write data sub-information corresponding to each piece of write address sub-information, so that each piece of write address sub-information corresponds to one piece of write data sub-information, achieving a one-to-one correspondence.

[0199] Furthermore, in order to split the write address information to obtain write sub-instructions that meet the AHB requirements, in an optional embodiment, when the write address range corresponding to the write instruction crosses a preset boundary, the controller 12 splits the write ID, the write first address, the write transfer length, and the write transfer width in the write address information into N pieces of write address sub-information, including:

[0200] When the write address range corresponding to the write instruction crosses the preset boundary, the controller 12 determines the write ID and the coding field a in the write address information as the write ID of the a-th write address sub-information;

[0201] When a is equal to 1, the controller 12 determines the write start address of the write address information as the write start address of the a-th write address sub-information; when a is greater than or equal to 2 and less than or equal to N, the controller 12 determines N-1 boundary addresses starting from the write start address of the write address information, and determines the j-th boundary address among the N-1 boundary addresses as the write start address of the a-th write address sub-information; wherein j is equal to a-1;

[0202] When a is greater than or equal to 1 and less than or equal to N-1, the controller 12 determines N-1 boundary addresses starting from the write start address of the write address information, and determines the jth boundary address among the N-1 boundary addresses as the write end address of the ath write address sub-information; when a is equal to N, the write end address of the write address information is determined as the write end address of the ath write address sub-information;

[0203] The controller 12 determines the write transfer length in the a-th write address sub-information by using the write end address of the a-th write address sub-information and the write start address of the a-th write address sub-information when N is equal to 2, determines the write transfer length in the 1st write address sub-information by using the write end address of the 1st write address sub-information and the write start address of the 1st write address sub-information when N is greater than 2, determines the preset write transfer length as the write transfer length in the 2nd to N-1st write address sub-information, and determines the write transfer length in the N-th write address sub-information by using the write end address of the N-th write address sub-information and the write start address of the N-th write address sub-information; wherein the preset write transfer length is obtained by right-shifting the maximum number of the preset number of bytes by the single digit of the write transfer width;

[0204] The controller 12 determines the write transfer width of the write address information as the write transfer width in the a-th write address sub-information.

[0205] It can be understood that, with respect to the ID, the write ID in the write address information and the coding field a are determined as the write ID of the a-th write address sub-information, that is, AxIDa={AxID,SID}, wherein AxIDa represents the write ID of the a-th write address sub-information, AxID represents the identifier of the write address sub-information, and the coding field SID is equal to a; for example, AxID1 of the first address sub-information is {ID,1}, and AxID2 of the second address sub-information is {ID,2}.

[0206] There are two types of write first addresses in the write address sub-information. One is that the write first address of the first write address sub-information is: the write first address in the write address information. The other is that the write first addresses in the second to Nth write address sub-information are: N-1 boundary addresses starting from the write first address of the write address information. Then, the write first address of the ath write address sub-information can be expressed as follows:

[0207] (AxADDR / 2 10 +a-1)*2 10 , a is a positive integer, and 2≤a≤N (3)

[0208] Regarding the write end address in the write address sub-information, there are two types. One is that the write end address in the 1st to N-1st write address sub-information is: the 1st to N-1th boundary addresses starting from the write start address of the write address information; the other is that the write end address in the Nth write address sub-information is: the write end address in the write address information.

[0209] For the write transfer length in the write address sub-information, there are two cases, one is the case where N is equal to 2, and the other is the case where N is greater than 2. When N is equal to 2, it means that the number of times the write address range crosses the preset boundary is 1, so it is necessary to calculate two write transfer lengths. Here, after knowing the write start address and the write end address of each write address sub-information, the write transfer length of the first write address sub-information can be obtained by using the write end address and the write start address of the first write address sub-information using the following formula:

[0210] AxLEN1=(((AxADDR / 2 10 +1)*2 10 -2 AxSIZE )-AxADDR) / 2 AxSIZE (4)

[0211] Among them, AxLEN1 represents the write transfer length in the first write address information, (AxADDR / 2 10 +1)*2 10 -2 AxSIZE ) indicates the boundary address where the write address range crosses the preset boundary, namely, the write end address of the first write address sub-information and the write start address of the second write address sub-information; the above formula (4) uses the write end address of the first write address sub-information, and right-shifts the difference between it and the write start address of the first write address sub-information by AxSIZE digits to obtain the write transfer length in the first write address information. Then, the write transfer length in the second write address sub-information can be obtained by the following formula in the same way:

[0212] AxLEN2=((AxADDR+AxLEN*2 AxSIZE )-(AxADDR / 210 +1)*2 10 -2 AxSIZE ) / 2 AxSIZE (5)

[0213] Wherein, AxLEN2 represents the write transfer length in the second write address information.

[0214] When N is greater than 2, the write transfer length in the first write address sub-information is: the first boundary address that uses the write address range to cross the preset boundary, that is, the write end address of the first write address sub-information, and the write start address in the write address information. The specific formula is as follows:

[0215] AxLEN1=(((AxADDR / 2 10 +1)*2 10 -2 AxSIZE )-AxADDR) / 2 AxSIZE (6)

[0216] Then, ((AxADDR / 2 10 +1)*2 10 -2 AxSIZE ) represents the first boundary address, that is, the write end address of the first write address sub-information. The write transfer length in the second to N-1 write address sub-information is the write transfer length in the write address information. The specific formula is as follows:

[0217] AxLENa=2 10 / 2 AxSIZE , 2≤a≤N-1 (7)

[0218] That is to say, the above AxLENa represents the preset write transfer length, which is obtained by shifting the maximum number of preset bytes right by AxSIZE digits, that is, shifting 1111111111 right by AxSIZE digits.

[0219] The write transfer length in the Nth write address sub-information is obtained by right shifting the difference between the write end address of the Nth write address sub-information and the write start address of the Nth write address sub-information by AxSIZE digits. The specific formula is as follows:

[0220] AxLEN N =((AxADDR+AxLEN*2 AxSIZE )-(AxADDR / 2 10 +N-1)*2 10 )) / 2 AxSIZE (8)

[0221] Where (AxADDR / 2 10 +N-1)*2 10 ) represents N-1 boundary addresses.

[0222] With respect to the write transfer width in the write address sub-information, the write transfer width in each piece of write address information is consistent, that is, they are all the write transfer width in the write address information, that is, the above-mentioned AxSIZE.

[0223] In this way, the write ID, write start address, write transfer length and write transfer width in the 1st to Nth write address sub-information can be obtained, that is, the 1st to Nth write address sub-information is obtained.

[0224] After S202 and S203, N pieces of write operation information are obtained, and the N pieces of write operation information are sent to the AHB slave 13. In order to implement data writing, in an optional embodiment, S205 may include:

[0225] The AHB slave 13 writes the N pieces of write data sub-information into the N pieces of write address sub-information;

[0226] The AHB slave 13 generates N write response messages corresponding to the N write data sub-messages, and sends them to the controller 12;

[0227] When the encoding fields in the N write response messages include all integers from 1 to N, and the N write response messages all indicate that the write is successful, the controller 12 generates write success information, performs AXI protocol conversion on the write success information, and sends the converted write success information to the AXI host 11;

[0228] When the encoding fields in the N write response messages do not include all integers from 1 to N, and / or at least one of the N write response messages indicates a write failure, the controller 12 generates write failure information, performs AXI protocol conversion on the write failure information, and sends the converted write failure information to the AXI host 11.

[0229] It can be understood that after the AHB slave 13 receives N write operation information, it writes the N write data sub-information into the corresponding write address sub-information, and generates N write response information corresponding to the N write data sub-information. The N write response information is used to inform the AXI slave 11 whether the write instruction is successful. Therefore, the AHB slave 13 sends the N write response information to the controller 12. After the controller 12 receives the N write response information, it checks the encoding field in each write response information and the content of each write response information. When the encoding field includes all integers from 1 to N, and the content indicates that the write is successful, it means that all the N write data sub-information are written successfully, so the controller 12 generates a write success message. In order to enable the AXI host 11 to receive the information, the write success message is converted to the AXI protocol, so that the controller 12 sends the converted write success message to the AXI host 11.

[0230] If the encoding field does not include all integers from 1 to N, and / or, at least one of the contents indicates a write failure, for example, N only includes a portion, and / or, there is one content indicating a write failure, it means that not all N write data sub-information are written successfully, so the controller 12 generates write failure information. In order to enable the AXI host 11 to receive the information, the write failure information is converted into the AXI protocol, and the controller 12 sends the converted write failure information to the AXI host 11.

[0231] The converted write success information and the converted write failure information are the write results in the read-write results.

[0232] In this way, the AXI host 11 receives the converted write success information or the converted write failure information to know whether the sent write instruction is successfully written into the AHB slave 13 .

[0233] In addition, for the process of reading data, in an optional embodiment, when the read / write instruction is a read instruction, the read instruction includes: read address information, and the read / write operation information is read operation information; S202 may include:

[0234] When the read / write address range corresponding to the read instruction crosses a preset boundary, the controller 12 splits the read address information in the read instruction into N read sub-instructions; wherein the N read sub-instructions include: N read address sub-information;

[0235] S203 may include:

[0236] The controller 12 performs AHB protocol conversion on the N pieces of read address sub-information to obtain N pieces of read operation information.

[0237] It can be understood that for read instructions, the controller 12 needs to split the read address information to obtain N read address sub-information. After the splitting is completed, the controller 12 performs AHB protocol conversion on the N read address sub-information to obtain the converted N read address sub-information, that is, N read operation information, which is used for reading data.

[0238] Further, with respect to the process of reading data, in an optional embodiment, when the read address range corresponding to the read instruction crosses a preset boundary, the controller 12 splits the read address information into N read sub-instructions, including:

[0239] When the read address range corresponding to the read instruction crosses a preset boundary, the controller 12 splits the ID, the read head address, the read transfer length and the read transfer width in the read address information into N pieces of read address sub-information respectively.

[0240] It can be understood that since the read instruction includes read address information, then, in the process of splitting the read address information, the controller 12 needs to split the read ID in the read address information, split the read start address, split the read transfer length, and split the read transfer width, thereby obtaining N pieces of read address information, wherein each piece of read address sub-information includes: read ID, read start address, read transfer length, and read transfer width.

[0241] In this way, each piece of read address sub-information can be obtained, so as to facilitate reading the data corresponding to each piece of read address sub-information from the AHB slave 13 .

[0242] Furthermore, in order to split the read address information to obtain the read sub-instructions that meet the AHB requirements, in an optional embodiment, when the read address range corresponding to the read instruction crosses the preset boundary, the controller 12 splits the read ID, the read first address, the read transfer length and the read transfer width in the read address information into N pieces of read address sub-information, including:

[0243] When the read address range corresponding to the read instruction crosses the preset boundary, the controller 12 determines the read ID and the coding field a in the read address information as the read ID of the a-th read address sub-information; wherein a is a positive integer greater than or equal to 1 and less than or equal to N;

[0244] When a is equal to 1, the read start address of the read address information is determined as the read start address of the a-th read address sub-information; when a is greater than or equal to 2 and less than or equal to N, the N-1 boundary addresses starting from the read start address of the read address information are determined, and the j-th boundary address among the N-1 boundary addresses is determined as the start address of the a-th read address sub-information; wherein j is equal to a-1;

[0245] When a is greater than or equal to 1 and less than or equal to N-1, the controller 12 determines N-1 boundary addresses starting from the read start address of the read address information, and determines the jth boundary address among the N-1 boundary addresses as the read end address of the ath read address sub-information; when a is equal to N, the read end address of the read address information is determined as the read end address of the ath read address sub-information;

[0246] The controller 12 determines the read transfer length in the a-th read address sub-information by using the read end address of the a-th read address sub-information and the read start address of the a-th read address sub-information when N is equal to 2, determines the read transfer length in the 1st read address sub-information by using the read end address of the 1st read address sub-information and the read start address of the 1st read address sub-information when N is greater than 2, determines the preset read transfer length as the read transfer length in the 2nd to N-1st read address sub-information, and determines the read transfer length in the N-th read address sub-information by using the read end address of the N-th read address sub-information and the read start address of the N-th read address sub-information; wherein the preset read transfer length is obtained by right-shifting the maximum number of the preset number of bytes by the number of digits of the read transfer width;

[0247] The controller 12 determines the read transfer width of the read address information as the read transfer width in the a-th read address sub-information.

[0248] It can be understood that, with respect to the ID, the read ID and the coding field a in the read address information are determined as the read ID of the a-th write address sub-information, that is, ARIDa={AxID,SID}, wherein ARIDa represents the read ID of the a-th read address sub-information, ARID represents the identifier of the read address sub-information, and the representation field SID is equal to a; for example, ARID1 of the first read address sub-information is {ID,1}, and ARID2 of the second read address sub-information is {ID,2}.

[0249] There are two types of read first addresses in the read address sub-information. One is that the read first address in the first read address sub-information is: the read first address in the read address information. The other is that the read first addresses in the second to N read address sub-information are: the N-1 boundary addresses starting from the read first address of the read address information. Then, the read first address of the ath read address sub-information is as follows:

[0250] (ARADDR / 2 10 +a-1)*2 10 , a is a positive integer, and 2≤a≤N (9)

[0251] Among them, the above ARADDR represents the read first address.

[0252] For the read end address in the read address sub-information, the read end address in the 1st to N-1st read address sub-information is: the 1st to N-1st boundary addresses from the read start address of the read address information are (ARADDR / 2 10 +a)*2 10 -2 ARSIZE , a is a positive integer, and 1≤a≤N-1, the end-of-read address in the Nth read address sub-information is: the end-of-read address in the read address information is (ARADDR+ARLEN*2 ARSIZE), wherein the above ARSIZE represents the read transfer width.

[0253] For the read transfer length in the read address sub-information, there are two cases, one is the case where N is equal to 2, and the other is the case where N is greater than 2. When N is equal to 2, it means that the number of times the read address range crosses the preset boundary is 1, so it is necessary to calculate two read transfer lengths. Here, after knowing the read start address and the read end address of each read address sub-information, the read transfer length of the first read address sub-information can be obtained by using the read end address and the read start address of the first read address sub-information using the following formula:

[0254] ARLEN1=(((ARADDR / 2 10 +1)*2 10 -2 ARSIZE )-ARADDR) / 2 ARSIZE (10)

[0255] Among them, ARLEN above represents the read transfer length, ARLEN1 represents the read transfer length in the first read address sub-information, ARADDR / 2 10 +1)*2 10 -2 ARSIZE The boundary address indicating that the read address range crosses the preset boundary is the read end address of the first read address sub-information and the read start address of the second read address sub-information. The above formula (10) is obtained by right shifting the difference between the read end address of the first read address sub-information and the read / write start address of the first read address sub-information by AxSIZE digits. Then, for the read transfer length in the second read address sub-information, the same method can be used to obtain the following formula:

[0256] ARLEN2=((ARADDR+ARLEN*2 AxSIZE )-(ARADDR / 2 10 +1)*2 10 -2 ARSIZE ) / 2 ARSIZE (11)

[0257] ARLEN2 represents the read transfer length in the second read address information.

[0258] When N is greater than 2, the read transfer length in the first read address sub-information is: the first boundary address across the preset boundary using the read address range, that is, the write end address of the first write address sub-information, and the read start address in the read address information. The specific formula is as follows:

[0259] ARLEN1=(((ARADDR / 2 10 +1)*2 10 -2 ARSIZE)-ARADDR) / 2 ARSIZE (12)

[0260] Then, ((ARADDR / 2 10 +1)*2 10 -2 ARSIZE ) represents the first boundary address, that is, the read end address of the first read address sub-information. The read transfer length in the second to N-1 read address sub-information is the read transfer length in the read address information. The specific formula is as follows:

[0261] ARLENa=2 10 / 2 ARSIZE , 2≤a≤N-1(13)

[0262] That is to say, the above ARLENa represents the preset read transfer length, which is obtained by shifting the maximum number of preset bytes right by ARSIZE digits, that is, shifting 1111111111 right by ARSIZE digits.

[0263] The read transmission length in the Nth read address sub-information is obtained by right-shifting the difference between the read end address of the Nth read address sub-information and the read start address of the Nth read address sub-information by AxSIZE digits. The specific formula is as follows:

[0264] ARLEN N =((ARADDR+ARLEN*2 ARSIZE )-(ARADDR / 2 10 +N-1)*2 10 ) / 2 ARSIZE (14)

[0265] With respect to the read transfer width in the read address sub-information, the read transfer widths are consistent, and are all the read transfer width in the read address information, that is, the above-mentioned ARSIZE.

[0266] In this way, the ID, read start address, read transfer length and read transfer width in the 1st to Nth read address sub-information can be obtained, that is, the 1st to Nth read address sub-information is obtained.

[0267] After S202 and S203, N pieces of read operation information are obtained, and the N pieces of read operation information are sent to the AHB slave 13. In order to read data, in an optional embodiment, S205 may include:

[0268] The AHB slave 13 obtains N pieces of read data sub-information based on the N pieces of read address sub-information, and generates N pieces of read response information corresponding to the N pieces of read data sub-information;

[0269] The AHB slave 13 sends N read data sub-information and N read response information to the controller 12;

[0270] The controller 12 performs AXI protocol conversion on the N pieces of read data sub-information and the N pieces of read response information to obtain converted N pieces of read data sub-information and converted N pieces of read response information;

[0271] The controller 12 sends the converted N pieces of read data sub-information and the converted N pieces of read response information to the AXI host 11 .

[0272] It can be understood that the AHB slave 13 receives N read operation information, that is, N read address sub-information, and the AHB slave 13 reads out N read data sub-information based on the N read address sub-information, and generates read response information corresponding to each data sub-information, that is, N read response information, and then sends the N read data sub-information and the N read response information to the controller 12.

[0273] After receiving the N pieces of read data sub-information and the N pieces of read response information, the controller 12 performs AXI protocol conversion on the N pieces of read data sub-information and the N pieces of read response information to obtain the converted N pieces of read data sub-information and the converted N pieces of read response information, and sends them to the AXI host 11, so that the AXI host 11 receives the converted N pieces of read data sub-information and the converted N pieces of read response information, and determines whether the read is successful based on the converted N pieces of read response information, thereby completing the data reading.

[0274] The converted N pieces of read data sub-information and the converted N pieces of read response information are the read results in the read-write results.

[0275] In order to enable the AXI host 11 to send a read / write instruction to the controller 12, in an optional embodiment, the AXI host 11 sends a read / write instruction to the controller 12, which may include:

[0276] The AXI host 11 sends a read / write request to the controller 12;

[0277] The controller 12 sends the read and write request to the AHB slave 13;

[0278] The AHB slave 13 sends a response message to the controller 12 for the read and write request;

[0279] The controller 12 sends a response message to the AXI host 11 for the read and write request;

[0280] When the response information to the read / write request indicates that the AHB slave 13 is not in the read state or the write state, the AXI host 11 sends a read / write instruction to the controller 12 .

[0281] Among them, the above-mentioned read and write requests may include: read requests and write requests. Correspondingly, the response messages of the read and write requests may include: response information of the read request and response information of the write request. It can be understood that when the AXI host 11 needs to read and write data to the AHB slave 13, it needs to first send a read and write request to the controller 12. The controller 12 is responsible for forwarding the read and write request to the AHB slave 13. The AHB slave 13 carries whether it is also in a read and write state in the response information of the read and write request and sends it to the controller 12. The controller 12 sends the response information of the read and write request to the AXI host 11. In this way, the AXI host 11 parses the response information of the read and write request to determine whether the AHB slave 13 is in a read and write state. If yes, it sends a read and write instruction to the controller 12. If not, it waits for the AHB slave 13 to be not in a read state or a write state before sending a read and write instruction to it.

[0282] In this way, it is ensured that the AXI host 11 can read and write data after issuing a read or write instruction.

[0283] In addition, after the AXI host 11 sends a read / write instruction to the controller 12, in order to ensure that the read / write is successful, in an optional embodiment, when the read / write address range corresponding to the read / write instruction crosses a preset boundary, the controller 12 splits the read / write instruction into N read / write sub-instructions, including:

[0284] When the read / write address range corresponding to the read / write instruction is within the preset read / write address range of the AHB slave and the read / write address range corresponding to the read / write instruction crosses a preset boundary, the controller 12 splits the read / write instruction into N read / write sub-instructions.

[0285] It can be understood that after receiving the read-write instruction, the controller 12 first determines the read-write address range corresponding to the read-write instruction, compares it with the preset read-write address range of the AHB slave 13, and determines whether the read-write address range corresponding to the read-write instruction crosses the read-write address range of the AHB slave. If so, and the read-write address range corresponding to the read-write instruction crosses the preset boundary, the read-write instruction is split into N read-write sub-instructions; if not, an error prompt message is returned to the AXI host 11; in this way, the success of this read and write is guaranteed.

[0286] The above-mentioned read-write state may include a read state or a write state.

[0287] The data reading and writing method in one or more of the above embodiments is described below with examples.

[0288] Figure 3 A schematic diagram of a structure of an optional SOC example provided in an embodiment of the present invention, such as Figure 3As shown, the SOC system 300 may include: an AXI host 31, an AXI to AHB controller 32 and an AHB slave 33, wherein the AXI to AHB controller 32 includes: an AXI slave interface module 321, an AHB host interface module 322, a control module 323, an address buffer module 324, a data buffer module 325, a read operation protocol conversion module 326 and a write operation protocol conversion module 327. The AXI slave interface module 321 is an interface for information exchange with an external AXI host 31; the AHB host interface module 322 is an interface for information exchange with an external AHB slave 33; the control module 323 is used for judging and splitting read and write operation commands (equivalent to the above-mentioned read and write instructions), controlling the work of the read operation protocol conversion module 326 and the write operation protocol conversion module 327, and communicating the entire controller workflow information flow; the address buffer module 324 is used for caching the read and write address information during the read and write operations; the data buffer module 325 is used for caching the read and write data information during the read and write operations; the read operation protocol conversion module 326 is used for converting the AXI protocol format read address information to the AHB protocol format during the read operation, and converting the AHB protocol format read data information and read response information to the AXI protocol format; the write operation protocol conversion module 327 is used for converting the AXI protocol format write address information to the AHB protocol format during the write operation, converting the AXI protocol format write data information to the AHB protocol format, and converting the AHB protocol format write response information to the AXI protocol format.

[0289] Based on the above Figure 3 , Figure 4 A flowchart of an example 1 of an optional data reading and writing method provided by an embodiment of the present invention is shown as follows: Figure 4 As shown, the data reading and writing methods may include:

[0290] S401: The AXI host 31 initiates a write operation request (equivalent to the above-mentioned read / write request), and the AXI to AHB controller 32 determines whether the AHB slave 33 is ready to receive the write operation. If yes, S402 is executed; if not, a busy signal of the AHB slave 33 is returned to the AXI host 31 (equivalent to the response information of the read / write request indicating that the AHB slave 33 is in the read / write state), and the AXI host 31 waits until the AHB slave 33 is ready to receive the write operation;

[0291] S402: The AXI host 31 initiates a write operation command (equivalent to the above-mentioned write instruction), and the AXI slave interface module 321 receives and latches the burst transfer write address information sent by the AXI host 31, the write address information including the write ID (AxID), the write first address (AxADDR), the write transfer length (AxLEN), and the write transfer width (AxSIZE), and executes S403;

[0292] S403: The control module 323 determines whether the range of the write operation address of the AXI host 31 (equivalent to the above-mentioned write address range) is all within the address range of the AHB slave 33. If so, S404 is executed; if not, a write address error signal is returned to the AXI host 31, the write operation ends, and returns to S401.

[0293] S404: The control module 323 determines whether the burst transfer write address range crosses the 1KB address boundary according to the burst transfer write start address, write transfer length, and write transfer width. The number of boundaries can be calculated using the above formula (2); wherein AxADDR is the write start address, the write transfer length Burst_Length = AxLEN+1 (where AxLEN is 8 bits wide, 0≤AxLEN≤255), and the write transfer width is 2 AxSIZE Number of bytes (AxSIZE is 3 bits wide, 0≤AxSIZE≤7), (AxADDR+AxLEN*2 AxSIZE ) is the write end address; if R=0, it means that the burst transfer write address range does not cross the 1KB boundary, and execute S405 and S406; if R>0, it means that the burst transfer write address range crosses the 1KB boundary, and execute S407 and S408.

[0294] S405: The control module 323 converts the format of the information in the write operation command, such as the write ID identifier (AxID), write start address (AxADDR), write transfer length (AxLEN) and write transfer width (AxSIZE) received in S402, i.e., converts it into a write ID identifier AxID0 = {AxID, SID} (AxID0 is composed of the write ID identifier AxID and the command number SID in the original write operation command, the bit width of SID is 6 bits, and SID = 0), a write start address AxADDR, a write transfer length AxLEN and a write transfer width AxSIZE (the write start address, write transfer length and write transfer width are the same as the original write operation command), and sends it to the address buffer module 324, and then sends a conversion start signal to the write operation protocol conversion module 327 to execute S409.

[0295] S406 : The AXI slave interface module 321 receives the burst transfer write data information sent by the AXI host 31 , and sends it to the data buffer module 325 , and executes S409 .

[0296] S407: The control module 323 splits the write operation command received in S402 into N write operation subcommands (equivalent to the above-mentioned write subcommands) (N=R+1, N is a positive integer and 2≤N≤33, the reason for setting the maximum value of N to 33 here is that the AXI protocol stipulates that the maximum burst transfer length is 256 and the maximum burst transfer width is 128 bytes, so theoretically the maximum value of a burst transfer data is 256*128 bytes=32KByte, which can cross 32 1KB boundaries at most, that is, it occupies a maximum of 33 KB storage area), the write operation subcommand includes write address subinformation, and the write address subinformation includes write ID identification, write first address, write transfer length, and write transfer width, and the calculation method is as follows:

[0297] ① The write ID identifier AxIDa={AxID,SID} of the a-th write operation subcommand, 1≤a≤N, AxIDa is composed of the write ID identifier AxID and the split subcommand number SID (equivalent to the above-mentioned identification field) in the write operation command, the bit width of SID is 6 bits, and SID=a.

[0298] ② The write first address of the write operation subcommand is as follows: the write first address of the first write operation subcommand is the write first address of the write operation command, i.e., AxADDR. The write first addresses of the second to Nth write operation subcommands are the starting addresses of the 1KB boundary obtained by using the above formula (3);

[0299] ③ The write end address of the write operation subcommand is as follows: The write end address of the write operation subcommand from 1 to N-1 is the 1KB boundary address (AxADDR / 2 10 +a)*2 10 -2 AxSIZE , a is a positive integer, and 1≤a≤N-1, the write end address of the Nth write operation subcommand is the write end address of the write operation command, that is, (AxADDR+AxLEN*2 AxSIZE );

[0300] ④ The write transfer length of the write operation subcommand is as follows: When N = 2, the write transfer length of the first write operation subcommand AxLEN1 =

[0301] (((AxADDR / 2 10 +1)*2 10 -2 AxSIZE )-AxADDR) / 2 AxSIZE , the write transfer length AxLEN of the Nth write operation subcommand N =((AxADDR+AxLEN*2 AxSIZE )-(AxADDR / 2 10 +N-1)*2 10 ) / 2 AxSIZE; When N>2, the write transfer length of the first write operation subcommand AxLEN1=(((AxADDR / 2 10 +1)*2 10 -2 AxSIZE )-AxADDR)

[0302] / 2 AxSIZE , the write transfer length of the 2nd to (N-1)th write operation subcommand AxLENa=2 10 / 2 AxSIZE , 2≤a≤N-1; the write transfer length parameter AxLEN of the Nth write operation subcommand N =((AxADDR+AxLEN*2 AxSIZE )-

[0303] (AxADDR / 2 10 +N-1)*2 10 ) / 2 AxSIZE .

[0304] ⑤The write transfer width of the write operation subcommand is the same as the write transfer width of the write operation command before splitting.

[0305] The control module 323 sends the address information such as the write ID, write start address, write transfer length, write transfer width, etc. of the split N write operation sub-commands to the address buffer module 324, and then sends a conversion start signal to the write operation protocol conversion module 327; execute S409.

[0306] S408: The control module 323 enables the AXI slave interface module 321 to receive the write data information of the write burst transmission of the AXI host 31 according to the splitting result of the N write operation sub-commands of the write operation command in S407, and splits it into N write data sub-information matching the N write operation sub-commands, and then sends it to the data buffer module 325 to execute S409.

[0307] S409: The write operation protocol conversion module 327 reads the write address command information of the address buffer module 324 and the write data information in the data buffer module 325, and converts them into AHB protocol format write operation information (equivalent to the above N pieces of write operation information), and then sends the AHB protocol format write operation information to the AHB host interface module 322. The value of the SID field in the write ID identifier of the write address subcommand is used to determine whether the entire write operation transaction is completely converted. When SID=0, the conversion of the AHB protocol format write operation information of the entire write operation transaction is completed after one conversion; when SID≠0, N conversions are required to complete the conversion of the AHB protocol format write operation information of the entire write operation transaction; and S410 is executed.

[0308] S410: The AHB host interface module 322 writes the AHB protocol format write operation information into the AHB slave 33, and receives the write response signal HRESP (equivalent to the above-mentioned N write response information) fed back by the AHB slave 33, and then sends the write response signal HRESP to the write operation protocol conversion module 327, and executes S411.

[0309] S411: After the write operation protocol conversion module 327 receives the write response signal HRESP sent by the AHB host interface module 322, it determines whether to receive the write response of the entire write operation according to the value of the SID field in the write ID identifier. When SID=0, receiving the write response signal HRESP once completes the write response receiving work of the entire write operation, converts the write response signal HRESP into write reply information in the AXI protocol format and sends it to the AXI slave interface module 321, and executes S412; when SID≠0, it is necessary to receive all write responses of the entire write operation, that is, receive N write response signals HRESP, and take the result after "logical AND" of the received N HRESPs as the write response signal of the entire write operation (the reason for taking "AND" for the N write responses here is that any failure of any of the N write operation sub-commands will cause the failure of the entire write operation), convert it into write reply information in the AXI protocol format and send it to the AXI slave interface module 321, and execute S412.

[0310] S412: The AXI slave interface module 321 sends the received write reply information (equivalent to the above-mentioned converted write success information or the converted write failure information) to the AXI host 31, and the write operation task initiated by the AXI host 31 is completed, the process ends, and returns to S401, waiting for the execution of the next round of write operation tasks.

[0311] Based on the above Figure 3 , Figure 5 A flowchart of an optional data reading and writing method according to an embodiment of the present invention is shown in FIG. Figure 5 As shown, the reading and writing methods of the above data may include:

[0312] S501: The AXI host 31 initiates a read operation request (equivalent to the read request in the above read-write request), and the AXI to AHB controller 32 determines whether the AHB slave 33 is ready to receive the read operation. If yes, S502 is executed; if not, a busy signal of the AHB slave 33 is returned to the AXI host 31 (equivalent to the response information of the read request indicating that the AHB slave 33 is in the read state or the write state), and the AXI host 31 waits until the AHB slave 33 is ready to receive the read operation.

[0313] S502: The AXI host 31 initiates a read operation command (equivalent to the above-mentioned read instruction), the AXI slave interface module 321 receives and latches the burst transfer read address information sent by the AXI host 31, the read address information includes a read ID identifier (ARID), a read first address (ARADDR), a read transfer length (ARLEN), and a read transfer width (ARSIZE), and executes S503.

[0314] S503: The control module 323 determines whether the range of the read operation address of the AXI host 31 (equivalent to the above-mentioned read address range) is all within the address range of the AHB slave 33. If so, S504 is executed; if not, a read address error signal is returned to the AXI host 31, the read operation ends, and returns to step S501.

[0315] S504: The control module 323 determines whether the burst transfer read address range crosses the 1KB address boundary according to the burst transfer read head address, read transfer length, and read transfer width. ARSIZE ) / 2 10 -ARADDR / 2 10 , ARADDR is the read first address, the read transfer length Burst_Length = ARLEN + 1 (where ARLEN is 8 bits wide, 0 ≤ ARLEN ≤ 255), and the read transfer width is 2 ARSIZE Bytes (ARSIZE is 3 bits wide, 0≤ARSIZE≤7), (ARADDR+ARLEN*2 ARSIZE ) is the read end address; if R=0, it means that the burst transfer read address range does not cross the 1KB boundary, and execute S505; if R>0, it means that the burst transfer read address range crosses the 1KB boundary; execute S506.

[0316] S505: The control module 323 converts the format of the information in the read operation command such as the read ID identifier (ARID), read start address (ARADDR), read transfer length (ARLEN) and read transfer width (ARSIZE) received in S502, that is, converts it into a read ID identifier ARID0 = {ARID, SID} (ARID0 is composed of the read ID identifier ARID and the command number SID in the original read operation command, the bit width of SID is 6 bits, and SID = 0), read start address ARADDR, read transfer length ARLEN and read transfer width ARSIZE (the read start address, read transfer length and read transfer width are the same as the original read operation command), and sends it to the address buffer module 324, and then sends a conversion start signal to the read operation protocol conversion module 326; execute S507.

[0317] S506: The control module 323 splits the read operation command received by S502 into N read operation subcommands (equivalent to the above-mentioned read subcommands) (N=R+1, N is a positive integer and 2≤N≤33, the reason for setting the maximum value of N to 33 here is that the AXI protocol stipulates that the maximum burst transfer length is 256 and the maximum burst transfer width is 128 bytes, so theoretically the maximum value of a burst transfer data is 256*128 bytes=32KByte, which can cross 32 1KB boundaries at most, that is, it occupies a maximum of 33 KB storage area), the read address sub-information in the read operation subcommand, the read address sub-information includes: read ID identification, read first address, read transfer length, read transfer width, calculated as follows:

[0318] ① The read ID identifier ARIDa={ARID,SID} of the a-th read operation subcommand, 1≤a≤N, ARIDa is composed of the read ID identifier ARID in the read operation command and the split subcommand number SID, the bit width of SID is 6 bits, and SID=a.

[0319] ② The read start address of the read operation subcommand is as follows: The read start address of the first read operation subcommand is the read start address of the read operation command, i.e. ARADDR. The read start address of the second to Nth read operation subcommands is the starting address of the 1KB boundary, i.e. (ARADDR / 2 10 +a-1)*2 10 , a is a positive integer, and 2≤a≤N;

[0320] ③ The read end address of the read operation subcommand is as follows: The read end address of the read operation subcommand from 1 to N-1 is the 1KB boundary address (ARADDR / 2 10 +a)*2 10 -2 ARSIZE , a is a positive integer, and 1≤a≤N-1, the read end address of the Nth read operation subcommand is (ARADDR+ARLEN*2 ARSIZE );

[0321] ④ The read transfer length of the read operation subcommand is as follows: When N = 2, the read transfer length of the first read operation subcommand ARLEN1 =

[0322] (((ARADDR / 2 10 +1)*2 10 -2 ARSIZE )-ARADDR) / 2 ARSIZE , the read transfer length ARLEN of the Nth read operation subcommand N =((ARADDR+ARLEN*2 ARSIZE )-(ARADDR / 2 10 +N-1)*2 10 ) / 2 AxSIZE; When N

[0323] >2, the read transfer length of the first read operation subcommand ARLEN1=(((ARADDR / 2 10 +1)*2 10 -2 ARSIZE )

[0324] -ARADDR) / 2 AxSIZE , the read transfer length of the 2nd to (N-1)th read operation subcommand ARLENa=2 10 / 2 ARSIZE , 2

[0325] ≤a≤N-1; the read transfer length of the Nth read operation subcommand ARLENN=((ARADDR+ARLEN*2 ARSIZE )

[0326] -(ARADDR / 2 10 +N-1)*2 10 ) / 2 ARSIZE .

[0327] ⑤The read transfer width of the read operation subcommand is the same as the read transfer width of the read operation command before splitting.

[0328] The control module 323 sends the address information such as the read ID, read start address, read transfer length, and read transfer width of the split N read operation subcommands to the address buffer module 324, and then sends a conversion start signal to the read operation protocol conversion module 326; execute S507.

[0329] S507: The read operation protocol conversion module 326 reads the read address command information of the address buffer module 324 and converts it into the AHB protocol format read operation information, and sends the AHB protocol format read operation information (equivalent to the above N read operation information) to the AHB host interface module 322. The read operation protocol conversion module 326 determines whether the entire read operation transaction is completely converted according to the value of the SID field in the read ID identifier of the read address command. When SID=0, completing one conversion completes the AHB protocol format read operation information conversion of the entire read operation transaction; when SID≠0, N conversions are required to complete the AHB protocol format read operation information conversion of the entire read operation transaction. Execute S508.

[0330] S508: The AHB host interface module 322 sends the AHB protocol format read operation information to the AHB slave 33, and receives the read data HRDATA (equivalent to the above-mentioned N read data sub-information) and the read response HRESP (equivalent to the above-mentioned N read response information) returned by the AHB slave 33, and then sends the read data HRDATA and the read response HRESP to the data buffer module 325, and executes S509.

[0331] S509: The read operation protocol conversion module 326 reads the read data HRDATA and the read response HRESP of the data buffer module 325, and converts them into AXI protocol format read data information, and then sends the AXI protocol format read data information to the AXI slave interface module 321. The read data and read response reading of the entire read operation transaction are judged according to the value of the SID field in the read ID identifier of the read address command. When SID=0, the read data conversion corresponding to one read ID identifier is completed, that is, the AXI protocol format read data conversion of the entire read operation transaction is completed; when SID≠0, it is necessary to read the AHB format read data corresponding to all N read ID identifiers and aggregate and convert them into one AXI protocol format read data to complete the AXI protocol format read data conversion of the entire read operation transaction (here, N AHB format read data are aggregated into one AXI format read data, which corresponds to the splitting of the read operation command in S506); execute S510.

[0332] S510: The AXI slave interface module 321 sends the received AXI read data information (equivalent to the N read data sub-information after the above conversion) to the AXI host 31, and the read operation task initiated by the AXI host 31 is completed. The process ends and returns to S501 to wait for the execution of the next round of read operation tasks.

[0333] This example provides an AXI to AHB controller and a read / write operation working method, and provides a method for splitting read / write address commands when accessing across 1KB address boundaries, and a method for splitting and aggregating read / write data and read / write responses. Compared with the problem that AXI to AHB cannot support access across 1KB address boundaries and can only meet access to continuous addresses less than or equal to 1KB, resulting in reduced AXI throughput, this example can enable the AXI bus host device to continuously access the AHB bus slave device in a continuous address increment burst type across the 1KB boundary, effectively solving the problem of low data throughput and inability to give full play to the high throughput advantage of the AXI protocol when the AXI host continuously accesses the AHB bus slave device in a continuous address increment burst type, and effectively improving the throughput and transmission efficiency of AXI to AHB. At the same time, the protocol conversion splitting method of this example can also break through the limitation of the AXI protocol address access 4KB boundary, and the single AXI burst transmission during continuous address increment burst transmission can reach a maximum of 32KB, greatly improving the transmission efficiency of AXI to AHB, and has strong practical value.

[0334] An embodiment of the present invention provides a data reading and writing method. When it is determined that the read and write address range crosses a preset boundary, the read and write instructions are split and converted, so that the obtained N read and write operation information are information that can be processed by an AHB slave, so that the read and write instructions that cross the preset boundary can be applicable to the requirements of the AHB slave, and based on the N operation information, the AHB slave is sent to the AHB slave to return the read and write results to the AXI host, so that the AXI to AHB conversion can be applicable to the situation of crossing the preset boundary, thereby improving the applicability and further improving the data throughput.

[0335] The reading method in the above data reading and writing method is described below with reference to each device side deployed in the SOC.

[0336] First, the data reading method is described from the controller side.

[0337] An embodiment of the present invention provides a data reading method, which is applied in a controller. Figure 6 A schematic diagram of an optional data reading method provided in an embodiment of the present invention Figure 1 ,like Figure 6 As shown, the data reading method may include:

[0338] S601: receiving a read instruction from the AXI host;

[0339] S602: When the read address range corresponding to the read instruction crosses a preset boundary, split the read instruction into N read sub-instructions;

[0340] The preset boundary is the address of bytes that are positive integer multiples of the preset number of bytes; N is the number of read address ranges that cross the preset boundary plus 1;

[0341] S603: Perform AHB protocol conversion on the N read sub-instructions to obtain N read operation information;

[0342] S604: Send the N pieces of read operation information to the AHB slave to return the read result to the AXI master.

[0343] In an optional embodiment, the above method further includes:

[0344] Based on the read instruction, determining the number of times the read address range crosses a preset boundary;

[0345] When the number is greater than 0, it is determined that the read address range crosses the preset boundary;

[0346] When the number is equal to 0, it is determined that the read address range does not cross the preset boundary.

[0347] In an optional embodiment, the above method further includes:

[0348] When the read address range corresponding to the read instruction does not cross the preset boundary, the read ID and the encoding field 0 in the read address information in the read instruction are re-determined as the ID in the read address information to obtain the read instruction again;

[0349] Perform AHB protocol conversion on the read instruction to obtain a read operation message;

[0350] Send a read operation message to the AHB slave to return the read result to the AXI master.

[0351] In an optional embodiment, determining the number of preset boundaries that the read address range crosses based on the read instruction includes:

[0352] Determine the read end address based on the read start address, the read transfer length and the read transfer width in the read instruction;

[0353] The read end address and the read start address are respectively shifted right by a preset number of bits, and the difference between the shifted read end address and the shifted read start address is calculated; wherein the preset number of bits is equal to the minimum bit width corresponding to the preset number of bytes;

[0354] The difference is determined as the number of times the read address range crosses the preset boundary.

[0355] In an optional embodiment, S602 includes:

[0356] When the read address range corresponding to the read instruction crosses a preset boundary, the read address information in the read instruction is split into N read sub-instructions; wherein the N read sub-instructions include: N read address sub-information;

[0357] Accordingly, S603 includes:

[0358] Perform AHB protocol conversion on N pieces of read address sub-information to obtain N pieces of read operation information.

[0359] In an optional embodiment, when the read address range corresponding to the read instruction crosses a preset boundary, the read address information in the read instruction is split into N read sub-instructions, including:

[0360] When the read address range corresponding to the read instruction crosses a preset boundary, the read ID, the read first address, the read transfer length and the read transfer width in the read address information are respectively split into N pieces of read address sub-information.

[0361] In an optional embodiment, when the read address range corresponding to the read instruction crosses a preset boundary, the read ID, the read first address, the read transfer length, and the read transfer width in the read address information are respectively split into N pieces of read address sub-information, including:

[0362] When the read address range corresponding to the read instruction crosses the preset boundary, the read ID and the identification field a in the read address information are determined as the read ID of the a-th read address sub-information; wherein a is a positive integer greater than or equal to 1 and less than or equal to N;

[0363] When a is equal to 1, the read start address of the read address information is determined as the read start address of the a-th read address sub-information; when a is greater than or equal to 2 and less than or equal to N, the N-1 boundary addresses starting from the read start address of the read address information are determined, and the j-th boundary address among the N-1 boundary addresses is determined as the read start address of the a-th read address sub-information; wherein j is equal to a-1;

[0364] When a is greater than or equal to 1 and less than or equal to N-1, determine the N-1 boundary addresses starting from the read start address of the read address information, and determine the jth boundary address among the N-1 boundary addresses as the read end address of the ath read address sub-information; when a is equal to N, determine the read end address of the read address information as the read end address of the ath read address sub-information;

[0365] When N is equal to 2, the read transfer length in the a-th read address sub-information is determined by using the read end address of the a-th read address sub-information and the read start address of the a-th read address sub-information; when N is greater than 2, the read transfer length in the 1st read address sub-information is determined by using the read end address of the 1st read address sub-information and the read start address of the 1st read address sub-information; the preset read transfer length is determined as the read transfer length in the 2nd to N-1st read address sub-information; the read transfer length in the N-th read address sub-information is determined by using the read end address of the N-th read address sub-information and the read start address of the N-th read address sub-information; wherein the preset read transfer length is obtained by right-shifting the maximum number of the preset number of bytes by the number of digits of the write transfer width;

[0366] The read transfer width of the read address information is determined as the read transfer width in the a-th read address sub-information.

[0367] In an optional embodiment, S605 includes:

[0368] Send N read operation messages to the AHB slave to obtain N read data sub-messages and N read response messages of the N read data sub-messages;

[0369] Receive N read data sub-information and N read response information of N read data sub-information from the AHB slave;

[0370] Performing AXI protocol conversion on the N pieces of read data sub-information and the N pieces of read response information to obtain converted N pieces of read data sub-information and converted N pieces of read response information; wherein the read result is the converted N pieces of read data sub-information and the converted N pieces of read response information;

[0371] The converted N read data sub-information and the converted N read response information are sent to the AXI host.

[0372] In an optional embodiment, S601 includes:

[0373] Receive a read request from the AXI host;

[0374] Send a read request to the AHB slave;

[0375] Receive the response information for the read request from the AHB slave, and send the response information for the read request to the AXI master;

[0376] When the response information to the read request indicates that the AHB slave is in a read state or a write state, a read instruction from the AXI master is received.

[0377] In an optional embodiment, when the read address range corresponding to the read instruction crosses a preset boundary, the read instruction is split into N read sub-instructions, including:

[0378] When the read address range corresponding to the read instruction is within the preset read address range of the AHB slave and the read address range corresponding to the read instruction crosses a preset boundary, the read instruction is split into N read sub-instructions.

[0379] In an optional embodiment, the method further includes:

[0380] Receive write instructions from the AXI host;

[0381] When the write address range corresponding to the write instruction crosses a preset boundary, the write instruction is split into N write sub-instructions; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; and N is the number of the write address range crossing the preset boundary plus 1;

[0382] Perform AHB protocol conversion on N write sub-instructions to obtain N write operation information;

[0383] Send N write operation information to the AHB slave to return the write result to the AXI master.

[0384] In an optional embodiment, when the write address range corresponding to the write instruction crosses a preset boundary, the write instruction is split into N write sub-instructions, including:

[0385] When the write address range corresponding to the write instruction crosses a preset boundary, the write address information in the write instruction and the write data information in the write instruction are respectively split into N write sub-instructions; wherein the N write sub-instructions include: N write address sub-information and N write data sub-information;

[0386] Accordingly, the N write sub-instructions are converted into the AHB protocol to obtain N write operation information, including:

[0387] Perform AHB protocol conversion on N pieces of write address sub-information and N pieces of write data sub-information respectively to obtain N pieces of write operation information; wherein the N pieces of write operation information include: the converted N pieces of write address sub-information and the converted N pieces of write data sub-information; and the converted N pieces of write address sub-information correspond one-to-one to the converted N pieces of write data sub-information.

[0388] In an optional embodiment, when the write address range corresponding to the write instruction crosses a preset boundary, the write address information in the write instruction and the write data information in the write instruction are respectively split into N write sub-instructions, including:

[0389] When the write address range corresponding to the write instruction crosses the preset boundary, the write ID, the write first address, the write transfer length and the write transfer width in the write address information are split into N pieces of write address sub-information respectively;

[0390] Based on the N pieces of write address sub-information, the write data information is split into write data sub-information corresponding to each piece of write address information to obtain N pieces of write data sub-information.

[0391] In an optional embodiment, N pieces of write operation information are sent to the AHB slave to return the write result to the AXI master, including:

[0392] Send N write operation information to the AHB slave to obtain N write response information of the N write operation information;

[0393] Receive N write response messages from the AHB slave for N write operation messages;

[0394] When the encoding fields in the N write response messages include all integers from 1 to N, and the N write response messages all indicate that the write is successful, generate write success information, perform AXI protocol conversion on the write success information, and send the converted write success information to the AXI host;

[0395] When the encoding fields in the N write response messages do not include all integers from 1 to N, and / or at least one of the N write response messages indicates a write failure, generate write failure information, perform AXI protocol conversion on the write failure information, and send the converted write failure information to the AXI host;

[0396] The write result includes: converted write success information or converted write failure information.

[0397] Next, the data reading method is described based on the AXI host side.

[0398] An embodiment of the present invention provides a data reading method, which is applied to an AXI host. Figure 7 A schematic diagram of an optional data reading method provided in an embodiment of the present invention Figure 2 ,like Figure 7 As shown, the data reading method may include:

[0399] S701: Send a read instruction to the controller;

[0400] S702: Receive a read result of a read instruction from a controller.

[0401] Among them, the read instruction is used for the controller. When the read address range corresponding to the read instruction crosses the preset boundary, the read instruction is split into N read sub-instructions and AHB protocol conversion is performed to obtain N read operation information and send them to the AHB slave. The read result of the read instruction is obtained through the AHB slave and the controller; wherein the preset boundary is the address of bytes that are positive integer multiples of the preset number of bytes; N is the number of read address ranges that cross the preset boundary plus 1.

[0402] In an optional embodiment, the read result is: N converted read data sub-information and N converted read response information; the converted N read data sub-information and the converted N read response information are obtained by the controller based on N read data sub-information and N read response information from the AHB slave.

[0403] Again, the data reading method is described using the AHB slave side.

[0404] The embodiment of the present invention provides a data reading method, which is applied to an AHB slave. Figure 8 A schematic diagram of an optional data reading method provided in an embodiment of the present invention Figure 3 ,like Figure 8 As shown, the data reading method may include:

[0405] S801: Receive N pieces of read operation information from the controller;

[0406] The N pieces of read operation information are obtained by the controller splitting the read instruction from the AXI host into N read sub-instructions and performing AHB protocol conversion on the N read sub-instructions when the read address range corresponding to the read instruction from the AXI host crosses the preset boundary; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; and N is the number of times the read address range crosses the preset boundary plus 1;

[0407] S802: Based on the N pieces of read operation information, read is performed to send the read result to the AXI host through the controller.

[0408] In an optional embodiment, the above method further includes:

[0409] Based on the N pieces of read address sub-information, N pieces of read data sub-information are obtained, and N pieces of read response information corresponding to the N pieces of read data sub-information are generated;

[0410] N pieces of read data sub-information and N pieces of read response information are sent to the controller, so that the controller obtains a read result based on the N pieces of read data sub-information and the N pieces of read response information; wherein the read result is: the converted N pieces of read data sub-information and the converted N pieces of read response information.

[0411] Finally, the data reading method is described from the perspective of the SOC.

[0412] An embodiment of the present invention provides a data reading method, which is applied in a SOC. Fig. 9 A schematic diagram of an optional data reading method provided in an embodiment of the present invention Figure 4 ,like Fig. 9 As shown, the data reading method may include:

[0413] S901: The AXI host sends a read command to the controller;

[0414] S902: When the read address range corresponding to the read instruction crosses a preset boundary, the controller splits the read instruction into N read sub-instructions, performs AHB protocol conversion on the N read sub-instructions, and obtains N pieces of read operation information;

[0415] The preset boundary is the address of bytes that are positive integer multiples of the preset number of bytes; N is the number of read address ranges that cross the preset boundary plus 1;

[0416] S903: Send N pieces of read operation information to the AHB slave;

[0417] S904: The AHB slave performs read-in based on the N pieces of read operation information to send the read result to the AXI host through the controller.

[0418] Based on the same inventive concept as the above-mentioned embodiment, an embodiment of the present invention provides a data reading device, which is arranged in a controller. Fig.10 A schematic diagram of an optional data reading device provided in an embodiment of the present invention Figure 1 ,like Fig.10 As shown, the data reading device comprises:

[0419] A first receiving module 101 is used to receive a read instruction from an AXI host;

[0420] The splitting module 102 is used to split the read instruction into N read sub-instructions when the read address range corresponding to the read instruction crosses a preset boundary; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; and N is the number of read address ranges that cross the preset boundaries plus 1;

[0421] The conversion module 103 is used to perform AHB protocol conversion on N read sub-instructions to obtain N read operation information;

[0422] The first sending module 104 is used to send N pieces of read operation information to the AHB slave to return the read result to the AXI master.

[0423] In an optional embodiment, the device is also used for:

[0424] Based on the read instruction, determining the number of times the read address range crosses a preset boundary;

[0425] When the number is greater than 0, it is determined that the read address range crosses the preset boundary;

[0426] When the number is equal to 0, it is determined that the read address range does not cross the preset boundary.

[0427] In an optional embodiment, the device is also used for:

[0428] When the read address range corresponding to the read instruction does not cross the preset boundary, the read ID and the encoding field 0 in the read address information in the read instruction are re-determined as the read ID in the read address information to obtain the read instruction again;

[0429] Perform AHB protocol conversion on the read instruction to obtain a read operation message;

[0430] Send a read operation message to the AHB slave to return the read result to the AXI master.

[0431] In an optional embodiment, the device determines the number of times the read address range crosses a preset boundary based on the read instruction, including:

[0432] Determine the read end address based on the read start address, the read transfer length and the read transfer width in the read instruction;

[0433] The read end address and the read start address are respectively shifted right by a preset number of bits, and the difference between the shifted read end address and the shifted read start address is calculated; wherein the preset number of bits is equal to the minimum bit width corresponding to the preset number of bytes;

[0434] The difference is determined as the number of times the read address range crosses the preset boundary.

[0435] In an optional embodiment, the splitting module 102 is specifically configured to:

[0436] When the read address range corresponding to the read instruction crosses a preset boundary, the read address information in the read instruction is split into N read sub-instructions; wherein the N read sub-instructions include: N read address sub-information;

[0437] Accordingly, the conversion module 103 is specifically configured to:

[0438] Perform AHB protocol conversion on N pieces of read address sub-information to obtain N pieces of read operation information.

[0439] In an optional embodiment, when the read address range corresponding to the read instruction crosses a preset boundary, the conversion module 103 splits the read address information in the read instruction into N read sub-instructions, including:

[0440] When the read address range corresponding to the read instruction crosses a preset boundary, the read ID, the read first address, the read transfer length and the read transfer width in the read address information are respectively split into N pieces of read address sub-information.

[0441] In an optional embodiment, when the read address range corresponding to the read instruction crosses a preset boundary, the conversion module 103 splits the read ID, the read first address, the read transfer length, and the read transfer width in the read address information into N pieces of read address sub-information, including:

[0442] When the read address range corresponding to the read instruction crosses the preset boundary, the read ID and the identification field a in the read address information are determined as the read ID of the a-th read address sub-information; wherein a is a positive integer greater than or equal to 1 and less than or equal to N;

[0443] When a is equal to 1, the read start address of the read address information is determined as the read start address of the a-th read address sub-information; when a is greater than or equal to 2 and less than or equal to N, the N-1 boundary addresses starting from the read start address of the read address information are determined, and the j-th boundary address among the N-1 boundary addresses is determined as the read start address of the a-th read address sub-information; wherein j is equal to a-1;

[0444] When a is greater than or equal to 1 and less than or equal to N-1, determine the N-1 boundary addresses starting from the read start address of the read address information, and determine the jth boundary address among the N-1 boundary addresses as the read end address of the ath read address sub-information; when a is equal to N, determine the read end address of the read address information as the read end address of the ath read address sub-information;

[0445] When N is equal to 2, the read transfer length in the a-th read address sub-information is determined by using the read end address of the a-th read address sub-information and the read start address of the a-th read address sub-information; when N is greater than 2, the read transfer length in the 1st read address sub-information is determined by using the read end address of the 1st read address sub-information and the read start address of the 1st read address sub-information; the preset read transfer length is determined as the read transfer length in the 2nd to N-1st read address sub-information; the read transfer length in the N-th read address sub-information is determined by using the read end address of the N-th read address sub-information and the read start address of the N-th read address sub-information; wherein the preset read transfer length is obtained by right-shifting the maximum number of the preset number of bytes by the number of digits of the read transfer width;

[0446] The read transfer width of the read address information is determined as the read transfer width in the a-th read address sub-information.

[0447] In an optional embodiment, the first sending module 104 is specifically configured to:

[0448] Send N read operation messages to the AHB slave to obtain N read data sub-messages and N read response messages of the N read data sub-messages;

[0449] Receive N read data sub-information and N read response information of N read data sub-information from the AHB slave;

[0450] Performing AXI protocol conversion on the N pieces of read data sub-information and the N pieces of read response information to obtain converted N pieces of read data sub-information and converted N pieces of read response information; wherein the read result is the converted N pieces of read data sub-information and the converted N pieces of read response information;

[0451] The converted N read data sub-information and the converted N read response information are sent to the AXI host.

[0452] In an optional embodiment, the first receiving module 101 is specifically configured to:

[0453] Receive a read request from the AXI host;

[0454] Send a read request to the AHB slave;

[0455] Receive the response information for the read request from the AHB slave, and send the response information for the read request to the AXI master;

[0456] When the response information to the read request indicates that the AHB slave is in a read state or a write state, a read instruction from the AXI master is received.

[0457] In an optional embodiment, the splitting module 102 is specifically configured to:

[0458] When the read address range corresponding to the read instruction is within the preset read address range of the AHB slave and the read address range corresponding to the read instruction crosses a preset boundary, the read instruction is split into N read sub-instructions.

[0459] In an optional embodiment, the device is also used for:

[0460] Receive write instructions from the AXI host;

[0461] When the write address range corresponding to the write instruction crosses a preset boundary, the write instruction is split into N write sub-instructions; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; and N is the number of the write address range crossing the preset boundary plus 1;

[0462] Perform AHB protocol conversion on N write sub-instructions to obtain N write operation information;

[0463] Send N write operation information to the AHB slave to return the write result to the AXI master.

[0464] In an optional embodiment, when the write address range corresponding to the write instruction crosses a preset boundary, the device splits the write instruction into N write sub-instructions, including:

[0465] When the write address range corresponding to the write instruction crosses a preset boundary, the write address information in the write instruction and the write data information in the write instruction are respectively split into N write sub-instructions; wherein the N write sub-instructions include: N write address sub-information and N write data sub-information;

[0466] Accordingly, the device performs AHB protocol conversion on N write sub-instructions to obtain N write operation information, including:

[0467] Perform AHB protocol conversion on N pieces of write address sub-information and N pieces of write data sub-information respectively to obtain N pieces of write operation information; wherein the N pieces of write operation information include: the converted N pieces of write address sub-information and the converted N pieces of write data sub-information; and the converted N pieces of write address sub-information correspond one-to-one to the converted N pieces of write data sub-information.

[0468] In an optional embodiment, when the write address range corresponding to the write instruction crosses a preset boundary, the device splits the write address information in the write instruction and the write data information in the write instruction into N write sub-instructions respectively, including:

[0469] When the write address range corresponding to the write instruction crosses the preset boundary, the write ID, the write first address, the write transfer length and the write transfer width in the write address information are split into N pieces of write address sub-information respectively;

[0470] Based on the N pieces of write address sub-information, the write data information is split into write data sub-information corresponding to each piece of write address information to obtain N pieces of write data sub-information.

[0471] In an optional embodiment, the device sends N pieces of write operation information to the AHB slave to return a write result to the AXI host, including:

[0472] Send N write operation information to the AHB slave to obtain N write response information of the N write operation information;

[0473] Receive N write response messages from the AHB slave for N write operation messages;

[0474] When the encoding fields in the N write response messages include all integers from 1 to N, and the N write response messages all indicate that the write is successful, generate write success information, perform AXI protocol conversion on the write success information, and send the converted write success information to the AXI host;

[0475] When the encoding fields in the N write response messages do not include all integers from 1 to N, and / or at least one of the N write response messages indicates a write failure, generate write failure information, perform AXI protocol conversion on the write failure information, and send the converted write failure information to the AXI host;

[0476] The write result includes: converted write success information or converted write failure information.

[0477] In practical applications, the above-mentioned first receiving module 101, splitting module 102, conversion module 103 and first sending module 104 can be implemented by a processor located on the data reading device, specifically a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP) or a field programmable gate array (FPGA).

[0478] An embodiment of the present invention provides a data reading device, which is arranged in an AXI host. Fig.11 A schematic diagram of an optional data reading device provided in an embodiment of the present invention Figure 2 ,like Fig.11 As shown, the data reading device comprises:

[0479] A second sending module 111, used to send a read instruction to the controller;

[0480] A second receiving module 112, configured to receive a read result of a read instruction from a controller;

[0481] Among them, the read instruction is used for the controller. When the read address range corresponding to the read instruction crosses the preset boundary, the read instruction is split into N read sub-instructions and AHB protocol conversion is performed to obtain N read operation information and send them to the AHB slave. The read result of the read instruction is obtained through the AHB slave and the controller; wherein the preset boundary is the address of bytes that are positive integer multiples of the preset number of bytes; N is the number of read address ranges that cross the preset boundary plus 1.

[0482] In an optional embodiment, the read result is: N converted read data sub-information and N converted read response information; the converted N read data sub-information and the converted N read response information are obtained by the controller based on N read data sub-information and N read response information from the AHB slave.

[0483] In practical applications, the second sending module 111 and the second receiving module 112 may be implemented by a processor located on the data reading device, specifically a CPU, an MPU, a DSP or an FPGA.

[0484] The embodiment of the present invention provides a data reading device, which is applied to an AHB slave. Fig.12 A schematic diagram of an optional data reading device provided in an embodiment of the present invention Figure 3 ,like Fig.12 As shown, the data reading device comprises:

[0485] A third receiving module 121, configured to receive N pieces of read operation information from the controller;

[0486] The N pieces of read operation information are obtained by the controller splitting the read instruction from the AXI host into N read sub-instructions and performing AHB protocol conversion on the N read sub-instructions when the read address range corresponding to the read instruction from the AXI host crosses a preset boundary;

[0487] The preset boundary is the address of bytes that are positive integer multiples of the preset number of bytes; N is the number of read address ranges that cross the preset boundary plus 1;

[0488] The reading module 122 is used to read data based on N pieces of read operation information, so as to send the reading result to the AXI host through the controller.

[0489] In an optional embodiment, the above device is also used for:

[0490] Based on the N pieces of read address sub-information, N pieces of read data sub-information are obtained, and N pieces of read response information corresponding to the N pieces of read data sub-information are generated;

[0491] N pieces of read data sub-information and N pieces of read response information are sent to the controller, so that the controller obtains a read result based on the N pieces of read data sub-information and the N pieces of read response information; wherein the read result is: the converted N pieces of read data sub-information and the converted N pieces of read response information.

[0492] An embodiment of the present invention provides a SOC, such as Figure 1 As shown, the SOC 100 includes: an AXI host 11, a controller 12 and an AHB slave 13; wherein,

[0493] AXI host 11, used to send a read instruction to the controller 12;

[0494] The controller 12 is used for splitting the read instruction into N read sub-instructions when the read address range corresponding to the read instruction crosses a preset boundary, performing AHB protocol conversion on the N read sub-instructions to obtain N read operation information, and sending the N read operation information to the AHB slave; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; and N is the number of the read address range that crosses the preset boundary plus 1;

[0495] The AHB slave 13 is used for reading based on N pieces of read operation information, and sending the reading result to the AXI host through the controller.

[0496] Fig.13 A schematic diagram of the structure of an optional controller provided in an embodiment of the present invention, such as Fig.13As shown, an embodiment of the present invention provides a controller 1300, including:

[0497] A processor 131 and a storage medium 132 storing executable instructions of the processor 131, wherein the storage medium 132 relies on the processor 131 to perform operations through a communication bus 133, and when the instructions are executed by the processor 131, the data reading method described in one or more of the above embodiments is executed.

[0498] It should be noted that in actual application, the various components in the terminal are coupled together through the communication bus 133. It is understandable that the communication bus 143 is used to realize the connection and communication between these components. In addition to the data bus, the communication bus 133 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Fig.13 Various buses are labeled as communication buses 133.

[0499] Fig.14 A schematic diagram of the structure of an optional AXI host provided by an embodiment of the present invention, such as Fig.14 As shown, an embodiment of the present invention provides an AXI host 1400, including:

[0500] A processor 141 and a storage medium 142 storing executable instructions of the processor 141. The storage medium 142 relies on the processor 141 to perform operations through a communication bus 143. When the instructions are executed by the processor 141, the data reading method described in one or more of the above embodiments is executed.

[0501] It should be noted that in actual application, the various components in the terminal are coupled together through the communication bus 143. It is understandable that the communication bus 143 is used to realize the connection and communication between these components. In addition to the data bus, the communication bus 143 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Fig.14 Various buses are labeled as communication buses 143.

[0502] Fig.15 A schematic diagram of the structure of an optional AHB slave provided by an embodiment of the present invention, such as Fig.15 As shown, an embodiment of the present invention provides an AHB slave 1500, including:

[0503] A processor 151 and a storage medium 152 storing executable instructions of the processor 151. The storage medium 152 relies on the processor 151 to perform operations through a communication bus 153. When the instructions are executed by the processor 151, the data reading method described in one or more of the above embodiments is executed.

[0504] It should be noted that, in actual application, the various components in the terminal are coupled together via the communication bus 153. It is understandable that the communication bus 153 is used to realize the connection and communication between these components. In addition to the data bus, the communication bus 153 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Fig.15 Various buses are labeled as communication buses 153.

[0505] An embodiment of the present invention provides a computer storage medium storing executable instructions. When the executable instructions are executed by one or more processors, the processors execute the data reading method described in one or more of the above embodiments.

[0506] Among them, the computer-readable storage medium can be a ferromagnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disk, or a compact disc read-only memory (CD-ROM) and other memories.

[0507] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0508] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0509] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0510] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0511] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention.

Claims

1. A data reading method, characterized in that: The method is applied in a controller, comprising: Receive read command from AXI host; When the read address range corresponding to the read instruction crosses a preset boundary, the read instruction is split into N read sub-instructions; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; and N is the number of preset boundaries that the read address range crosses plus 1; Performing AHB protocol conversion on the N read sub-instructions to obtain N pieces of read operation information; The N pieces of read operation information are sent to the AHB slave to return the read result to the AXI host.

2. The method according to claim 1, characterized in that The method further comprises: Based on the read instruction, determining the number of preset boundaries that the read address range crosses; When the number is greater than 0, determining that the read address range crosses a preset boundary; When the number is equal to 0, it is determined that the read address range does not cross a preset boundary.

3. The method according to claim 2, characterized in that The determining, based on the read instruction, the number of preset boundaries crossed by the read address range includes: Determine a read end address based on a read start address, a read transfer length, and a read transfer width in the read instruction; The read end address and the read start address are respectively right-shifted by a preset number of bits, and a difference between the shifted read end address and the shifted read start address is calculated; wherein the preset number of bits is equal to the minimum bit width corresponding to a preset number of bytes; The difference is determined as the number of preset boundaries crossed by the read address range.

4. The method according to any one of claims 1 to 3, characterized in that: When the read address range corresponding to the read instruction crosses a preset boundary, splitting the read instruction into N read sub-instructions includes: When the read address range corresponding to the read instruction crosses a preset boundary, the read address information in the read instruction is split into N read sub-instructions; wherein the N read sub-instructions include: N read address sub-information; Accordingly, performing AHB protocol conversion on the N read sub-instructions to obtain N pieces of read operation information includes: Perform AHB protocol conversion on the N pieces of read address sub-information to obtain N pieces of read operation information.

5. The method according to claim 4, characterized in that When the read address range corresponding to the read instruction crosses a preset boundary, splitting the read address information in the read instruction into N read sub-instructions includes: When the read address range corresponding to the read instruction crosses a preset boundary, the read ID, the read head address, the read transfer length and the read transfer width in the read address information are respectively split into N pieces of read address sub-information.

6. The method according to claim 5, characterized in that When the read address range corresponding to the read instruction crosses a preset boundary, the read ID, the read first address, the read transfer length and the read transfer width in the read address information are respectively split into N pieces of read address sub-information, including: When the read address range corresponding to the read instruction crosses a preset boundary, the read ID and the coding field a in the read address information are determined as the read ID of the a-th read address sub-information; wherein a is a positive integer greater than or equal to 1 and less than or equal to N; When a is equal to 1, the read start address of the read address information is determined as the read start address of the a-th read address sub-information; when a is greater than or equal to 2 and less than or equal to N, the N-1 boundary addresses starting from the read start address of the read address information are determined, and the j-th boundary address among the N-1 boundary addresses is determined as the read start address of the a-th read address sub-information; wherein j is equal to a-1; When a is greater than or equal to 1 and less than or equal to N-1, determine N-1 boundary addresses starting from the read start address of the read address information, and determine the jth boundary address among the N-1 boundary addresses as the read end address of the ath read address sub-information; when a is equal to N, determine the read end address of the read address information as the read end address of the ath read address sub-information; When N is equal to 2, the read transfer length in the a-th read address sub-information is determined by using the read end address of the a-th read address sub-information and the read start address of the a-th read address sub-information; when N is greater than 2, the read end address of the 1st read address sub-information and the read start address of the 1st read address sub-information are used to determine the read transfer length in the 1st read address sub-information; the preset read transfer length is determined as the read transfer length in the 2nd to N-1st read address sub-information; the read end address of the N-th read address sub-information and the read start address of the N-th read address sub-information are used to determine the read transfer length in the N-th read address sub-information; wherein the preset read transfer length is obtained by right-shifting the maximum number of the preset number of bytes by the number of digits of the read transfer width; The read transmission width of the read address information is determined as the read transmission width in the a-th read address sub-information.

7. The method according to any one of claims 1 to 3, characterized in that: The sending the N pieces of read operation information to the AHB slave to return the read result to the AXI host includes: Send the N pieces of read operation information to the AHB slave to obtain N pieces of read data sub-information and N pieces of read response information of the N pieces of read data sub-information; receiving the N pieces of read data sub-information and N pieces of read response information of the N pieces of read data sub-information from the AHB slave; Performing AXI protocol conversion on the N pieces of read data sub-information and the N pieces of read response information to obtain converted N pieces of read data sub-information and converted N pieces of read response information; wherein the read result is the converted N pieces of read data sub-information and the converted N pieces of read response information; The converted N pieces of read data sub-information and the converted N pieces of read response information are sent to the AXI host.

8. The method according to any one of claims 1 to 3, characterized in that: The receiving of a read instruction from an AXI host comprises: receiving a read request from the AXI host; Sending the read request to the AHB slave; receiving a response message for the read request from the AHB slave, and sending the response message for the read request to the AXI host; When the response information to the read request indicates that the AHB slave is in a read state or a write state, a read instruction from the AXI host is received.

9. The method according to any one of claims 1 to 3, characterized in that: When the read address range corresponding to the read instruction crosses a preset boundary, splitting the read instruction into N read sub-instructions includes: When the read address range corresponding to the read instruction is within the preset read address range of the AHB slave, and the read address range corresponding to the read instruction crosses a preset boundary, the read instruction is split into N read sub-instructions.

10. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: Receive write instructions from the AXI host; When the write address range corresponding to the write instruction crosses a preset boundary, the write instruction is split into N write sub-instructions; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; and N is the number of preset boundaries that the write address range crosses plus 1; Performing AHB protocol conversion on the N write sub-instructions to obtain N write operation information; The N pieces of write operation information are sent to the AHB slave to return the write result to the AXI host.

11. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: When the read address range corresponding to the read instruction does not cross the preset boundary, the read ID and the encoding field 0 in the read address information in the read instruction are re-determined as the read ID in the read address information to obtain the read instruction again; Performing AHB protocol conversion on the read instruction to obtain a piece of read operation information; The piece of read operation information is sent to the AHB slave to return the read result to the AXI host.

12. A data reading method, characterized in that: Applied to AXI host, including: Send a read command to the controller; receiving a read result of the read instruction from the controller; Wherein, when the read address range corresponding to the read instruction crosses a preset boundary, the controller splits the read instruction into N read sub-instructions and performs AHB protocol conversion to obtain N read operation information and send them to the AHB slave, and obtains the read result of the read instruction through the AHB slave and the controller; wherein, the preset boundary is the address of bytes that are a positive integer multiple of a preset number of bytes; and N is the number of read address ranges that cross the preset boundary plus 1.

13. The method according to claim 12, characterized in that The read result is: N converted pieces of read data sub-information and N converted pieces of read response information; the N converted pieces of read data sub-information and the N converted pieces of read response information are obtained by the controller based on the N pieces of read data sub-information from the AHB slave and the N pieces of read response information of the N pieces of read data sub-information.

14. A data reading method, characterized in that: Applied in AHB slave, including: Receive N pieces of read operation information from the controller; wherein the N pieces of read operation information are obtained by the controller splitting the read instruction from the AXI host into N read sub-instructions when the read address range corresponding to the read instruction crosses a preset boundary, and performing AHB protocol conversion on the N read sub-instructions; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; and N is the number of read address ranges that cross the preset boundary plus 1; Based on the N pieces of read operation information, reading is performed to send a read result to the AXI host through the controller.

15. The method according to claim 14, characterized in that The method further comprises: Based on the N pieces of read address sub-information, N pieces of read data sub-information are obtained, and N pieces of read response information corresponding to the N pieces of read data sub-information are generated; N pieces of read data sub-information and N pieces of read response information are sent to the controller so that the controller obtains the read result based on the N pieces of read data sub-information and the N pieces of read response information; wherein the read result is: the converted N pieces of read data sub-information and the converted N pieces of read response information.

16. A data reading method, characterized in that: Applied in a system-on-chip (SOC), the SOC includes: an AXI host, a controller and an AHB slave; the method includes: The AXI host sends a read instruction to the controller; When the read address range corresponding to the read instruction crosses a preset boundary, the controller splits the read instruction into N read sub-instructions, performs AHB protocol conversion on the N read sub-instructions, and obtains N read operation information; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; and N is the number of the read address range crossing the preset boundary plus 1; Sending the N pieces of read operation information to the AHB slave; The AHB slave performs reading based on the N pieces of read operation information to send the reading result to the AXI host through the controller.

17. A data reading device, characterized in that: The device is applied to a controller and includes: A first receiving module, used for receiving a read instruction from an AXI host; A splitting module, used for splitting the read instruction into N read sub-instructions when the read address range corresponding to the read instruction crosses a preset boundary; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; and N is the number of preset boundaries crossed by the read address range plus 1; A conversion module, used for performing AHB protocol conversion on the N read sub-instructions to obtain N read operation information; The first sending module is used to send the N pieces of read operation information to the AHB slave to return the read result to the AXI host.

18. A data reading device, characterized in that: The device is applied to an AXI host and includes: A second sending module, used for sending a read instruction to the controller; A second receiving module, used for receiving a read result of the read instruction from the controller; Wherein, when the read address range corresponding to the read instruction crosses a preset boundary, the controller splits the read instruction into N read sub-instructions and performs AHB protocol conversion to obtain N read operation information and send them to the AHB slave, and obtains the read result of the read instruction through the AHB slave and the controller; wherein, the preset boundary is the address of bytes that are a positive integer multiple of a preset number of bytes; and N is the number of read address ranges that cross the preset boundary plus 1.

19. A data reading device, characterized in that: The device is applied to an AHB slave, and comprises: A third receiving module is used to receive N pieces of read operation information from the controller; wherein the N pieces of read operation information are obtained by the controller splitting the read instruction from the AXI host into N read sub-instructions when the read address range corresponding to the read instruction crosses a preset boundary, and performing AHB protocol conversion on the N read sub-instructions; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; and N is the number of read address ranges that cross the preset boundary plus 1; The reading module is used to perform reading based on the N pieces of read operation information, so as to send the reading result to the AXI host through the controller.

20. A controller, characterized in that: include: A processor and a storage medium storing instructions executable by the processor, wherein the storage medium relies on the processor to perform operations through a communication bus, and when the instructions are executed by the processor, the data reading method described in any one of claims 1 to 11 is executed.

21. An AXI host, characterized in that: include: A processor and a storage medium storing instructions executable by the processor, wherein the storage medium relies on the processor to perform operations via a communication bus, and when the instructions are executed by the processor, the data reading method described in claim 12 or 13 is executed.

22. An AHB slave, characterized in that: include: A processor and a storage medium storing instructions executable by the processor, wherein the storage medium relies on the processor to perform operations via a communication bus, and when the instructions are executed by the processor, the data reading method described in claim 14 or 15 is executed.

23. A computer storage medium, characterized in that Executable instructions are stored. When the executable instructions are executed by a processor, the processor executes the data reading method according to any one of claims 1 to 11, or executes the data reading method according to claim 12 or 13, or executes the data reading method according to claim 14 or 15.

24. A SOC, characterized in that: include: AXI master, controller and AHB slave; among them, The AXI host is used to send a read instruction to the controller; The controller is used for splitting the read instruction into N read sub-instructions when the read address range corresponding to the read instruction crosses a preset boundary, performing AHB protocol conversion on the N read sub-instructions to obtain N read operation information, and sending the N read operation information to the AHB slave; wherein the preset boundary is an address of bytes that is a positive integer multiple of a preset number of bytes; and N is the number of the read address range crossing the preset boundary plus 1; The AHB slave is used to perform reading based on the N pieces of read operation information, and send the reading result to the AXI host through the controller.

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