System and method for starting double BIOSs (Basic Input / Output System) of spatial high-performance processor

Abstract

The invention provides a double-BI OS starting system and method for a spatial high-performance processor, and the system comprises a controller which is used for reading a BIOS program before the processor is powered on, verifying the correctness of the BIOS program, correcting the data error of the BIOS program if the data error of the BI OS program exists, and starting the BIOS program if the data error of the BI OS program exists. After the processor is powered on, the BIOS program passing verification is forwarded to the processor through the interface converter; the controller is also used for controlling power supply and reset of the processor and monitoring the starting state and running state of the processor; and to update the memory based on an update indication; the memory comprises a first BIOS (Basic Input / Output System) memory and a second BIOS memory and is used for storing BIOS programs and a verification result of the controller; the processor is used for receiving a BI OS program of the controller; according to the method and the device, error detection and correction of a single bit error can be realized, and the single bit error can be timely found and corrected through updating, so that the requirement of a complex calculation task is met, and the stability and the reliability of a system are ensured.

Description

Technical Field

[0001] The invention belongs to the technical field of high-performance processors, and in particular to a system and method for dual BIOS startup of a spatial high-performance processor. Background Art

[0002] The Basic Input / Output System (BIOS) is a firmware built into the computer motherboard. Its main functions include hardware detection and initialization, system settings, boot management, and providing a basic interface for interaction between the operating system and hardware. It plays a vital role in the computer startup process. BIOS is usually stored in non-volatile memory, such as PROM, EPROM, EEPROM, FRAM, MRAM, and FLASH. In space applications, such as computer systems on satellites or spacecraft, the BIOS memory is susceptible to single-particle effects, causing single-particle upsets (SEUs). Instructions or data in the BIOS program are incorrectly modified, which in turn causes errors when the computer starts, causing the computer to fail to start. In order to ensure the reliability and stability of the system, multi-mode redundant memory, such as dual BIOS, and anti-radiation reinforcement measures are often used.

[0003] The existing dual BIOS technology is implemented by installing two physically independent BIOS chips on the motherboard, and the backup method is used to prevent the main BIOS from being damaged due to virus attacks, software failures or update errors. The main BIOS is used first when the system starts up. If an error or damage is detected, it automatically switches to the backup BIOS. However, the existing technology can usually only verify the correctness of the BIOS and cannot automatically repair errors during the startup process. If there is a problem with the BIOS, the operating system must be started before the relevant application can be run to repair it. In space applications, high-energy particles (such as cosmic rays) can easily cause damage to both BIOS at the same time. At this time, the system will not be able to start and must be returned to the factory for repair, which is difficult to achieve in space applications. Summary of the invention

[0004] In order to solve the problems existing in the prior art, the present invention provides a system and method for dual BIOS startup of a space high-performance processor, which is used to solve the technical problems of poor reliability and great repair difficulty of BIOS space application existing in the prior related technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A space high-performance processor dual BIOS boot system, including

[0007] The controller is used to read the BIOS program and verify the correctness of the BIOS program before the processor is powered on, correct the BIOS program data error if there is one, and forward the verified BIOS program to the processor via the interface converter after the processor is powered on; it is also used to control the power supply and reset of the processor, monitor the startup state and running state of the processor; and update the memory based on the update indication;

[0008] A memory, including a first BIOS memory and a second BIOS memory, for storing a BIOS program and a verification result of the controller; and

[0009] The processor is used for receiving the BIOS program of the controller.

[0010] Further, the controller includes an injection program cache module, a Hamming code check module, a Hamming code decoding module, a state monitoring module, a CRC check module and a data selection module;

[0011] The betting program cache module is used to temporarily store the betting program, receive external program input or data selection module program input, and output to the Hamming code verification module;

[0012] The Hamming code verification module is used to verify the correctness of the Hamming code of the BIOS program data, receive the BIOS program data encoded by the Hamming code of the upper program cache module, and write the BIOS program data into the BIOS memory if the verification is correct, and do not write the data if the verification is wrong;

[0013] The Hamming code decoding module is used to read the program data of the BIOS memory, parse the valid data in the Hamming code, locate and correct the erroneous data, and output the correct or corrected valid data to the CRC check module and the data selection module;

[0014] The state monitoring module is used to monitor the operating state of the processor and control the power supply and reset of the processor;

[0015] The CRC check module is used to check the correctness of each data segment of the BIOS, receive the data of the Hamming code decoding module, and store the check result in the CRC check result memory;

[0016] The data selection module is used to select and judge data word by word according to the input of the upper program cache module, the Hamming code decoding module and the CRC check result memory, and output the selected data to the interface converter or the upper program cache module.

[0017] Furthermore, the CRC check result memory is used to store CRC check results of multiple program fragments.

[0018] Furthermore, the state monitoring module includes a timer, a counter and a threshold comparator; the first BIOS memory and the second BIOS memory back up each other.

[0019] Furthermore, the first BIOS memory and the second BIOS memory are both used to store BIOS programs encoded with Hamming codes and CRC check codes.

[0020] A method for starting dual BIOS of a space high-performance processor comprises the following steps:

[0021] Before the processor is powered on, the controller reads the BIOS program from the memory, verifies the correctness of the read BIOS program based on the Hamming code and CRC, and stores the CRC verification result;

[0022] After the processor is powered on, the controller reads the BIOS program from the memory according to the processor read request, checks and corrects the erroneous data based on the Hamming code, reads the stored CRC check result, selects data based on the CRC check result and the Hamming code check result; and forwards the data to the processor via the interface converter;

[0023] The controller periodically collects a startup completion indication signal and a normal operation indication signal of the processor, and based on the collected startup completion indication signal and normal operation indication signal, monitors the startup state and the operation state of the processor, and controls the power supply and reset of the processor based on the startup state and the operation state;

[0024] If the processor is in normal operation or shutdown state, the controller updates the memory based on the update instruction, or receives external program input to update the memory when there is a BIOS program data error that cannot be corrected by itself.

[0025] Further, the controller is also used to receive external program data, and when the controller forwards the corrected or verified data to the processor, the program data of the BIOS in the first BIOS memory or the second BIOS memory, or the external program data received by the controller is selected according to the following principles;

[0026] If the CRC check result of the first BIOS memory is correct, selecting the BIOS program data of the first BIOS memory;

[0027] If the CRC check result of the first BIOS memory is wrong, and the CRC check result of the second BIOS memory is correct, selecting the BIOS program data of the second BIOS memory;

[0028] If the CRC check results of the first BIOS memory and the second BIOS memory are both wrong, selecting the BIOS program data of the first BIOS memory or the second BIOS memory according to the result of the Hamming code decoding module;

[0029] If the Hamming code result of the first BIOS memory is correct or the error has been corrected, the first BIOS memory is selected; if the Hamming code result of the first BIOS memory is not corrected and the Hamming code result of the second BIOS memory is correct or the error has been corrected, the BIOS program data of the second BIOS memory is selected;

[0030] If the Hamming code results of the first BIOS memory and the second BIOS memory are both wrong and cannot be corrected, then read the upper program cache module; if the upper program exists and the Hamming code result is correct or the error has been corrected, then select the BIOS program data of the upper program cache module;

[0031] Otherwise, the selection of BIOS program data is stopped.

[0032] Furthermore, after the processor is powered on, a counter is used to start counting from 0, and the counter is reset when a startup completion indication signal or a normal operation indication signal is received;

[0033] If the start-up completion indication signal or the normal operation indication signal is not received when the count value is greater than the threshold comparator value, a reset signal is sent;

[0034] If the reset signal is sent more than the threshold number of times, the power-on signal is disconnected.

[0035] Furthermore, the controller outputs a power-on signal under the premise that the controller receives a power-on command from the control input, completes at least one CRC check on the first BIOS memory and the second BIOS memory after power-on, and writes the check result into the memory.

[0036] Further, the update memory includes internal update and external update;

[0037] The internal updates are:

[0038] The controller reads the BIOS program from the memory, and verifies the correctness of the BIOS program based on the Hamming code and the CRC. If the data of the BIOS program is wrong, the block where the wrong data is located is marked, the wrong data is corrected, and the corrected BIOS program data is stored.

[0039] Verifying the stored corrected BIOS program data, and if correct, writing and updating the memory;

[0040] The external updates are:

[0041] The controller receives an external program input and temporarily stores the external program;

[0042] The temporarily stored external program is checked, and if correct, it is written into and updated in the memory.

[0043] Compared with the prior art, the present invention has the following beneficial technical effects:

[0044] The present invention provides a system and method for dual BIOS startup of a space high-performance processor, comprising: a controller, used for reading a BIOS program and verifying the correctness of the BIOS program before the processor is powered on, correcting the BIOS program data error if there is a BIOS program data error, and forwarding the verified BIOS program to the processor via an interface converter after the processor is powered on; also used for controlling the power supply and reset of the processor, monitoring the startup state and running state of the processor; and for updating the memory based on an update indication; the memory, comprising a first BIOS memory and a second BIOS memory, for storing the BIOS program and the verification result of the controller; and a processor, A BIOS program for receiving a controller; the present application can realize error detection and correction of single-bit errors, and when one channel of data correction fails, it can automatically switch to another channel of data. When the data in the upper program cache module is valid, the reliability of the data is further enhanced through the three-channel data selection mechanism; at the same time, it can monitor the operating status of the processor, execute a restart operation when the startup fails or an operating error occurs, and output the operating status of the processor in real time. The present application effectively solves the problem that multiple-bit errors cannot be detected, and through updates, single-bit errors can be discovered and corrected in time to prevent the occurrence of multiple-bit errors; the present application not only meets the needs of complex computing tasks, but also ensures the stability and reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A system diagram of dual BIOS booting of a spatial high-performance processor according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0046] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present invention. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0047] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0048] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0049] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0050] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0051] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0052] Various structural schematic diagrams of the embodiments disclosed in the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0053] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0054] Figure 1 A system diagram of dual BIOS booting of a space high-performance processor according to an embodiment of the present disclosure is shown. Figure 1 Shown, including

[0055] The controller is used to read the BIOS program and verify the correctness of the BIOS program before the processor is powered on, correct the BIOS program data error if there is one, and forward the verified BIOS program to the processor via the interface converter after the processor is powered on; it is also used to control the power supply and reset of the processor, monitor the startup state and running state of the processor; and update the memory based on the update indication;

[0056] A memory, including a first BIOS memory and a second BIOS memory, for storing a BIOS program and a verification result of the controller; and

[0057] The processor is used for receiving the BIOS program of the controller.

[0058] It should be noted that in the disclosed embodiment, the BIOS program is not stored in its original form, but is a version processed by Hamming code and CRC check code. The original BIOS program is divided into multiple segments, and the segmentation interval can be set to 128 words. The CRC check code is calculated for each program segment to obtain the CRC check standard result. The CRC check standard result and the BIOS program are alternately sorted. For example, the BIOS program of 128 words is first arranged, and then the CRC check standard result corresponding to the above 128 words is arranged, and then the BIOS program of 128 words is arranged, and then the CRC check standard result corresponding to the above 128 words is arranged. The arrangement of all BIOS programs and check standard results is completed by analogy, and then the Hamming code is applied to the arranged data to obtain the encoded data. The encoded data is stored in the first BIOS memory and the second BIOS memory.

[0059] Preferably, in the disclosed embodiment, the controller includes an injection program cache module, a Hamming code check module, a Hamming code decoding module, a state monitoring module, a CRC check module and a data selection module;

[0060] The betting program cache module is used to temporarily store the betting program, receive external program input or data selection module program input, and output to the Hamming code verification module;

[0061] The Hamming code verification module is used to verify the correctness of the Hamming code of the BIOS program data, receive the BIOS program data encoded by the Hamming code of the upper program cache module, and write the BIOS program data into the BIOS memory if the verification is correct, and do not write the data if the verification is wrong;

[0062] The Hamming code decoding module is used to read the program data of the BIOS memory, parse the valid data in the Hamming code, locate and correct the erroneous data, and output the correct or corrected valid data to the CRC check module and the data selection module; specifically, the Hamming code decoding module reads the BIOS data encoded by the Hamming code in the memory, parses the valid data, recalculates the check bit, and compares it with the read check bit to detect whether there is an error in the data. If the check result is correct, it is directly output. If an error is found, a single bit error is located and corrected by the Hamming code algorithm, and the corrected valid data is output. If multiple bit errors occur, it exceeds its correction capability, and an error report is output.

[0063] The state monitoring module is used to monitor the operating state of the processor and control the power supply and reset of the processor;

[0064] The CRC check module is used to check the correctness of each data segment of the BIOS, receive the data of the Hamming code decoding module, and store the check result in the CRC check result memory;

[0065] The data selection module is used to select and judge data word by word according to the input of the upper program cache module, the Hamming code decoding module and the CRC check result memory, and output the selected data to the interface converter or the upper program cache module.

[0066] Specifically, if Figure 1As shown, the controller adopts a high-reliability controller, and the high-reliability controller has anti-radiation reinforcement characteristics, which includes an injection program cache module, a Hamming code check module, a Hamming code decoding module, a status monitoring module, a CRC check module and a data selection module; wherein the injection program cache module is used to receive program input, and is respectively connected to the Hamming code check module and the data selection module signal, the Hamming code check module is respectively connected to the first BIOS memory and the second BIOS memory signal of the memory, the output signals of the first BIOS memory and the second BIOS memory are respectively connected to the Hamming code decoding module, the signal output of the Hamming code decoding module is connected to the CRC module and the data selection module, the signal of the CRC module is transmitted to the data selection module via the CRC check result memory, the output signal of the data selection module is respectively connected to the injection program cache module and the interface converter, the interface converter inputs the received signal to the processor, the processor adopts a high-performance processor, and the high-performance processor usually adopts a commercial non-radiation-hardened chip.

[0067] Specifically, the Hamming code decoding module outputs the decoded data to the CRC module, which uses the CRC method to verify the correctness of the BIOS data and stores the verification results in the CRC verification result memory. The available space of the CRC verification result memory must be greater than the number of fragments divided by the original BIOS program. According to the BIOS program storage rules, every 128-word BIOS program and the corresponding CRC verification standard result are stored alternately. The decoding module calculates the CRC verification results of every 128-word BIOS program in turn. If it is consistent with the CRC verification standard result, write 1 to the address corresponding to the fragment number in the CRC verification result memory; if it is inconsistent with the CRC verification standard result, write 0 to the address corresponding to the fragment number in the CRC verification result memory. The CRC verification of all BIOS programs is completed by analogy, and all verification results are written to the CRC verification result memory; further, the power supply receives the power-on signal and powers on the high-performance processor. After the high-performance processor is powered on, it starts and sends a BIOS read request to the interface converter. The data communication interface of the high-performance processor can be EMMC or SPI, and the data communication interface of the high-reliability controller can be EMI F or SPI. The interface converter has EMIF, EMMC, SPI interface conversion and address conversion functions to achieve communication between high-reliability controllers and high-performance processors.

[0068] After the CRC check is completed, if the state monitoring module receives a power-on command from the control input, a power-on signal is output to the high-performance processor power supply. The condition for the state monitoring module to output the power-on signal is: receiving a power-on command from the control input, and completing at least one CRC check of the first BIOS memory and the second BIOS memory after the high-reliability controller is powered on, and writing the check result into the CRC check result memory.

[0069] The data selection module selects the data word by word, and the selection method is to read the CRC check result of the current part of the program fragment in the CRC check result memory, and if the CRC check result of the first BIOS memory is correct, the first BIOS memory is selected; if the CRC check result of the first BIOS memory is wrong, and the CRC check result of the second BIOS memory is correct, the second BIOS memory is selected; if the CRC check results of the first BIOS memory and the memory 2 are both wrong, select according to the result of the Hamming code decoding module; if the Hamming code result of the first BIOS memory is correct or the error has been corrected, the first BIOS memory is selected; if the Hamming code result of the first BIOS memory is incorrect and cannot be corrected, and the Hamming code result of the second BIOS memory is correct or the error has been corrected, the second BIOS memory is selected; if the Hamming code results of the first BIOS memory and the 2 BIOS memory are both incorrect and cannot be corrected, then read the upper annotation program cache module, if the upper annotation program exists and the Hamming code result is correct or the error has been corrected, then select the upper annotation program cache module; if the above conditions are not met, stop data selection. According to the above method, the data selection module forwards the corrected BIOS program data to the high-performance processor via the interface converter.

[0070] Preferably, in the disclosed embodiment, the CRC check result memory is used to store the CRC check results of multiple program fragments; specifically, a cyclic redundancy check (CRC) is an error detection method for detecting errors that may occur after data transmission or storage, which generates a check value (i.e., a CRC check code) by performing a specific algorithm operation on a set of data, and this check value is then transmitted or stored with the data. At the receiving end, the same algorithm is applied to the received data and a new check value is generated. If the newly generated check value is the same as the check value originally sent, it can be considered that no error occurred during the data transmission or storage process.

[0071] For scenarios where multiple program fragments need to be processed, such as different parts in a firmware update package, multiple records in a database, etc., CRC checks are usually performed on each program fragment separately, and the CRC check results of each fragment are stored. The storage of these check results can be implemented using a dedicated "CRC check result storage", although in actual applications, this "storage" may not always refer to a physically independent storage device, but may be an area in memory, a table in a database, or a file in a file system, etc.

[0072] That is, when data is read or used, the CRC value of the data can be recalculated and compared with the stored CRC value to quickly detect whether the data has been damaged during storage or transmission. And when data errors are found, by comparing the CRC check results, the scope of the problem can be narrowed down and the source of data damage can be quickly located.

[0073] Preferably, in the embodiment of the present disclosure, the state monitoring module includes a timer, a counter and a threshold comparator; specifically, the state monitoring method of the controller state monitoring module is:

[0074] After the high-performance processor is powered on, the counter starts counting from 0, and the counter is reset when the startup completion indication signal or the normal operation indication signal is received. If the count value is greater than the threshold comparator value and the startup completion indication signal or the normal operation indication signal is still not received, a reset signal is sent. If the reset signal is sent more than 3 times, the power-on signal is disconnected.

[0075] After the high-performance processor is started, it sends a startup completion indication signal to the controller's status monitoring module. If the startup completion indication signal is not output within the agreed time, it means that the startup has failed. During the operation of the high-performance processor, it is necessary to regularly send a normal operation indication signal to the controller's status monitoring module. If the normal operation indication signal is not regularly output within the agreed time, it means that the operation is abnormal. The controller continuously monitors the operating status of the high-performance processor and restarts the high-performance processor when the startup fails or the operation is abnormal. If the number of restarts exceeds 3 times, the power supply is turned off.

[0076] Preferably, in the embodiment of the present disclosure, the first BIOS memory and the second BIOS memory back up each other; further, the first BIOS memory and the second BIOS memory are both used to store BIOS programs encoded with Hamming codes and CRC check codes.

[0077] The embodiment of the present disclosure also provides a method for starting dual BIOS of a space high-performance processor, comprising the following steps:

[0078] Before the processor is powered on, the controller reads the BIOS program from the memory, verifies the correctness of the read BIOS program based on the Hamming code and CRC, and stores the CRC verification result;

[0079] After the processor is powered on, the controller reads the BIOS program from the memory according to the processor read request, checks and corrects the erroneous data based on the Hamming code, reads the stored CRC check result, selects data based on the CRC check result and the Hamming code check result; and forwards the data to the processor via the interface converter;

[0080] The controller periodically collects a startup completion indication signal and a normal operation indication signal of the processor, and based on the collected startup completion indication signal and normal operation indication signal, monitors the startup state and the operation state of the processor, and controls the power supply and reset of the processor based on the startup state and the operation state;

[0081] If the processor is in normal operation or shutdown state, the controller updates the memory based on the update instruction, or receives external program input to update the memory when there is a BIOS program data error that cannot be corrected by itself.

[0082] Specifically, the update indication includes a control input update instruction and an internal control update instruction. The control input update instruction is an instruction of an external control input received by a controller status monitoring module, that is, an external program input, which is a passive update instruction, that is, an external update process. The internal control update instruction is an update instruction triggered by a timer of the controller status monitoring module at a certain time interval, that is, an internal update process. Compared with the internal control update instruction, the control input update instruction is a one-time trigger mechanism.

[0083] Preferably, the controller is further used to receive external program data, and when the controller forwards the corrected or verified data to the processor, the BIOS program data of the first BIOS memory or the second BIOS memory, or the external program data received by the controller is selected according to the following principles;

[0084] If the CRC check result of the first BIOS memory is correct, selecting the BIOS program data of the first BIOS memory;

[0085] If the CRC check result of the first BIOS memory is wrong, and the CRC check result of the second BIOS memory is correct, selecting the BIOS program data of the second BIOS memory;

[0086] If the CRC check results of the first BIOS memory and the second BIOS memory are both wrong, selecting the BIOS program data of the first BIOS memory or the second BIOS memory according to the result of the Hamming code decoding module;

[0087] If the Hamming code result of the first BIOS memory is correct or the error has been corrected, the first BIOS memory is selected; if the Hamming code result of the first BIOS memory is not corrected and the Hamming code result of the second BIOS memory is correct or the error has been corrected, the BIOS program data of the second BIOS memory is selected;

[0088] If the Hamming code results of the first BIOS memory and the second BIOS memory are both wrong and cannot be corrected, then read the upper program cache module; if the upper program exists and the Hamming code result is correct or the error has been corrected, then select the BIOS program data of the upper program cache module;

[0089] Otherwise, the selection of BIOS program data is stopped.

[0090] Preferably, in an embodiment of the present disclosure, after the processor is powered on, a counter is used to start counting from 0, and the counter is reset when a startup completion indication signal or a normal operation indication signal is received;

[0091] If the start-up completion indication signal or the normal operation indication signal is not received when the count value is greater than the threshold comparator value, a reset signal is sent;

[0092] If the reset signal is sent more than the threshold number of times, the power-on signal is disconnected.

[0093] Preferably, in the embodiment of the present disclosure, the controller outputs a power-on signal under the prerequisite that the controller receives a control input power-on command and completes at least one CRC check of the first BIOS memory and the second BIOS memory after power-on, and writes the check result into the memory.

[0094] Preferably, in an embodiment of the present disclosure, the update memory includes internal update and external update;

[0095] The internal updates are:

[0096] The controller reads the BIOS program from the memory, and verifies the correctness of the BIOS program based on the Hamming code and the CRC. If the data of the BIOS program is wrong, the block where the wrong data is located is marked, the wrong data is corrected, and the corrected BIOS program data is stored.

[0097] Verifying the stored corrected BIOS program data, and if correct, writing and updating the memory;

[0098] The external updates are:

[0099] The controller receives an external program input and temporarily stores the external program;

[0100] The temporarily stored external program is checked, and if correct, it is written into and updated in the memory.

[0101] Specifically, when the processor is running normally or in shutdown state, there is no read or write operation on the BIOS memory. The controller can use this time to check and update the BIOS memory, and timely detect and correct single-bit errors through regular checks to prevent the occurrence of multiple-bit errors. Or the BIOS program can be re-burned when a serious error occurs that cannot be corrected.

[0102] The first BIOS memory and the second BIOS memory can realize internal update and external update. The internal update data path is as follows: from the data selection module, through the injection program cache module, the Hamming code check module to the first BIOS memory and the second BIOS memory. The external update data path is as follows: from the external program input, through the injection program cache module, the Hamming code check module to the first BIOS memory and the second BIOS memory.

[0103] The internal update process is as follows: The high-reliability controller reads the BIOS program from the memory and verifies the correctness of the program based on the Hamming code and CRC. When a program data error is found, the block where the error data is located is marked, and the error data is corrected. The corrected BIOS program data is written to the upper program cache module through the data selection module. When the program data is correct, there is no need to write it to the upper program cache module. The upper program cache module receives the corrected data and outputs it to the Hamming code verification module. The Hamming code verification module verifies the correctness of the data Hamming code. If the verification is correct, the data is written to the BIOS memory to correct the error data in the memory.

[0104] The external update process is as follows: The high-reliability controller receives external program input and temporarily stores the program in the upper program cache module. The upper program cache module receives data and outputs it to the Hamming code verification module. The Hamming code verification module verifies the correctness of the data Hamming code. If the verification is correct, the data is written to the BIOS memory to update the BIOS program in the memory.

[0105] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention. Therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the attached claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims are included in the present invention. Any figure mark in the claims should not be regarded as limiting the claims involved.

[0106] In addition, it should be understood that although this specification is described in accordance with the implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation modes that can be understood by those skilled in the art. The above content is only to illustrate the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution according to the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A dual BIOS boot system for a high-performance processor, characterized in that: include A controller, used to read the BIOS program and verify the correctness of the BIOS program before the processor is powered on, correct the BIOS program data error if there is one, and forward the verified BIOS program to the processor via the interface converter after the processor is powered on; It is also used to control the power and reset of the processor and monitor the startup and running status of the processor; and for updating the memory based on the update indication; A memory, including a first BIOS memory and a second BIOS memory, for storing a BIOS program and a verification result of the controller; as well as A processor is used to receive a BIOS program of a controller.

2. The system for dual BIOS booting of a high-performance processor according to claim 1, characterized in that: The controller includes an injection program cache module, a Hamming code check module, a Hamming code decoding module, a state monitoring module, a CRC check module and a data selection module; The betting program cache module is used to temporarily store the betting program, receive external program input or data selection module program input, and output to the Hamming code verification module; The Hamming code verification module is used to verify the correctness of the Hamming code of the BIOS program data, receive the BIOS program data encoded by the Hamming code of the upper program cache module, and write the BIOS program data to the BIOS memory if the verification is correct, and do not write the data if the verification is wrong; The Hamming code decoding module is used to read the program data of the BIOS memory, parse the valid data in the Hamming code, locate and correct the erroneous data, and output the correct or corrected valid data to the CRC check module and the data selection module; The state monitoring module is used to monitor the operating state of the processor and control the power supply and reset of the processor; The CRC check module is used to check the correctness of each data segment of the BIOS, receive the data of the Hamming code decoding module, and store the check result in the CRC check result memory; The data selection module is used to select and judge data word by word according to the input of the upper program cache module, the Hamming code decoding module and the CRC check result memory, and output the selected data to the interface converter or the upper program cache module.

3. The system for dual BIOS booting of a high-performance processor according to claim 2, characterized in that: The CRC check result memory is used to store the CRC check results of multiple program fragments.

4. The system for dual BIOS booting of a high-performance processor according to claim 2, characterized in that: The state monitoring module includes a timer, a counter and a threshold comparator; the first BIOS memory and the second BIOS memory back up each other.

5. The system for dual BIOS booting of a high-performance processor according to claim 4, characterized in that: The first BIOS memory and the second BIOS memory are both used to store BIOS programs encoded with Hamming codes and CRC check codes.

6. A method for dual BIOS booting of a high-performance processor, characterized in that: The system for dual BIOS booting of a space high-performance processor according to any one of claims 1 to 5 comprises the following steps: Before the processor is powered on, the controller reads the BIOS program from the memory, verifies the correctness of the read BIOS program based on the Hamming code and CRC, and stores the CRC verification result; After the processor is powered on, the controller reads the BIOS program from the memory according to the processor read request, checks and corrects the erroneous data based on the Hamming code, reads the stored CRC check result, selects data based on the CRC check result and the Hamming code check result; and forwards the data to the processor via the interface converter; The controller periodically collects a startup completion indication signal and a normal operation indication signal of the processor, and based on the collected startup completion indication signal and normal operation indication signal, monitors the startup state and the operation state of the processor, and controls the power supply and reset of the processor based on the startup state and the operation state; If the processor is in normal operation or shutdown state, the controller updates the memory based on the update instruction, or receives external program input to update the memory when there is an error in the BIOS program data that cannot be corrected by itself.

7. The method for dual BIOS booting of a space high-performance processor according to claim 6, characterized in that: The controller is also used to receive external program data, and when the controller forwards the corrected or verified data to the processor, the program data of the BIOS in the first BIOS memory or the second BIOS memory, or the external program data received by the controller is selected according to the following principles; If the CRC check result of the first BIOS memory is correct, selecting the BIOS program data of the first BIOS memory; If the CRC check result of the first BIOS memory is wrong, and the CRC check result of the second BIOS memory is correct, selecting the BIOS program data of the second BIOS memory; If the CRC check results of the first BIOS memory and the second BIOS memory are both wrong, selecting the BIOS program data of the first BIOS memory or the second BIOS memory according to the result of the Hamming code decoding module; If the Hamming code result of the first BIOS memory is correct or the error has been corrected, the first BIOS memory is selected; if the Hamming code result of the first BIOS memory is incorrect and cannot be corrected, and the Hamming code result of the second BIOS memory is correct or the error has been corrected, the BIOS program data of the second BIOS memory is selected; If the Hamming code results of the first BIOS memory and the second BIOS memory are both wrong and cannot be corrected, then read the upper annotation program cache module, and if the upper annotation program exists and the Hamming code result is correct or the error has been corrected, then select the BIOS program data of the upper annotation program cache module; Otherwise, stop selecting BIOS program data.

8. The method for dual BIOS booting of a high-performance processor according to claim 6, characterized in that: After the processor is powered on, a counter is used to start counting from 0, and the counter is reset when a startup completion indication signal or a normal operation indication signal is received; If the start-up completion indication signal or the normal operation indication signal is not received when the count value is greater than the threshold comparator value, a reset signal is sent; If the reset signal is sent more than the threshold number of times, the power-on signal is disconnected.

9. The method for dual BIOS booting of a space high performance processor according to claim 6, characterized in that: The controller outputs a power-on signal under the premise that the controller receives a power-on command from the control input, completes at least one CRC check on the first BIOS memory and the second BIOS memory after powering on, and writes the check result into the memory.

10. The method for dual BIOS booting of a space high performance processor according to claim 6, characterized in that: The update memory includes internal update and external update; The internal updates are: The controller reads the BIOS program from the memory, and verifies the correctness of the BIOS program based on the Hamming code and the CRC. If the data of the BIOS program is wrong, the block where the wrong data is located is marked, the wrong data is corrected, and the corrected BIOS program data is stored; Verifying the stored corrected BIOS program data, and if correct, writing and updating the memory; The external updates are: The controller receives an external program input and temporarily stores the external program; The temporarily stored external program is checked, and if correct, it is written into and updated in the memory.

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