Signal generation method and system based on multi-core DSP, electronic equipment and storage medium

Abstract

The invention relates to a signal generation method and system based on a multi-core DSP, electronic equipment and a storage medium, and belongs to the technical field of digital signal processing, one core in the multi-core DSP is designated as a management core, the other cores are processing cores, when an input signal of a current period is received, the management core classifies the input signal received in the current period into a plurality of groups and sends the groups to the processing core; through cyclically traversing each group, allocating an idle processing core to each non-empty group, and setting the state of the corresponding processing core to be occupied; when the processing core finishes processing the allocated grouping signal, the management core is notified by sending EDMA interrupt; and the management core pauses traversal, sets the state of the corresponding processing core to be idle, and returns to continue traversal until the processing of the input signal in the current period is completed. The problem that performance is reduced due to the fact that multi-core DSP processing resources cannot be fully utilized in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and in particular to a signal generation method, system, electronic equipment and storage medium based on a multi-core DSP. Background Art

[0002] In the complex electromagnetic environment, multi-core DSP is a commonly used one in electromagnetic signal processing. A signal generation system mainly includes a host control unit, a signal generation unit (DSP) digital signal processing (Digital Signal Processing, DSP), a signal synthesis unit (FPGA) field programmable gate array (Field Programmable Gate Array, FPGA). The signal generation unit generates baseband data and configuration according to the signal list sent by the host control unit. Most signal generation methods use serial processing, that is, the FPGA performs interpolation, frequency shifting, and combining before sending out the signal.

[0003] This approach will result in limited signal paths, with some cores being idle, and the inability to fully utilize the speed and performance of the multi-core DSP, which will reduce the signal processing generation performance indicators. Summary of the invention

[0004] In view of the above analysis, the embodiments of the present invention aim to provide a signal generation method, system, electronic device and storage medium based on multi-core DSP, so as to solve the problem that the signal processing method in the prior art causes the DSP processing resources to be unable to be fully utilized, resulting in performance degradation.

[0005] On the one hand, an embodiment of the present invention provides a signal generation method based on a multi-core DSP, wherein the DSP includes a management core and multiple processing cores, and performs the following process on an input signal received in each cycle, wherein the process specifically includes:

[0006] The management core classifies the input signal received in the current cycle into a plurality of groups;

[0007] The management core traverses each group in a loop, assigns each non-empty group to an idle processing core, and sets the status of the assigned processing core to occupied;

[0008] When the assigned processing core completes processing of the corresponding packet signal and outputs it, notifies the management core;

[0009] After receiving the notification, the management core suspends the traversal and sets the state of the processing core that has completed the processing to idle;

[0010] The management core returns to the pause position and continues traversal until the input signal received in the current cycle is processed completely.

[0011] The beneficial effects of the above technical solution are as follows: one core in the multi-core DSP is designated as a management core, and the remaining cores are used as processing cores. The management core groups the input signals of each cycle based on categories, and then traverses each of the groups and the status of each processing core in turn, and allocates an idle processing core to each group, so that all processing cores are in an occupied state before the processing of each group signal is completed. Therefore, all processing core resources of the DSP are in an efficient utilization state, and there is no situation where a processing core is idle before the group is not processed. Compared with the existing technology, DSP resources are optimally utilized and performance indicators will not be reduced.

[0012] Based on a further improvement of the above method, the management core classifies the input signal received in the current period into a plurality of groups through the following process, and the process specifically includes:

[0013] S21: Sort the input signals received in the current period from low to high according to the carrier frequency to obtain a sequence to be grouped;

[0014] S22: establishing a new group based on the first signal in the sequence to be grouped and setting grouping conditions, and moving the first signal into the new group and removing it from the sequence to be grouped;

[0015] S23: traverse all remaining signals in the sequence to be grouped, move signals that meet the grouping conditions into the new group in turn, and remove them from the sequence to be grouped, until no signal that meets the grouping conditions can be moved into the new group or the new group is full, then return to iteratively execute S22-S23 until all groups are established and there is no groupable signal in the sequence to be grouped;

[0016] S24: Combining the signals in all the groups into a whole, and saving the center frequency of the whole signal.

[0017] The beneficial effect of the above further improved solution is: the input signals received in the current period are grouped, and the same type of signals are grouped and processed uniformly by sorting based on the carrier frequency, which can further improve the signal processing efficiency.

[0018] Based on the further improvement of the above method, the inclusion condition specifically refers to that the signal must simultaneously meet the sampling rate, frequency, and validity requirements, wherein:

[0019] The sampling rate requirement refers to that the sampling rate of the signal is the same as the sampling rate of the first signal;

[0020] The frequency requirement means that the signal start frequency is not less than the packet start frequency, and the signal end frequency is not greater than the packet end frequency, wherein:

[0021] The packet start frequency is the difference between the carrier frequency of the first signal and half of its bandwidth.

[0022] The group end frequency is the sum of the group start frequency and 80% of the first signal sampling rate;

[0023] The validity requirement is that the signal is a non-real-time signal and the signal flag is valid.

[0024] The beneficial effects of the above further improvement scheme are: by setting the grouping conditions, small invalid signals can be excluded, and the same type of signals can be grouped into the same group for processing, and by setting the starting frequency and ending frequency of the grouping, the lengths of the signals in each group can be kept similar, which can further improve the signal processing efficiency.

[0025] Based on a further improvement of the above method, when the signal meets the sampling rate requirement and the validity requirement, but does not meet the frequency requirement, the new group is full;

[0026] When no signal can be moved into the new group or the new group is full, the group end frequency is updated to the end frequency of the last signal in the new group.

[0027] The beneficial effects of the above further improvement scheme are: ensuring that the signals entering each group meet the unified entry criteria, ensuring the consistency of algorithm processing, and thus improving processing efficiency; using the termination frequency of the last signal in each group as the termination frequency of the corresponding group, in order to ensure the accuracy of the sequence signal information composed of the signals within the group.

[0028] Based on the further improvement of the above method, allocating each non-empty group to an idle processing core specifically includes:

[0029] The management core traverses all processing core states;

[0030] When an idle processing core is found, the management core allocates the non-empty packet to the idle processing core by sending an IPC interrupt to the idle processing core.

[0031] The beneficial effect of the above further improvement scheme is: the non-empty groups, that is, the groups with signals, are found through a loop traversal method to find the idle processing cores, and the non-empty groups are assigned to the idle processing cores for processing. It is impossible for non-empty groups and idle processing cores to exist at the same time, so that the DSP processing core resources are always in a state of efficient utilization, and the resource utilization and performance are always in an optimal state.

[0032] Based on a further improvement of the above method, after the assigned processing core completes processing of the corresponding packet signal and outputs it, it notifies the management core, specifically by sending an EDMA interrupt to the management core.

[0033] The beneficial effect of the above further improvement scheme is that the processing core communicates with the management core through the EDMA interrupt mode, which can avoid the problem of information failure caused by multiple processing cores using IPC interrupts to communicate with the management core at the same time.

[0034] Based on the further improvement of the above method, when the management core reads the current status and number of each processing core and each processing core is occupied, the management core suspends traversal until receiving an EDMA interrupt and continues traversal.

[0035] The beneficial effect of the above further improved scheme is: when there are non-empty groups to be allocated and there are no idle cores available, pausing the traversal can not only save DSP management core resources, but also record the non-empty groups to be allocated; when the management core receives an EDMA interrupt, that is, a processing core has completed the processing, the management core will set the completed processing core to idle and then continue the traversal, ensuring the continuity of the management core's use of the processing core resources.

[0036] On the other hand, an embodiment of the present invention provides a signal generation system based on a multi-core DSP, the system comprising a storage module, a processing module, and an output module, wherein:

[0037] The storage module is used to receive and store the current cycle input signal, and also save the status and number of each processing core;

[0038] The processing module includes a management core and multiple processing cores, wherein:

[0039] The management core groups the input signals of the current cycle, and then traverses each group in a loop. When a non-empty group is found, the management core reads and traverses the status and number of each processing core, finds an idle processing core, allocates the non-empty group to the idle processing core, and sets the status of the allocated processing core to occupied and saved; after the processing core is allocated, it reads and processes the corresponding signal in the non-empty group, and after completion, sends the processed signal to the output module and notifies the management core; after receiving the notification, the management core pauses the traversal, sets the status of the processing core that sends the notification to idle and saves, and then returns to the pause position to continue the traversal;

[0040] The output module outputs the processed signal.

[0041] The beneficial effects of the above technical solution are as follows: it can establish a concise and efficient multi-core DSP system architecture, which not only realizes the optimal utilization of multi-core DSP resources, but also is easy to implement.

[0042] An embodiment of the present invention further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, a signal generation method based on a multi-core DSP provided by an embodiment of the present invention is implemented.

[0043] The beneficial effects of the above technical solution are as follows: the electronic device can process signals faster than the prior art.

[0044] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, a signal generation method based on a multi-core DSP provided by an embodiment of the present invention is implemented.

[0045] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. In the entire drawings, the same reference symbols represent the same components;

[0047] Figure 1 is a flow chart of the method of embodiment 1 of the present invention;

[0048] Figure 2 This is an example diagram of an IPC interrupt signal in Embodiment 1 of the present invention;

[0049] Figure 3 This is an example diagram of the EDMA interrupt signal in Example 1 of the present invention. DETAILED DESCRIPTION

[0050] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0051] Embodiment 1:

[0052] A specific embodiment of the present invention discloses a signal generation method based on a multi-core DSP, such as Figure 1 shown.

[0053] The DSP includes a management core and multiple processing cores, and performs the following process on the input signal received in each cycle, and the process specifically includes:

[0054] The management core classifies the input signal received in the current cycle into a plurality of groups;

[0055] The management core traverses each group in a loop, assigns each non-empty group to an idle processing core, and sets the status of the assigned processing core to occupied;

[0056] When the assigned processing core completes processing of the corresponding packet signal and outputs it, notifies the management core;

[0057] After receiving the notification, the management core suspends the traversal and sets the state of the processing core that has completed the processing to idle;

[0058] The management core returns to the pause position and continues traversal until the input signal received in the current cycle is processed completely.

[0059] Generally, in order to realize parallel processing, a multi-core DSP uses one of its cores as a management core for overall control and resource allocation, and the remaining cores as processing cores for processing signal data. A shared memory is also allocated to store the content of the signal data and the number and status of each processing core. The signal data is periodically input to the multi-core DSP, and after being processed and output by the multi-core DSP, the next cycle of signals is input to the multi-core DSP. For electromagnetic signals, the signal data input to the multi-core DSP in each cycle specifically includes multiple electromagnetic signals with different sampling rates, signal parameters, and carrier frequencies. Each electromagnetic signal is a signal segment including a start frequency and an end frequency. For the signal data input to the multi-core DSP in each cycle, the following process is performed:

[0060] Sub-process 1: The management core classifies the input signal received in the current cycle into multiple groups.

[0061] Further, the management core classifies the input signal received in the current period into a plurality of groups through the following process, wherein the process specifically includes:

[0062] S21: Sort the input signals received in the current period from low to high according to the carrier frequency to obtain a sequence to be grouped;

[0063] S22: establishing a new group based on the first signal in the sequence to be grouped and setting grouping conditions, and moving the first signal into the new group and removing it from the sequence to be grouped;

[0064] S23: traverse all remaining signals in the sequence to be grouped, move signals that meet the grouping conditions into the new group in turn, and remove them from the sequence to be grouped, until no signal that meets the grouping conditions can be moved into the new group or the new group is full, then return to iteratively execute S22-S23 until all groups are established and there is no groupable signal in the sequence to be grouped;

[0065] S24: Combining the signals in all the groups into a whole, and saving the center frequency of the whole signal.

[0066] Wherein, S21 is executed to first sort the input signals received in the current period from low to high based on the carrier frequency to obtain a sequence to be grouped, so as to facilitate subsequent retrieval and grouping processing.

[0067] Then, S22 is executed to establish a new group based on the first signal of the sequence to be grouped and set the grouping conditions. The process of establishing each group is performed by traversing all the signals in the sequence to be grouped each time, specifically, starting from the beginning according to the order of the signals in the sequence to be grouped, and taking the first signal retrieved as the first signal to be included in the new group and the basis for setting the grouping conditions.

[0068] Furthermore, the inclusion conditions specifically refer to that the signal must simultaneously meet the sampling rate, frequency, and validity requirements, where:

[0069] The sampling rate requirement refers to that the sampling rate of the signal is the same as the sampling rate of the first signal;

[0070] The frequency requirement means that the signal start frequency is not less than the packet start frequency, and the signal end frequency is not greater than the packet end frequency, wherein:

[0071] The packet start frequency is the difference between the carrier frequency of the first signal and half of its bandwidth.

[0072] The group end frequency is the sum of the group start frequency and 80% of the first signal sampling rate;

[0073] The validity requirement is that the signal is a non-real-time signal and the signal flag is valid.

[0074] Specifically, the sampling rate of the first signal is used as a classification condition, and the start frequency and the end frequency of the group are set based on the carrier frequency and the sampling rate of the first signal. Specifically, the start frequency of the group is the difference between the carrier frequency of the first signal and half of its bandwidth, and the end frequency of the group is the sum of the start frequency of the group and 80% of the sampling rate of the first signal. The purpose of this setting is that when the signal is processed by the multi-core DSP and output to the FPGA, the signal is generally interpolated and filtered. According to the Nyquist theorem, the total bandwidth of the signal should not exceed 80% of the sampling rate. At the same time, the grouping conditions also include removing invalid signals. Specifically, the invalid signal is a real-time signal or a signal with an invalid signal flag.

[0075] Next, execute S23, traverse all remaining signals in the sequence to be grouped, move the signals that meet the grouping conditions into the new group in turn, and remove them from the sequence to be grouped until there are no signals that meet the grouping conditions and can be moved into the new group or the new group is full, then return to iterate and execute S22-S23 until all groups are established and there are no groupable signals in the sequence to be grouped.

[0076] Specifically, by iteratively executing S22-S23 on the sequence to be grouped, a new group is established in each iteration round, and signals that meet the grouping conditions are moved from the sequence to be grouped into the new group, so that the signals in the sequence to be grouped become fewer and fewer, until after multiple iterations, all the groupable signals in the sequence to be grouped are removed, and only invalid signals remain or the sequence to be grouped is empty.

[0077] There is a special case when iteratively executing S22-S23. Further, when the signal meets the sampling rate requirement and the validity requirement but does not meet the frequency requirement, the new group is full.

[0078] Specifically, when the starting frequency of the signal does not exceed the ending frequency of the group, but the ending frequency of the signal exceeds the ending frequency of the group, that is, the signal does not meet the frequency requirement of the grouping condition, and since all signals of the sequence to be grouped are sorted from low to high based on the carrier frequency, and each time S23 is executed, the traversal starts from the first signal of the sequence to be grouped, then the signal and all other signals in the sequence to be grouped do not meet the grouping condition, which means that the group is full and no new signal enters the group, then the ending frequency of the last signal in the group is set as the ending frequency of the group. The purpose of doing this is that since the group ending frequency set in the grouping condition is a preset value, after the group establishment and signal grouping are completed, in order to ensure accuracy, the ending frequency of the group needs to be updated to the ending frequency of the last signal to be grouped.

[0079] Finally, S24 is executed to merge the signals in all the groups into a whole and save the center frequency of the whole signal. Since the signals in each group are processed by the multi-core DSP and output to the FPGA, the FPGA regards all the signals in each group as a whole, so it is necessary to calculate the center frequency of the signal after all the signals in each group are combined into a whole, so as to facilitate the subsequent FPGA recognition and processing.

[0080] Sub-process 2: After the management core completes grouping the input signals received in the current cycle, the management core loops through the groups, assigns each non-empty group to an idle processing core, and sets the status of the assigned processing core to occupied.

[0081] Specifically, the management core starts two layers of nested loop traversal, wherein the outer loop is the management core loop traversing each group, and when a non-empty group is traversed, the inner loop is started, that is, the management core traverses each processing core and assigns each non-empty group to an idle processing core, specifically including:

[0082] The management core traverses all processing core states;

[0083] When an idle processing core is found, the management core allocates the non-empty packet to the idle processing core by sending an IPC interrupt to the idle processing core.

[0084] Specifically, for ease of management, the numbers and states of all processing cores are stored separately. When the management core needs to allocate a processing core to a non-empty group and starts the inner loop, the numbers and state information of the processing cores are traversed. Optionally, the numbers and state information of the processing cores can be stored in a shared memory. When the management core traverses to a processing core that is idle, the non-empty group is allocated to the processing core by sending an IPC interrupt to the processing core.

[0085] Figure 2 FIG. 1 shows an example of a management core sending an IPC interrupt to an idle processing core. The IPC interrupt includes information about the signal type, storage address, generation duration, and number of signals in the group of the assigned group. Since the amount of data such as signals is large, they are generally stored in a shared memory. The management core can quickly complete the allocation and information transmission by sending an IPC interrupt to the processing core. After the processing core receives the IPC interrupt, it reads the corresponding group signal data from the shared memory and executes the processing process.

[0086] When the management core completes the allocation and sets the processing core state to occupied, it returns to continue executing the outer loop. All allocated processing cores run concurrently and process the allocated packet signals respectively. Therefore, all cores of the multi-core DSP are in an occupied processing state, resources are fully utilized, and the operating performance will not be reduced.

[0087] When the assigned processing core completes processing of the corresponding packet signal and outputs it, it notifies the management core.

[0088] Furthermore, after the assigned processing core completes processing of the corresponding packet signal and outputs it, it notifies the management core, specifically by sending an EDMA interrupt to the management core.

[0089] In this embodiment, the timing for all processing cores in the occupied state to complete processing of the corresponding group signals and output them may occur in parallel. When the processing is completed, each processing core sends a notification to the management core to inform it of the completion. Then, through the existing method of sending IPC interrupts, due to the inter-core communication mechanism of IPC interrupts, the management core may not receive notifications from some processing cores, causing communication status confusion. Therefore, the use of EDMA interrupts can avoid this problem.

[0090] Figure 3 An example of a processing core sending an EDMA interrupt signal to a management core is shown in FIG. Figure 3 The EDMA signals in the packet include a reply message identifier, a message type, an intra-group signal generation completion identifier, and a generation status.

[0091] After receiving the notification, the management core suspends the traversal and sets the state of the processing core that has completed the processing to idle;

[0092] Specifically, when the management core receives a notification, that is, receives an EDMA interrupt sent by a processing core, the management core will immediately suspend the traversal and record the suspension point. After that, the management core will set the corresponding processing core status to idle in turn based on the order of the received EDMA interrupts.

[0093] After the setting is completed, the management core returns to the pause position to continue traversing. When the management core reads the current status and number of each processing core and each processing core is occupied, the management core pauses the traversal until an EDMA interrupt is received, and continues the traversal until the input signal received in the current cycle is processed.

[0094] Specifically, in one case, when the management core traverses to a non-empty group and starts the inner loop traversal, it is found that all processing cores are occupied. Then the management core suspends traversal and waits for a processing core to complete processing. Then, an EDMA interrupt is sent to the management core. Then, the management core sets the corresponding processing core status to idle and then returns to continue traversal. When all processing cores are occupied and the management core is waiting, although the management core suspends processing, since all processing cores are in a parallel processing state, the signal processing resources of the multi-core DSP are still in full load operation until a processing core completes processing. After the management core sets its status to idle, it returns to traversal and immediately allocates non-empty groups to the idle processing core. Then, the processing core resources have not been idle, and the optimal use of processing resources is achieved.

[0095] In this embodiment, one core in the multi-core DSP is designated as a management core, and the remaining cores are processing cores. When receiving the input signal of the current cycle, the management core classifies the input signal received in the current cycle into multiple groups, and then traverses each group in a loop, assigns an idle processing core to each non-empty group, and sets the corresponding processing core state to occupied; when the processing core processes the assigned group signal, it notifies the management core by sending an EDMA interrupt; the management core pauses the traversal, sets the corresponding processing core state to idle, and then returns to continue the traversal. By traversing in a loop and continuously assigning non-empty groups to idle processing cores, all processing cores are in an uninterrupted operation state until the processing of the input signal of the current cycle is completed. Compared with the prior art, this embodiment achieves the optimal utilization of multi-core DSP resources and improves the signal processing speed and the performance indicators of the multi-core DSP.

[0096] Embodiment 2:

[0097] The second embodiment of the present invention discloses a signal generation system based on a multi-core DSP. Embodiment 2 includes all the technical features of embodiment 1. The system includes a storage module, a processing module, and an output module, wherein:

[0098] The storage module is used to receive and store the current cycle input signal, and also save the status and number of each processing core;

[0099] The processing module includes a management core and multiple processing cores, wherein:

[0100] The management core groups the input signals of the current cycle, and then traverses each group in a loop. When a non-empty group is found, the management core reads and traverses the status and number of each processing core, finds an idle processing core, allocates the non-empty group to the idle processing core, and sets the status of the allocated processing core to occupied and saved; after the processing core is allocated, it reads and processes the corresponding signal in the non-empty group, and after completion, sends the processed signal to the output module and notifies the management core; after receiving the notification, the management core pauses the traversal, sets the status of the processing core that sends the notification to idle and saves, and then returns to the pause position to continue the traversal;

[0101] The output module outputs the processed signal.

[0102] Optionally, the storage module is implemented in a shared memory, and the current cycle input signal, the status and number of each processing core are saved in the form of a structure. The following is an example of a signal parameter data structure:

[0103] typedef struct{

[0104] UINT64 m_fc; / / Carrier frequency (Hz)

[0105] UINT8 m_enable; / / Signal enable UINT8 m_analogSrcType; / / Analog signal internal data source type UINT16 m_signalIndex; / / Signal identifier UINT16 m_type; / / Signal type UINT16 m_slideTNum; / / Number of sliding pulse groups UINT32 m_B; / / Signal bandwidth (Hz)

[0106] UINT32 m_fs; / / sampling rate (Hz)

[0107] DOUBLE m_time; / / Signal generation time (s) DOUBLE m_tao; / / Signal pulse width (us)

[0108] DOUBLE m_T; / / Signal period (us)

[0109] UINT32 m_BAll; / / Signal occupied bandwidth (Hz) UINT16 m_ChangeFcType; / / Change frequency mark UINT16 m_ChangeTType; / / Change cycle mark UINT16 m_JumpV; / / Frequency hopping rate FLOAT m_voltage; / / Signal amplitude UINT8 m_JitterRange; / / Repetition rate jitter range (1%) UINT8 m_decayType; / / decay type UINT8 m_metaIndex; / / Data source type UINT8 m_isRealTime; / / Real-time signal flag UINT16 m_multipathNum; / / Multipath number UINT16 m_RealSigGroup; / / Real-time signal grouping UINT32 m_fd; / / Doppler frequency shift SINT32 m_pulseFd; / / Pulse Doppler frequency shift

[0110] FLOAT m_ricianK; / / Rician factor

[0111] UINT16 m_verify; / / Verification flag

[0112] UINT16 m_group75M; / / 75M group

[0113] UINT16 m_group375M; / / 375M group

[0114] UINT16 m_group1500M; / / 750M group

[0115] SINT32 m_dspdds; / / dsp internal frequency shift

[0116] UINT16 m_FdListLength; / / Frequency set length

[0117] UINT16 m_TlistLength; / / Periodic set length

[0118] UINT16 m_onesParam1; / / spare parameter 1,

[0119] UINT16 m_onesParam2; / / spare parameter 2

[0120] UINT8 m_genType; / / Generation method

[0121] UINT8 m_codeNum; / / Number of codes

[0122] UINT8 m_pulseType; / / Basic type

[0123] UINT8 m_subType; / / Subtype

[0124] SINT32 m_onesParam3; / / spare parameter 3

[0125] DOUBLE m_slideTStep; / / sliding step length

[0126] UINT32 m_metaLength; / / code element length

[0127] UINT32 m_sourceFs; / / symbol sampling rate / external data sampling rate SINT32 m_FdList[FDLIST_MAX_NUM]; / / Frequency collection

[0128] DOUBLE m_Tlist[TLIST_MAX_NUM]; / / Periodic collection

[0129] MULTIPATH_PARAM m_multipathList[MULTIPATH_MAX_NUM]; / / Multipath parameters

[0130] }SIG_PARAM_STRU;

[0131] Through the implementation of the structure, the efficiency of data reading and processing can be further improved;

[0132] The processing module sets one core in the multi-core DSP as a management core, and the remaining cores are set as processing cores, and stores the status and number of each processing core in the storage module; the management core reads the current cycle input signal stored in the storage module, and after grouping the current cycle input signal, stores the information of each group and the signal information in each group in the storage module; the management core starts a loop to traverse each group, and for the group that is not empty, it traverses the status of each processing core stored in the storage module to find an idle processing core, and sends the group information to the idle processing core by sending an IPC interrupt to the idle processing core found, and updates the status of the idle processing core to occupied and updates the corresponding record stored in the storage module; the processing core obtains the signal parameters of the assigned group by reading the structure from the storage module based on the received IPC interrupt, and starts processing and generates an output signal; when the processing core completes the processing, it sends the generated signal to the output module, and notifies the completion status by sending an EDMA interrupt to the management core, then the management core suspends the traversal, sets the status of the processing core corresponding to the sent EDMA interrupt to idle, and then returns to continue the traversal.

[0133] The output module outputs the output signal.

[0134] In this embodiment, through a simple system configuration, the multi-core DSP can quickly implement the system disclosed in this embodiment, and achieve fast signal processing and optimal use of multi-core DSP resources.

[0135] Embodiment 3:

[0136] The third embodiment of the present invention discloses an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, a signal generation method based on a multi-core DSP disclosed in Embodiment 1 is implemented.

[0137] Embodiment 4:

[0138] A fourth embodiment of the present invention discloses a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the signal generation method based on a multi-core DSP disclosed in the first embodiment is implemented.

[0139] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0140] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A signal generation method based on multi-core DSP, characterized in that: The DSP includes a management core and multiple processing cores, and performs the following process on the input signal received in each cycle, and the process specifically includes: The management core classifies the input signal received in the current cycle into a plurality of groups; The management core loops through each group, assigns each non-empty group to an idle processing core, and sets the status of the assigned processing core to occupied; When the assigned processing core completes processing of the corresponding packet signal and outputs it, the management core is notified; After receiving the notification, the management core suspends the traversal and sets the state of the processing core that has completed the processing to idle; The management core returns to the pause position and continues traversal until the input signal received in the current cycle is processed completely.

2. The signal generation method based on multi-core DSP according to claim 1, characterized in that: The management core classifies the input signal received in the current period into a plurality of groups through the following process, wherein the process specifically includes: S21: Sort the input signals received in the current period from low to high according to the carrier frequency to obtain a sequence to be grouped; S22: establishing a new group based on the first signal in the sequence to be grouped and setting grouping conditions, and moving the first signal into the new group and removing it from the sequence to be grouped; S23: traverse all remaining signals in the sequence to be grouped, move signals that meet the grouping conditions into the new group in turn, and remove them from the sequence to be grouped, until no signal that meets the grouping conditions can be moved into the new group or the new group is full, then return to iteratively execute S22-S23 until all groups are established and there is no groupable signal in the sequence to be grouped; S24: Combining the signals in all the groups into a whole, and saving the center frequency of the whole signal.

3. The signal generation method based on multi-core DSP according to claim 2, characterized in that: The inclusion conditions specifically refer to that the signal must simultaneously meet the sampling rate, frequency, and validity requirements, where: The sampling rate requirement refers to that the sampling rate of the signal is the same as the sampling rate of the first signal; The frequency requirement means that the signal start frequency is not less than the packet start frequency, and the signal end frequency is not greater than the packet end frequency, wherein: The packet start frequency is the difference between the carrier frequency of the first signal and half of its bandwidth. The group end frequency is the sum of the group start frequency and 80% of the first signal sampling rate; The validity requirement is that the signal is a non-real-time signal and the signal flag is valid.

4. The signal generation method based on multi-core DSP according to claim 3 is characterized in that: When the signal meets the sampling rate requirement, the validity requirement, and does not meet the frequency requirement, the new group is full; When no signal can be moved into the new group or the new group is full, the group end frequency is updated to the end frequency of the last signal in the new group.

5. The signal generation method based on multi-core DSP according to claim 4, characterized in that: The allocating each non-empty group to an idle processing core specifically includes: The management core traverses all processing core states; When an idle processing core is found, the management core allocates the non-empty packet to the idle processing core by sending an IPC interrupt to the idle processing core.

6. The signal generation method based on multi-core DSP according to claim 5, characterized in that: After the assigned processing core completes processing of the corresponding packet signal and outputs it, it notifies the management core, specifically by sending an EDMA interrupt to the management core.

7. The signal generation method based on multi-core DSP according to claim 6, characterized in that: When the management core reads the current status and number of each processing core and each processing core is occupied, the management core suspends traversal until an EDMA interrupt is received and the traversal is continued.

8. A signal generation system based on multi-core DSP, characterized in that: The system includes a storage module, a processing module, and an output module, wherein: The storage module is used to receive and store the current cycle input signal, and also save the status and number of each processing core; The processing module includes a management core and multiple processing cores, wherein: The management core groups the input signals of the current cycle, and then traverses each group in a loop. When a non-empty group is found, the management core reads and traverses the status and number of each processing core, finds an idle processing core, allocates the non-empty group to the idle processing core, and sets the status of the allocated processing core to occupied and saved; after the processing core is allocated, it reads and processes the corresponding signal in the non-empty group, and after completion, sends the processed signal to the output module and notifies the management core; after receiving the notification, the management core pauses the traversal, sets the status of the processing core that sends the notification to idle and saves, and then returns to the pause position to continue the traversal; The output module outputs the processed signal.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, a signal generation method based on a multi-core DSP as described in claims 1 to 7 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, a signal generation method based on a multi-core DSP is implemented as described in any one of claims 1 to 7.

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