Hard lock detection method and system of virtualization system, storage medium and electronic equipment

Abstract

The invention discloses a hard lock detection method and system of a virtualization system, a storage medium and electronic equipment. The method comprises the following steps: constructing a topology network, carrying out interrupt processing on a plurality of processors of the topology network and timers corresponding to the plurality of processors, and carrying out mutual detection among the plurality of processors; judging whether the interrupt count values of the detection processor and the detected processor are the same or not, and if yes, indicating that the detected processor does not respond to the interrupt; if not, the response of the detected processor is interrupted; a hard lock detection method is designed, and a ring topology network capable of being dynamically updated is designed, so that the detection reliability of the hard lock is improved, a hard lock problem can be quickly reported to a system, and the occurrence condition of the hard lock is reserved to the greatest extent; and the possibility of taking rescue measures and quickly positioning the hard lock problem after the problem of a PMU-interruption-free system such as hypervisor is provided.

Description

Technical Field

[0001] The present invention relates to the field of automobile electronic system development, and in particular to a hard lock detection method, system, storage medium and electronic equipment of a virtualized system. Background Art

[0002] With virtualization technology, developers can create multiple simulated environments or dedicated resources based on a single physical hardware system. Software called "Hypervisor" (virtual machine monitor) can be directly connected to the hardware to divide a system into different, separate and secure environments, namely virtual machines (VMs). Taking the ACRN hypervisor in the automotive electronics field as an example, ACRN hypervisor can be used to build a software-defined cockpit (SDC) or in-vehicle entertainment system (IVE). As a reference implementation, ACRN can provide a good foundation for embedded hypervisor manufacturers' solutions, as well as a set of reference designs for I / O device virtualization.

[0003] However, compared with conventional Unix-like systems, existing virtualization solutions still have some problems. There is a common problem in Unix-like systems - "chip lockup", namely Lockup. Lockup is divided into two types: soft lockup and hard lockup. Its essence is that the kernel occupies the CPU, and the CPU not only cannot execute other processes, but also no longer responds to interrupts. It is difficult to simulate the NMI (Non-Maskable Interrupt) interrupt of PMU (Performance Monitoring Unit) on Arcn hypervisor. The main reason is that Arcn hypervisor is a virtualization layer, which provides an intermediate layer between hardware and operating system. This architecture will introduce certain complexity and limitations, making it difficult to directly simulate the NMI interrupt of PMU. The virtualization layer needs to manage and allocate hardware resources and provide them to virtual machines for use. However, for some special hardware functions, such as PMU, the virtualization layer may not be able to directly simulate or provide the corresponding interrupt mechanism. Therefore, for scenarios such as hypervisor, the probability of hard lockup problems is high for such Unix systems and embedded systems with a single OS, and the complexity and cost of problem analysis are relatively high. Summary of the invention

[0004] The purpose of the present invention is to solve the shortcomings of the prior art and to propose a hard lock detection method, system, storage medium and electronic device for a virtualization system.

[0005] In order to achieve the above object, the present invention adopts the following technical solution: a hard lock detection method for a virtualization system, comprising:

[0006] S1: construct a topology network, perform interrupt processing on a number of processors of the topology network and timers corresponding to the processors, and perform mutual detection between the processors;

[0007] S2: Determine whether the interrupt count values ​​of the detecting processor and the detected processor are the same. If they are the same, it means that the detected processor does not respond to the interrupt; if they are different, it means that the detected processor responds to the interrupt.

[0008] As a further description of the above technical solution: after step S2, if it is determined that the interrupt count values ​​of the detecting processor and the detected processor are different, then within the time threshold, the system load average is read and saved in the system load queue, the system load queue is averaged, and the difference between the average value and the system load average is calculated. The difference is compared with the update detection threshold to determine whether the topology network is updated.

[0009] As a further description of the above technical solution: after step S2, if it is determined that the interrupt count values ​​of the detecting processor and the detected processor are the same, the interrupt miss number of the timer corresponding to the detected processor is increased, and the interrupt miss number is compared with the set interrupt detection threshold. If it is greater than the interrupt detection threshold, an interrupt signal is sent to the detected processor. If it is less than the interrupt detection threshold, the interrupt processing is exited.

[0010] As a further description of the above technical solution: after receiving the interrupt signal, the detected processor performs stack backtracking to locate the hard lock position.

[0011] As a further description of the above technical solution: in the step S1, the topology network is a ring network, and the mutual detection between the several processors includes: controlling several processors to detect adjacent processors one by one, and the end processor detects the head-end processor, and after entering the interrupt processing, obtaining the interrupt count values ​​of the several processors.

[0012] As a further description of the above technical solution: if the above are not the same, it means that the detected processor responds to the interrupt specifically including:

[0013] If they are not the same, the interrupt processing is responded to, the interrupt count value of the detected timer is assigned to the interrupt count value stored in the detection processor, and the interrupt miss count of the detected timer stored in the detection processor is cleared.

[0014] As a further description of the above technical solution: the step of constructing a topological network includes: constructing an adjacent edge data structure according to a processor matrix, and calculating weights, sorting the adjacent edges according to the weights and then traversing them to form an edge set, constraining the edge set through an algorithm model, and generating the topological network.

[0015] Also included is a detection system, which is applicable to the detection method described in any one of the above technical solutions, including:

[0016] A collection module collects data sets of timer setting time threshold, interrupt detection threshold and update detection threshold and processor;

[0017] The interrupt test module performs interrupt processing on several processors and several timers, detects and records the interrupt count value and the number of interrupt misses;

[0018] A topology network updating module, which updates the topology network according to the data in the acquisition module and the interruption test module;

[0019] The judgment module is used to judge the time threshold, the interruption detection threshold and the update detection threshold.

[0020] It also includes a computer-readable storage medium storing a computer program for running the detection method, wherein the computer program enables a computer to execute the detection method as described in any one of the above technical solutions.

[0021] Also included is an electronic device, comprising:

[0022] one or more processors; memory; and

[0023] One or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the programs include a program for executing a detection method as described in any one of the above technical solutions.

[0024] The above technical solution has the following advantages or beneficial effects:

[0025] 1. Designed a hard lock detection method based on hypervisor and other systems that lack PMU and NMI interrupt systems, and designed a ring topology network that can be dynamically updated to improve the reliability of hard lock detection.

[0026] 2. It can quickly report hard lock problems to the system and retain the hard lock occurrence situation to the greatest extent, making it possible for hypepvisor and other PMU-free interruption systems to take rescue measures and quickly locate hard lock problems after the problem occurs. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A flow chart of the detection method proposed by the present invention;

[0028] Figure 2 A flowchart for performing interrupt processing detection in the present invention;

[0029] Figure 3 A flowchart of topology network updating in the present invention;

[0030] Figure 4 A flowchart for generating a topological network in the present invention;

[0031] Figure 5 It is a structural schematic diagram of the detection system proposed by the present invention;

[0032] Legend:

[0033] 1. Acquisition module; 2. Interruption test module; 3. Topology network update module; 4. Judgment module. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] The applicant found in the research that the current Unix-like system provides a mature solution for detecting hard lockup, and its principle uses the NMI perf event of PMU. Use per-cpu hrtimer interrupt to record the number of interrupts, and configure perf event to trigger NMI interrupt. Every time NMI interrupt comes, the number of hrtimer interrupts will be read and saved. When the number of hrtimer interrupts detected in NMI interrupt processing is the same as the last saved value, it means that the hrtimer interrupt did not come during the two NMI interrupts. It can be considered that the normal interrupt is closed, that is, the system has hard lockup.

[0036] However, it is difficult to simulate the NMI (Non-Maskable Interrupt) interrupt of PMU (Performance Monitoring Unit) on Arcn hypervisor. The main reasons are as follows:

[0037] 1. Virtualization layer limitations: Arcn hypervisor is a virtualization layer that provides an intermediate layer between the hardware and the operating system. This architecture introduces certain complexities and limitations, making it difficult to directly simulate the NMI interrupt of the PMU. The virtualization layer needs to manage and allocate hardware resources and provide them to virtual machines, but for some special hardware functions, such as PMU, the virtualization layer may not be able to directly simulate or provide the corresponding interrupt mechanism.

[0038] 2. PMU’s particularity: PMU is a hardware unit used for performance monitoring and analysis. It is usually tightly integrated with the processor and has a highly specialized and dedicated design. PMU usually provides a set of performance counters and event selectors for measuring and tracking various performance indicators of the processor. The design and implementation of PMU usually depends on the details of the underlying hardware platform and processor architecture, which makes it complex and difficult to simulate PMU in a virtualized environment.

[0039] 3. Limitations of NMI interrupts: NMI is a special type of interrupt that has high priority and is non-maskable. On actual hardware platforms, NMI interrupts are usually used to handle some critical system events, such as hardware failures, software exceptions, etc. Due to the particularity of NMI interrupts, it needs to interact directly with the processor and operating system to ensure timely processing and response. Simulating NMI interrupts in a virtualized environment requires an in-depth understanding of the interrupt handling mechanism of the processor and operating system, and implementing the corresponding interrupt simulation and processing logic in the virtualization layer.

[0040] In summary, it is very difficult to simulate the NMI interrupt of PMU on Arcn hypervisor, and the solution is difficult to implement. The probability of hardlockup problem is greater than that of embedded systems with a single OS, and the complexity and cost of problem analysis are relatively high.

[0041] Reference Figure 1 In order to solve the above technical problems, the present invention provides an embodiment: a hard lock detection method for a virtualization system, comprising:

[0042] S1: construct a topology network, perform interrupt processing on several processors of the topology network and timers corresponding to the several processors, and perform mutual detection between the several processors;

[0043] In this embodiment, a suitable topology is selected, such as star, bus, ring, mesh, etc. Different topologies have different characteristics and applicable scenarios. The best topology is determined according to factors such as application requirements, number of devices, communication requirements, etc., and a suitable communication protocol is selected according to the characteristics and requirements of the topological network. Common communication protocols include TCP / IP, UDP, CAN bus, etc. Several processors are connected according to the selected topology. Physical connection methods such as Ethernet cables, serial ports, wireless communications, etc. can be used. A timer is configured for each processor, and the timer can be used to trigger specific tasks or events at regular intervals. For example, a timer can be set to perform operations such as data acquisition, status monitoring, and communication regularly. When the timer is triggered or other specific events occur, the processor needs to perform interrupt processing. Interrupt processing can respond to events quickly and avoid delayed execution of tasks. A mutual detection mechanism between processors is designed to ensure the reliability and stability of the network.

[0044] S2: Determine whether the interrupt count values ​​of the detecting processor and the detected processor are the same. If they are the same, it means that the detected processor does not respond to the interrupt; if they are different, it means that the detected processor responds to the interrupt.

[0045] In this embodiment, in the processor system, an interrupt is an important event notification mechanism used to respond to external events or internal abnormal conditions. Each processor usually has an interrupt counter for recording the number of interrupts that occur. When an interrupt occurs, the interrupt counter increases the corresponding value. By monitoring the value of the interrupt counter, the response of the processor to the interrupt can be understood. Determining whether the interrupt count values ​​of the detecting processor and the detected processor are the same is mainly to determine whether the detected processor responds to the interrupt normally. If the interrupt count values ​​of the two processors are the same, it means that the detected processor may not handle the interrupt correctly, or a fault has occurred that causes the interrupt to not be responded to. If the interrupt count values ​​are different, it means that the detected processor has responded to the interrupt and is handling the interrupt event normally.

[0046] The timer sets the time threshold, detection threshold and update detection threshold, which are adjusted and set through the timer interface;

[0047] The data set of the processor includes: sequence number, interrupt count value of the timer, interrupt count value of the processor, interrupt miss count of the timer and system load queue.

[0048] In this embodiment, the time threshold, detection threshold and update detection threshold set by the timer are adjusted through the / proc interface. / proc is a virtual file system, which provides a method for accessing kernel and process information through a file system interface. In the Linux system, the / proc directory contains a large number of files and directories related to the system status. These files and directories do not actually exist in the storage device on the hard disk, but are dynamically generated by the kernel in the memory. Each running process has a corresponding directory under the / proc directory, named with the process ID, such as / proc / 1234 / . In these directories, you can view information such as the status of the process, resource usage, and open files. Some system parameters can be dynamically configured by modifying the files in / proc. By reading the files in / proc, you can debug and analyze the performance of the system. The detection threshold and time threshold are adjusted and set through the / proc interface of the timer.

[0049] Initialize the processor topology relationship, establish a neighboring core monitoring relationship network, adjust the timer data information through the / proc interface, so that the corresponding processor establishes a data structure set, confirms the trigger period of interrupt processing by setting the time threshold, modifies the data information through the / proc interface, adjusts the control timer interrupt to be periodically triggered within the time threshold, interrupts the processor, and the corresponding timer counts the interrupts to obtain the interrupt count value.

[0050] The data information includes the cycle, topology network update interval, mean load difference Min value, mean load difference Max value, and establishes a data structure for each processor, including the serial number that the processor needs to detect, the interrupt count value of the timer, the interrupt count value of the processor, the number of interrupt misses of the timer, and the system load fifo queue.

[0051] The topology network is a ring network, and the mutual detection between several processors includes: controlling several processors to detect adjacent processors one by one, and the end processor detects the head end processor. After the timer enters the interrupt processing, the topology network is accessed to obtain the serial numbers of several processors and the interrupt count value of the timer.

[0052] In this embodiment, the types of topological networks include star network, bus network, ring network, tree network, mesh network and hybrid network. In a star network, all devices are directly connected through a centralized network device (such as a hub, switch). All data traffic is forwarded and managed through this central point. A star network is easy to install and maintain, but a failure of the central device may affect the entire network.

[0053] In a bus network, all devices are connected together through a shared communication medium (such as a cable). Data is transmitted over this bus, and each device listens to the data transmission and decides whether to receive it. Bus networks are simple and low cost, but performance may degrade as more devices are added or the distance increases.

[0054] In a ring network, each device is connected to two adjacent devices, forming a closed loop. Data is passed along the loop, and each device listens to and processes the data passing through. The ring network avoids collisions, but if any point in the ring fails, the entire network may be affected.

[0055] A tree network is a hierarchical structure, similar to the branching structure of a star network. It connects star networks to form a larger network and is usually used in large enterprises or organizations. A tree network has good scalability and segmentation capabilities, but has a high management complexity.

[0056] In a mesh network, each device is directly connected to every other device in the network. This approach provides a high degree of redundancy and reliability because multiple paths allow data to be transmitted around failure points. Mesh networks have high wiring costs and complex configurations and are typically used in critical application scenarios that require high availability and performance.

[0057] A hybrid network is a combination of the above topologies. It can take into account the advantages of various topologies to meet specific performance and reliability requirements. Hybrid networks are common in large enterprises or cross-geographical network deployments.

[0058] The corresponding topology network type can be selected according to actual design needs. In this embodiment, the topology network is preferably a ring topology network. According to the characteristics of the ring topology network, the unresponsive processor is located. In the ring topology network, the number of processors is set to at least three, which can realize sequential detection and head-to-tail mutual detection.

[0059] After step S2, if it is determined that the interrupt count values ​​of the detecting processor and the detected processor are different, the system load average is read within the time threshold, saved in the system load queue, the system load queue is averaged, the difference between the average value and the system load average is calculated, the difference is compared with the update detection threshold, and it is determined whether the topology network is updated.

[0060] In this embodiment, multiple system load averages within a time threshold are read and saved in a system load queue. Optionally, the system load average is read once every 1 minute, 5 minutes, 10 minutes or 15 minutes until all system load averages within the time threshold are read. The average of several system load averages in the system load queue is calculated, and the difference between the average and the latest system load average is calculated.

[0061] This application uses a system load FIFO queue, which only needs to maintain a sequentially arranged task list, and the tasks are arranged in the order of their submission or entry into the system. The task that enters the queue first will be processed first, and the later tasks will be queued in turn to wait for execution. Compared with other more complex scheduling algorithms (such as priority scheduling or time slice rotation), the FIFO queue does not consider the priority or execution time of the task, but only determines the execution order based on the order in which the tasks enter. It is suitable for simple task queuing and execution management, and is compatible with the designed ring topology network. It detects several processors and can quickly and accurately locate the unresponsive processor;

[0062] Reference Figure 2 , the specific steps are as follows:

[0063] S21: within the time threshold, detect whether the topology network needs to be updated, calculate the average value of the system load queue, and if the difference value with the latest system load is between [average load difference Min value, average load difference Max value], then update the topology network;

[0064] S22: If the difference value is between [-average load difference Min value, +average load difference Min value], and the topology network has been updated once before, no update is performed;

[0065] S23: If the difference value is less than the mean load difference Min value, or greater than the mean load difference Max value, no update is performed, the interrupt processing is exited, and the next interrupt is waited.

[0066] In this embodiment, the update detection threshold includes the mean load difference Min value and the mean load difference Max value. In order to ensure that the detection topology network is as consistent as possible with the current load condition of the system, it is necessary to update the detection topology network after a certain period of time and after meeting the update conditions, and determine whether the time threshold is reached, and update the topology network. If the time threshold is reached, the array of the system load queue is averaged. If the average value differs from the latest system load within [± mean load difference Min value - mean load difference Max value], it is considered that the current system is relatively stable as a whole and the topology network can be updated.

[0067] If the difference between the average and the latest system load is within [-average load difference Min value, + average load difference Min value] and the topology network has been updated once before, it is considered that the busyness of the system business has not changed much during this period, and the topology network does not need to be updated;

[0068] If the system load difference is less than the average load difference Min value, or greater than the average load difference Max value, no update is performed, the interrupt processing is exited, and the next interrupt is waited.

[0069] If it is determined that the interrupt count values ​​of the detecting processor and the detected processor are the same, the interrupt miss count of the timer corresponding to the detected processor is increased, and the interrupt miss count is compared with the set interrupt detection threshold. If it is greater than the interrupt detection threshold, an interrupt signal is sent to the detected processor. If it is less than the interrupt detection threshold, the interrupt processing is exited.

[0070] In this embodiment, the interrupt count value of the timer corresponding to the detecting processor is obtained, and compared with the interrupt count value stored in the detected processor to determine whether they are the same. If they are not the same, the interrupt count value of the timer corresponding to the detected processor is assigned to the detected processor, and the interrupt miss count of the timer corresponding to the detected processor is cleared, and the system load average is read and saved in the system load queue; if they are the same, it means that the detected processor has become unable to respond, and the interrupt miss count of the timer of the detecting processor is increased by 1. After adding 1, it is determined whether the value is greater than or equal to the detection threshold set by the / proc interface. If it is less than the detection threshold, the interrupt processing is exited and the next interrupt is waited for; if it is greater than or equal to, it means that the interrupt has not been responded to for a long time. At this time, the detecting processor sends an interrupt signal to the detected processor. The interrupt signal can be an IPI signal (NMI_VECTOR, which refers to the entry address or vector of the NMI interrupt handler). In a multi-processor system, IPI (NMI_VECTOR) is an interrupt sent to other processors by way of NMI, or a specific handler entry address, which is used to handle related interrupt events.

[0071] Reference Figure 3 In this embodiment, the system first detects according to the default ring topology network, and for each processor core in the order of 0, 1, 2, 3...N, specifies that core 0 detects core 1, core 1 detects core 2, and so on. The control processors detect each other and perform interrupt processing. The operation after the timer corresponding to each processor enters the interrupt processing is as follows:

[0072] S31: accessing the ring topology network to obtain the serial number of the detected processor;

[0073] S32: the timer interrupt count value corresponding to the detected processor is increased by 1, and the timer interrupt is responded to;

[0074] S33: Obtain the interrupt count value of the timer corresponding to the detected processor through the serial number; and compare it with the interrupt count value stored in the detection processor to determine whether they are the same. If they are not the same, it means that the detected processor can respond to the interrupt of the timer corresponding to the detected processor. The interrupt count value of the timer corresponding to the detected processor is assigned to the interrupt count value of the detecting processor, and the interrupt miss count of the timer saved by the detection processor is cleared.

[0075] After receiving the interrupt signal, the detected processor performs stack backtracking to locate the hard lock position

[0076] This embodiment uses stack backtracking to locate the unresponsive processor. In the stack backtracking algorithm, the solution space of the problem is usually organized into a tree structure, and each node represents a state or choice of the problem. By recursively calling the function, the solution space can be explored along the depth-first path of the tree. When it is found that the current path cannot continue (that is, there are no more choices), it returns to the previous recursive state and tries another choice. The stack is used to save the state information of each recursive layer. Through the principle of this algorithm, the unresponsive processor can be accurately located, and the positioning accuracy can be improved.

[0077] The steps of constructing a topological network include: constructing an adjacent edge data structure according to a processor matrix, calculating weights, sorting adjacent edges according to weights and traversing them to form an edge set, constraining the edge set through an algorithm model, and generating a topological network.

[0078] For a hypervisor with multiple virtual clients, the business busyness is unknown. Static topology detection networks usually cannot cope with this scenario well. In addition, due to computer locality, in a computer hardware system, the access patterns of programs and data tend to be concentrated in a relatively tight spatial range. For system abnormalities such as hard lockup, when it occurs in the same virtual client, it is very likely that other processors on it will also become abnormal. In order to accurately retain effective information such as the stack on the abnormal core, locate the problem as soon as possible and maximize the detection efficiency, it is very necessary to establish a topology detection network across virtual clients and as many adjacent cores as possible.

[0079] Reference Figure 4 In this embodiment, the minimum spanning tree algorithm is used as an example to model and generate a topological network. It is assumed that the complete graph formed by the processor matrix is ​​a dense graph. The Kruskal algorithm model is used for calculation. The specific process is as follows:

[0080] S311: construct an adjacent edge data structure according to the processor matrix, generate adjacent edge objects, and construct a complete graph matrix, where the matrix elements are adjacent edge objects;

[0081] S312: Sort all edges in ascending order of weight, and initialize an empty spanning tree linked list and an empty edge set;

[0082] S313: Traverse the sorted edge set starting from the edge with the smallest weight, and determine whether the two nodes of the current edge are in the same connected component. If yes, add the edge to the spanning tree and merge the two nodes into the same connected component. If no, discard the edge and do not select it afterwards.

[0083] S314: Check whether the spanning tree meets the constraint conditions. If not, traverse again. If the spanning tree meets the constraint conditions, connect the first and last endpoints on the spanning tree to form a ring topology network, and the update is completed.

[0084] The adjacent edge data structure contains the endpoint serial number, the virtual client number to which the processor belongs, and the weight wij=|ai-aj| (where i and j represent two nodes respectively);

[0085] The constraint is that for each node v, find two adjacent nodes u1 and u2. If v, u1 and u2 belong to the same category, the spanning tree does not meet the constraint.

[0086] The difference in weight between any two nodes is as large as possible. For each edge (u, v), calculate its weight w(u, v). If there is an edge (u, v') where v' is not equal to v and w(u, v') is less than w(u, v), the spanning tree does not meet the constraints.

[0087] Example 2

[0088] Reference Figure 5 , a detection system, the detection system is applicable to the detection method of any one of the above technical solutions, including:

[0089] Acquisition module 1, collecting timer setting time threshold, interrupt detection threshold and update detection threshold and processor data set;

[0090] Interrupt test module 2, performs interrupt processing on several processors and several timers, detects and records interrupt count values ​​and interrupt miss counts;

[0091] A topology network updating module 3 is used to update the topology network according to the data in the acquisition module and the interruption test module;

[0092] The judgment module 4 is used for judging the time threshold, the interruption detection threshold and the update detection threshold.

[0093] It is understandable that the detection system provided in the embodiment of the present invention corresponds to the above-mentioned detection method, and the explanations, examples, beneficial effects and other parts of the relevant contents can refer to the corresponding contents in the detection method, which will not be repeated here.

[0094] Example 3

[0095] Also included is a computer-readable storage medium storing a computer program for running the detection method, wherein the computer program causes a computer to execute the following steps:

[0096] S1: construct a topology network, perform interrupt processing on several processors of the topology network and timers corresponding to the several processors, and perform mutual detection between the several processors;

[0097] S2: Determine whether the interrupt count values ​​of the detecting processor and the detected processor are the same. If they are the same, it means that the detected processor does not respond to the interrupt; if they are different, it means that the detected processor responds to the interrupt.

[0098] Among them, the computer-readable storage medium can be a computer storage medium or a communication medium. The communication medium includes any medium that facilitates the transmission of a computer program from one place to another. The computer storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer. For example, a computer-readable storage medium is coupled to a processor so that the processor can read information from the computer-readable storage medium and write information to the computer-readable storage medium. Of course, the computer-readable storage medium can also be a component of the processor. The processor and the computer-readable storage medium can be located in an application-specific integrated circuit (ASIC). In addition, the ASIC can be located in a user device. Of course, the processor and the computer-readable storage medium can also exist in a communication device as discrete components.

[0099] Specifically, the computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0100] Example 4

[0101] Also included is an electronic device, comprising:

[0102] one or more processors; memory; and

[0103] One or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more processors, the programs comprising steps for performing the following steps:

[0104] S1: construct a topology network, perform interrupt processing on several processors of the topology network and timers corresponding to the several processors, and perform mutual detection between the several processors;

[0105] S2: Determine whether the interrupt count values ​​of the detecting processor and the detected processor are the same. If they are the same, it means that the detected processor does not respond to the interrupt; if they are different, it means that the detected processor responds to the interrupt.

[0106] Memory is used to store computer programs. The memory may include high-speed random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk memory, and may also be a USB flash drive, a mobile hard disk, a read-only memory, a disk or an optical disk.

[0107] The processor is used to execute the computer program stored in the memory. The processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. The general-purpose processor can be a microprocessor or the processor can be any conventional processor, etc. The steps of the method disclosed in the invention can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor.

[0108] Optionally, the memory can be independent or integrated with the processor.

[0109] When the memory is a device independent of the processor, the electronic device may further include a bus. The bus is used to connect the memory and the processor. The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. The bus may be divided into an address bus, a data bus, a control bus, and the like.

[0110] It should be noted that, through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiment. In this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements that are not explicitly listed, or also includes elements inherent to such process, method, article or device. Without more constraints, an element defined by the phrase "comprising a..." does not exclude the existence of other identical elements in the process, method, article or apparatus comprising the element.

[0111] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it is still possible for those skilled in the art to modify the technical solutions described in the aforementioned embodiments or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A hard lock detection method for a virtualization system, characterized in that: include: S1: construct a topology network, perform interrupt processing on a number of processors of the topology network and timers corresponding to the processors, and perform mutual detection between the processors; S2: Determine whether the interrupt count values ​​of the detecting processor and the detected processor are the same. If they are the same, it means that the detected processor does not respond to the interrupt; if they are different, it means that the detected processor responds to the interrupt.

2. The detection method according to claim 1, characterized in that: After step S2, if it is determined that the interrupt count values ​​of the detecting processor and the detected processor are different, the system load average is read within the time threshold, saved in the system load queue, the system load queue is averaged, the difference between the average value and the system load average is calculated, and the difference is compared with the update detection threshold to determine whether the topology network is updated.

3. The detection method according to claim 1, characterized in that: After step S2, if it is determined that the interrupt count values ​​of the detecting processor and the detected processor are the same, the interrupt miss count of the timer corresponding to the detected processor is increased, and the interrupt miss count is compared with the set interrupt detection threshold. If it is greater than the interrupt detection threshold, an interrupt signal is sent to the detected processor. If it is less than the interrupt detection threshold, the interrupt processing is exited.

4. The detection method according to claim 3, characterized in that: After receiving the interrupt signal, the detected processor performs stack backtracing to locate the hard lock position.

5. The detection method according to claim 1, characterized in that: In step S1, the topology network is a ring network, and the mutual detection between the processors includes: controlling the processors to detect adjacent processors one by one, and the end processor to detect the head processor, and after entering the interrupt processing, obtaining the interrupt count values ​​of the processors.

6. The detection method according to claim 1 or 2, characterized in that: If they are not the same, it means that the detected processor responds to the interrupt specifically including: If they are not the same, the interrupt processing is responded to, the interrupt count value of the detected timer is assigned to the interrupt count value stored in the detection processor, and the interrupt miss count of the detected timer stored in the detection processor is cleared.

7. The detection method according to claim 1, characterized in that: The steps of constructing the topological network include: constructing an adjacent edge data structure according to a processor matrix, calculating weights, sorting adjacent edges according to weights and then traversing to form an edge set, constraining the edge set through an algorithm model, and generating the topological network.

8. A detection system, characterized in that: The detection system is applicable to the detection method according to any one of claims 1 to 7, comprising: A collection module collects data sets of timer setting time threshold, interrupt detection threshold and update detection threshold and processor; The interrupt test module performs interrupt processing on several processors and several timers, detects and records the interrupt count value and the number of interrupt misses; A topology network updating module, which updates the topology network according to the data in the acquisition module and the interruption test module; The judgment module is used to judge the time threshold, the interruption detection threshold and the update detection threshold.

9. A computer-readable storage medium, characterized in that: It stores a computer program for running the detection method, wherein the computer program enables a computer to execute the detection method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: include: one or more processors; Memory; as well as One or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, the programs comprising instructions for executing the detection method according to any one of claims 1 to 7.

Images