Electronic equipment, access method and device and storage medium

Abstract

The embodiment of the invention provides electronic equipment, an access method and device and a storage medium, and relates to the technical field of computers. The electronic equipment comprises a bus, master equipment arranged on the bus, and slave equipment arranged on the bus, the master device includes: a processor; the electronic equipment further comprises a memory protection unit, the memory protection unit is integrated in the bus, or the memory protection unit is arranged at an interface of the slave equipment, or the memory protection unit is arranged at a position between the bus and the interface of the slave equipment; and the memory protection unit is used for limiting the access of the master device to the slave device. According to the method, access of the processor core to the slave device can be limited, access of other master devices except the processor core to the slave device can also be limited, and the safety of data in the slave device is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an electronic device, an access method, an access device and a storage medium. Background Art

[0002] In electronic devices, a memory protection unit (MPU) is usually integrated into a core (such as a processor) to control the processor's access rights to certain data in a slave device.

[0003] However, the master device that actively initiates access in the electronic device includes not only the processor core, but also the master device outside the core. The memory protection unit in the existing electronic device cannot restrict the master device outside the core from accessing certain data in the slave device, resulting in poor security performance of the data in the slave device. Summary of the invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide an electronic device that overcomes the above problems or at least partially solves the above problems, so as to improve the security performance of data.

[0005] In a first aspect, the present invention provides an electronic device, comprising: a bus, a master device arranged on the bus, and a slave device arranged on the bus; the master device comprises: a processor; The electronic device further comprises: a memory protection unit, the memory protection unit being integrated in the bus, or the memory protection unit being arranged at the interface of the slave device, or the memory protection unit being arranged at a position between the bus and the interface of the slave device; The memory protection unit is used to limit the access of the master device to the slave device.

[0006] In a second aspect, the present invention provides an access method, which is applied to a memory protection unit in any of the aforementioned electronic devices; the access method comprises: Receiving an access request sent by a master device to a target slave device via a bus; the access request includes: a target address and an access operation; Obtaining a configuration file corresponding to the target address; the configuration file includes: configuration access rights of the master device for the access operation of the target address; In a case where it is determined based on the configuration file that the configured access right of the master device for the access operation to the target address is permitted, the access request to the target slave device is permitted.

[0007] In a third aspect, the present invention provides an access device, which is applied to a memory protection unit in any of the aforementioned electronic devices; the access device comprises: A receiving module, used for receiving an access request sent by a master device to a target slave device via a bus; the access request includes: a target address and an access operation; A configuration file acquisition module, used to acquire a configuration file corresponding to the target address; the configuration file includes: configuration access rights of the master device for the access operation of the target address; The access permission module is used to allow the access request to the target slave device when it is determined based on the configuration file that the configured access permission of the access operation of the master device to the target address is allowed.

[0008] In a fourth aspect, the present invention provides an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned access method when executing the program.

[0009] In a fifth aspect, the present invention provides a readable storage medium, which, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to execute the above-mentioned access method.

[0010] In a sixth aspect, the present invention provides a computer program product, comprising instructions, which, when executed by a processor in an electronic device, enable the electronic device to execute any one of the aforementioned access methods.

[0011] The present invention includes the following advantages: In the present application, in an electronic device, a memory protection unit is integrated in a bus, or a memory protection unit is arranged at an interface of a slave device, or a memory protection unit is arranged at a position between the bus and an interface of a slave device. The memory protection unit is arranged at any one of the above three positions, and any access of a master device to a slave device must first pass through the memory protection unit. Therefore, the memory protection unit can not only limit the access of the processor core to the slave device, but also limit the access of other master devices other than the processor core to the slave device, thereby improving the security of data in the slave device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0013] Figure 1is a schematic structural diagram of a first electronic device provided by an embodiment of the present invention; Figure 2 is a schematic structural diagram of a second electronic device provided by an embodiment of the present invention; Figure 3 It is a schematic diagram of connection between a memory protection unit and its surrounding components in an electronic device provided by an embodiment of the present invention; Figure 4 It is a working logic diagram of a memory protection unit provided by an embodiment of the present invention; Figure 5 A flow chart showing the steps of a first access method embodiment of the present invention is shown; Figure 6 A flow chart showing the steps of a second access method embodiment of the present invention is shown; Figure 7 A flow chart showing the steps of a third access method embodiment of the present invention is shown; Figure 8 A structural block diagram of an access device embodiment of the present invention is shown; Fig. 9 It is a schematic structural diagram of a third electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] In existing electronic devices, for ease of integration, a memory protection unit is usually integrated into the core (such as a processor) to control the processor's access rights to certain data in a slave device. Since the memory protection unit is only integrated in the core, it can only control the core's access rights to certain data in a slave device. However, other master devices outside the core may be able to access the slave device without the intervention of the processor, resulting in poor security performance of the data in the slave device.

[0016] One of the core concepts of an embodiment of the present invention is to decouple a memory protection unit from a processor core. In an electronic device, the memory protection unit is integrated in a bus, or the memory protection unit is arranged at an interface of a slave device, or the memory protection unit is arranged at a position between the bus and the interface of the slave device. The memory protection unit is tightly coupled with the slave device. The memory protection unit is arranged at any of the above three positions. Any access of a master device to a slave device must first pass through the memory protection unit. That is, the memory protection unit can restrict the access to the slave device for all master devices. Therefore, the memory protection unit can not only restrict the access of the processor core to the slave device, but also restrict the access of other master devices other than the processor core to the slave device, thereby improving the security of data in the slave device.

[0017] Reference Figure 1 and Figure 2 , the electronic device comprises: a bus ( Figure 1 and Figure 2 A bus matrix in the bus), a master device set on the bus, and a slave device set on the bus; the master device includes: a processor. Figure 1 and Figure 2 In the embodiment, master device 1 and master device 2 refer to other master devices except the processor. A master device refers to a device that can actively initiate an access request, and a slave device refers to a device that can complete a corresponding task according to the request. For example, a master device can be a USB device, an Ethernet card, an Ethernet interface, etc. For example, a slave device can be a printer, a scanner, etc. There is no specific limitation on the specific types of master devices and slave devices, and the number of master devices and slave devices in the electronic device.

[0018] The electronic device also includes: a memory protection unit (MPU), the memory protection unit is integrated in the bus, or the memory protection unit is set at the interface of the slave device, or the memory protection unit is set at a position between the bus and the interface of the slave device. In the electronic device, the memory protection unit can be set at any of the above three positions, and there is no specific limitation on this. It should be noted that integrating the memory protection unit in the bus may lead to more improvements to the bus. Therefore, the memory unit can be set at the interface of the slave device, or the memory protection unit can be set at a position between the bus and the interface of the slave device to reduce the difficulty of integration. For example, Figure 1 and Figure 2 In both cases, the memory protection unit is set between the bus and the interface of the slave device. Figures 1 to 3 The MPU in the text refers to the memory protection unit.

[0019] The memory protection unit is used to limit the access of the master device to the slave device, mainly based on the master device's access rights to the slave device to limit its access to the slave device. In the present application, the memory protection unit is decoupled from the processor core. In the electronic device, the memory protection unit is integrated into the bus, or the memory protection unit is set at the interface of the slave device, or the memory protection unit is set at a position between the bus and the interface of the slave device. The memory protection unit is tightly coupled with the slave device, and the memory protection unit is set at any of the above three positions. Figure 3 Any master device's access to a slave device must first pass through the memory protection unit, that is, the memory protection unit can limit the access to the slave device for all master devices. Therefore, the memory protection unit can not only limit the processor core's access to the slave device, but also limit the access to the slave device by other master devices other than the processor core, thereby improving the security of the data in the slave device.

[0020] Reference Figure 3 In this application, the access request issued by the master device is transmitted to the corresponding memory protection unit (MPU) through the bus. After the configuration access permission comparison of the memory protection unit, only the access request that meets the permission setting will be received by the corresponding slave device, that is, only the access request that meets the permission setting can access the corresponding slave device, and the access request that does not meet the permission setting is intercepted or blocked by the memory protection unit and cannot be received by the corresponding slave device, thereby improving the security of the data in the slave device. Figure 3 The peripherals here refer to slave devices such as printers. Figure 3 In the embodiment, the working bus interface of the memory protection unit can be a general interface or other customized interface, and there is no specific limitation on this. The memory protection unit has an external configuration interface for configuring access rights of different master devices corresponding to different address ranges.

[0021] Optionally, the master device includes: a direct memory access (DMA) device, and the slave device includes: a memory. Specifically, the DMA device can directly access the memory of the memory and other slave devices without the intervention of the processor. When the memory protection unit is set in the kernel, the security of the data in the slave device is greatly endangered, especially the security of the data in the memory of the memory. Through the improvement of the present application, the DMA device needs to be restricted by the memory protection unit before accessing the memory, instead of directly accessing it, thereby greatly improving the security performance of the data in the memory of the memory.

[0022] It should be noted that Figure 1 and Figure 2 The other slave devices that need to be protected refer to other slave devices in the electronic device except the memory.

[0023] Optional, see Figure 1 , one slave device is configured with one memory protection unit, and / or, at least two slave devices are configured with one memory protection unit, and the corresponding relationship between the memory protection unit and the slave device is flexible and diverse, which can be adapted to a variety of system designs and easy to integrate. For example, Figure 1 In the example, a slave device is configured with a memory protection unit, that is, memory 1 is configured with MPU1, then the access request that needs to access memory 1 will reach memory 1 only after passing the restriction of MPU1, thereby improving the security of the data in memory 1; memory 2 is configured with MPU2, then the access request that needs to access memory 2 will reach memory 2 only after passing the restriction of MPU2, thereby improving the security of the data in memory 2; other slave devices that need to be protected are configured with MPU3, then the access request that needs to access other slave devices that need to be protected will reach other slave devices that need to be protected only after passing the restriction of MPU3, thereby improving the security of the data in other slave devices that need to be protected. For another example, Figure 2 In the example, one slave device is configured with one memory protection unit, and both slave devices are configured with one memory protection unit, that is, memory 1 and memory 2 are configured with MPU1. Then, the access request that needs to access memory 1 and memory 2 will reach memory 1 and memory 2 only after passing the restriction of MPU1, thereby improving the security of data in memory 1 and memory 2; other slave devices that need to be protected are configured with MPU2. Then, the access request that needs to access other slave devices that need to be protected will reach other slave devices that need to be protected only after passing the restriction of MPU2, thereby improving the security of data in other slave devices that need to be protected.

[0024] Reference Figure 4, the memory protection unit includes: an address comparator and a permission comparator. Specifically, the space of the slave device is usually partitioned, that is, Region setting. The space of the slave device can be partitioned according to the configuration access rights to obtain several regions, each region contains several addresses, and all the space of the slave device can be divided into one region or multiple regions, which is not specifically described here. A region obtained by partitioning can contain one address or multiple addresses, and there is no specific limitation on this. The configuration access rights corresponding to all addresses in a region obtained by partitioning are the same, and then all addresses in a region can be applied to the same configuration file, which can reduce the number of configuration files and improve the efficiency of obtaining configuration files. After receiving the access request of the master device, the bus will decode, obtain the target address and access operation of the access request, and then pass the access request to the memory protection unit corresponding to the target address. The address comparator in the memory protection unit first determines whether the target address is within its restricted address range. If the target address is not within its restricted address range, an error is reported, and the error type (i.e., Region No Hit) that the target address is not within its restricted address range is given. If the target address is within its restricted address range, the address comparator continues to determine which region the target address is located in, and then obtains the configuration file corresponding to the region where the target address is located, and obtains the configuration access rights of the target address. The configuration access rights of the target address. The permission comparator then compares the access information in the access request with the configuration access rights of the target address. If the access information in the access request matches the configuration access rights of the master device for the target address, it is determined that the access is a correct access, and the correct access is passed to the corresponding slave device. If the access information in the access request does not match the configuration access rights of the master device for the target address, it is determined that the access is an error, and an error is reported, and an error type is given that the access request is within its restricted address range, but the permission is wrong (i.e., Region Hit but permission error).

[0025] The present application also provides an access method, which is applied to a memory protection unit in any of the aforementioned electronic devices, referring to Figure 5 , the access method may specifically include the following steps.

[0026] Step 101: receiving an access request sent by a master device to a target slave device via a bus; the access request includes: a target address and an access operation.

[0027] After receiving the access request sent by the master device, the bus decodes it and obtains the target address and access operation of the access request. The target address refers to the specific address space of the slave device that the access request needs to access. The access operation refers to the operations that the access request intends to perform on the target address. The access operation can include: read operation, write operation and execute. The read operation refers to reading the data stored in the target address, the write operation refers to writing data to the target address, and the execute operation refers to executing the relevant code at the target address.

[0028] Step 102: Obtain a configuration file corresponding to the target address; the configuration file includes: configuration access rights of the master device for the access operation of the target address.

[0029] For the target address, different access operations of the same master device may correspond to different configuration access rights, or for the target address, different access operations of the same master device may correspond to the same configuration access rights. For the target address, different master devices may have different or the same configuration access rights corresponding to the same access operation, which is set according to actual needs and is not specifically limited. The configuration access rights of the master device for the access operation of the target address include: allow or prohibit, where allow means allowing the master device to perform the access operation of the target address, and prohibit means not allowing the master device to perform the access operation of the target address.

[0030] The configuration access permission of the master device for the access operation of the target address is set in a configuration file corresponding to the target address, so the configuration file corresponding to the target address is obtained first.

[0031] Step 103: When it is determined based on the configuration file that the configured access permission of the master device for the access operation to the target address is allowed, allow the access request to the target slave device.

[0032] As mentioned above, the memory protection unit includes a permission comparator, which compares the master device number and access operation in the access request with the configured access permissions of the master device for the access operation to the target address. If the configured access permissions of the master device for the access operation to the target address in the configuration file are allowed, it is determined that the access is a correct access, and the correct access is passed to the corresponding slave device, allowing the access operation to the target address of the slave device, thereby improving the security of the data in the slave device.

[0033] The method may also include: determining based on the configuration file that the configured access permission for the access operation of the master device to the target address is prohibited, determining that the access request is an erroneous access or an illegal access, and determining that an access error is present, reporting an error, and blocking the access request to the target slave device, thereby improving the security of the data in the slave device.

[0034] The present application also provides another access method, which is also applied to the memory protection unit in the aforementioned electronic device, referring to Figure 6 , the access method may specifically include the following steps.

[0035] Step 201: Receive an access request sent by a master device to a target slave device via a bus; the access request includes: a target address and an access operation.

[0036] The step 201 may refer to the aforementioned step 101, and will not be described again here to avoid repetition.

[0037] Step 202: partition the addresses in the slave device to obtain a plurality of regions; the regions include: a plurality of addresses; the configuration access rights corresponding to the addresses in the same region are the same.

[0038] The number of addresses in different regions obtained by partitioning can be the same or different, and there is no specific limitation on this. Partitioning a slave device can obtain one region or multiple regions, and there is no specific limitation on this. A region can contain only one address or can contain multiple addresses, and there is no specific limitation on this. For a slave device, there is no limitation on whether the number of addresses in each region obtained by partitioning is equal, and they can be equal or different.

[0039] The same configuration access rights corresponding to each address in the same area means that each address in the same area has the same configuration access rights for the same access operation of the same master device, which are all allowed or prohibited. In this way, the configuration files corresponding to each address in the same area are the same, and only one configuration file is required for each address in the same area, which can reduce the number of configuration files and improve the efficiency of obtaining configuration files.

[0040] Step 203: For each of the areas, a configuration file for configuring access rights for each access operation of each of the master devices is set.

[0041] Setting a configuration file for access rights for a region is equivalent to setting a configuration file for access rights for each address in the region.

[0042] It should be noted that the configuration access rights here also include modes. A master device can correspond to user mode and supervisor mode. The access rights for the same access operation of the same target address for the same master device in different modes can be different or the same. The following Table 1 is a schematic diagram of a configuration file for a region. In Table 1, master refers to the master device. There are five master devices shown in Table 1, namely master0, master1, master2, master3 and master4. Each master device corresponds to two modes, namely user mode and supervisor mode. The configuration file sets configuration access rights for each access operation of the five master devices in different modes. The access operations in Table 1 include read operations, write operations and execution. The configuration file shown in Table 1 corresponds to the nth region (region_n), and RGD_n_WD0, RGD_n_WD1 and RGD_n_WD2 refer to different locations of the configuration file. In the configuration file, the RGD_n_WD0 position indicates the starting address of the nth region, and the RGD_n_WD1 position indicates the ending address of the nth region.

[0043] Table 1: Parameters in the configuration file

[0044] Step 204: Obtain a configuration file corresponding to the area where the target address is located; the configuration file includes: configuration access rights of the master device for the access operation of the target address.

[0045] Obtaining the configuration file corresponding to the area where the target address is located means obtaining the configuration file corresponding to the target address.

[0046] Step 205: When it is determined based on the configuration file that the configured access permission of the master device for the access operation to the target address is allowed, allow the access request to the target slave device.

[0047] Step 205 may refer to the aforementioned step 103, and will not be described again here to avoid repetition.

[0048] Refer to the following Figure 7 , taking the memory protection unit as the execution body, the present application is further explained in combination with specific embodiments.

[0049] The first step is to set a configuration file for access rights for each access operation of each master device for each area. The storage space of the slave device can be partitioned to obtain several areas, each area includes: several addresses; the configuration access rights corresponding to each address in the same area are the same.

[0050] In the second step, after receiving the access request, the master device accesses the slave device through the bus. The bus interface will carry the following parameters in the access request: (1) target address; (2) access operation: read operation, write operation or execution; (3) the number of the master device that currently initiates the access, which is used to represent the identity information of the master device; (4) access mode: normal user mode or manager mode; (5) data or instruction type access. The above parameters are all present when accessing the general bus, so there is no need to increase the complexity of the bus design.

[0051] The third step is to determine whether the target address is within the area under its jurisdiction. When the memory protection unit corresponding to the target address detects that the master device initiates access to the slave device, it first determines which area the target address is in and whether it is within its jurisdiction. If so, it proceeds to the fourth step. If not, it reports an error and the error type. The error type may be that the target address is not within its jurisdiction.

[0052] The fourth step is to compare the access rights configured in the area with the access operation initiated by the master device. If the access operation of the master device in this mode is allowed in the configuration file, access to the target address of the slave device is allowed. If the mode, access operation, and data or instruction do not match, an error is reported. The access operation here is: read operation, write operation.

[0053] For example, in the configuration file of the area where the target address is located, the access permission is set to only allow master device 1 to perform data read operations in administrator mode. However, this access request is for master device 1 to perform data read operations in ordinary user mode. In this case, the modes do not match, an error is reported, as well as the error type of the mode mismatch, and access is blocked.

[0054] To summarize, the present application decouples the memory protection unit from the processor core. In the electronic device, the memory protection unit is integrated in the bus, or the memory protection unit is set at the interface of the slave device, or the memory protection unit is set at a position between the bus and the interface of the slave device. The memory protection unit is tightly coupled with the slave device. The memory protection unit is set at any of the above three positions. Any access to the slave device by any master device must first pass through the memory protection unit, that is, the memory protection unit can limit the access to the slave device for all master devices. Therefore, the memory protection unit can not only limit the access of the processor core to the slave device, but also limit the access of other master devices other than the processor core to the slave device, thereby improving the security of the data in the slave device.

[0055] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0056] Reference Figure 8 , Figure 8 The structural block diagram of an access device embodiment of the present invention is shown, which is applied to the memory protection unit in the aforementioned electronic device. The access device may specifically include the following modules: a receiving module 301, used to receive an access request sent by a master device to a target slave device through a bus; the access request includes: a target address and an access operation; a configuration file acquisition module 302, used to acquire a configuration file corresponding to the target address; the configuration file includes: the configuration access permission of the master device for the access operation of the target address; an access permission module 303, used to allow the access request to the target slave device when it is determined based on the configuration file that the configuration access permission of the master device for the access operation of the target address is allowed.

[0057] Optionally, the access device further comprises: a partitioning module, used for partitioning the addresses in the slave device to obtain a plurality of regions; the regions comprise: a plurality of addresses; the configuration access rights corresponding to the addresses in the same region are the same; A configuration module, used for setting, for each of the areas, a configuration file for configuring access rights for each access operation of each of the master devices; The configuration file acquisition module includes: The configuration file acquisition submodule is used to acquire the configuration file corresponding to the area where the target address is located.

[0058] Optionally, the access device further includes: an access blocking module, configured to block the access request to the target slave device and report an error when it is determined based on the configuration file that the configured access permission for the access operation of the master device to the target address is prohibited.

[0059] It should be noted that the related parts of the electronic device, access method and access device in the present application can be referenced to each other and have the same or similar beneficial effects. In order to avoid repetition, the related parts are abbreviated.

[0060] Fig. 9 is a structural diagram of an electronic device provided by an embodiment of the present invention. Fig. 9The present invention also provides an electronic device, see Fig. 9 , including: a processor 501, a memory 502, and a computer program 5021 stored in the memory and executable on the processor, wherein the processor implements the steps of each embodiment of the access method described above when executing the program.

[0061] The present invention also provides a readable storage medium. When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the steps of each embodiment of the above-mentioned access method.

[0062] The present invention also provides a computer program product, comprising instructions, which, when executed by a processor in an electronic device, enable the electronic device to execute the steps of any one of the aforementioned access method embodiments.

[0063] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0064] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0065] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data transmission terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data transmission terminal device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0066] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data transmission terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0067] These computer program instructions can also be loaded onto a computer or other programmable data transmission terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0068] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0069] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0070] The access method and device, an electronic device and a storage medium provided by the present invention are introduced in detail above. The principle and implementation mode of the present invention are explained by using specific examples in this article. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. An electronic device, characterized in that: include: A bus, a master device arranged on the bus, and a slave device arranged on the bus; The main device includes: a processor; The electronic device further comprises: a memory protection unit, the memory protection unit being integrated in the bus, or the memory protection unit being arranged at the interface of the slave device, or the memory protection unit being arranged at a position between the bus and the interface of the slave device; The memory protection unit is used to limit the access of the master device to the slave device.

2. The electronic device according to claim 1, characterized in that: The master device further includes: a direct memory access device; the slave device includes: a memory.

3. The electronic device according to claim 1, characterized in that: One of the slave devices is configured with one of the memory protection units; and / or, At least two of the slave devices are configured with one memory protection unit.

4. The electronic device according to any one of claims 1 to 3, characterized in that: The memory protection unit includes: an address comparator and a permission comparator.

5. An access method, characterized in that: A memory protection unit applied to an electronic device as claimed in any one of claims 1 to 4; the access method comprising: Receiving an access request sent by a master device to a target slave device via a bus; the access request includes: a target address and an access operation; Obtaining a configuration file corresponding to the target address; the configuration file includes: configuration access rights of the master device for the access operation of the target address; In a case where it is determined based on the configuration file that the configured access right of the master device for the access operation to the target address is permitted, the access request to the target slave device is permitted.

6. The access method according to claim 5, characterized in that: Before obtaining the configuration file corresponding to the target address, the method further includes: The addresses in the slave device are partitioned to obtain a plurality of regions; the regions include: a plurality of addresses; the configuration access rights corresponding to the addresses in the same region are the same; For each of the areas, a configuration file for configuring access rights for each access operation of each of the master devices is set; The obtaining the configuration file corresponding to the target address includes: Get the configuration file corresponding to the area where the target address is located.

7. The access method according to claim 5, characterized in that: The method further comprises: In a case where it is determined based on the configuration file that the configuration access permission for the access operation of the master device to the target address is prohibited, the access request to the target slave device is blocked and an error is reported.

8. An access device, characterized in that: A memory protection unit applied to an electronic device as claimed in any one of claims 1 to 4; The access device comprises: A receiving module, used for receiving an access request sent by a master device to a target slave device via a bus; the access request includes: a target address and an access operation; A configuration file acquisition module, used to acquire a configuration file corresponding to the target address; the configuration file includes: configuration access rights of the master device for the access operation of the target address; The access permission module is used to allow the access request to the target slave device when it is determined based on the configuration file that the configured access permission of the access operation of the master device to the target address is allowed.

9. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the access method as claimed in any one of claims 5 to 7 when executing the program.

10. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the access method according to any one of claims 5 to 7.

11. A computer program product, characterized in that The invention comprises instructions, which, when executed by a processor in an electronic device, enable the electronic device to execute the access method according to any one of claims 5 to 7.

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