SOC area evaluation method and device based on FPGA comprehensive result

Abstract

The invention discloses an SOC area evaluation method and device based on an FPGA (Field Programmable Gate Array) synthesis result, which can reduce the dc synthesis frequency, solve the problem of overlong SOC direct synthesis time and shorten the project development period. The device comprises a theoretical area acquisition module, an actual area acquisition module, a submodule coefficient acquisition module and a total area acquisition module.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a SOC area evaluation method based on FPGA (Field-Programmable Gate Array) synthesis results, and a SOC (System-on-a-Chip) area evaluation device based on FPGA synthesis results. Background Art

[0002] With the rapid development of modern electronic technology and integrated circuit design technology, SOC chips have been widely used in various fields, such as communications, computers, embedded systems, etc. SOC chips are integrated integrated circuit chips that integrate multiple functional modules. They integrate hardware components such as processor cores, memory controllers, input and output interfaces, graphics processing units, accelerators, etc. into one chip, achieving high integration and high-performance computing. SOC chips usually contain multiple functional modules, such as processor cores, memories, interfaces, and various peripherals, and their scale is becoming more and more complex and their area is getting larger and larger.

[0003] In the traditional SOC design process, in order to obtain accurate area, it is necessary to use Synopsys' DesignCompiler (DC) or Cadence's genus software to synthesize the RTL. For a small module, the dc or genus software processes very quickly and can obtain accurate module area results in a short time. However, as the complexity of the system increases, some modules such as CPU (Central Processing Unit), DDR (Double Data Rate Synchronous Dynamic Random Access Memory), PCIE (Peripheral Component Interconnect Express) are relatively large, and it may take several days to complete the synthesis using dc or genus. For a complete and complex SOC system, even dc or genus tools will not be able to synthesize and will exit directly, resulting in an inability to obtain an accurate area result in a short time.

[0004] In SOC, there are often multiple sub-modules. A basic SOC block diagram is as follows: Figure 1As shown in the figure, it contains multiple sub-modules such as CPU, DMA (Direct Memory Access), DDR, UART (Universal Asynchronous Receiver / Transmitter), and I2C (Inter-Integrated Circuit). Traditional SOC area evaluation requires using tools such as DC from Synopsys to read the top-level RTL code containing each sub-module, and then performing area evaluation after DC synthesis is completed. With the development of integrated circuits, SOC systems are becoming increasingly large, and the time consumed by traditional synthesis is gradually increasing, from several hours to one day and even several days, which is obviously intolerable in the urgent R & D process. Summary of the Invention

[0005] To overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide a method for SOC area evaluation based on the synthesis results of FPGA, which can reduce the number of DC syntheses, solve the problem of too long direct synthesis time of SOC, and shorten the project development cycle.

[0006] The technical solution of the present invention is as follows: This method for SOC area evaluation based on the synthesis results of FPGA includes the following steps: (1) Synthesize the top-level RTL code containing each sub-module through the FPGA supporting software to obtain the area result of the entire TOP on the FPGA; (2) Synthesize m sub-modules block1 - blockm in the top-level TOP using standard SOC synthesis tools to obtain the actual area report of the sub-modules, where m << n, and n is the total number of sub-modules in the TOP; STD CELL represents the area result of the sub-module mapped into the standard cell standard cell, MACRO represents the area of the IP part, and TOTAL represents the total area; (3) List the following system of equations: , , , , , , , Among them, a1, b1, c1, d1, e1, f1, and g1 are the FPGA resource occupancy of sub-module block1 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic; a2, b2, c2, d2, e2, f2, and g2 are the FPGA resource occupancy of sub-module block2 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic; a3, b3, c3, d3, e3, f3, and g3 are the FPGA resource occupancy of sub-module block3 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, lookup table LUT as Logic used as logic in FPGA resource occupancy, a4, b4, c4, d4, e4, f4, g4 are respectively the sub-module block4 in the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, lookup table LUT as Logic used as logic in FPGA resource occupancy, a5, b5, c5, d5, e5, f5, g5 are respectively the sub-module block5 in the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic in FPGA resource usage. a6, b6, c6, d6, e6, f6, and g6 are respectively the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit addition carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic in FPGA resource usage of submodule block6.a7, b7, c7, d7, e7, f7, g7 are the FPGA resource usages of sub-module block7 in the configuration logic block look-up table CLB LUTs, configuration logic block registers CLBRegisters, 8-bit carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and look-up table LUT as Logic used as logic, respectively. Solve for coefficients A, B, C, D, E, F, and G according to the system of equations; (4)The total area of the SOC MARCO is directly read from the library. The total area of the SOC STDCELL is: , The total area of the SOC = the total area of the SOC STDCELL + the total area of the SOC MARCO.

[0007] The present invention can quickly obtain the area result of the SOC on the FPGA platform, reduce the dc synthesis time and obtain an accurate SOC area result; when the project design is frequently modified, using this method to directly analyze the SOC area from the FPGA synthesis result can reduce the number of dc syntheses and shorten the project development cycle.

[0008] Also provided is a device for evaluating the area of an SOC based on the FPGA synthesis result, which includes: A theoretical area acquisition module configured to synthesize the top-level RTL code containing each sub-module through the FPGA supporting software to obtain the area result of the entire TOP on the FPGA; An actual area acquisition module configured to synthesize m sub-modules block1-blockm in the top-level TOP using a standard SOC synthesis tool to obtain the actual area report of the sub-modules, where m << n and n is the total number of sub-modules in the TOP; where STDCELL represents the area result of the sub-module mapped into the standard cell standard cell, MACRO represents the area of the IP part, and TOTAL represents the total area; A sub-module coefficient acquisition module, where the system of equations is as follows: , , , , , , , Among them, a1, b1, c1, d1, e1, f1, and g1 are the FPGA resource occupancy of sub-module block1 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic; a2, b2, c2, d2, e2, f2, and g2 are the FPGA resource occupancy of sub-module block2 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic; a3, b3, c3, d3, e3, f3, and g3 are the FPGA resource occupancy of sub-module block3 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, lookup table LUT as Logic used as logic in FPGA resource occupancy, a4, b4, c4, d4, e4, f4, g4 are respectively the sub-module block4 in the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, lookup table LUT as Logic used as logic in FPGA resource occupancy, a5, b5, c5, d5, e5, f5, g5 are respectively the sub-module block5 in the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic in FPGA resource usage. a6, b6, c6, d6, e6, f6, and g6 are respectively the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit addition carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic in FPGA resource usage of submodule block6.a7, b7, c7, d7, e7, f7, and g7 are the FPGA resource usage of submodule block7 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit addition carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic. Solve the coefficients A, B, C, D, E, F, and G according to the system of equations; Total area acquisition module, where the total area of ​​SOC MARCO is directly read from the library, and the total area of ​​SOC STDCELL is: , Total SOC area = total SOC STDCELL area + total SOC MARCO area. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Shown is the basic block diagram of SOC.

[0010] Figure 2 A SOC area estimation method based on FPGA synthesis results is shown.

[0011] Figure 3 shows the FPGA synthesis area format.

[0012] Figure 4 The SOC composite area format is shown. DETAILED DESCRIPTION

[0013] FPGA (Field-Programmable Gate Array) is a programmable logic device, which consists of programmable logic units (CLBs, Configurable Logic Blocks), input / output blocks (IOBs, Input / Output Block), and programmable interconnect resources (Interconnect). The supporting EDA software of FPGA can synthesize and map RTL to implement the functions of the corresponding SOC and obtain the area report of the SOC on the FPGA board. Generally, the synthesis using the FPGA supporting EDA tool (such as vivado) is faster than the SOC synthesis (such as dc), and the area result can be obtained faster. However, the area result obtained by FPGA cannot directly correspond to the actual synthesis result value of the SOC. Because the SOC synthesis needs to use the standard cell library provided by a specific process manufacturer (such as TSMC), map it into the standard cells of a specific process, and then calculate the area; while the FPGA synthesis directly maps it into the internal logic resources of the FPGA device (such as LUT), and calculates the area by calculating the occupancy of internal resources.

[0014] This method for evaluating the SOC area based on the FPGA synthesis result includes the following steps: (1) Synthesize the top-level RTL code containing each sub-module through the FPGA supporting software to obtain the area result of the entire TOP on the FPGA; (2) Synthesize the m sub-modules block1-blockm in the top-level TOP using the standard SOC synthesis tool to obtain the actual area report of the sub-modules, where m << n, and n is the total number of sub-modules in the TOP; among them, STD CELL represents the area result of the sub-module mapped into the standard cell standard cell, MACRO represents the area of the IP part, and TOTAL represents the total area; (3) List the following system of equations: , , , , , , , Among them, a1, b1, c1, d1, e1, f1, and g1 are the FPGA resource occupancy of sub-module block1 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic; a2, b2, c2, d2, e2, f2, and g2 are the FPGA resource occupancy of sub-module block2 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic; a3, b3, c3, d3, e3, f3, and g3 are the FPGA resource occupancy of sub-module block3 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, lookup table LUT as Logic used as logic in FPGA resource occupancy, a4, b4, c4, d4, e4, f4, g4 are respectively the sub-module block4 in the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, lookup table LUT as Logic used as logic in FPGA resource occupancy, a5, b5, c5, d5, e5, f5, g5 are respectively the sub-module block5 in the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic in FPGA resource usage. a6, b6, c6, d6, e6, f6, and g6 are respectively the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit addition carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic in FPGA resource usage of submodule block6.a7, b7, c7, d7, e7, f7, and g7 are the FPGA resource usage of submodule block7 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit addition carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic. Solve the coefficients A, B, C, D, E, F, and G according to the system of equations; (4) The total area of ​​SOC MARCO is directly read from the library, and the total area of ​​SOC STDCELL is: , Total SOC area = total SOC STDCELL area + total SOC MARCO area.

[0015] The present invention uses an FPGA synthesis platform to synthesize the entire SOC, and can quickly obtain the area result of the SOC on the FPGA platform. Then, based on the area of ​​the small module synthesized by DC or genus, the actual area of ​​the entire SOC is derived by using a specific set of equations. This method can reduce the DC synthesis time and obtain accurate SOC area results. When the project design is frequently changed, the traditional process requires DC re-synthesis to evaluate the area on the one hand, and re-FPGA synthesis to perform FPGA prototype verification on the other hand. Because FPGA prototype verification is a must, the FPGA synthesis step cannot be omitted. Using this method to directly analyze the FPGA synthesis result to obtain the SOC area can reduce the number of DC synthesis times and shorten the project development cycle.

[0016] Configurable Logic Block Look-Up Tables are the main means of implementing combinatorial logic and are used to implement any Boolean function. Configurable Logic Block Registers are used to implement sequential logic and maintain data status. 8-bit Carry Logic for 8-bit Operations is a special logic unit that is mainly used to support carry chains in arithmetic operations such as adders and subtractors, and can efficiently handle carry propagation problems in multi-bit addition or subtraction. 7-to-1 multiplexers (F7 Multiplexers) and 8-to-1 multiplexers (F8 Multiplexers) are multiplexers used to select the output of LUTs. Configurable Logic Block is the basic logic unit in FPGA. Each CLB contains multiple LUTs, registers, and carry logic and other functional modules. CLBs are connected through internal and external interconnection networks and can be configured to implement specific digital logic functions. Look-Up Tables used as Logic refers to LUT resources used for logic operations.

[0017] Preferably, in step (1), the FPGA supporting software is Vivado software of XILINX.

[0018] Preferably, in step (1), the SOC synthesis method uses Synopsys' Design Compiler software.

[0019] Preferably, in step (2), the MACRO area is directly read out according to the lib file.

[0020] Preferably, in step (4), the EDA synthesis result formats of different manufacturers are modified: , in, The area obtained by synthesizing the RTL for the submodule using Synopsys' Design Compiler software or Cadence's genus software. is the area obtained by FPGA software synthesis, k is the basic cell type in the FPGA software synthesis report, m is the number of cell types in the FPGA synthesis area report, and m≥k.

[0021] Those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes the steps of the above-mentioned embodiment method, and the storage medium can be: ROM / RAM, disk, CD, memory card, etc. Therefore, corresponding to the method of the present invention, the present invention also includes a SOC area evaluation device based on FPGA synthesis results, which is usually expressed in the form of functional modules corresponding to the steps of the method. The device includes: Theoretical area acquisition module, which is configured to synthesize the top-level RTL code containing each sub-module through the FPGA supporting software to obtain the area result of the entire TOP on the FPGA; The actual area acquisition module is configured to use the standard SOC synthesis tool to synthesize some sub-modules in the SOC and obtain the actual area report of the sub-module, where STD CELL represents the area result of the sub-module mapped to the standard cell, MACRO represents the area of ​​the IP part, and TOTAL represents the total area; Submodule coefficient acquisition module, where the equations are as follows: , , , , , , , Among them, a1, b1, c1, d1, e1, f1, and g1 are the FPGA resource occupancy of sub-module block1 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic; a2, b2, c2, d2, e2, f2, and g2 are the FPGA resource occupancy of sub-module block2 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic; a3, b3, c3, d3, e3, f3, and g3 are the FPGA resource occupancy of sub-module block3 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, lookup table LUT as Logic used as logic in FPGA resource occupancy, a4, b4, c4, d4, e4, f4, g4 are respectively the sub-module block4 in the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, lookup table LUT as Logic used as logic in FPGA resource occupancy, a5, b5, c5, d5, e5, f5, g5 are respectively the sub-module block5 in the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic in FPGA resource usage. a6, b6, c6, d6, e6, f6, and g6 are respectively the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit addition carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic in FPGA resource usage of submodule block6.a7, b7, c7, d7, e7, f7, and g7 are the FPGA resource usage of submodule block7 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit addition carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic. Solve the coefficients A, B, C, D, E, F, and G according to the system of equations; Total area acquisition module, where the total area of ​​SOC MARCO is directly read from the library, and the total area of ​​SOC STDCELL is: , Total SOC area = total SOC STDCELL area + total SOC MARCO area.

[0022] Preferably, in the theoretical area acquisition module, the FPGA supporting software is Vivado software of XILINX.

[0023] Preferably, in the theoretical area acquisition module, the SOC synthesis method uses the DesignCompiler software of Synopsys.

[0024] Preferably, in the actual area acquisition module, the MACRO area is directly read out according to the lib file.

[0025] Preferably, the total area acquisition module is modified according to the EDA synthesis result formats of different manufacturers: , in, The area obtained by synthesizing the RTL for the submodule using Synopsys' Design Compiler software or Cadence's genus software. is the area obtained by FPGA software synthesis, k is the basic cell type in the FPGA software synthesis report, m is the number of cell types in the FPGA synthesis area report, and m≥k.

[0026] Specifically: , , … , in, is the area of ​​the submodule obtained according to the traditional synthesis process, such as Figure 4 T1-T7 in ; is the area obtained by FPGA software synthesis, such as Figure 3 middle Corresponding to a1-g1, Corresponding to a7-g7. k is the basic unit type in the FPGA software synthesis report. Figure 3 In this case, k is 7, m is the number of cell types in the FPGA synthesis area report, and also the number of submodules that need to be synthesized according to the traditional soc process, m ≥ k. Different FPGA synthesis software obtains different types and numbers of devices in the synthesis report, that is, the parameter k is different, but it can also be adjusted according to the above formula, so this method can adapt to FPGAs from various manufacturers.

[0027] The present invention has the following beneficial effects: 1. Instead of directly synthesizing top through software such as dc / genus, use FPGA synthesis top instead, which greatly reduces the SOC synthesis time and can get the area report as soon as possible.

[0028] 2. When the project design is frequently changed but some modules are not modified, the SOC area can be directly calculated without DC synthesis.

[0029] 3. Strong versatility: This method is not limited to specific FPGA models and can be calculated according to different FPGA manufacturers.

[0030] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. A SOC area evaluation method based on FPGA synthesis results, characterized by: It includes the following steps: (1) Synthesize the top-level RTL code containing each sub-module through the FPGA supporting software to obtain the area result of the entire TOP on the FPGA; (2) Synthesize the m sub-modules block1 - blockm in the top-level TOP using the standard SOC synthesis tool to obtain the actual area report of the sub-modules, where m << n, and n is the total number of sub-modules in the TOP; STD CELL represents the area result of the sub-module mapped into the standard cell standard cell, MACRO represents the area of the IP part, and TOTAL represents the total area; (3) List the following system of equations: ， ， ， ， ， ， ， Among them, a1, b1, c1, d1, e1, f1, and g1 are the FPGA resource occupancy of sub-module block1 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic; a2, b2, c2, d2, e2, f2, and g2 are the FPGA resource occupancy of sub-module block2 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic; a3, b3, c3, d3, e3, f3, and g3 are the FPGA resource occupancy of sub-module block3 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, lookup table LUT as Logic used as logic in FPGA resource occupancy, a4, b4, c4, d4, e4, f4, g4 are respectively the sub-module block4 in the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, lookup table LUT as Logic used as logic in FPGA resource occupancy, a5, b5, c5, d5, e5, f5, g5 are respectively the sub-module block5 in the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic in FPGA resource usage. a6, b6, c6, d6, e6, f6, and g6 are respectively the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit addition carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic in FPGA resource usage of submodule block6.a7, b7, c7, d7, e7, f7, and g7 are the FPGA resource usage of submodule block7 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit addition carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic. Solve for the coefficients A, B, C, D, E, F, G according to the system of equations; (4) The total area of SOC MARCO is directly read from the library, and the total area of SOC STDCELL is: ， Total SOC area = Total SOC STDCELL area + Total SOC MARCO area.

2. The SOC area evaluation method based on FPGA synthesis results according to claim 1, characterized in that: In the step (1), the FPGA supporting software is Vivado software of XILINX.

3. The SOC area evaluation method based on FPGA synthesis results according to claim 2, characterized in that: In the step (1), the SOC synthesis method uses Design Compiler software of synopsys.

4. The SOC area evaluation method based on FPGA synthesis results according to claim 3, characterized in that: In the step (2), the MACRO area is directly read according to the lib file.

5. The SOC area evaluation method based on FPGA synthesis results according to claim 4 is characterized in that: In the step (4), modify according to the EDA synthesis result formats of different manufacturers: ， in, The area obtained by synthesizing the RTL for the submodule using Synopsys' Design Compiler software or Cadence's genus software. is the area obtained by FPGA software synthesis, k is the basic cell type in the FPGA software synthesis report, m is the number of cell types in the FPGA synthesis area report, and m≥k.

6. The device of the SOC area evaluation method based on FPGA synthesis results according to claim 1, characterized in that: It includes: Theoretical area acquisition module, which is configured to synthesize the top-level RTL code containing each sub-module through the FPGA supporting software to obtain the area result of the entire TOP on the FPGA; Actual area acquisition module, which is configured to synthesize the m sub-modules block1 - blockm included in the TOP in the SOC using the standard SOC synthesis tool, where m << n, and n is the total number of sub-modules in the TOP, to obtain the actual area report of the sub-modules, where STD CELL represents the area result of the sub-module mapped into the standard cell standard cell, MACRO represents the area of the IP part, and TOTAL represents the total area; Sub-module coefficient acquisition module, where the following system of equations is listed: ， ， ， ， ， ， ， Among them, a1, b1, c1, d1, e1, f1, and g1 are the FPGA resource occupancy of sub-module block1 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic; a2, b2, c2, d2, e2, f2, and g2 are the FPGA resource occupancy of sub-module block2 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic; a3, b3, c3, d3, e3, f3, and g3 are the FPGA resource occupancy of sub-module block3 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLB Registers, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, lookup table LUT as Logic used as logic in FPGA resource occupancy, a4, b4, c4, d4, e4, f4, g4 are respectively the sub-module block4 in the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, lookup table LUT as Logic used as logic in FPGA resource occupancy, a5, b5, c5, d5, e5, f5, g5 are respectively the sub-module block5 in the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit adder carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic in FPGA resource usage. a6, b6, c6, d6, e6, f6, and g6 are respectively the configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit addition carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic used as logic in FPGA resource usage of submodule block6.a7, b7, c7, d7, e7, f7, and g7 are the FPGA resource usage of submodule block7 in configuration logic block lookup table CLB LUTS, configuration logic block registers CLBRegisters, 8-bit addition carry logic CARRY8, 7-to-1 multiplexer F7 Muxes, 8-to-1 multiplexer F8 Muxes, configuration logic block CLB, and lookup table LUT as Logic. Solve for the coefficients A, B, C, D, E, F, G according to the system of equations; Total area acquisition module, where the total area of SOC MARCO is directly read from the library, and the total area of SOC STDCELL is: ， Total SOC area = Total SOC STDCELL area + Total SOC MARCO area.

7. The device of the SOC area evaluation method based on FPGA synthesis results according to claim 6 is characterized in that: In the theoretical area acquisition module, the FPGA supporting software is Vivado software of XILINX.

8. The device of the SOC area evaluation method based on FPGA synthesis results according to claim 7 is characterized in that The SOC synthesis method uses Design Compiler software of Synopsys.

9. The device of the SOC area evaluation method based on FPGA synthesis results according to claim 8, characterized in that: In the actual area acquisition module, the MACRO area is directly read according to the lib file.

10. The device of the SOC area evaluation method based on FPGA synthesis results according to claim 9, characterized in that: In the total area acquisition module, modify according to the EDA synthesis result formats of different manufacturers: ， in, The area obtained by synthesizing the RTL for the submodule using Synopsys' Design Compiler software or Cadence's genus software. is the area obtained by FPGA software synthesis, k is the basic cell type in the FPGA software synthesis report, m is the number of cell types in the FPGA synthesis area report, and m≥k.

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