Project file building method and system, chip verification system and storage medium

Abstract

The invention discloses a project file building method and system, a chip verification system and a storage medium. The project file is used for providing a simulation environment of a to-be-tested chip, and the project file building method comprises the following steps: creating a project directory; storing project files of previous projects according to the project directory to obtain a sample library, wherein the sample library comprises a plurality of intellectual property modules and a plurality of verification intellectual property modules; obtaining an intellectual property module required for constructing the iteration project and a verification intellectual property module for verifying the function point from a sample library according to the function point of the iteration project; and filling the project directory according to the obtained intellectual property module and the verification intellectual property module to obtain a project file of the iterative project. The project file of the iterative project is automatically established based on the project file of the previous project, so that the establishment efficiency of the project file of the iterative project is improved, and the research and development period of the iterative project is further shortened.

Description

Technical Field

[0001] The present invention relates to the field of chip verification, and in particular to a project file building method, system, chip verification system and storage medium. Background Art

[0002] In order to discover and correct design defects in a timely manner, the chip needs to be verified through corresponding verification environment, verification tools, and verification methods during the chip design process.

[0003] Universal Verification Methodology (UVM) is a verification method based on SystemVerilog. It provides a set of standard class libraries and methods, allowing verification engineers to more easily build and manage complex verification environments. When using the UVM verification methodology to complete the verification of a project, you first need to build project files based on the functional points of the project to create the simulation environment required for verification.

[0004] In the prior art, project files are usually manually built by verification engineers. However, as the scale of chips increases, the composition structure of chips becomes more and more complex, and the size of project files will also become larger and more complex. If the manual construction method is continued, it will be time-consuming, tedious and error-prone, resulting in the verification process taking up more and more time and resources in the chip design process, which is not conducive to improving verification efficiency and shortening the R&D cycle. Summary of the invention

[0005] In view of the above problems, the purpose of this application is to provide a project file building method, system, chip verification system and storage medium, which automatically builds the project files of iterative projects based on the project files of previous projects, thereby improving the efficiency of building the project files of iterative projects and further shortening the R&D cycle of iterative projects.

[0006] According to one aspect of the present application, a project file building method is provided, wherein the project file is used to provide a simulation environment for a chip to be tested, and the project file building method comprises: creating a project directory; storing project files of previous projects according to the project directory to obtain a sample library, wherein the sample library comprises a plurality of intellectual property modules and a plurality of verification intellectual property modules; obtaining from the sample library the intellectual property modules required for building the iterative project and the verification intellectual property modules for verifying the functional points according to the functional points of the iterative project; and filling the project directory according to the obtained intellectual property modules and the verification intellectual property modules to obtain the project files of the iterative project.

[0007] Optionally, the project directory includes a top-level folder of the verification environment, and the top-level folder includes: a basic subfolder, storing basic test cases of the simulation environment, configuration functions of the chip to be tested, and a clock module of the simulation environment; an environment subfolder, storing a top-level environment file obtained by instantiating and connecting each of the verification intellectual property modules; and a setting subfolder, storing configuration data of the verification intellectual property module.

[0008] Optionally, the project directory includes a verification file directory and a design file directory, the verification file directory provides a storage path for files required to build and run the simulation environment, and the verification file directory also provides a storage path for the top-level folder; the design file directory provides a storage path for the intellectual property module source files required to build the chip to be tested.

[0009] Optionally, the verification file directory includes: a test scenario subdirectory, which provides test cases for the verification intellectual property modules corresponding to each of the functional points; a simulation system subdirectory, which provides a list of system files in the simulation environment and the storage path of functions and scripts required to run the simulation environment; and a simulation model subdirectory, which provides the storage path of the source files of each of the verification intellectual property modules and the storage path of the top-level folder.

[0010] Optionally, the step of filling the project directory according to the obtained intellectual property module and the verification intellectual property module includes: filling the functions and scripts in the design file directory, the test scenario subdirectory, the simulation system subdirectory and the source files of each verification intellectual property module in the simulation model subdirectory according to the obtained intellectual property module and the verification intellectual property module; filling the system file list in the simulation system subdirectory according to the design file directory and the test scenario subdirectory; and filling the top-level folder according to the verification intellectual property module.

[0011] Optionally, obtaining the intellectual property module required for building the iterative project and the verification intellectual property module for verifying the functional point from the sample library and filling the project directory according to the obtained intellectual property module and the verification intellectual property module are all implemented through a build script, and the project file building method also includes: writing the build script.

[0012] Optionally, the test scenario subdirectory includes a plurality of first folders, each of which is named with a preset name of the corresponding verification intellectual property module and is used to provide a storage path for the test cases of the verification intellectual property module.

[0013] Optionally, the simulation system subdirectory includes: a function folder for storing a simulation creation function, wherein the simulation creation function is used to generate a simulation directory for running each of the test cases; a script folder for storing scripts required to run the simulation environment; a system file list for providing path resolution of the intellectual property module in the simulation environment and path resolution of the verification intellectual property module; and multiple second folders, each of which is named after the preset name of the corresponding verification intellectual property module and is used to provide a storage path for the simulation directory of the verification intellectual property module.

[0014] Optionally, the simulation model subdirectory also includes a general design folder, which includes multiple verification intellectual property module subfolders, each of which is named with a preset name of the corresponding verification intellectual property module, and is used to provide a storage path for the source file of the verification intellectual property module. Each of the verification intellectual property module subfolders includes: a source file folder, which provides a storage path for the source file of the verification intellectual property module; an interface file folder, which provides a storage path for the interface file of the verification intellectual property module; and a header file, which is used to declare reusable constants and / or functions.

[0015] Optionally, the verification file directory also includes: a tool subdirectory, including software tools used for simulation verification.

[0016] Optionally, the design file directory includes: a design file list, which provides path resolution of the intellectual property module for building the simulation model of the chip to be tested; multiple intellectual property module folders, each of which is named with a preset name of the corresponding intellectual property module and includes a list of source files of the intellectual property module; and a file inclusion command, which is used to define the reference relationship between the design file list and each of the intellectual property module folders.

[0017] Optionally, the previous project and the iterative project are different projects applied to the same product line.

[0018] According to another aspect of the present application, a project file building system is provided, wherein the project file is used to provide a simulation environment for a chip to be tested, and the building system includes: a storage module, storing a pre-created project directory and a sample library, the sample library including project files of previous projects stored according to the project directory, the sample library including multiple intellectual property modules and multiple verification intellectual property modules; an input module, used to input an iterative project and functional points of the iterative project; a retrieval module, retrieving from the sample library the intellectual property modules required to build the iterative project and the verification intellectual property modules to verify the functional points; and a generation module, filling the project directory according to the obtained intellectual property modules and the verification intellectual property modules to obtain the project file of the iterative project.

[0019] Optionally, the project directory includes a top-level folder of the verification environment, and the top-level folder includes: a basic subfolder, storing basic test cases of the simulation environment, configuration functions of the chip to be tested, and a clock module of the simulation environment; an environment subfolder, storing a top-level environment file obtained by instantiating and connecting each of the verification intellectual property modules; and a setting subfolder, storing configuration data of the simulation environment.

[0020] According to the third aspect of the present application, a chip verification system is provided, wherein the chip verification system comprises: a memory for storing computer-readable instructions; and a processor for executing the computer-readable instructions to implement the project file building method provided in any one of the above items, and the processor is also used to provide a chip simulation environment based on the project file.

[0021] According to a fourth aspect of the present application, a storage medium is provided, wherein a computer program is stored on the storage medium, and when the computer program is executed by a processor, the project file building method as described in any one of the above items is implemented.

[0022] According to the project file building method, system, chip verification system and storage medium provided in this application, a sample library is obtained through the standardized and modular management of previous projects, thereby providing a basis for automatically building project files for iterative projects, which is beneficial to improving the efficiency of building project files for iterative projects and further shortening the R&D cycle of iterative projects.

[0023] Furthermore, the verification environment is split and stored separately, which enables independent management of basic test cases in the verification environment, connections of verification intellectual property modules, and configurations of verification intellectual property modules, making it easier to find or replace verification intellectual property modules or basic test cases based on functional points later, thereby improving the efficiency of setting up the verification environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0025] Figure 1 A schematic flow chart showing the method for building a project file of this application;

[0026] Figure 2 A schematic diagram showing the structure of a project directory;

[0027] Figure 3 Show Figure 2 The schematic structure diagram of the simulation system subdirectory in ;

[0028] Figure 4 Show Figure 2 Schematic diagram of the general design folder in the;

[0029] Figure 5 Show Figure 1 A schematic flow chart of filling the project directory in ;

[0030] Figure 6 A schematic structural diagram of the system for building project files for this application is shown;

[0031] Figure 7 A schematic structural diagram of the chip verification system of the present application is shown. DETAILED DESCRIPTION

[0032] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the following description of the present application, some specific details are described in detail. At the same time, in order to avoid confusing the essence of the present application, known methods, processes, and flows are not described in detail, and those skilled in the art can fully understand the present application without the description of these known parts. For the sake of clarity, the various parts in the drawings are not necessarily drawn to scale.

[0033] In addition, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0034] It should also be noted that, in the various methods and processes of the present application, the size of the step numbers does not mean the order of execution, nor does it constitute any limitation on the implementation process of the embodiments of the present application.

[0035] In order to facilitate the understanding of this application, a brief introduction to some professional terms involved in this specification is first given.

[0036] UVM (Universal Verification Methodology) is a universal verification method. It is an open source verification library based on the SystemVerilog language and is used to design and verify complex semiconductor chips. UVM provides a standardized method to create a reusable and scalable simulation environment to more effectively verify the functionality and performance of the chip under test.

[0037] Intellectual Property Core (also called Intellectual Property Core or IP Core) refers to a pre-designed reusable logic circuit module or analog circuit module. The use of IP core can greatly improve design efficiency, reduce design difficulty, and shorten product design time.

[0038] Verification Intellectual Property Core (also called Verification Intellectual Property Core or VIP Core) is an IP core used to verify System on Chips (SoC) protocol standards and interfaces. VIP Core can quickly create complex verification environments and improve verification efficiency.

[0039] A project file (Data Base) is a file that can be read by simulation software to create a simulation environment and contains all the information required for simulation.

[0040] A feature is a specific function or property of each chip or each intellectual property module that makes up a chip. During the verification phase, these feature points need to be tested to ensure that the chip can work properly according to the design requirements in actual use.

[0041] In chip design, as projects accumulate, the IP cores that make up the chip and the VIP cores corresponding to the various functional points of the chip are basically fixed, and the functions of each IP core and VIP core are also becoming mature. After that, the chip is upgraded and improved (i.e., project iteration) to meet the increasing demand for chip functions and performance. In the R&D process of iterative projects, verification engineers first need to build project files. How to realize the automatic construction of project files has become the key to saving costs and shortening product development cycles.

[0042] According to one aspect of the present application, a project file building method is provided, which obtains a sample library through standardized and modular management of previous projects, thereby providing a basis for automatically building project files for iterative projects, which is beneficial to improving the efficiency of building project files for iterative projects and further shortening the R&D cycle of iterative projects.

[0043] It should be noted that, since the functions of IP cores and VIP cores are relatively complete and the project structure is fixed in different projects on the same product line, the previous projects and iterative projects involved in this application are preferably applied to different projects on the same product line, thereby reducing the error rate of project files generated by retrieval and copying. However, it should be understood that the present application is not limited to this. For example, in some embodiments, previous projects and iterative projects can also be applied to similar product lines respectively. In the following, previous projects and iterative projects applied to the same product line are used as examples.

[0044] Figure 1 The schematic flow chart of the project file construction method of the present application is shown. The project file is used to provide a simulation environment for the chip to be tested. Figure 1 As shown, the project file construction method provided by this application includes the following steps:

[0045] Step S11, creating a project directory;

[0046] In this step, based on the experience accumulated in the chip design and iteration process of the same product line, a file structure directory that is conducive to modular management and inheritance is created. It should be noted that the names of the directories, sub-directories, folders, and sub-folders at all levels in the engineering directory provided in this application are only used as examples. In actual applications, the verification personnel can choose appropriate names for naming.

[0047] In order to optimize the directory structure as much as possible, in the embodiment of the present application, the verification environment is split and stored separately in the top-level folder (test_top).

[0048] Specifically, the top-level folder includes the following parallel subfolders:

[0049] The basic subfolder stores the basic test cases in the simulation environment, the configuration functions of the chip under test, and the clock module of the simulation environment.

[0050] The environment (env) subfolder stores the top-level environment files obtained by instantiating and connecting each verification intellectual property module. In the environment subfolder, the code and connections of each verification intellectual property module are centrally placed in modules and annotated with the corresponding preset module name. In some embodiments, the environment subfolder also defines the read and write functions of each bus.

[0051] The setting subfolder stores the configuration data of each verification intellectual property module. Specifically, the setting subfolder includes the system configuration code (configuration.sv), the default configuration code (default_config), and the clock signal generation code (tb_clk_gen.sv). The system configuration code contains the configuration information of all verification intellectual property modules, random constraint information, and the function modules of the current configuration obtained from the test scenario. The default configuration code contains the initial values ​​of all configuration information, which is used to configure the initial working state of all components in the verification environment. The clock signal generation code is used to generate the corresponding clock signal according to the configuration information, thereby driving the simulation model of the chip in the simulation environment.

[0052] By splitting the fixed structure of the verification environment, the basic subfolder, environment subfolder and setting subfolder are stored separately. In the environment subfolder, since the code and connection of each verification intellectual property module are centrally placed according to the module, and there is a corresponding preset module name as an annotation, it is convenient for the script to automatically retrieve the module name in the process of building subsequent project files to inherit the corresponding code and connection relationship, reducing the time spent on interface integration. In this application, the relevant files of the basic test case (basic subfolder) and the relevant files of the verification intellectual property module (setting subfolder) are further stored separately, which is convenient for the subsequent search / modification / replacement of the basic test case and / or the verification intellectual property module according to the needs of the function point, which is more conducive to improving the efficiency of building the verification environment.

[0053] As an example, this application provides a directory structure of a project directory. Figure 2 A schematic structural diagram showing the engineering catalog provided by this application is shown. Figure 3 Show Figure 2 The schematic structure diagram of the simulation system subdirectory in , Figure 4 Show Figure 2 The schematic structure diagram of the general design folder in Figures 2 to 4 The example of the project catalog provided in this application is further explained. Figure 2 As shown, in some embodiments, the following project directory is used:

[0054] The project file (Data Base) directory is the root directory of the project directory, which is used to provide the storage path for all the information required for simulation. The project file directory includes parallel verification file directories and design file directories.

[0055] The verification file (DV) directory provides the storage path for the files required to build and run the simulation environment.

[0056] The design file (RTL) directory provides the storage path for the source files of the intellectual property modules required to build the chip under test.

[0057] Furthermore, the DV directory includes a test scenario sub-directory, a simulation system sub-directory, a simulation model sub-directory, and a tool sub-directory.

[0058] The test scenarios (cases) subdirectory is used to provide test cases for verifying the intellectual property module corresponding to each functional point. Specifically, Figure 2 As shown, the cases subdirectory includes a plurality of first folders, each of which is named with a preset name of a corresponding verification intellectual property module (in Figure 2 In the example, VIP0~VIPn is used to provide the storage path of the test case for verifying the intellectual property module.

[0059] The simulation system (sim) subdirectory provides a list of system files in the simulation environment, and the storage path of functions and scripts required to run the simulation environment. Specifically, Figure 3 As shown, the sim subdirectory includes:

[0060] Function folder (create_sim), which stores simulation creation functions. The simulation creation function is used to generate simulation directories for running various test cases.

[0061] The script folder (script) stores the automation scripts required to run the simulation environment.

[0062] The system file list (flist) provides path resolution for the IP module and the verification IP module in the simulation environment. The system file list resolves the paths of the IP module and the verification IP module respectively, which facilitates the independent management of the IP module and the verification IP module in the project file and their integration in the simulation environment, providing a basis for the subsequent automatic retrieval of scripts and the generation of files.

[0063] Multiple second folders. Each second folder is named with the preset name of the corresponding verification intellectual property module (in Figure 3 VIP0~VIPn are still used as examples in the figure) to provide the storage path of the simulation directory of the verification intellectual property module.

[0064] The simulation model subdirectory provides the storage path of the source files of each verification intellectual property module and the storage path of the top-level folder as mentioned above. Figure 2 As shown, the model subdirectory includes:

[0065] The common design folder is used to provide source files for each verification intellectual property module.

[0066] Specifically, Figure 4 As shown in the figure, the common folder includes multiple verification intellectual property module subfolders, each verification intellectual property module subfolder is named with the preset name of the corresponding verification intellectual property module (in Figure 4 VIP0~VIPn are still used as examples) to provide the storage path of the source files of the verification intellectual property module. The structure of each verification intellectual property module folder is the same, including:

[0067] Source file folder (src), which provides the storage path of the source file of the verification intellectual property module;

[0068] An interface file folder (interface), which provides the storage path of the interface file of the verification intellectual property module; and

[0069] Header files (.svh files) are used to declare reusable constants and / or functions. Header files can be referenced or included by other SystemVerilog source files (.sv files) during the construction of the simulation environment. This can improve the reusability and maintainability of the code and is also more conducive to automated script search.

[0070] The top-level folder (test_top) has the same structure as described above and will not be repeated here.

[0071] The tools subdirectory includes software tools used for simulation verification.

[0072] According to Figure 2 The schematic structure of the project directory shown is managed in blocks under the DV directory. Among them, the file content under the tools subdirectory basically does not change. After the functional points of the iterative project are determined, the file content under the cases subdirectory and the common folder can also be determined, and this part of the content will no longer change during the simulation operation, reducing the difficulty of subsequent retrieval through automated scripts. In addition, the sim subdirectory is separated from the model subdirectory. Even if a large number of files are generated when running the simulation, it will not affect the content under the model subdirectory, which is more conducive to the retrieval of automated scripts.

[0073] Furthermore, in order to facilitate the search of scripts, subdirectories, folders, subfolders and related files of the same VIP module at different levels under the DV directory are named with the same name. Taking VIP0 as an example, the first folder corresponding to VIP0 under the cases subdirectory, the second folder corresponding to VIP0 under the sim subdirectory, the corresponding verification intellectual property module subfolder under the common folder and the header file under the subfolder, and the corresponding code and connection under the environment subfolder are all named VIP0.

[0074] The RTL directory includes:

[0075] Design file list (flist_rtl.f), ​​which provides the path analysis of the intellectual property module for building the simulation model of the chip under test;

[0076] Multiple IP module folders, each IP module folder is named after the preset name of the corresponding IP module (in Figure 2 IP0~IPm are used as examples), including a list of source files for the intellectual property module; and

[0077] The file inclusion command (include) is used to define the reference relationship between the design file list and each intellectual property module folder.

[0078] Set up independent DV directories and RTL directories. List all IP cores that make up the chip to be tested through the design file list, and arrange the source files corresponding to these IP cores in the form of folders under the RTL directory, which is conducive to the automatic retrieval of the script. After the design of the chip to be tested is determined, the various intellectual property modules that make up the chip are also determined, and the file content under the RTL directory is also determined. During the simulation run, the content under the RTL directory will not change, which also facilitates the subsequent search for corresponding files through automated script retrieval.

[0079] Step S12, storing the project files of previous projects according to the project directory to obtain a sample library;

[0080] In this step, the project files of previous projects are stored according to the project directory provided in step S11, so as to build a sample library. The sample library includes multiple intellectual property modules for building these previous projects and multiple verification intellectual property modules for verifying the functional points of these previous projects. Through standardized project file management, a foundation is provided for the subsequent automated construction of project files for iterative projects.

[0081] Step S13, obtaining the intellectual property module required for building the iteration project and the verification intellectual property module for verifying the function point from the sample library according to the function point of the iteration project;

[0082] In this step, the intellectual property modules for building the iteration project and the verification intellectual property modules for verifying the functional points of the iteration project (that is, the IP cores and VIP cores in the simulation environment of the iteration project) are retrieved from the sample library through pre-designed scripts. These IP cores and VIP cores are determined as the structure and functional points of the iteration project are determined.

[0083] Step S14, filling the project directory according to the obtained intellectual property module and the verified intellectual property module to obtain the project file of the iterative project;

[0084] In this step, the project directory created in step S11 is copied, and the names of corresponding directories, sub-directories, folders, and sub-folders are modified according to the preset names of IP cores and VIP cores in the iterative project simulation environment, so as to obtain the structural framework of the iterative project.

[0085] The IP core and VIP core in the iterative project simulation environment obtained in step S13 are retrieved from the sample library through an automated script, and the retrieved files are copied to corresponding positions in the iterative file structure framework, thereby filling and obtaining the project files of the iterative project.

[0086] Figure 5 Shows Figure 1 Schematic flow chart of filling the project directory (i.e. filling the iterative project structure framework in step S14). The specific filling steps include:

[0087] In step S21, the functions and scripts (i.e., function folders and script folders) in the design file (RTL) directory, the test scenario (cases) subdirectory, and the simulation system (sim) subdirectory and the common design (common) folder (i.e., the source files of each verification intellectual property module) are filled according to the obtained intellectual property modules and verification intellectual property modules; in some embodiments, the tools (tools) subdirectory is also filled in step S21.

[0088] In step S22, a system file list in the simulation system subdirectory is filled according to the design file directory and the test scenario subdirectory; and

[0089] In step S23, the top-level folder is populated according to the verification intellectual property module.

[0090] Prioritize copying and filling the RTL directory, the cases subdirectory under the DV directory, the tools subdirectory, the common folder under the model subdirectory, and other file contents that are determined as the intellectual property module and the verification intellectual property module are determined; then copy and fill the sim subdirectory. At this time, since the storage paths of the corresponding files of the intellectual property module and the verification intellectual property module have been determined, it is more conducive to the script to automatically modify and generate the system file list; finally, copy and fill the top-level folder to perform a comprehensive and systematic verification of the chip under test.

[0091] Although in the above example, the complete structural framework of the iterative file is filled in according to the search results after the structural framework is built, it should be understood that in the actual operation, the verification personnel can complete the construction and filling of the project file structural framework in units of directories, sub-directories, folders or sub-folders according to the needs, and this application does not make too many restrictions.

[0092] In an embodiment of the present application, searching for IP cores and VIP cores in the sample library, copying and modifying the project directory to obtain the structural framework of the iterative project, and filling the structural framework are all achieved by building a script. Therefore, in the project file building method provided in the present application, it also includes: writing a building script. The building script is written in python or other programming languages, for example. Further, in some embodiments, the building script includes, for example, multiple sub-scripts to respectively implement the above-mentioned retrieval, copying, modification and other functions. In some embodiments, the building script can also be an integral script, and the present application does not impose too many restrictions. Further, in some embodiments, a standardized project directory can be built at the beginning of chip design, and project files can be stored according to the project directory, which is more conducive to the management and maintenance of project files at various stages of the production line. At the same time, it also avoids the need for secondary sorting of project files during the subsequent sample library establishment process, which is more conducive to shortening the research and development cycle.

[0093] According to the project file building method, system, chip verification system and storage medium provided in this application, a sample library is obtained through the standardized and modular management of previous projects, thereby providing a basis for automatically building project files for iterative projects, which is beneficial to improving the efficiency of building project files for iterative projects and further shortening the R&D cycle of iterative projects.

[0094] Furthermore, the verification environment is split and stored separately, which enables independent management of basic test cases in the verification environment, connections of verification intellectual property modules, and configurations of verification intellectual property modules, making it easier to find or replace verification intellectual property modules or basic test cases based on functional points later, thereby improving the efficiency of setting up the verification environment.

[0095] This application also provides a project file building system. Figure 5 The schematic structure diagram of the project file building system of this application is shown. The project file is used to provide a simulation environment for the chip to be tested. Figure 5 As shown, the project file construction system 100 provided by the present application can implement the project file construction method provided by the present application. Specifically, the project file construction system includes a storage module 110, an input module 120, a retrieval module 130 and a generation module 140.

[0096] The storage module 110 stores the pre-created project directory and sample library. The sample library includes the project files of the previous projects stored according to the project directory. Therefore, the sample library includes multiple intellectual property modules for building these previous projects and multiple verification intellectual property modules for verifying the functional points of these previous projects. The project directory is, for example, the above-mentioned project directory, which will not be described in detail here.

[0097] The input module 120 is used to input the iteration project and the functional points of the iteration project. According to the input iteration project and the functional points of the iteration project, the intellectual property module used to build the iteration project and the verification intellectual property module used to verify the functional points of the iteration project (i.e., the IP module and VIP module in the simulation environment of the iteration project) can be determined.

[0098] The retrieval module 130 retrieves the IP modules and VIP modules in the iterative project simulation environment by searching in the sample library.

[0099] The generation module 140 calls the project directory stored in the storage module 110 to build a structural framework of the iterative project, and fills the directory framework according to the IP modules and VIP modules in the iterative project simulation environment obtained by the retrieval module 130 to obtain the project files of the iterative project.

[0100] The project file building system 100 can be used to implement each process of each embodiment of the project file building method provided in this application, and thus can achieve the same technical effect, which will not be repeated here.

[0101] Figure 6 FIG. 2 shows a schematic structural block diagram of a chip verification system according to an embodiment of the present application. Figure 6 As shown, the chip verification system 200 provided in the present application includes a memory 210 and a processor 220 .

[0102] The memory 210 is used to store computer readable instructions.

[0103] The processor 220 is used to execute the computer-readable instructions stored in the memory 210 to implement the various processes of the various embodiments of the project file building method provided in this application, and can achieve the same technical effect, which will not be repeated here. In addition, the processor 220 is also used to provide a chip simulation environment according to the built project file.

[0104] Those skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructions, or by controlling related hardware through instructions, and the instructions can be stored in a computer-readable storage medium and loaded and executed by a processor. To this end, the present application embodiment also provides a storage medium, on which a computer program or instruction is stored, and when the computer program or instruction is executed by the processor, each process of each embodiment of the above update method can be implemented.

[0105] Since the instructions stored in the storage medium can execute the steps in the update method provided in the embodiment of the present application, the beneficial effects that can be achieved by the verification method provided in the embodiment of the present application can be achieved, which will not be repeated here.

[0106] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A project file construction method, wherein: The project file is used to provide a simulation environment for the chip to be tested, and the project file building method includes: Create a project directory; Storing project files of previous projects according to the project directory to obtain a sample library, wherein the sample library includes a plurality of intellectual property modules and a plurality of verification intellectual property modules; According to the functional points of the iterative project, the intellectual property module required for building the iterative project and the verification intellectual property module for verifying the functional points are obtained from the sample library; and The project directory is filled according to the obtained intellectual property module and the verification intellectual property module to obtain the project file of the iterative project.

2. The project file building method according to claim 1, wherein: The project directory includes the top-level folder of the verification environment, The top-level folders include: A basic subfolder storing basic test cases of the simulation environment, configuration functions of the chip to be tested, and a clock module of the simulation environment; An environment subfolder storing the top-level environment files obtained by instantiating and connecting each of the verification intellectual property modules; and A subfolder is set to store the configuration data of the verification intellectual property module.

3. The project file building method according to claim 2, wherein: The project directory includes a verification file directory and a design file directory. The verification file directory provides the storage path of the files required to build and run the simulation environment, and the verification file directory also provides the storage path of the top-level folder; The design file directory provides the storage path of the intellectual property module source files required to build the chip to be tested.

4. The project file building method according to claim 3, wherein: The verification file directory includes: A test scenario subdirectory, providing test cases for verifying the intellectual property module corresponding to each of the functional points; A simulation system subdirectory, providing a list of system files in the simulation environment and storage paths of functions and scripts required to run the simulation environment; and The simulation model subdirectory provides the storage path of each verification intellectual property module source file and the storage path of the top-level folder.

5. The project file building method according to claim 4, wherein: The step of filling the engineering catalog according to the obtained intellectual property module and the verified intellectual property module comprises: Fill the functions and scripts in the design file directory, the test scenario subdirectory, the simulation system subdirectory, and the source files of each verification intellectual property module in the simulation model subdirectory according to the obtained intellectual property module and verification intellectual property module; Filling the system file list in the simulation system subdirectory according to the design file directory and the test scenario subdirectory; and The top-level folder is populated according to the verification intellectual property module.

6. The project file building method according to claim 5, wherein: The obtaining of the intellectual property module required for building the iterative project and the verification intellectual property module for verifying the function point from the sample library and the filling of the project directory according to the obtained intellectual property module and the verification intellectual property module are both implemented by building a script, The project file building method also includes: writing the building script.

7. The project file building method according to claim 4, wherein: The test scenario subdirectory includes a plurality of first folders, each of which is named with a preset name of the corresponding verification intellectual property module and is used to provide a storage path for the test cases of the verification intellectual property module.

8. The project file building method according to claim 4, wherein: The simulation system subdirectory includes: A function folder storing a simulation creation function, wherein the simulation creation function is used to generate a simulation directory for running each of the test cases; A script folder, storing scripts required to run the simulation environment; A system file list, providing path resolution of the intellectual property module in the simulation environment and path resolution of the verification intellectual property module; A plurality of second folders, each of which is named with a preset name of the corresponding verification intellectual property module, and is used to provide a storage path for the simulation directory of the verification intellectual property module.

9. The project file building method according to claim 4, wherein: The simulation model subdirectory also includes a general design folder, which includes multiple verification intellectual property module subfolders. Each verification intellectual property module subfolder is named with a preset name of the corresponding verification intellectual property module and is used to provide a storage path for the source file of the verification intellectual property module. Each verification intellectual property module subfolder includes: Source file folder, providing the storage path of the source file of the verification intellectual property module; An interface file folder, providing the storage path of the verification intellectual property module interface file; and Header files are used to declare constants and / or functions that are used repeatedly.

10. The project file building method according to claim 4, wherein: The verification file directory also includes: The tool subdirectory includes software tools used for simulation verification.

11. The project file building method according to claim 3, wherein: The design file directory includes: A list of design files, providing a path analysis of the intellectual property module for building the simulation model of the chip under test; A plurality of intellectual property module folders, each of which is named after a preset name of a corresponding intellectual property module and includes a list of source files of the intellectual property module; and The file contains commands for defining the reference relationship between the design file list and each of the intellectual property module folders.

12. The project file building method according to claim 1, wherein: The previous project and the iterative project are different projects applied to the same product line.

13. A project file building system, wherein: The project file is used to provide a simulation environment for the chip to be tested, and the construction system includes: A storage module, storing a pre-created project directory and a sample library, wherein the sample library includes project files of previous projects stored according to the project directory, and the sample library includes a plurality of intellectual property modules and a plurality of verification intellectual property modules; An input module, used for inputting an iterative project and functional points of the iterative project; A retrieval module, which retrieves from the sample library the intellectual property module required to build the iterative project and the verification intellectual property module for verifying the functional point; and A generation module is provided to fill the project directory according to the obtained intellectual property module and the verification intellectual property module to obtain the project file of the iterative project.

14. The project file building system according to claim 13, wherein: The project directory includes the top-level folder of the verification environment, The top-level folders include: A basic subfolder storing basic test cases of the simulation environment, configuration functions of the chip to be tested, and a clock module of the simulation environment; An environment subfolder storing the top-level environment files obtained by instantiating and connecting each of the verification intellectual property modules; and A subfolder is set to store the configuration data of the simulation environment.

15. A chip verification system, wherein: The chip verification system comprises: a memory for storing computer-readable instructions; and A processor executes the readable instructions to implement the project file building method provided in any one of claims 1 to 12, and the processor is also used to provide a chip simulation environment according to the project file.

16. A storage medium, wherein: The storage medium stores a computer program, and when the computer program is executed by the processor, the project file building method according to any one of claims 1 to 12 is implemented.

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