Self-adaptive clock system for developing reconfigurable processor time sequence margin and implementation method

Abstract

The invention provides a self-adaptive clock implementation method and system for developing a time sequence margin of a reconfigurable processor. The method comprises the steps that S1, a simulation tool conducts dynamic time sequence analysis on an application program executed by the reconfigurable processor to obtain delay information; the delay information is sent to a compiler, the compiler carries out data flow diagram generation and mapping optimization on the application program, meanwhile, the corresponding delay information is coded into configuration information, and a working load factor is obtained based on the coded configuration information; and S2, inputting the working load factor and a PVT factor generated by the PVT detection module into a phase selection module together, selecting one of the multi-phase clocks generated by the multi-phase clock generation module by the phase selection module according to the working load factor and the PVT factor as an adaptive clock, and providing the adaptive clock to the reconfigurable processor.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to an adaptive clock system for developing a timing margin of a reconfigurable processor and an implementation method thereof. Background Art

[0002] In digital VLSI circuits, static timing analysis (STA) is used to verify timing performance and ensure that timing errors do not occur on critical paths under various process, voltage, and temperature (PVT) conditions. However, in most cases, the critical path will not be triggered and the worst PVT situation rarely occurs. Therefore, taking this pessimistic STA approach will result in considerable timing slack. This indicates that the chip can actually operate at a higher frequency or a lower voltage. Therefore, taking advantage of timing slack can significantly improve performance and reduce energy consumption. Timing slack can be divided into two parts according to its source: PVT slack and workload slack. PVT slack comes from the fact that the chip rarely runs under the worst PVT conditions, which means that the safety margin added to ensure correct timing becomes a useless timing margin. Since the critical path is not triggered every clock cycle, non-critical paths do not consume all the reserved logic delays, so workload slack occurs.

[0003] The prior art uses an instruction-driven adaptive clock scheme for a low-power microprocessor (page 2327 of the August 2019 journal "IEEE JOURNAL OF SOLID-STATE CIRCUITS" discloses "An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assi stance for a Low Power Microprocessor"). This scheme can generate an adaptive clock based on instructions, develop the timing margin caused by workload, and perform PVT calibration before each task. However, it cannot avoid the timing error caused by changes in the runtime environment, does not solve the time margin caused by PVT changes, and requires a long calibration cycle and a complex process. This structure is only suitable for serial processors such as CPUs.

[0004] Patent document CN110336545B (application number: 201910514122.5) discloses a bidirectional adaptive clock circuit supporting a wide frequency range, which belongs to the technical field of basic electronic circuits. The circuit consists of a phase clock generation module, a phase clock selection module, an adaptive clock stretching or compression adjustment module, and a control module. The adaptive clock stretching or compression adjustment module can monitor the delay information of the critical path in the chip in real time and feed the information back to the control module. After receiving the clock stretching or compression enable signal and the stretching or compression scale signal, the control module selects the target phase clock from the clock generated by the phase clock generation module and completes the rapid adjustment of the adaptive clock within the current cycle. The circuit can effectively reduce the PVT timing margin and thus improve the energy efficiency of the circuit, but the timing margin caused by the workload is not utilized, and the timing margin still has room for development. At the same time, the circuit cannot be used in an array structure.

[0005] Patent document US20210247797A1 (application number: US17170187) discloses "COMPUTE-ADAPTIVECLOCK MANAGEMENT FOR MACHINE LEARNING ACCELERTORS", which provides a globally asynchronous and locally synchronous adaptive clock chain for array-structured accelerators. However, this method targets fixed and regular interconnections, such as the interconnections in DNN accelerator arrays, and is not suitable for uncertain, irregular and complex interconnection patterns in reconfigurable processors. This scheme only develops the timing margin caused by workload, without considering the timing margin caused by PVT. In addition, asynchrony brings complex communication problems, resulting in a complex structure and high overhead for the scheme. Summary of the invention

[0006] In view of the defects in the prior art, the object of the present invention is to provide an adaptive clock system and implementation method for developing timing margin of a reconfigurable processor.

[0007] According to the present invention, an adaptive clock implementation method for developing a timing margin of a reconfigurable processor includes:

[0008] Step S1: The simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor to obtain delay information; the delay information is sent to the compiler, and the compiler generates and optimizes the mapping of the data flow graph for the application, and encodes the corresponding delay information into the configuration information, and obtains the workload factor based on the encoded configuration information;

[0009] Step S2: The workload factor and the PVT factor generated by the PVT detection module are input into the phase selection module. The phase selection module selects one of the multi-phase clocks generated by the multi-phase clock generation module as an adaptive clock according to the workload factor and the PVT factor, and provides it to the reconfigurable processor.

[0010] Preferably, the step S1 adopts: a simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor, and obtains the worst-case delay of various operations and routes through dynamic timing simulation analysis; in each cycle, the sum of the operation delay and routing delay of each PE constitutes the workload delay of the current PE; by traversing all PEs in the array, the PE with the largest workload delay is identified; and the current maximum workload delay is quantified as a workload factor M.

[0011] Preferably, the compiler is optimized, including: aggregating high-latency nodes into the same time slot and minimizing the interconnection distance;

[0012] Determine the initialization interval and generate a schedule using iterative modular scheduling; identify the bottleneck nodes that limit the frequency, and adjust the scheduling of the nodes by assigning the bottleneck nodes to the same time slots as much as possible while considering resource constraints; use the fast space mapping algorithm and the improved Dijkstra algorithm for routing; if the current schedule fails to obtain the preset placement and routing results, reschedule the bottleneck node and repeat the above steps; if all attempts to adjust the schedule are unsuccessful, increase the initialization interval and perform rescheduling.

[0013] Preferably, the PVT detection module comprises: a tunable replica circuit TRC and a time-to-digital converter TDC;

[0014] Using the tunable replica circuit TRC to track a path whose delay varies with PVT;

[0015] The time-to-digital converter TDC is used to measure the time delay of the tunable replica circuit TRC, and the PVT factor is obtained through quantification.

[0016] Preferably, the multi-phase clock generation module comprises: a phase-locked loop and a delay-locked loop;

[0017] The phase-locked loop generates a reference clock which is input to the delay-locked loop, and the delay-locked loop obtains a multi-phase clock based on the reference clock.

[0018] Preferably, the phase selection module comprises: a phase calculation module and a phase switching module;

[0019] The phase calculation module adopts: calculating the clock index of the next cycle according to the PVT factor and the workload factor;

[0020]

[0021] Wherein, k′ represents the clock index of the next cycle; k represents the clock index of the current cycle; K represents the number of phases of the multi-phase clock; Δk represents the cycle factor;

[0022]

[0023] Where M represents the workload factor; N represents the PVT factor; ε represents a positive integer introduced to ensure clock quality;

[0024] The phase switching module generates a clock signal of the next cycle according to the obtained clock index of the next cycle and the multi-phase clock output generated by the multi-phase clock generating module.

[0025] Preferably, the period of the next clock is calculated according to the period factor;

[0026]

[0027] Wherein, T represents the period of the adaptive clock; Δk represents the period factor; and δt represents the time difference between the rising edges of adjacent phases of the multi-phase clock.

[0028] According to the present invention, an adaptive clock system for developing timing margin of a reconfigurable processor is provided, comprising:

[0029] Module M1: The simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor to obtain delay information; the delay information is sent to the compiler, and the compiler generates and optimizes the data flow graph for the application, and encodes the corresponding delay information into the configuration information, and obtains the workload factor based on the encoded configuration information;

[0030] Module M2: The workload factor and the PVT factor generated by the PVT detection module are input into the phase selection module. The phase selection module selects one of the multi-phase clocks generated by the multi-phase clock generation module as an adaptive clock according to the workload factor and the PVT factor, and provides it to the reconfigurable processor.

[0031] Preferably, the module M1 adopts: a simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor, and obtains the worst-case delay of various operations and routes through dynamic timing simulation analysis; in each cycle, the sum of the operation delay and the routing delay of each PE constitutes the workload delay of the current PE; by traversing all PEs in the array, the PE with the largest workload delay is identified; the current maximum workload delay is quantified as a workload factor M;

[0032] Compiler optimizations include: aggregating high-latency nodes into the same time slot and minimizing interconnect distances;

[0033] Determine the initialization interval and generate a schedule using iterative modular scheduling; identify the bottleneck nodes that limit the frequency, and adjust the scheduling of the nodes by assigning the bottleneck nodes to the same time slots as much as possible while considering resource constraints; use the fast space mapping algorithm and the improved Dijkstra algorithm for routing; if the current schedule fails to obtain the preset placement and routing results, reschedule the bottleneck node and repeat the above steps; if all attempts to adjust the schedule are unsuccessful, increase the initialization interval and perform rescheduling.

[0034] Preferably, the PVT detection module comprises: a tunable replica circuit TRC and a time-to-digital converter TDC;

[0035] Using the tunable replica circuit TRC to track a path whose delay varies with PVT;

[0036] The time-to-digital converter TDC is used to measure the time delay of the tunable replica circuit TRC, and the PVT factor is obtained by quantification;

[0037] The multi-phase clock generation module includes: a phase-locked loop and a delay-locked loop;

[0038] The phase-locked loop generates a reference clock which is input to the delay-locked loop, and the delay-locked loop obtains a multi-phase clock based on the reference clock;

[0039] The phase selection module includes: a phase calculation module and a phase switching module;

[0040] The phase calculation module adopts: calculating the clock index of the next cycle according to the PVT factor and the workload factor;

[0041]

[0042] Wherein, k′ represents the clock index of the next cycle; k represents the clock index of the current cycle; K represents the number of phases of the multi-phase clock; Δk represents the cycle factor;

[0043]

[0044] Where M represents the workload factor; N represents the PVT factor; ε represents a positive integer introduced to ensure clock quality;

[0045] The phase switching module generates a clock signal of the next cycle according to the obtained clock index of the next cycle and the multi-phase clock output generated by the multi-phase clock generating module.

[0046] Preferably, the period of the next clock is calculated according to the period factor;

[0047]

[0048] Wherein, T represents the period of the adaptive clock; Δk represents the period factor; and δt represents the time difference between the rising edges of adjacent phases of the multi-phase clock.

[0049] Compared with the prior art, the present invention has the following beneficial effects:

[0050] 1. The present invention uses an adaptive clock solution based on a PVT detection module, workload information encoding, and multi-phase clock selection technology to achieve the technical effect of simultaneously developing timing margins in both PVT and workload for the first time;

[0051] 2. The present invention adopts a compiler scheduling algorithm to rearrange the emission time of each operation, thereby solving the problem that the cycle of the reconfigurable processor is determined by the worst PE in the entire array, resulting in unavailability of the spatial timing margin of other PEs, thereby achieving the technical effect of further utilizing the timing margin in the reconfigurable processor, improving performance and resource utilization, and increasing the actual operating frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0053] Figure 1 Schematic diagram of the structure of the adaptive clock system.

[0054] Figure 2 It is a structural diagram of the PVT detection module.

[0055] Figure 3 Schematic diagram of the structure of the phase selection module.

[0056] Figure 4 A schematic diagram of the structure of a reconfigurable processor.

[0057] Figure 5 The figure is a schematic diagram of the principle of adaptive clock.

[0058] Figure 6 Schematic diagram of the principle of clock stretching and compression through phase selection.

[0059] Figure 7 Schematic diagram of the principle of generating PVT factor.

[0060] Figure 8 This is a schematic diagram of an example of improving performance by modifying the scheduling.

[0061] Fig. 9 Fig. 2 is the graph of the proposed software scheduling optimization algorithm. DETAILED DESCRIPTION

[0062] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0063] Example 1

[0064] According to the present invention, an adaptive clock implementation method for developing a timing margin of a reconfigurable processor provided by the present invention includes:

[0065] Step S1: The simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor to obtain delay information; the delay information is sent to the compiler, and the compiler generates and optimizes the mapping of the data flow graph for the application, and encodes the corresponding delay information into the configuration information, and obtains the workload factor based on the encoded configuration information;

[0066] Step S2: The workload factor and the PVT factor generated by the PVT detection module are input into the phase selection module. The phase selection module selects one of the multi-phase clocks generated by the multi-phase clock generation module as an adaptive clock according to the workload factor and the PVT factor, and provides it to the reconfigurable processor.

[0067] Specifically, the step S1 adopts: a simulation tool performs dynamic timing analysis on an application executed by a reconfigurable processor, and obtains the worst-case delay of various operations and routes through dynamic timing simulation analysis; in each cycle, the sum of the operation delay and routing delay of each PE constitutes the workload delay of the current PE; by traversing all PEs in the array, the PE with the largest workload delay is identified; and the current maximum workload delay is quantified as a workload factor M.

[0068] Specifically, the compiler is optimized, including: aggregating high-latency nodes into the same time slot and minimizing the interconnection distance;

[0069] Determine the initialization interval and generate a schedule using iterative modular scheduling; identify the bottleneck nodes that limit the frequency, and adjust the scheduling of the nodes by assigning the bottleneck nodes to the same time slots as much as possible while considering resource constraints; use the fast space mapping algorithm and the improved Dijkstra algorithm for routing; if the current schedule fails to obtain the preset placement and routing results, reschedule the bottleneck node and repeat the above steps; if all attempts to adjust the schedule are unsuccessful, increase the initialization interval and perform rescheduling.

[0070] Specifically, the PVT detection module includes: a tunable replica circuit TRC and a time digital converter TDC;

[0071] Using the tunable replica circuit TRC to track a path whose delay varies with PVT;

[0072] The time-to-digital converter TDC is used to measure the time delay of the tunable replica circuit TRC, and the PVT factor is obtained through quantification.

[0073] Specifically, the multi-phase clock generation module includes: a phase-locked loop and a delay-locked loop;

[0074] The phase-locked loop generates a reference clock which is input to the delay-locked loop, and the delay-locked loop obtains a multi-phase clock based on the reference clock.

[0075] Specifically, the phase selection module includes: a phase calculation module and a phase switching module;

[0076] The phase calculation module adopts: calculating the clock index of the next cycle according to the PVT factor and the workload factor;

[0077]

[0078] Wherein, k′ represents the clock index of the next cycle; k represents the clock index of the current cycle; K represents the number of phases of the multi-phase clock; Δk represents the cycle factor;

[0079]

[0080] Where M represents the workload factor; N represents the PVT factor; ε represents a positive integer introduced to ensure clock quality;

[0081] The phase switching module generates a clock signal of the next cycle according to the obtained clock index of the next cycle and the multi-phase clock output generated by the multi-phase clock generating module.

[0082] Specifically, the period of the next clock is calculated according to the period factor;

[0083]

[0084] Wherein, T represents the period of the adaptive clock; Δk represents the period factor; and δt represents the time difference between the rising edges of adjacent phases of the multi-phase clock.

[0085] According to the present invention, an adaptive clock system for developing timing margin of a reconfigurable processor is provided, comprising:

[0086] Module M1: The simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor to obtain delay information; the delay information is sent to the compiler, and the compiler generates and optimizes the data flow graph for the application, and encodes the corresponding delay information into the configuration information, and obtains the workload factor based on the encoded configuration information;

[0087] Module M2: The workload factor and the PVT factor generated by the PVT detection module are input into the phase selection module. The phase selection module selects one of the multi-phase clocks generated by the multi-phase clock generation module as an adaptive clock according to the workload factor and the PVT factor, and provides it to the reconfigurable processor.

[0088] Specifically, the module M1 adopts: a simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor, and obtains the worst-case delay of various operations and routes through dynamic timing simulation analysis; in each cycle, the sum of the operation delay and routing delay of each PE constitutes the workload delay of the current PE; by traversing all PEs in the array, the PE with the largest workload delay is identified; the current maximum workload delay is quantified as a workload factor M;

[0089] Compiler optimizations include: aggregating high-latency nodes into the same time slot and minimizing interconnect distances;

[0090] Determine the initialization interval and generate a schedule using iterative modular scheduling; identify the bottleneck nodes that limit the frequency, and adjust the scheduling of the nodes by assigning the bottleneck nodes to the same time slots as much as possible while considering resource constraints; use the fast space mapping algorithm and the improved Dijkstra algorithm for routing; if the current schedule fails to obtain the preset placement and routing results, reschedule the bottleneck node and repeat the above steps; if all attempts to adjust the schedule are unsuccessful, increase the initialization interval and perform rescheduling.

[0091] Specifically, the PVT detection module includes: a tunable replica circuit TRC and a time digital converter TDC;

[0092] Using the tunable replica circuit TRC to track a path whose delay varies with PVT;

[0093] The time-to-digital converter TDC is used to measure the time delay of the tunable replica circuit TRC, and the PVT factor is obtained by quantification;

[0094] The multi-phase clock generation module includes: a phase-locked loop and a delay-locked loop;

[0095] The phase-locked loop generates a reference clock which is input to the delay-locked loop, and the delay-locked loop obtains a multi-phase clock based on the reference clock;

[0096] The phase selection module includes: a phase calculation module and a phase switching module;

[0097] The phase calculation module adopts: calculating the clock index of the next cycle according to the PVT factor and the workload factor;

[0098]

[0099] Wherein, k′ represents the clock index of the next cycle; k represents the clock index of the current cycle; K represents the number of phases of the multi-phase clock; Δk represents the cycle factor;

[0100]

[0101] Where M represents the workload factor; N represents the PVT factor; ε represents a positive integer introduced to ensure clock quality;

[0102] The phase switching module generates a clock signal of the next cycle according to the obtained clock index of the next cycle and the multi-phase clock output generated by the multi-phase clock generating module.

[0103] Specifically, the period of the next clock is calculated according to the period factor;

[0104]

[0105] Wherein, T represents the period of the adaptive clock; Δk represents the period factor; and δt represents the time difference between the rising edges of adjacent phases of the multi-phase clock.

[0106] Example 2

[0107] Embodiment 2 is a preferred embodiment of Embodiment 1

[0108] The present invention is oriented to a reconfigurable processor and proposes for the first time an adaptive clock implementation method and system for developing timing margin of a reconfigurable processor. The adaptive clock scheme of the timing margin caused by workload and environmental changes is comprehensively utilized to fully improve performance and energy efficiency.

[0109] According to the present invention, an adaptive clock implementation method for developing a timing margin of a reconfigurable processor is provided, such as Figure 1 As shown in FIG. , a hardware-software collaborative scheme for exploiting timing margin of a reconfigurable processor is illustrated.

[0110] In terms of software, the simulation tool performs dynamic timing analysis to obtain delay information, and then sends the delay information to the compiler. The compiler generates and optimizes the data flow graph for the application, and encodes the corresponding delay information into the configuration information. The encoded configuration information is stored in the configuration memory in the reconfigurable processor 4.

[0111] In terms of hardware, the adaptive module includes a multi-phase clock generation module 1, a PVT detection module 2, and a phase selection module 3, which develops the timing margin for the reconfigurable processor 4. The PVT detection module 2 detects environmental changes and outputs the PVT factor, which is input into the phase selection module 3 together with the workload factor stored in the reconfigurable processor 4. Based on this information, the phase selection module 3 selects one of the 32 phases generated by the multi-phase clock generation module 1 as an adaptive clock and provides it to the reconfigurable processor 4.

[0112] The multi-phase clock generation module 1 uses a delay locked loop (DLL) to generate a multi-phase clock. The phase locked loop generates a reference clock and serves as an input of the DLL.

[0113] The structure of the PVT detection module 2 is as follows Figure 2 As shown, it consists of a tunable replica circuit (TRC) and a time-to-digital converter (TDC). The tunable replica circuit (TRC) consists of a variable-length hybrid delay chain consisting of inverters, NAND gates, NOR gates, and interconnected delay elements, as well as an inverter chain for fine-tuning. The time-to-digital converter (TDC) consists of a group of flip-flops, whose data inputs are connected to the outputs of the TRC, and whose clock inputs consist of Φ5, Φ 10 , Φ 16 , Φ 21 and Φ 26 The sampling result of the trigger is encoded by the encoder and used as the PVT factor.

[0114] The structure of the phase selection module 3 is as follows Figure 3 As shown in the figure, it is divided into two modules: phase calculation and phase switching. The phase calculation module includes a 3-bit multiplier, a 5-bit unsigned adder and corresponding control logic. The multiplier result enters the accumulator after selection, and the accumulated result is output to the phase switching module. The phase switching module includes a 5-32 decoder, 32 integrated gated clock (ICG) units and a 32-input OR gate. The output of the decoder passes through the register and is used as the enable input of the ICG module. The clock end of the ICG is 32 multi-phase clocks. The result of the ICG is passed to the 32-input OR gate, and the output result is the final adaptive clock.

[0115] The structure of the reconfigurable processor 4 is as follows Figure 4 As shown, it is composed of an array of interconnected processing units (PEs) and data memory, wherein each PE includes a configuration memory, an arithmetic logic unit, a crossbar switch and corresponding control logic.

[0116] like Figure 1As shown in the figure, the overall technical scheme of hardware and software collaboration for developing timing margin of reconfigurable processors is explained. The minimum clock cycle is determined by workload-related configuration and PVT conditions. The former is generated and optimized by software, and the latter is perceived by hardware. In terms of software, the simulation tool performs dynamic timing analysis to obtain the path delay of each operation inside the processing element (PE) and the routing delay between different PEs. The delay information is then passed to the compiler. During the compilation process, the compiler maps the application to the target architecture and encodes the corresponding delay value into the configuration information. The encoded configuration is then stored in the configuration memory and used at runtime. In terms of hardware, the adaptive module includes a multi-phase clock generation module 1, a PVT detection module 2, and a phase selection module 3 to develop timing margin for the reconfigurable processor 4. The PVT detection module captures the changes in PVT by sampling the delay changes of the reference circuit. The monitoring results, together with the encoded configuration, are transmitted to the phase selection module. The phase selection module uses this information to select the forward or backward phase in the multi-phase clock as the rising edge of the next clock, thereby achieving rapid adjustment of the clock cycle. The output clock can not only be used as the master clock of the reconfigurable processor to realize the development of timing relaxation, but also can be used as the input clock of the adaptive clock module for feedback to form a closed-loop control system and enhance the robustness of the system.

[0117] Specifically, since clock adjustment is achieved by adjusting the phase of the next rising edge, the clock period is determined by the difference between two consecutively selected phases. The current phase is denoted as φ, the next phase is denoted as φ′, and the multi-phase clock period is denoted as T ref Considering that the phase changes periodically with a period of 2π, the period of the adaptive clock can be expressed as formula (1).

[0118]

[0119] like Figure 5 As shown in Figure 1, the adaptive clock scheme uses the current phase and its reverse as the boundary. When the next phase falls within the interval (φ+π, φ+2π), the clock cycle is compressed. On the contrary, if the next phase falls within the interval (φ, φ+π), the clock cycle is stretched, indicating a delay of more than one cycle compared to the current phase. The adjustable range is 50% to 150% of the reference clock period.

[0120] The multiphase clock generator is used to generate K equidistant clock phases (Φ0, Φ1, ..., Φ K-1 ), where the time interval between adjacent clocks is δt = T ref / K, the phase difference is δΦ=2π / K. Figure 6As shown in Figure 1, when switching from Φ1 to Φ4 at time t1, the clock cycle is extended by 3δt; when switching from Φ4 to Φ3 at time t2, the clock cycle is compressed by δt. For the quantized phase, equation (1) can be transformed into equation (2).

[0121]

[0122] Wherein, T represents the period of the adaptive clock.

[0123] The clock period is proportional to the increment of the phase index (Δk, also known as the period factor). Since the clock period is determined orthogonally by the workload and PVT, the period factor is proportional to the product of the workload factor (M) and the PVT factor (N), calculated by equation (3).

[0124]

[0125] M and N are quantitative values ​​that reflect the impact of workload and PVT. The upper bound of the period factor is 3K / 2, and the lower bound is slightly larger than K / 2. This is to avoid glitches and timing errors caused by too small clock cycles under optimal workload and PVT conditions. In practice, due to the periodicity of the phase, the next selected phase index k′ is calculated as shown in formula (4).

[0126]

[0127] This behavior is similar to overflow in an unsigned adder, which suggests that if the value of K is a power of 2, it can be implemented using an unsigned adder. Therefore, quantization needs to satisfy the following constraints:

[0128]

[0129] For example, K = 32, M max =8,N max =6 is a set of feasible integer solutions for the above constraints. This set of solutions corresponds to a 32-phase clock, with the workload factor quantized to 8 discrete values ​​and the PVT factor quantized to 6 discrete values. Both the workload and the PVT factor can be represented by a 3-bit binary number. At runtime, after obtaining the values ​​of M and N, the value of k′ is calculated using equations (3) and (4), and then the phase corresponding to the value is selected as the rising edge of the next clock, allowing the clock period to be adaptively adjusted.

[0130] Specifically, the multi-phase clock is generated using a delay-locked loop (DLL). Once stabilized, the frequency of the DLL is locked to the frequency of the reference clock, generating a 32-phase clock with equal phase spacing. Each delay stage is carefully designed to minimize the phase mismatch between adjacent phases. In addition, in order to minimize the phase deviation caused by routing, the DLL is placed close to the phase selection module. The overall phase mismatch is limited to a very small range and is taken into account in the phase selection module to prevent any potential timing errors.

[0131] Specifically, the function of the PVT detection module 2 is to track and measure the delay changes caused by PVT changes. The system consists of a tunable replica circuit (TRC) as a test path and a time-to-digital converter (TDC) as a monitor. The output of the TDC provides a PVT factor, which reflects the impact of PVT on the delay. The TRC is used to track the path where the delay changes with PVT changes. The TRC consists of a variable-length hybrid delay chain consisting of inverters, NAND gates, NOR gates and interconnected delay elements, as well as an inverter chain for fine-tuning. Since the TRC is constructed with multiple logic gates and its length can be adjusted after silicon, it can effectively match the delay curve under different PVT conditions. The TDC is used to measure the delay of the TRC and obtain the PVT factor after quantization. The TDC consists of a series of flip-flops whose D inputs are connected to the output of the TRC and whose clk inputs are driven by a multi-phase clock. Since the PVT factor is a 3-bit binary value from 0 to 5, 5 clock phases Φ5, Φ 10 , Φ 16 , Φ 21 and Φ 26 As the clk input of the trigger in the TDC. Then, the encoder generates the corresponding PVT factor according to the first "1" after a series of "0". Figure 7 As shown in the figure, the first "1" appears after a series of "0"s in the fourth phase, indicating that N = 3. In the next cycle, no "1" appears after a series of "0", indicating that N = 5. The generated multi-phase clock can not only be synthesized into adaptive clocks with different periods, but also be used as the reference clock of the TDC, reducing the overhead of the entire system.

[0132] Specifically, the phase selection module is divided into two modules: phase calculation and phase switching. Figure 3As shown. The phase calculation module calculates the next phase to be selected based on the current workload factor and PVT factor. The phase switching module selects the corresponding clock phase as the rising edge of the next clock cycle. The phase calculation module takes the current phase index, workload factor and PVT factor as input, and generates the next phase index as output. The calculation method is shown in equations (3) and (4): On the one hand, equation (3) uses a 3-bit multiplier and control logic to calculate the phase offset; on the other hand, equation (4) uses a 5-bit unsigned adder to calculate the next phase index based on the current phase index and the calculated phase offset. Mapping the phase calculation to an unsigned adder and multiplier is an efficient and hardware-friendly implementation. After determining the phase index of the upcoming clock cycle, the phase switching module is activated to pull the corresponding phase high. The process includes using a decoder to convert the 5-bit binary representation into a 32-bit one-hot code, which is used as an enable signal for the multi-phase integrated gated clock (ICG) unit. These ICG units allow multi-phase clocks to pass through and then be transmitted to the multi-input OR gate. The multi-input OR gate uses Figure 3 The structure shown, rather than utilizing a synthesized tree-OR gate, ensures equalization of delays at each stage and reduces overhead.

[0133] More specifically, unlike the PVT factor which is hardware aware, the workload factor is obtained from the configuration information generated by the compiler. Therefore, the software process includes mapping the application onto the architecture and optimizing it, as well as encoding the timing information obtained from the simulation into the configuration. Through dynamic timing simulation, the worst-case latency of various operations and routes is obtained. In each cycle, the sum of the operation latency of each PE and the routing latency to its consumers constitutes the workload latency of the PE. By traversing all PEs in the array, the PE with the largest workload latency is identified. Then, this maximum workload latency is quantized into a 3-bit value, denoted as M, called the workload factor. Since all PEs share the same M, we only need to modify the relevant information of a single PE. We choose to use a constant value field to represent this information, because in most cases not all PEs' constant fields are valid, and use the compiler to handle any potential error conditions. Therefore, this modification does not have any side effects. At runtime, the load factor M is extracted and sent to the adaptive clock module to help adjust the clock cycle. This method quantizes the operation latency and routing latency into workload factors and integrates them seamlessly into the configuration without introducing too much overhead.

[0134] For such a statically scheduled reconfigurable processor, the compiler that generates the configuration is crucial to achieving high performance. Reconfigurable processor compilers usually use modular scheduling algorithms to implement placement and routing and generate configurations. In modular scheduling, the scheduling of one iteration of the cycle is repeated at a fixed time interval, called the initialization interval (II). The scheduling time of a node within an iteration is expressed in timeslots, which is calculated as timeslot = cycle%II. Figure 8 In the example shown, the data flow graph (DFG) schedule is repeated every two cycles, indicating that II = 2. Node a is allocated in timeslot0 and node c is allocated in timeslot1. When implementing adaptive clocks, the compiler must not only consider minimizing II, but also fully utilizing the available time slack. Therefore, the compiler optimizes from two aspects. First, high-latency nodes are aggregated into the same time slot. For example, Figure 8 As shown, by simply postponing the emission time of node d, the latency of timeslot1 can be reduced and the overall performance can be improved. Secondly, minimize the interconnection distance. Because the latency of a node is determined by both operation and interconnection. In summary, the goal of the compiler is to assign high-latency nodes to the same timeslot as much as possible and minimize the interconnection distance, especially for high-operation latency nodes.

[0135] The proposed optimization algorithm is Fig. 9 As shown in Algorithm 1 in . First, determine the initialization interval II and generate a schedule using iterative modulo scheduling. Then, identify the "bottleneck" nodes that limit the frequency. Subsequently, adjust the schedule of these "bottleneck" nodes by assigning them to the same time slot as much as possible, taking into account resource constraints. Due to the cacheless on-chip network, the reconfigurable processor architecture provides single-cycle communication between remote PEs, effectively decoupling routing and placement. After optimizing the schedule, we use the fast space mapping algorithm and the improved Dijkstra algorithm for routing. The improved routing algorithm gives higher priority to nodes with higher operation latency. It ensures that the mapped PEs can use the cacheless on-chip network for routing conflict-free communication and ensures that the distance between the high-latency PE and its corresponding predecessor and successor PE is the shortest. If the current schedule fails to obtain a valid placement and routing result, reschedule the "bottleneck" node and repeat the above steps. If all attempts to adjust the schedule are unsuccessful, increase II and perform rescheduling. This algorithm can effectively utilize the time redundancy of the reconfigurable processor and improve processor performance and resource utilization.

[0136] Those skilled in the art know that, in addition to implementing the system, device and its various modules provided by the present invention in a purely computer-readable program code, it is entirely possible to implement the same program in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers and embedded microcontrollers by logically programming the method steps. Therefore, the system, device and its various modules provided by the present invention can be considered as a hardware component, and the modules included therein for implementing various programs can also be considered as structures within the hardware component; the modules for implementing various functions can also be considered as both software programs for implementing the method and structures within the hardware component.

[0137] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. An adaptive clock implementation method for developing timing margin of a reconfigurable processor, characterized in that: include: Step S1: The simulation tool performs dynamic timing analysis on the application program executed by the reconfigurable processor to obtain delay information; The delay information is sent to the compiler, and the compiler generates and optimizes the data flow graph for the application, and encodes the corresponding delay information into the configuration information, and obtains the workload factor based on the encoded configuration information; Step S2: The workload factor and the PVT factor generated by the PVT detection module are input into the phase selection module. The phase selection module selects one of the multi-phase clocks generated by the multi-phase clock generation module as an adaptive clock according to the workload factor and the PVT factor, and provides it to the reconfigurable processor.

2. The method for implementing an adaptive clock for developing timing margin of a reconfigurable processor according to claim 1, characterized in that: The step S1 adopts: a simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor, and obtains the worst-case delay of various operations and routes through dynamic timing simulation analysis; in each cycle, the sum of the operation delay and routing delay of each PE constitutes the workload delay of the current PE; by traversing all PEs in the array, the PE with the largest workload delay is identified; and the current maximum workload delay is quantified as a workload factor M.

3. The method for implementing an adaptive clock for developing timing margin of a reconfigurable processor according to claim 1, characterized in that: Compiler optimizations include: aggregating high-latency nodes into the same time slot and minimizing interconnect distances; Determine the initialization interval and generate a schedule using iterative modular scheduling; identify the bottleneck nodes that limit the frequency, and adjust the scheduling of the nodes by assigning the bottleneck nodes to the same time slots as much as possible while considering resource constraints; use the fast space mapping algorithm and the improved Dijkstra algorithm for routing; if the current schedule fails to obtain the preset placement and routing results, reschedule the bottleneck node and repeat the above steps; if all attempts to adjust the schedule are unsuccessful, increase the initialization interval and perform rescheduling.

4. The method for implementing an adaptive clock for developing timing margin of a reconfigurable processor according to claim 1, characterized in that: The PVT detection module includes: a tunable replica circuit TRC and a time digital converter TDC; Using the tunable replica circuit TRC to track a path whose delay varies with PVT; The time-to-digital converter TDC is used to measure the time delay of the tunable replica circuit TRC, and the PVT factor is obtained through quantification.

5. The method for implementing an adaptive clock for developing timing margin of a reconfigurable processor according to claim 1, characterized in that: The multi-phase clock generation module includes: a phase-locked loop and a delay-locked loop; The phase-locked loop generates a reference clock which is input to the delay-locked loop, and the delay-locked loop obtains a multi-phase clock based on the reference clock.

6. The method for implementing an adaptive clock for developing timing margin of a reconfigurable processor according to claim 1, characterized in that: The phase selection module includes: a phase calculation module and a phase switching module; The phase calculation module adopts: calculating the clock index of the next cycle according to the PVT factor and the workload factor; Wherein, k′ represents the clock index of the next cycle; k represents the clock index of the current cycle; K represents the number of phases of the multi-phase clock; Δk represents the cycle factor; Where M represents the workload factor; N represents the PVT factor; ε represents a positive integer introduced to ensure clock quality; The phase switching module generates a clock signal of the next cycle according to the obtained clock index of the next cycle and the multi-phase clock output generated by the multi-phase clock generating module.

7. The method for implementing an adaptive clock for developing timing margin of a reconfigurable processor according to claim 1, characterized in that: The period of the next clock is calculated based on the period factor; Wherein, T represents the period of the adaptive clock; Δk represents the period factor; and δt represents the time difference between the rising edges of adjacent phases of the multi-phase clock.

8. An adaptive clock system for exploiting timing margin of a reconfigurable processor, characterized in that: include: Module M1: The simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor to obtain delay information; The delay information is sent to the compiler, and the compiler generates and optimizes the data flow graph for the application, and encodes the corresponding delay information into the configuration information, and obtains the workload factor based on the encoded configuration information; Module M2: The workload factor and the PVT factor generated by the PVT detection module are input into the phase selection module. The phase selection module selects one of the multi-phase clocks generated by the multi-phase clock generation module as an adaptive clock according to the workload factor and the PVT factor, and provides it to the reconfigurable processor.

9. The adaptive clock system for developing timing margin of a reconfigurable processor according to claim 8, characterized in that: The module M1 adopts: a simulation tool performs dynamic timing analysis on the application executed by the reconfigurable processor, and obtains the worst-case delay of various operations and routes through dynamic timing simulation analysis; in each cycle, the sum of the operation delay and routing delay of each PE constitutes the workload delay of the current PE; by traversing all PEs in the array, the PE with the largest workload delay is identified; and the current maximum workload delay is quantified as a workload factor M; Compiler optimizations include: aggregating high-latency nodes into the same time slot and minimizing interconnect distances; Determine the initialization interval and generate a schedule using iterative modular scheduling; identify the bottleneck nodes that limit the frequency, and adjust the scheduling of the nodes by assigning the bottleneck nodes to the same time slots as much as possible while considering resource constraints; use the fast space mapping algorithm and the improved Dijkstra algorithm for routing; if the current schedule fails to obtain the preset placement and routing results, reschedule the bottleneck node and repeat the above steps; if all attempts to adjust the schedule are unsuccessful, increase the initialization interval and perform rescheduling.

10. The adaptive clock system for developing timing margin of a reconfigurable processor according to claim 8, characterized in that: The PVT detection module includes: a tunable replica circuit TRC and a time digital converter TDC; Using the tunable replica circuit TRC to track a path whose delay varies with PVT; The time-to-digital converter TDC is used to measure the time delay of the tunable replica circuit TRC, and the PVT factor is obtained by quantification; The multi-phase clock generation module includes: a phase-locked loop and a delay-locked loop; The phase-locked loop generates a reference clock which is input to the delay-locked loop, and the delay-locked loop obtains a multi-phase clock based on the reference clock; The phase selection module includes: a phase calculation module and a phase switching module; The phase calculation module adopts: calculating the clock index of the next cycle according to the PVT factor and the workload factor; Among them, k ′ represents the clock index of the next cycle; k represents the clock index of the current cycle; K represents the number of phases of the multi-phase clock; Δk represents the cycle factor; Where M represents the workload factor; N represents the PVT factor; ε represents a positive integer introduced to ensure clock quality; The phase switching module generates a clock signal of the next cycle according to the obtained clock index of the next cycle and the multi-phase clock output generated by the multi-phase clock generating module.

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