Wafer defect detection method and device

Abstract

The invention provides a wafer defect detection method and device, and belongs to the technical field of semiconductor manufacturing. The wafer defect detection method comprises the steps that defect data of the surface of each wafer are acquired, and the defect data comprise defect position coordinates, defect sizes and defect types; superposing the defect data of the plurality of wafers to generate a comprehensive defect distribution diagram of the plurality of wafers; analyzing the comprehensive defect distribution diagram by utilizing a spatial clustering algorithm, and judging whether the comprehensive defect distribution diagram has a COP defect distribution mode or not; if the COP defect distribution pattern exists in the comprehensive defect distribution diagram, calculating risk scores of the plurality of wafers according to the defect distribution density, the defect size and the defect distribution rule by utilizing a defect identification model; and comparing the risk scores of the plurality of wafers with a preset risk threshold, and if the risk scores are greater than the preset risk threshold, determining that the plurality of wafers have COP defects. According to the invention, the COP defect of the wafer can be identified.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a wafer defect detection method and device. Background Art

[0002] In the semiconductor manufacturing process, the crystal originated particle (COP) defect is an important defect that affects the quality of the wafer. It is a void-type defect that exists in the wafer, and usually small etching pits will appear after being treated with an oxidizing solution. This defect will appear as a particle (Light Point Defect Non-Cleanable, LPD-N) under the particle detector on the wafer surface. Due to its small size, dispersed distribution and no aggregation, traditional single-wafer defect detection equipment often has difficulty in effectively identifying this type of defect distribution. Summary of the invention

[0003] The present invention provides a wafer defect detection method and device, which can identify the COP defect of the wafer.

[0004] In order to achieve the above object, the technical solution adopted by the embodiment of the present invention is:

[0005] A wafer defect detection method, comprising:

[0006] Acquire defect data on the surface of each wafer, wherein the defect data includes defect location coordinates, defect size, and defect type;

[0007] Overlaying defect data of multiple wafers to generate a comprehensive defect distribution map of the multiple wafers;

[0008] Analyzing the comprehensive defect distribution map using a spatial clustering algorithm to determine whether the comprehensive defect distribution map has a COP defect distribution pattern;

[0009] If the comprehensive defect distribution map has a COP defect distribution pattern, using a defect recognition model to calculate risk scores of the plurality of wafers according to defect distribution density, defect size and defect distribution law;

[0010] The risk scores of the plurality of wafers are compared with a preset risk threshold, and if the risk scores are greater than the preset risk threshold, the plurality of wafers are determined to have COP defects.

[0011] In some embodiments, the COP defect distribution pattern includes at least one of the following:

[0012] COP defects show a centrally clustered distribution;

[0013] COP defects show edge-aggregated distribution;

[0014] COP defects are distributed in concentric bands.

[0015] In some embodiments, the multiple wafers are from the same batch of wafers produced using the same production process parameters.

[0016] In some embodiments, the method further comprises:

[0017] Matching the production process parameters of the plurality of wafers with the production process parameters of the first wafer in the historical database;

[0018] The risk threshold is adjusted according to a matching degree between production process parameters of the plurality of wafers and production process parameters of the first wafer, where the first wafer is a wafer determined to have a COP defect.

[0019] In some embodiments, adjusting the risk threshold according to the matching degree between the production process parameters of the plurality of wafers and the production process parameters of the first wafer includes:

[0020] If the matching degree between the production process parameters of the plurality of wafers and the production process parameters of the first wafer is greater than or equal to a preset first matching degree, lowering the risk threshold;

[0021] If the matching degree between the production process parameters of the plurality of wafers and the production process parameters of the first wafer is less than or equal to a preset second matching degree, increasing the risk threshold;

[0022] The second matching degree is smaller than the first matching degree.

[0023] In some embodiments, after determining that the plurality of wafers have COP defects, the method further includes:

[0024] The plurality of wafers are intercepted, and risk reports of the plurality of wafers are generated, wherein the risk report includes COP defect modes, production process parameters and corresponding corrective measures of the plurality of wafers.

[0025] An embodiment of the present invention further provides a wafer defect detection device, comprising:

[0026] An acquisition module is used to acquire defect data on the surface of each wafer, wherein the defect data includes defect position coordinates, defect size and defect type;

[0027] A superposition module, used for superimposing defect data of multiple wafers to generate a comprehensive defect distribution map of the multiple wafers;

[0028] An analysis module, used to analyze the comprehensive defect distribution map using a spatial clustering algorithm to determine whether the comprehensive defect distribution map has a COP defect distribution pattern;

[0029] A calculation module, configured to calculate risk scores of the plurality of wafers according to defect distribution density, defect size and defect distribution law by using a defect recognition model if a COP defect distribution pattern exists in the comprehensive defect distribution map;

[0030] The determination module is used to compare the risk scores of the multiple wafers with a preset risk threshold, and if the risk scores are greater than the preset risk threshold, determine that the multiple wafers have COP defects.

[0031] An embodiment of the present invention further provides an electronic device, comprising: a processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the wafer defect detection method as described above.

[0032] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the wafer defect detection method as described above are implemented.

[0033] An embodiment of the present invention further provides a computer program product, including computer instructions, which, when executed by a processor, implement the steps of the wafer defect detection method as described above.

[0034] The beneficial effects of the present invention are:

[0035] In this embodiment, by superimposing and analyzing the defect data of multiple wafers, potential COP defect distribution patterns can be discovered at the batch level, effectively improving the interception capability of COP defects; this embodiment introduces a spatial clustering algorithm and a defect recognition model, which can comprehensively evaluate COP defect risks from multiple angles, improve the accuracy of the evaluation and the judgment effect. Based on the identified COP defects, accurate shipment decisions and interception can be made at the batch level, preventing batch COP defects from being released in batches, and improving the overall quality control level of wafer shipments. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram showing a flow chart of a wafer defect detection method according to an embodiment of the present invention;

[0037] Figure 2 A schematic diagram showing the distribution of COP defects after superimposing defect data of multiple wafers according to an embodiment of the present invention;

[0038] Figure 3 A schematic diagram showing the structure of a wafer defect detection device according to an embodiment of the present invention;

[0039] Figure 4A schematic diagram showing the structure of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.

[0041] The appearance of COP defects often has batch characteristics, that is, they may show a regular distribution pattern in the same batch of wafers, but they are difficult to detect on a single wafer. The inspection results of a single wafer often show a "normal" state, and the risk of COP defects will only appear when the defect distribution of the entire batch or multiple wafers (Lot) is superimposed and analyzed.

[0042] The current Automatic Defect Classification (ADC) model only focuses on the defect type and distribution of a single wafer, but ignores the overall defect characteristics at the batch or lot level. This leads to inaccurate capture when facing batch COP defects, and is unable to effectively warn and intercept.

[0043] The present invention provides a wafer defect detection method and device, which can effectively identify the COP defect of the wafer.

[0044] The embodiment of the present invention provides a wafer defect detection method, such as Figure 1 As shown, including:

[0045] Step 101: Obtaining defect data on the surface of each wafer, wherein the defect data includes defect location coordinates, defect size, and defect type;

[0046] In the wafer inspection process, wafer surface particle inspection equipment can be used to collect defect data on the surface of each wafer, and the defect data includes defect location coordinates, defect size, defect type, etc.

[0047] Step 102: superimposing defect data of multiple wafers to generate a comprehensive defect distribution map of the multiple wafers;

[0048] The defect data of all wafers in the same batch or lot can be superimposed and analyzed to generate a comprehensive defect distribution map at the batch or lot level. Through superposition processing, the COP defects scattered on a single wafer can be superimposed to form an overall spatial distribution pattern, such as Figure 2The figure shows the distribution diagram of COP defects after the defect data of multiple wafers are superimposed.

[0049] Among them, wafers in the same batch are wafers produced using the same production process parameters.

[0050] Step 103: Analyze the comprehensive defect distribution map using a spatial clustering algorithm to determine whether there is a COP defect distribution pattern in the comprehensive defect distribution map;

[0051] In some embodiments, the COP defect distribution pattern includes at least one of the following:

[0052] COP defects show a centrally clustered distribution;

[0053] COP defects show edge-aggregated distribution;

[0054] COP defects are distributed in concentric bands.

[0055] For the superimposed comprehensive defect distribution map, spatial clustering algorithms (such as DBSCAN, K-Means) and morphological analysis methods are used to identify whether there is a specific COP defect distribution pattern. If the COP defects show a central cluster distribution, an edge cluster distribution, or a concentric band distribution in the entire batch, these spatial features (such as the radius of the concentric band distribution, the density of the central cluster, etc.) will be extracted and marked as potential COP risk patterns.

[0056] Step 104: If the comprehensive defect distribution map has a COP defect distribution pattern, a defect recognition model is used to calculate risk scores of the plurality of wafers according to defect distribution density, defect size, and defect distribution law;

[0057] In this embodiment, the defect recognition model can be trained using defect sample data, and the risk scores of the plurality of wafers can be calculated using the trained defect recognition model according to the defect distribution density, defect size and defect distribution law.

[0058] In order to improve the accuracy of detection, the number of defect recognition models can be multiple, and the multiple defect recognition models can be trained independently. The weight corresponding to each defect recognition model can be set according to the actual situation, and the detection results corresponding to the multiple defect recognition models are weighted and fused to obtain the final risk score. Among them, the multiple defect recognition models can be random forest models, decision tree models, deep learning neural network models, etc.

[0059] Step 105: Compare the risk scores of the plurality of wafers with a preset risk threshold, and if the risk scores are greater than the preset risk threshold, determine that the plurality of wafers have COP defects.

[0060] In this embodiment, by superimposing and analyzing the defect data of multiple wafers, potential COP defect distribution patterns can be discovered at the batch level, effectively improving the interception capability of COP defects; this embodiment introduces a spatial clustering algorithm and a defect recognition model, which can comprehensively evaluate COP defect risks from multiple angles, improve the accuracy of the evaluation and the judgment effect. Based on the identified COP defects, accurate shipment decisions and interception can be made at the batch level, preventing batch COP defects from being released in batches, and improving the overall quality control level of wafer shipments.

[0061] In some embodiments, the multiple wafers may be wafers from the same batch produced using the same production process parameters. In actual production, since the surface morphology of the wafer will be affected by process fluctuations, a fixed risk threshold cannot effectively adapt to morphological changes. In this embodiment, the risk threshold can be dynamically updated to ensure that a high interception accuracy rate can be maintained under different process conditions. The method also includes:

[0062] Matching the production process parameters of the plurality of wafers with the production process parameters of the first wafer in a historical database;

[0063] The risk threshold is adjusted according to a matching degree between production process parameters of the plurality of wafers and production process parameters of the first wafer, where the first wafer is a wafer determined to have a COP defect.

[0064] In some embodiments, adjusting the risk threshold according to the matching degree between the production process parameters of the plurality of wafers and the production process parameters of the first wafer includes:

[0065] If the matching degree between the production process parameters of the plurality of wafers and the production process parameters of the first wafer is greater than or equal to a preset first matching degree, lowering the risk threshold;

[0066] If the matching degree between the production process parameters of the plurality of wafers and the production process parameters of the first wafer is less than or equal to a preset second matching degree, increasing the risk threshold;

[0067] The second matching degree is smaller than the first matching degree.

[0068] In this embodiment, based on the identified COP distribution pattern, the production process parameters (such as crystal growth conditions, batch number, equipment status, etc.) are matched with the known COP risk batches in the historical data. If the matching degree is high, it is determined to be a potential high-risk batch, and the risk threshold is lowered accordingly. In addition, by matching with the known COP risk batches in the historical data, high-risk production process parameters can be obtained, and potential process anomalies or equipment problems can be warned in time, helping process engineers to take preventive measures in advance to avoid the spread of batch defects.

[0069] In some embodiments, after determining that the plurality of wafers have COP defects, the method further includes:

[0070] The plurality of wafers are intercepted, and risk reports of the plurality of wafers are generated, wherein the risk report includes COP defect modes, production process parameters and corresponding corrective measures of the plurality of wafers.

[0071] In this embodiment, abnormal wafers can be intercepted in time, and detailed risk reports and improvement suggestions can be provided, thereby effectively preventing the outflow of batch defective products; by conducting risk assessment and shipment interception at the batch level, batch quality accidents can be effectively prevented, and large batches of defective wafers can be avoided. In addition, this embodiment can also perform correlation analysis on batches with similar growth conditions, batch numbers, and equipment status to risk wafers, to prevent the omission of potential COP risks between batches.

[0072] The embodiment of the present invention also provides a wafer defect detection device, such as Figure 3 As shown, including:

[0073] An acquisition module 21 is used to acquire defect data on the surface of each wafer, wherein the defect data includes defect position coordinates, defect size and defect type;

[0074] A superposition module 22 is used to superimpose defect data of multiple wafers to generate a comprehensive defect distribution map of the multiple wafers;

[0075] An analysis module 23 is used to analyze the comprehensive defect distribution map using a spatial clustering algorithm to determine whether the comprehensive defect distribution map has a COP defect distribution pattern;

[0076] A calculation module 24 is used to calculate the risk scores of the plurality of wafers according to the defect distribution density, the size of the defect and the distribution law of the defect by using a defect recognition model if the comprehensive defect distribution map has a COP defect distribution pattern;

[0077] The determination module 25 is used to compare the risk scores of the plurality of wafers with a preset risk threshold, and if the risk scores are greater than the preset risk threshold, determine that the plurality of wafers have COP defects.

[0078] In this embodiment, by superimposing and analyzing the defect data of multiple wafers, potential COP defect distribution patterns can be discovered at the batch level, effectively improving the interception capability of COP defects; this embodiment introduces a spatial clustering algorithm and a defect recognition model, which can comprehensively evaluate COP defect risks from multiple angles, improve the accuracy of the evaluation and the judgment effect. Based on the identified COP defects, accurate shipment decisions and interception can be made at the batch level, preventing batch COP defects from being released in batches, and improving the overall quality control level of wafer shipments.

[0079] In some embodiments, the COP defect distribution pattern includes at least one of the following:

[0080] COP defects show a centrally clustered distribution;

[0081] COP defects show edge-aggregated distribution;

[0082] COP defects are distributed in concentric bands.

[0083] In some embodiments, the multiple wafers are from the same batch of wafers produced using the same production process parameters.

[0084] In some embodiments, the device further comprises:

[0085] An adjustment module is used to match the production process parameters of the multiple wafers with the production process parameters of the first wafer in the historical database; adjust the risk threshold according to the matching degree between the production process parameters of the multiple wafers and the production process parameters of the first wafer, and the first wafer is a wafer determined to have a COP defect.

[0086] In some embodiments, the adjustment module is specifically used to reduce the risk threshold if the matching degree between the production process parameters of the multiple wafers and the production process parameters of the first wafer is greater than or equal to a preset first matching degree; if the matching degree between the production process parameters of the multiple wafers and the production process parameters of the first wafer is less than or equal to a preset second matching degree, increase the risk threshold;

[0087] The second matching degree is smaller than the first matching degree.

[0088] In some embodiments, if the plurality of wafers are determined to have COP defects, the device further includes:

[0089] The interception module is used to intercept the multiple wafers and generate risk reports for the multiple wafers, wherein the risk report includes COP defect modes, production process parameters and corresponding corrective measures for the multiple wafers.

[0090] Please refer to Figure 4 An embodiment of the present invention further provides an electronic device 30, including a processor 31, a memory 32, and a computer program stored in the memory 32 and executable on the processor 31. When the computer program is executed by the processor 31, each process of the above-mentioned wafer defect detection method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0091] The embodiment of the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, each process of the above-mentioned wafer defect detection method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. Among them, the computer-readable storage medium includes permanent and non-permanent, removable and non-removable media, and information storage can be realized by any method or technology. The information can be a computer-readable instruction, a data structure, a module of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape magnetic disk storage or other magnetic storage terminal device to be detected or any other non-transmission medium, which can be used to store information that can be accessed by the terminal device to be detected. According to the definition in this article, computer-readable storage media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0092] The present application also provides a computer program product, including computer instructions, which, when executed by a processor, implement the above Figure 1 The various processes of the method embodiment shown can achieve the same technical effect, and will not be described again here to avoid repetition.

[0093] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0094] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0095] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the sequence of the steps. For ordinary technicians in this field, without paying creative work, changes to the sequence of the steps are also within the protection scope of the present disclosure.

[0096] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments, since they are basically similar to the product embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiments.

[0097] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A wafer defect detection method, characterized in that: include: Acquire defect data on the surface of each wafer, wherein the defect data includes defect location coordinates, defect size, and defect type; Overlaying defect data of multiple wafers to generate a comprehensive defect distribution map of the multiple wafers; Analyzing the comprehensive defect distribution map using a spatial clustering algorithm to determine whether the comprehensive defect distribution map has a COP defect distribution pattern; If the comprehensive defect distribution map has a COP defect distribution pattern, using a defect recognition model to calculate risk scores of the plurality of wafers according to defect distribution density, defect size and defect distribution law; The risk scores of the plurality of wafers are compared with a preset risk threshold, and if the risk scores are greater than the preset risk threshold, the plurality of wafers are determined to have COP defects.

2. The wafer defect detection method according to claim 1, characterized in that: The COP defect distribution pattern includes at least one of the following: COP defects show a centrally clustered distribution; COP defects show edge-aggregated distribution; COP defects are distributed in concentric bands.

3. The wafer defect detection method according to claim 1, characterized in that: The multiple wafers are from the same batch of wafers produced using the same production process parameters.

4. The wafer defect detection method according to claim 3, characterized in that: The method further comprises: Matching the production process parameters of the plurality of wafers with the production process parameters of the first wafer in the historical database; The risk threshold is adjusted according to a matching degree between production process parameters of the plurality of wafers and production process parameters of the first wafer, where the first wafer is a wafer determined to have a COP defect.

5. The wafer defect detection method according to claim 4, characterized in that: The adjusting the risk threshold according to the matching degree between the production process parameters of the plurality of wafers and the production process parameters of the first wafer comprises: If the matching degree between the production process parameters of the plurality of wafers and the production process parameters of the first wafer is greater than or equal to a preset first matching degree, lowering the risk threshold; If the matching degree between the production process parameters of the plurality of wafers and the production process parameters of the first wafer is less than or equal to a preset second matching degree, increasing the risk threshold; The second matching degree is smaller than the first matching degree.

6. The wafer defect detection method according to claim 1, characterized in that: After determining that the plurality of wafers have COP defects, the method further includes: The plurality of wafers are intercepted, and risk reports of the plurality of wafers are generated, wherein the risk report includes COP defect modes, production process parameters and corresponding corrective measures of the plurality of wafers.

7. A wafer defect detection device, characterized in that: include: An acquisition module is used to acquire defect data on the surface of each wafer, wherein the defect data includes defect position coordinates, defect size and defect type; A superposition module, used for superimposing defect data of multiple wafers to generate a comprehensive defect distribution map of the multiple wafers; An analysis module, used to analyze the comprehensive defect distribution map using a spatial clustering algorithm to determine whether the comprehensive defect distribution map has a COP defect distribution pattern; A calculation module, configured to calculate risk scores of the plurality of wafers according to defect distribution density, defect size and defect distribution law by using a defect recognition model if a COP defect distribution pattern exists in the comprehensive defect distribution map; The determination module is used to compare the risk scores of the multiple wafers with a preset risk threshold, and if the risk scores are greater than the preset risk threshold, determine that the multiple wafers have COP defects.

8. An electronic device, characterized in that: include: A processor, a memory, and a program stored in the memory and executable on the processor, wherein when the program is executed by the processor, the steps of the wafer defect detection method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the wafer defect detection method according to any one of claims 1 to 6 are implemented.

10. A computer program product, characterized in that The method comprises computer instructions, which, when executed by a processor, implement the steps of the wafer defect detection method according to any one of claims 1 to 6.

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