Chip packaging structure

Abstract

The invention discloses a chip packaging structure. The chip packaging structure comprises a circuit substrate, a pin support, a first chip, a second chip, a connecting piece and a packaging body. The pin support is stacked on the circuit substrate, and the pin support is bent to form an accommodating space. The first chip is arranged on the pin support and located in the containing space. The second chip is arranged on the circuit substrate and located in the containing space. The connecting piece is connected with the pin support and the circuit substrate. The packaging body is arranged on the circuit substrate and wraps the first chip, the second chip and the pin support. Therefore, according to the invention, the pin support and the circuit substrate are vertically integrated, stacked and packaged, and different chips are arranged on different carriers, so that the plane size of the whole structure is effectively reduced, the difficulty of arranging circuit wiring on the circuit substrate is reduced, and the whole heat dissipation efficiency is improved.

Description

Technical Field

[0001] The present application relates to a chip packaging structure, and in particular to a chip packaging structure applied to a power module. Background Art

[0002] The power module integrates multiple power IC components in a package structure to form a surface mount power component package structure (SMPD Package). In the prior art, the power module is soldered together with the power IC components on the same plane of the carrier board for integration and collaboration. However, the carrier board usually also has other active and passive components and peripheral pins. Therefore, this method of integrating all components on the same plane is likely to cause difficulties in circuit routing layout, is not conducive to heat dissipation, and easily leads to low operating efficiency.

[0003] Therefore, how to overcome the above-mentioned defects through improvement of structural design has become one of the important issues to be solved in this field. Summary of the invention

[0004] The present application provides a chip packaging structure to solve the technical problems in the prior art that multiple components are integrated on the same plane of a carrier board, thereby causing difficulties in circuit routing and heat dissipation.

[0005] In order to solve the above technical problems, one of the technical solutions adopted in this application is to provide a chip packaging structure, which includes a circuit substrate, a pin bracket, a first chip, a second chip, a connector and a package body. The pin bracket is stacked on the circuit substrate, and the pin bracket is bent to form a accommodating space. The first chip is arranged on the pin bracket, and the first chip is located in the accommodating space. The second chip is arranged on the circuit substrate, and the second chip is located in the accommodating space. The connector connects the pin bracket and the circuit substrate. The package body is arranged on the circuit substrate and covers the first chip, the second chip and the pin bracket.

[0006] One of the beneficial effects of the present application is that the chip packaging structure provided by the present application can vertically integrate and stack the pin bracket and the circuit substrate through the technical solutions of "pin brackets stacked on the circuit substrate", "the first chip is arranged on the pin bracket" and "the second chip is arranged on the circuit substrate", and different chips are arranged on different carriers (pin brackets and circuit substrates), thereby effectively reducing the planar size of the overall structure, reducing the difficulty of arranging circuit routing on the circuit substrate, and improving the overall heat dissipation efficiency.

[0007] To further understand the features and technical contents of the present application, please refer to the following detailed description and drawings of the present application. However, the drawings provided are only for reference and illustration and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of a chip packaging structure according to the first embodiment of the present application.

[0009] Figure 2 It is a schematic diagram of a chip packaging structure according to the second embodiment of the present application.

[0010] Figure 3 It is a schematic diagram of a chip packaging structure according to the third embodiment of the present application.

[0011] Figure 4 It is a schematic diagram of a chip packaging structure according to a fourth embodiment of the present application.

[0012] Figure 5 It is a schematic diagram of a chip packaging structure according to the fifth embodiment of the present application.

[0013] Figures 6 to 10 It is a schematic diagram of the steps of the method for manufacturing the chip packaging structure according to the first embodiment of the present application.

[0014] Fig.11 and Fig.12 This is a flow chart of a method for manufacturing a chip packaging structure according to the first embodiment of the present application. DETAILED DESCRIPTION

[0015] The following is an explanation of the implementation methods of the "chip packaging structure" disclosed in this application through specific embodiments. Those skilled in the art can understand the advantages and effects of this application from the contents disclosed in this specification. This application can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of this application. In addition, the drawings of this application are only simple schematic illustrations and are not depicted according to actual sizes. It is stated in advance. The following implementation methods will further explain the relevant technical contents of this application in detail, but the disclosed contents are not intended to limit the scope of protection of this application.

[0016] It should be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are mainly used to distinguish one element from another element. In addition, the term "or" used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0017] First embodiment

[0018] See also Figure 1 As shown, Figure 1Schematic diagram of the chip packaging structure of the first embodiment of the present application. The first embodiment of the present application provides a chip packaging structure M, which includes a first chip 1, a second chip 2, a circuit substrate 3, a pin bracket 4, a connector 5 and a package body 6. The pin bracket 4 is stacked on the circuit substrate 3, and the pin bracket 4 is bent to form a receiving space S. The first chip 1 is arranged on the pin bracket 4 and is located in the receiving space S. The second chip 2 is arranged on the circuit substrate 3, and the pin bracket 4 covers the second chip 2, so that the second chip 2 is located in the receiving space S. In other words, the first chip 1 and the second chip 2 are both located in the receiving space S between the pin bracket 4 and the circuit substrate 3. The connector 5 connects the pin bracket 4 and the circuit substrate 3. The package body 6 is arranged on the circuit substrate 3 and covers the first chip 1, the second chip 2 and the pin bracket 4. More specifically, the package body 6 not only covers the outside of the pin bracket 4, but also fills the receiving space S inside the pin bracket 4, and covers the first chip 1 and the second chip 2.

[0019] In the present application, the first chip 1 disposed on the pin bracket 4 is a power integrated circuit chip (Power IC), such as a power chip made of GaN material. The second chip 2 disposed on the circuit substrate 3 is a driver integrated circuit chip (DriverIC). In addition, for example, the circuit substrate 3 is a laminated PCB structure, and the constituent material of the circuit substrate 3 may include, but is not limited to, ceramic materials, and the package body 6 may be a molding compound.

[0020] The pin support 4 includes a first support 41, a second support 42 and a third support 43. The third support 43 is disposed between the first support 41 and the second support 42. The third support 43 includes an outer surface 431 and an inner surface 432, and the first chip 1 is disposed on the inner surface 432. It should be noted that when the package body 6 covers the outside of the pin support 4, the outer surface 431 is exposed to the package body 6, that is, the outer surface 431 will not be covered by the package body 6.

[0021] The upper and lower surfaces of the circuit substrate 3 include a plurality of metal pads, and the metal pads on the upper surface are electrically connected to the metal pads on the lower surface. Figure 1As shown, the metal pads located on the upper surface include a first metal pad 31, a second metal pad 32 and a third metal pad 33, and the metal pads located on the lower surface include a fourth metal pad 34, a fifth metal pad 35 and a sixth metal pad 36. The present application is not limited by the number of metal pads. Further, the second chip 2 is disposed on the third metal pad 33, and the third metal pad 33 is located between the first metal pad 31 and the second metal pad 32. The connector 5 includes a first welding member 51 and a second welding member 52. When the pin bracket 4 is stacked on the circuit substrate 3, the first welding member 51 connects the first bracket 41 and the first metal pad 31, and the second welding member 52 connects the second bracket 42 and the second metal pad 32. Figure 1 In the embodiment, the first welding member 51 and the second welding member 52 can be made of tin.

[0022] In addition, the chip package structure M further includes a first metal wire 71 and a second metal wire 72, wherein the first metal wire 71 is used to connect the first chip 1 and the first bracket 41, and the second metal wire 72 is used to connect the first chip 1 and the second bracket 42. In addition, the first metal wire 71 and the second metal wire 72 are also enclosed by the package body 6 to prevent the first metal wire 71 and the second metal wire 72 from being electrically connected to each other or between the metal wire and other components to cause a short circuit.

[0023] Therefore, the present application forms a stack structure by stacking the pin bracket 4 on the circuit substrate 3 so that the pin bracket 4 and the circuit substrate 3 are vertically integrated. Through the stack structure, different chips can be set on different carriers, for example, the first chip 1 is set on the pin bracket 4, and the second chip 2 is set on the circuit substrate 3, thereby effectively reducing the plane size of the overall structure. In addition, through the design of the stack structure, the first chip 1 (power integrated circuit chip) and the second chip 2 (driver integrated circuit chip) can form a co-package structure, which can reduce the parasitic inductance generated by the gate loop and the common source between the first chip 1 and the second chip 2, and improve the operating efficiency of the component. Further, as the second chip 2 of the driver integrated circuit chip, it requires many circuit traces and the complexity of the trace layout is high, so the present application sets the second chip 2 on the circuit substrate 3 to meet its need for a larger range of circuit wiring area; as the first chip 1 of the power integrated circuit chip, it needs to transmit a large current and will generate more heat energy, so the present application sets the first chip 1 on the pin bracket 4 to meet its need for efficient heat dissipation. Furthermore, the present application further improves the heat dissipation efficiency by disposing the first chip 1 on the inner surface 432 of the third bracket 43 and using the external heat dissipation fins H to contact the outer surface 431 of the third bracket 43 exposed to the outside.

[0024] Second embodiment

[0025] See also Figure 2 As shown, Figure 2 Schematic diagram of the chip packaging structure of the second embodiment of the present application. The second embodiment of the present application provides a chip packaging structure M, which includes a first chip 1, a second chip 2, a circuit substrate 3, a pin bracket 4, a connector 5 and a packaging body 6. The chip packaging structure M of the second embodiment is similar to that of the first embodiment, and the similarities in structure are not repeated here. The main difference between the chip packaging structure M of the second embodiment and the first embodiment is that the connector 5, that is, the composition structure of the first welding member 51 is different from that of the second welding member.

[0026] As mentioned above, in the first embodiment, the first soldering member 51 and the second soldering member 52 are tin materials. However, in the second embodiment, the first soldering member 51 and the second soldering member 52 are copper core solder balls. The copper core solder ball is a composite structure composed of a copper ball as an inner core and a tin-plated layer on the outer periphery. By designing the first soldering member 51 and the second soldering member 52 as copper core solder balls, the amount of tin between the circuit substrate 3 and the pin bracket 4 can be accurately controlled to ensure that the heights of both sides of the pin bracket 4 are consistent, thereby avoiding tilting caused by uneven amounts of tin on both sides of the pin bracket 4.

[0027] Third embodiment

[0028] See also Figure 3 As shown, Figure 3 Schematic diagram of the chip packaging structure of the second embodiment of the present application. The third embodiment of the present application provides a chip packaging structure M, which includes a first chip 1, a second chip 2, a circuit substrate 3, a pin bracket 4, a connector 5 and a packaging body 6. The chip packaging structure M of the third embodiment is similar to that of the second embodiment, and the similarities in structure are not repeated here. The main difference between the chip packaging structure M of the third embodiment and the second embodiment is that the structure of the circuit substrate 3 is different.

[0029] exist Figure 3 In the embodiment, the circuit substrate 3 further includes at least one heat sink 37, and at least one second heat sink 37 is embedded in the circuit substrate 3 and contacts one of the plurality of metal pads. The present application is not limited by the number of heat sinks 37. For example, the circuit substrate 3 may include a heat sink 37, which is embedded in the circuit substrate 3 and is located between the third metal pad 33 and the sixth metal pad 36. Alternatively, for example, the circuit substrate 3 may include three heat sinks 37, which are embedded in the circuit substrate 3 and are respectively located between the first metal pad 31 and the fourth metal pad 34, between the second metal pad 32 and the fifth metal pad 35, and between the third metal pad 33 and the sixth metal pad 36.

[0030] The heat sink 37 can be made of ceramic material, but the present application is not limited thereto. The present application can improve the heat dissipation efficiency of the chip package structure M by burying the heat sink 37 in the circuit substrate 3. The heat generated by the second chip 2 can be dissipated through the circuit substrate 3. In addition, the pin bracket 4 can also transfer the heat from the first chip 1 to the circuit substrate 3 through the first bracket 41 and the second bracket 42 to further dissipate the heat.

[0031] Fourth embodiment

[0032] See also Figure 4 As shown, Figure 4 Schematic diagram of the chip packaging structure of the fourth embodiment of the present application. The fourth embodiment of the present application provides a chip packaging structure M, which includes a first chip 1, a second chip 2, a circuit substrate 3, a pin bracket 4, a connector 5 and a packaging body 6. The chip packaging structure M of the fourth embodiment is similar to that of the second embodiment, and the similarities in structure are not repeated here. The main difference between the chip packaging structure M of the fourth embodiment and the second embodiment is that the structure of the pin bracket 4 is different.

[0033] exist Figure 4 In the embodiment, the pin bracket 4 also includes a heat sink 44, which is buried in the third bracket 43. The heat sink 44 can be made of ceramic material, which is not limited in the present application. Furthermore, the heat sink 44 protrudes from the two side edges 433 of the third bracket 43, thereby increasing the bonding strength between the pin bracket 4 and the package body 6. Therefore, the present application uses the design of burying the heat sink 44 in the pin bracket 4 to dissipate the heat generated by the first chip 1 through the third bracket 43 and the heat sink 44 inside it, thereby further improving the heat dissipation efficiency of the chip packaging structure M.

[0034] Fifth embodiment

[0035] See also Figure 5 As shown, Figure 5 Schematic diagram of the chip packaging structure of the fifth embodiment of the present application. The fifth embodiment of the present application provides a chip packaging structure M, which includes a first chip 1, a second chip 2, a circuit substrate 3, a pin bracket 4, a connector 5 and a packaging body 6. The chip packaging structure M of the fifth embodiment is similar to that of the fourth embodiment, and the similarities in structure are not repeated here. The main difference between the chip packaging structure M of the fifth embodiment and the fourth embodiment is that the structure of the circuit substrate 3 is different.

[0036] Further, the fifth embodiment of the present application is a combination of the third embodiment and the fourth embodiment. Figure 5 In the embodiment, the circuit substrate 3 further includes at least one heat sink 37 embedded between the upper and lower metal pads, and the pin bracket 4 further includes a heat sink 44 embedded in the third bracket 43 .

[0037] The heat sink 37 and the heat sink 44 can be made of ceramic materials, which is not limited in this application. This application can improve the heat dissipation efficiency of the chip packaging structure M by burying the heat sink 37 in the circuit substrate 3 and the heat sink 44 in the pin bracket 4. The heat generated by the second chip 2 can be dissipated through the circuit substrate 3 and the heat sink 37 inside it, and the heat generated by the first chip 1 can be dissipated through the third bracket 43 and the heat sink 44 inside it.

[0038] Sixth embodiment

[0039] See also Figures 6 to 10 ,as well as Fig.11 and Fig.12 As shown, Figures 6 to 10 Schematic diagram of the steps of the method for manufacturing the chip packaging structure of the first embodiment of the present application, Fig.11 and Fig.12 This is a flow chart of a method for manufacturing a chip packaging structure according to the first embodiment of the present application. The sixth embodiment of the present application provides a method for manufacturing a chip packaging structure, which is applicable to manufacturing a chip packaging structure M according to the first to fifth embodiments. The manufacturing method includes at least the following steps:

[0040] Step S11 : providing a pin bracket 4 , wherein the pin bracket 4 is bent to form an accommodating space S, wherein the pin bracket 4 includes a first bracket 41 , a second bracket 42 and a third bracket 43 , and the third bracket 43 is disposed between the first bracket 41 and the second bracket 42 .

[0041] Step S12 : placing a first chip 1 on the third bracket 43 , so that the first chip 1 is located in the accommodating space S.

[0042] Step S13 : performing a wire bonding process to connect the first chip 1 and the first bracket 41 through a first metal wire 71 , and to connect the first chip 1 and the second bracket 42 through a second metal wire 72 .

[0043] Step S14 : a first welding member 51 is disposed on the pin 411 of the first bracket 41 , and a second welding member 52 is disposed on the pin 421 of the second bracket 42 .

[0044] Step S15: Provide a circuit substrate 3 and set it on the pin bracket 4, wherein the circuit substrate 3 includes a first metal pad 31, a second metal pad 32 and a third metal pad 33, a first welding member 51 is used to connect the first bracket 41 and the first metal pad 31, a second welding member 52 is used to connect the second bracket 42 and the second metal pad 32, and a second chip 2 is provided and set on the third metal pad 33.

[0045] Step S16 : providing a package body 6 disposed on the circuit substrate 3 and covering the first chip 1 , the second chip 2 and the lead support 4 .

[0046] Steps S11 to S13 mainly perform die bonding and wire bonding processes. After the pin support 4 is bent to form a receiving space S, the first chip 1, i.e., the power integrated circuit chip, is placed on the third support 43. It should be noted that the heat sink 44 mentioned in the above embodiment can be embedded in the pin support 4 (see Figure 4 or Figure 5 In addition, the first metal wire 71 and the second metal wire 72 can be connected by a normal bond or a reverse bond, which is not limited in the present application.

[0047] Step S14 and step S15 mainly perform the processes of solder dispensing, lamination and packaging. After the first soldering piece 51 and the second soldering piece 52 are arranged on the pins on both sides of the lead bracket 4, the circuit substrate 3 is then stacked on the lead bracket 4 and joined together by the first soldering piece 51 and the second soldering piece 52. After the circuit substrate 3 and the lead bracket 4 are assembled together, the first chip 1, the second chip 2, the lead bracket 4, the first metal wire 71 and the second metal wire 72 are then encapsulated in the package body 6, and finally inverted to complete the production of the chip package structure M.

[0048] Advantageous Effects of Embodiments

[0049] The chip packaging structure M and its manufacturing method provided in the present application form a stack structure by stacking the pin bracket 4 on the circuit substrate 3 so that the pin bracket 4 and the circuit substrate 3 are vertically integrated. Through the stack structure, the first chip 1 is set on the pin bracket 4, and the second chip 2 is set on the circuit substrate 3, thereby effectively reducing the plane size of the overall structure. In addition, through the design of the stack structure, the first chip 1 (power integrated circuit chip) and the second chip 2 (driver integrated circuit chip) can form a co-package structure, which can reduce the parasitic inductance generated by the gate loop and the common source between the first chip 1 and the second chip 2, and improve the operating efficiency of the component.

[0050] Furthermore, as the second chip 2 of the driving integrated circuit chip, it requires many circuit lines and the line layout is highly complex, so the present application sets the second chip 2 on the circuit substrate 3 to meet its need for a larger circuit wiring area; as the first chip 1 of the power integrated circuit chip, it needs to transmit large currents and will generate more heat energy, so the present application sets the first chip 1 on the pin bracket 4 to meet its need for efficient heat dissipation.

[0051] Furthermore, the present application can accurately control the amount of tin between the circuit substrate 3 and the pin bracket 4 by designing the first welding member 51 and the second welding member 52 as copper core solder balls, ensure the height of both sides of the pin bracket 4 is consistent, and avoid tilting caused by uneven tin on both sides of the pin bracket 4. In addition, the present application can improve the heat dissipation efficiency of the chip packaging structure M by burying the heat sink 37 in the circuit substrate 3 and the heat sink 44 in the pin bracket 4.

[0052] The contents disclosed above are only preferred feasible embodiments of the present application, and are not intended to limit the protection scope of the claims of the present application. Therefore, all equivalent technical changes made using the contents of the present application specification and drawings are included in the protection scope of the claims of the present application.

Claims

1. A chip packaging structure, characterized in that: The chip packaging structure comprises: a circuit substrate; A pin bracket is stacked on the circuit substrate, and the pin bracket is bent to form an accommodating space; A first chip is disposed on the pin bracket, and the first chip is located in the accommodating space; A second chip is disposed on the circuit substrate, and the second chip is located in the accommodating space; a connecting member, connecting the pin bracket and the circuit substrate; and A packaging body is disposed on the circuit substrate and covers the first chip, the second chip and the lead support.

2. The chip packaging structure according to claim 1, characterized in that: The first chip is a power integrated circuit chip, and the second chip is a driver integrated circuit chip.

3. The chip packaging structure according to claim 1, characterized in that: The pin bracket includes a first bracket, a second bracket and a third bracket, the third bracket is arranged between the first bracket and the second bracket, the third bracket includes an outer surface and an inner surface, the first chip is arranged on the inner surface, and the outer surface is exposed to the package body.

4. The chip packaging structure according to claim 3, characterized in that: The circuit substrate includes a plurality of metal pads, the plurality of metal pads include a first metal pad, a second metal pad and a third metal pad, and the second chip is arranged on the third metal pad; the connecting member includes a first welding member and a second welding member, the first welding member is used to connect the first bracket and the first metal pad, and the second welding member is used to connect the second bracket and the second metal pad.

5. The chip packaging structure according to claim 4, characterized in that: The first welding member and the second welding member are made of tin.

6. The chip packaging structure according to claim 4, characterized in that: The first welding member and the second welding member are copper core solder balls.

7. The chip packaging structure according to claim 3, characterized in that: The chip packaging structure further includes a first metal wire and a second metal wire, wherein the first metal wire is used to connect the first chip and the first bracket, and the second metal wire is used to connect the first chip and the second bracket.

8. The chip packaging structure according to claim 4, characterized in that: The pin bracket also includes a heat sink embedded in the third bracket.

9. The chip packaging structure according to claim 8, characterized in that: The heat sink protrudes from a side edge of the third bracket.

10. The chip packaging structure according to claim 9, characterized in that: The heat sink is made of ceramic material.

11. The chip packaging structure according to claim 4, characterized in that: The circuit substrate includes at least one heat sink. The at least one second heat sink is embedded in the circuit substrate and contacts one of the plurality of metal pads.

12. The chip packaging structure according to claim 1, characterized in that: The circuit substrate is a multi-layer circuit board structure.

13. The chip packaging structure according to claim 1, characterized in that: The circuit substrate is made of ceramic material.

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