Method for optimizing manufacturing parameters of special material for high-performance ic chip

Abstract

The invention discloses a special material manufacturing parameter optimization method for a high-performance ic chip, and relates to the technical field of integrated circuits, and the method comprises the steps: employing a multi-stage cache structure to optimize the overall architecture of an integrated circuit chip, and arranging heat dissipation fins on the surface of the integrated circuit chip to carry out heat management optimization on the chip; optimizing the doping process parameters of the integrated circuit chip; optimizing the combination of ion implantation and diffusion process parameters; photoetching process parameters of the integrated circuit chip are optimized; optimizing etching process parameters of the integrated circuit chip; analyzing a time sequence path in the integrated circuit chip, and outputting a path with the longest signal transmission delay and a time sequence conflict point; layout and wiring of circuits in an integrated circuit chip are adjusted, logic design is optimized, and signal delay of a path with the longest signal transmission delay and time sequence conflicts of time sequence conflicts are reduced. By designing a special high-performance IC chip, higher performance and efficiency are provided.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a method for optimizing manufacturing parameters of special materials for high-performance IC chips. Background Art

[0002] Integrated circuits (ICs) are a technology that integrates a large number of semiconductor devices on a single chip. These semiconductor devices include diodes, transistors, field-effect transistors, etc. They store, process and transmit information by controlling the movement of electrons. According to the degree of integration, integrated circuits can be divided into small-scale integrated circuits, medium-scale integrated circuits, large-scale integrated circuits, and ultra-large-scale integrated circuits.

[0003] Integrated circuit chips are widely used in various fields such as computers, mobile phones, televisions, automotive electronics, industrial control, etc. With the continuous development of science and technology, the demand for integrated circuit chips in these fields is also growing. At the same time, with the continuous emergence of new materials and new processes, it will also bring new opportunities and challenges to the development of integrated circuit chips. Especially in emerging fields such as artificial intelligence and the Internet of Things, high-performance, low-power integrated circuit chips have become the hot spot and focus of the market. Summary of the invention

[0004] In order to solve the above technical problems, a method for optimizing the manufacturing parameters of special materials for high-performance IC chips is provided. This technical solution solves the problems raised in the above background technology.

[0005] In order to achieve the above purpose, the technical solution adopted by the present invention is:

[0006] A method for optimizing manufacturing parameters of special materials for high-performance IC chips, comprising:

[0007] The overall architecture of the integrated circuit chip is optimized by using a multi-level cache structure, and heat sink fins are set on the surface of the integrated circuit chip to optimize the thermal management of the chip;

[0008] Based on detecting the change in the carrier mobility of the integrated circuit chip, the doping process parameters of the integrated circuit chip are optimized;

[0009] Optimize the combination of ion implantation and diffusion process parameters, and obtain and output the process parameter combination with the highest doping uniformity by designing at least one set of experiments;

[0010] Improve the accuracy of photolithography patterns by optimizing photolithography process parameters of integrated circuit chips, wherein the photolithography process parameters include light source wavelength, exposure time, development time and photoresist thickness;

[0011] By optimizing the etching process parameters of the integrated circuit chip, the accuracy of the etching pattern and the verticality of the side wall are improved, wherein the etching process parameters include the concentration of the etching solution, the etching temperature and the etching time;

[0012] Analyze the timing paths inside the integrated circuit chip, output the paths with the longest signal transmission delay and the timing conflict points;

[0013] By adjusting the layout and routing of circuits in the integrated circuit chip and optimizing the logic design, the signal delay of the path with the longest signal transmission delay and the timing conflict at the timing conflict point are reduced.

[0014] Preferably, the use of a multi-level cache structure to optimize the overall architecture of the integrated circuit chip and the provision of heat sink fins on the surface of the integrated circuit chip to optimize the thermal management of the chip specifically include:

[0015] Determine whether the update frequency of the data is higher than a first preset threshold, if so, cache the data to the first-level cache layer, if not, do not output it;

[0016] Determine whether the access frequency of the data is higher than a second preset threshold, if so, cache the data in the second-level cache layer, if not, cache the data in the third-level cache layer;

[0017] Obtaining the transmission frequency of each signal transmission module in the integrated circuit chip;

[0018] Based on the transmission frequency of each signal transmission module, the signal transmission modules are placed from the inside to the outside of the integrated circuit chip in order from large to small, so as to reduce the attenuation and interference of the signal during the transmission process;

[0019] Heat dissipation fins are arranged on the surface of the integrated circuit chip to optimize the thermal management of the chip.

[0020] Preferably, the optimizing the doping process parameters of the integrated circuit chip based on detecting the change in the carrier mobility of the integrated circuit chip specifically includes:

[0021] Determine whether the carriers required by the integrated circuit chip are negatively charged free electrons. If so, use pentavalent impurity elements for doping and output that the chip is an N-type semiconductor. If not, use trivalent impurity elements for doping and output that the chip is a P-type semiconductor. The pentavalent impurity elements include phosphorus and arsenic elements, and the trivalent impurity elements include boron and gallium elements.

[0022] On a complete silicon wafer, different doping processes are used to form an N-type semiconductor on one side and a P-type semiconductor on the other side.

[0023] Setting up at least one set of experiments by adjusting the concentration of the doping source, the doping time and the temperature parameters;

[0024] The carrier mobility of the semiconductor in each group of experiments was measured using the transit time method;

[0025] Apply the same DC voltage to the semiconductor sample;

[0026] Select pulse light with the same pulse width to stimulate the semiconductor sample through the transparent electrode to generate a thin layer of electron and hole pairs;

[0027] The induced current is formed on the lower electrode due to the movement of carriers and increases with time;

[0028] Monitor the voltage intensity of the semiconductor sample in real time and calculate the voltage intensity change rate of the semiconductor sample at each moment;

[0029] Determine whether the voltage intensity change rate is higher than a preset change rate threshold. If so, output that the moment is a transition moment and the total power loss value at the transition moment. If not, no output is made.

[0030] The carrier mobility formula was used to calculate the carrier mobility of the semiconductor in each group of experiments;

[0031] The set of experiments with the highest output carrier mobility corresponds to the concentration, doping time, and temperature parameters of the doping source;

[0032] The carrier mobility formula is:

[0033]

[0034] In the formula, μ is the carrier mobility of the semiconductor in each group of experiments, L is the thickness of the semiconductor sample, t0 is the transit time, is the total power loss value at the transition time.

[0035] Preferably, the optimization of the ion implantation and diffusion process parameter combination, by designing at least one set of experiments, to obtain and output the process parameter combination with the highest doping uniformity specifically includes:

[0036] Obtain the doping depth and doping concentration required for integrated circuit chips;

[0037] By adjusting the acceleration voltage parameters of the ion implanter, the implantation energy of the ions can be controlled to obtain the doping depth required for the integrated circuit chip;

[0038] By adjusting the beam current and time of the ion implanter, the ion implantation dose can be controlled, thereby regulating the concentration of doping atoms required for the integrated circuit chip;

[0039] Design at least one set of experiments by adjusting the ion implantation angle, the annealing temperature after ion implantation, the diffusion temperature and the diffusion time;

[0040] Divide the integrated circuit chip in each group of experiments into at least one small cube evenly;

[0041] Calculate the concentration of dopant atoms in at least one small cube respectively;

[0042] Based on the concentration data of doping atoms in the small cube, the uniformity formula is used to calculate the doping uniformity of the integrated circuit chips in each group of experiments;

[0043] Obtain and output the process parameter combination with the highest doping uniformity;

[0044] The uniformity formula is:

[0045]

[0046] Where σ is the doping uniformity of the integrated circuit chip in each group of experiments, ρ i is the concentration of doping atoms in the i-th small cube, ρ is the average value of the concentration data of doping atoms in the small cube, and n is the total number of small cubes.

[0047] Preferably, the step of improving the accuracy of the photolithography pattern by optimizing the photolithography process parameters of the integrated circuit chip specifically includes:

[0048] By adjusting the wavelength parameters of the light source, the resolution of the corresponding photolithography patterns is calculated respectively;

[0049] The wavelength of the light source that outputs the highest resolution of the photolithography pattern;

[0050] Adjust the exposure time parameters and development time parameters;

[0051] Determine whether there is a missing part in the photolithography pattern, if yes, output the corresponding exposure time parameter and development time parameter combination as an undesirable parameter combination, if no, output the corresponding exposure time parameter and development time parameter combination as a desirable parameter combination;

[0052] Obtaining the resolution of the edge portion of the lithographic pattern;

[0053] Outputting the exposure time of a group with the highest resolution of the edge portion of the photolithography pattern from the possible parameter combinations;

[0054] By adjusting the thickness parameters of the photoresist, the contrast of the corresponding photolithographic patterns is calculated respectively;

[0055] Output the thickness parameters of the group with the highest contrast of the photolithography pattern;

[0056] The output light source wavelength parameter, exposure time parameter, development time parameter and photoresist thickness parameter are combined to obtain the optimized photolithography process parameters for the integrated circuit chip.

[0057] Preferably, the step of optimizing the etching process parameters of the integrated circuit chip to improve the accuracy of the etching pattern and the verticality of the sidewalls specifically includes:

[0058] Obtain the required etching depth of the integrated circuit chip;

[0059] By adjusting the etching solution, concentration, temperature and time parameters, the etching rate is controlled to obtain the required etching depth of the integrated circuit chip;

[0060] The pattern exposed and developed on the photoresist is transferred to the integrated circuit chip material by plasma etching to form the desired design pattern;

[0061] The gas in the chamber is excited by an external electromagnetic field to generate a plasma containing high-energy particles;

[0062] The high-energy particles in the plasma remove substances from the surface of the integrated circuit chip material by chemical reactions to generate volatile products;

[0063] The reference surface is determined to be the bottom surface of the integrated circuit chip, and at least two measuring points of the same height are selected on the side wall of the etching pattern by using a laser positioning method;

[0064] Measure the distance from each measuring point along the side wall to the reference surface;

[0065] Calculating the verticality of each side wall of the etching pattern using a side wall verticality formula;

[0066] Determine whether the verticality of each sidewall of the etching pattern is lower than a preset verticality threshold, if so, readjust the etching process parameters, if not, combine and output the concentration of the etching solution, the etching temperature and the etching time as the optimized etching process parameters of the integrated circuit chip;

[0067] The side wall verticality formula is:

[0068]

[0069] In the formula, is the verticality of each side wall of the etching pattern, h is the height of the measurement point, It is the average distance from each measuring point along the side wall to the reference plane.

[0070] Preferably, the timing paths within the integrated circuit chip are analyzed, and the paths with the longest output signal transmission delay and the timing conflict points specifically include:

[0071] Using static timing analysis, by traversing all transmission paths inside the integrated circuit chip, the path with the longest signal transmission delay is output;

[0072] The shortest time that the data signal remains stable before the clock is triggered is the setup time;

[0073] The shortest time that the data signal remains stable after the clock is triggered is the hold time;

[0074] It is determined whether the setup time and hold time of each transmission path inside the integrated circuit chip exceed the preset time threshold range. If so, the transmission path is output as a timing conflict point. If not, no output is made.

[0075] Preferably, the reducing the signal delay of the path with the longest signal transmission delay and the timing conflict of the timing conflict point by adjusting the layout and wiring of the circuit in the integrated circuit chip and optimizing the logic design specifically includes:

[0076] By adjusting the position of the register in the integrated circuit, the signal delay on the path with the longest signal transmission delay is balanced;

[0077] Expand complex logic structures into simple logic units, reducing the number of logic layers and signal delays;

[0078] By reorganizing the signal paths in the circuit and redesigning the layout and wiring of the circuit, the delay and timing conflict of signal transmission can be reduced;

[0079] In chip design, additional timing constraints are used to control the logic synthesis, mapping, placement, and routing processes to reduce logic and routing delays.

[0080] Compared with the prior art, the present invention has the following beneficial effects:

[0081] It helps to reduce defects and failure rates of chips during production and use. By precisely controlling the parameters of the lithography and etching processes, it can reduce chip breakage and rework rates, reduce the waste of raw materials and unnecessary processing steps, and thus reduce chip manufacturing costs. By reasonably designing the heat dissipation system, the heat dissipation effect of the chip can be improved, thereby ensuring stable operation of the chip under high load, helping to extend the service life of the chip and improve the overall performance of the equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0082] Figure 1 It is a flow chart of the method for optimizing the manufacturing parameters of the special material for high-performance IC chips of the present invention;

[0083] Figure 2 A flow chart of a method for optimizing the overall architecture of an integrated circuit chip using a multi-level cache structure according to the present invention;

[0084] Figure 3 A flow chart of a method for optimizing doping process parameters of an integrated circuit chip according to the present invention;

[0085] Figure 4 A flow chart of the method for optimizing the combination of ion implantation and diffusion process parameters of the present invention;

[0086] Figure 5 A flow chart of the method for optimizing photolithography process parameters of integrated circuit chips of the present invention;

[0087] Figure 6 A flow chart of a method for optimizing etching process parameters of an integrated circuit chip according to the present invention;

[0088] Figure 7 A flow chart of a method for analyzing a timing path inside an integrated circuit chip according to the present invention;

[0089] Figure 8 The present invention is a flow chart of a method for adjusting the layout and wiring of circuits in an integrated circuit chip and optimizing logic design. DETAILED DESCRIPTION

[0090] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art may think of other obvious variations.

[0091] Reference Figure 1 As shown, a method for optimizing manufacturing parameters of a dedicated material for a high-performance IC chip includes:

[0092] The overall architecture of the integrated circuit chip is optimized by using a multi-level cache structure, and heat sink fins are set on the surface of the integrated circuit chip to optimize the thermal management of the chip;

[0093] Based on detecting the change in the carrier mobility of the integrated circuit chip, the doping process parameters of the integrated circuit chip are optimized;

[0094] Optimize the combination of ion implantation and diffusion process parameters, and obtain and output the process parameter combination with the highest doping uniformity by designing at least one set of experiments;

[0095] Improve the accuracy of photolithography patterns by optimizing photolithography process parameters of integrated circuit chips, wherein the photolithography process parameters include light source wavelength, exposure time, development time and photoresist thickness;

[0096] By optimizing the etching process parameters of the integrated circuit chip, the accuracy of the etching pattern and the verticality of the side wall are improved, wherein the etching process parameters include the concentration of the etching solution, the etching temperature and the etching time;

[0097] Analyze the timing paths inside the integrated circuit chip, output the paths with the longest signal transmission delay and the timing conflict points;

[0098] By adjusting the layout and routing of circuits in the integrated circuit chip and optimizing the logic design, the signal delay of the path with the longest signal transmission delay and the timing conflict at the timing conflict point are reduced.

[0099] Reference Figure 2 As shown, the overall architecture of the integrated circuit chip is optimized by using a multi-level cache structure, and heat sink fins are set on the surface of the integrated circuit chip to optimize the thermal management of the chip, which specifically includes:

[0100] Determine whether the update frequency of the data is higher than a first preset threshold, if so, cache the data to the first-level cache layer, if not, do not output it;

[0101] Determine whether the access frequency of the data is higher than a second preset threshold, if so, cache the data in the second-level cache layer, if not, cache the data in the third-level cache layer;

[0102] Obtaining the transmission frequency of each signal transmission module in the integrated circuit chip;

[0103] Based on the transmission frequency of each signal transmission module, the signal transmission modules are placed from the inside to the outside of the integrated circuit chip in order from large to small, so as to reduce the attenuation and interference of the signal during the transmission process;

[0104] Heat dissipation fins are arranged on the surface of the integrated circuit chip to optimize the thermal management of the chip.

[0105] High-performance integrated circuit chips generate a lot of heat during operation. If the heat cannot be dissipated in time, the chip temperature will rise, the performance will decline, or even be damaged. Therefore, thermal management optimization is also an important part of structural design. Through reasonable thermal design layout, the use of efficient heat dissipation materials and structures, and the introduction of intelligent thermal control technology, the temperature rise of the chip can be effectively reduced and its heat dissipation performance can be improved. For example, setting heat dissipation fins on the chip surface or using heat pipe heat dissipation technology can significantly improve the heat dissipation efficiency of the chip.

[0106] Reference Figure 3 As shown, based on detecting the change in the carrier mobility of the integrated circuit chip, the optimization of the doping process parameters of the integrated circuit chip specifically includes:

[0107] Determine whether the carriers required by the integrated circuit chip are negatively charged free electrons. If so, use pentavalent impurity elements for doping and output that the chip is an N-type semiconductor. If not, use trivalent impurity elements for doping and output that the chip is a P-type semiconductor. The pentavalent impurity elements include phosphorus and arsenic elements, and the trivalent impurity elements include boron and gallium elements.

[0108] On a complete silicon wafer, different doping processes are used to form an N-type semiconductor on one side and a P-type semiconductor on the other side.

[0109] Setting up at least one set of experiments by adjusting the concentration of the doping source, the doping time and the temperature parameters;

[0110] The carrier mobility of the semiconductor in each group of experiments was measured using the transit time method;

[0111] Apply the same DC voltage to the semiconductor sample;

[0112] Select pulse light with the same pulse width to stimulate the semiconductor sample through the transparent electrode to generate a thin layer of electron and hole pairs;

[0113] The induced current is formed on the lower electrode due to the movement of carriers and increases with time;

[0114] Monitor the voltage intensity of the semiconductor sample in real time and calculate the voltage intensity change rate of the semiconductor sample at each moment;

[0115] Determine whether the voltage intensity change rate is higher than a preset change rate threshold. If so, output that the moment is a transition moment and the total power loss value at the transition moment. If not, no output is made.

[0116] The carrier mobility formula was used to calculate the carrier mobility of the semiconductor in each group of experiments;

[0117] The set of experiments with the highest output carrier mobility corresponds to the concentration, doping time, and temperature parameters of the doping source;

[0118] The carrier mobility formula is:

[0119]

[0120] In the formula, μ is the carrier mobility of the semiconductor in each group of experiments, L is the thickness of the semiconductor sample, t0 is the transit time, is the total power loss value at the transition time.

[0121] Electron mobility is a physical quantity in solid-state physics that describes how fast electrons inside a metal or semiconductor move under the action of an electric field. In semiconductors, another similar physical quantity is called hole mobility. People often use carrier mobility to refer to the overall movement speed of electrons and holes inside a semiconductor.

[0122] Reference Figure 4 As shown, the combination of ion implantation and diffusion process parameters is optimized, and by designing at least one set of experiments, the process parameter combination with the highest doping uniformity is obtained and output, specifically including:

[0123] Obtain the doping depth and doping concentration required for integrated circuit chips;

[0124] By adjusting the acceleration voltage parameters of the ion implanter, the implantation energy of the ions can be controlled to obtain the doping depth required for the integrated circuit chip;

[0125] By adjusting the beam current and time of the ion implanter, the ion implantation dose can be controlled, thereby regulating the concentration of doping atoms required for the integrated circuit chip;

[0126] Design at least one set of experiments by adjusting the ion implantation angle, the annealing temperature after ion implantation, the diffusion temperature and the diffusion time;

[0127] Divide the integrated circuit chip in each group of experiments into at least one small cube evenly;

[0128] Calculate the concentration of dopant atoms in at least one small cube respectively;

[0129] Based on the concentration data of doping atoms in the small cube, the uniformity formula is used to calculate the doping uniformity of the integrated circuit chips in each group of experiments;

[0130] Obtain and output the process parameter combination with the highest doping uniformity;

[0131] The uniformity formula is:

[0132]

[0133] Where σ is the doping uniformity of the integrated circuit chip in each group of experiments, ρ i is the concentration of doping atoms in the ith small cube, is the average value of the concentration data of doping atoms in the small cubes, and n is the total number of small cubes.

[0134] Doping is the process of introducing impurity atoms into semiconductor materials to change their electrical properties. In integrated circuit chip manufacturing, doping is usually used to form PN junctions, adjust resistivity, create ohmic contacts, etc. The doping process can be divided into two main types: diffusion doping and ion implantation doping.

[0135] Reference Figure 5 As shown, by optimizing the lithography process parameters of the integrated circuit chip, the precision of the lithography pattern is improved, specifically including:

[0136] By adjusting the wavelength parameters of the light source, the resolution of the corresponding photolithography patterns is calculated respectively;

[0137] The wavelength of the light source that outputs the highest resolution of the photolithography pattern;

[0138] Adjust the exposure time parameters and development time parameters;

[0139] Determine whether there is a missing part in the photolithography pattern, if yes, output the corresponding exposure time parameter and development time parameter combination as an undesirable parameter combination, if no, output the corresponding exposure time parameter and development time parameter combination as a desirable parameter combination;

[0140] Obtaining the resolution of the edge portion of the lithographic pattern;

[0141] Outputting the exposure time of a group with the highest resolution of the edge portion of the photolithography pattern from the possible parameter combinations;

[0142] By adjusting the thickness parameters of the photoresist, the contrast of the corresponding photolithographic patterns is calculated respectively;

[0143] Output the thickness parameters of the group with the highest contrast of the photolithography pattern;

[0144] The output light source wavelength parameter, exposure time parameter, development time parameter and photoresist thickness parameter are combined to obtain the optimized photolithography process parameters for the integrated circuit chip.

[0145] The photolithography process is an important step in the semiconductor device manufacturing process. This step uses exposure and development to depict geometric structures on the photoresist layer, and then transfers the pattern on the photomask to the substrate through an etching process. The substrate not only includes silicon wafers, but can also be other metal layers and dielectric layers, such as glass and sapphire in SOS.

[0146] Reference Figure 6 As shown, by optimizing the etching process parameters of the integrated circuit chip, improving the accuracy of the etching pattern and the verticality of the sidewall specifically includes:

[0147] Obtain the required etching depth of the integrated circuit chip;

[0148] By adjusting the etching solution, concentration, temperature and time parameters, the etching rate is controlled to obtain the required etching depth of the integrated circuit chip;

[0149] The pattern exposed and developed on the photoresist is transferred to the integrated circuit chip material by plasma etching to form the desired design pattern;

[0150] The gas in the chamber is excited by an external electromagnetic field to generate a plasma containing high-energy particles;

[0151] The high-energy particles in the plasma remove substances from the surface of the integrated circuit chip material by chemical reactions to generate volatile products;

[0152] The reference surface is determined to be the bottom surface of the integrated circuit chip, and at least two measuring points of the same height are selected on the side wall of the etching pattern by using a laser positioning method;

[0153] Measure the distance from each measuring point along the side wall to the reference surface;

[0154] Calculating the verticality of each side wall of the etching pattern using a side wall verticality formula;

[0155] Determine whether the verticality of each sidewall of the etching pattern is lower than a preset verticality threshold, if so, readjust the etching process parameters, if not, combine and output the concentration of the etching solution, the etching temperature and the etching time as the optimized etching process parameters of the integrated circuit chip;

[0156] The side wall verticality formula is:

[0157]

[0158] In the formula, is the verticality of each side wall of the etching pattern, h is the height of the measurement point, It is the average distance from each measuring point along the side wall to the reference plane.

[0159] Etching is a technique that uses chemical reactions or physical impact to remove parts of a material. Etching technology can be divided into two categories: wet etching and dry etching. It was first used to make printing embossed plates such as copper plates and zinc plates. It is also widely used to reduce the weight of instrument panels, nameplates, and thin workpieces that are difficult to process using traditional processing methods. After continuous improvements and development of process equipment, it can also be used for the processing of precision etching products for electronic thin-film parts in the aviation, machinery, and chemical industries. Especially in semiconductor manufacturing, etching is an indispensable technology.

[0160] Reference Figure 7 As shown, the timing paths inside the integrated circuit chip are analyzed, and the paths with the longest output signal transmission delay and timing conflict points specifically include:

[0161] Using static timing analysis, by traversing all transmission paths inside the integrated circuit chip, the path with the longest signal transmission delay is output;

[0162] The shortest time that the data signal remains stable before the clock is triggered is the setup time;

[0163] The shortest time that the data signal remains stable after the clock is triggered is the hold time;

[0164] It is determined whether the setup time and hold time of each transmission path inside the integrated circuit chip exceed the preset time threshold range. If so, the transmission path is output as a timing conflict point. If not, no output is made.

[0165] Timing path analysis is a key step in chip design. It involves the precise calculation and analysis of the delays of all signal transmission paths within the chip. These delays include logic gate delays, interconnect delays, and register delays. By analyzing these delays, it is possible to determine which paths in the chip are critical, that is, which paths have the longest delays and have the greatest impact on the overall performance of the chip.

[0166] Reference Figure 8As shown, by adjusting the layout and wiring of the circuit in the integrated circuit chip and optimizing the logic design, the signal delay of the path with the longest signal transmission delay and the timing conflict of the timing conflict point are reduced, specifically including:

[0167] By adjusting the position of the register in the integrated circuit, the signal delay on the path with the longest signal transmission delay is balanced;

[0168] Expand complex logic structures into simple logic units, reducing the number of logic layers and signal delays;

[0169] By reorganizing the signal paths in the circuit and redesigning the layout and wiring of the circuit, the delay and timing conflict of signal transmission can be reduced;

[0170] In chip design, additional timing constraints are used to control the logic synthesis, mapping, placement, and routing processes to reduce logic and routing delays.

[0171] Timing optimization is a key link in the design and manufacturing process of high-performance integrated circuit chips. It aims to improve the overall performance and stability of the chip by adjusting the signal transmission and processing timing inside the chip, reduce signal delays and timing conflicts inside the chip, and ensure that the signal can be transmitted and processed stably and efficiently inside the chip.

[0172] Furthermore, the present solution also proposes a computer-readable storage medium on which a computer-readable program is stored. When the computer-readable program is called, the above-mentioned method for optimizing manufacturing parameters of special materials for a high-performance IC chip is executed.

[0173] It is understandable that the storage medium may be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; an optical medium, such as a DVD; or a semiconductor medium, such as a solid state drive (SSD).

[0174] In summary, the advantages of the present invention are: it helps to reduce the defects and failure rates of chips during production and use; by precisely controlling the parameters of the lithography and etching processes, it can reduce the breakage rate and rework rate of the wafer, reduce the waste of raw materials and unnecessary processing steps, thereby reducing the manufacturing cost of the chip; by reasonably designing the heat dissipation system, it can improve the heat dissipation effect of the chip, thereby ensuring the stable operation of the chip under high load, helping to extend the service life of the chip and improving the overall performance of the equipment.

[0175] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions only describe the principles of the present invention. The present invention may be subject to various changes and improvements without departing from the spirit and scope of the present invention. These changes and improvements fall within the scope of the present invention. The scope of protection claimed by the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for optimizing manufacturing parameters of special materials for high-performance IC chips, characterized in that: include: The overall architecture of the integrated circuit chip is optimized by using a multi-level cache structure, and heat sink fins are set on the surface of the integrated circuit chip to optimize the thermal management of the chip; Based on detecting the change in the carrier mobility of the integrated circuit chip, the doping process parameters of the integrated circuit chip are optimized; Optimize the combination of ion implantation and diffusion process parameters, and obtain and output the process parameter combination with the highest doping uniformity by designing at least one set of experiments; Improve the accuracy of photolithography patterns by optimizing photolithography process parameters of integrated circuit chips, wherein the photolithography process parameters include light source wavelength, exposure time, development time and photoresist thickness; By optimizing the etching process parameters of the integrated circuit chip, the accuracy of the etching pattern and the verticality of the side wall are improved, wherein the etching process parameters include the concentration of the etching solution, the etching temperature and the etching time; Analyze the timing paths inside the integrated circuit chip, output the paths with the longest signal transmission delay and the timing conflict points; By adjusting the layout and routing of circuits in the integrated circuit chip and optimizing the logic design, the signal delay of the path with the longest signal transmission delay and the timing conflict at the timing conflict point are reduced.

2. The method for optimizing manufacturing parameters of special materials for high-performance IC chips according to claim 1, characterized in that: The use of a multi-level cache structure to optimize the overall architecture of the integrated circuit chip and the provision of heat sink fins on the surface of the integrated circuit chip to optimize the thermal management of the chip specifically include: Determine whether the update frequency of the data is higher than a first preset threshold, if so, cache the data to the first-level cache layer, if not, do not output it; Determine whether the access frequency of the data is higher than a second preset threshold, if so, cache the data in the second-level cache layer, if not, cache the data in the third-level cache layer; Obtaining the transmission frequency of each signal transmission module in the integrated circuit chip; Based on the transmission frequency of each signal transmission module, the signal transmission modules are placed from the inside to the outside of the integrated circuit chip in order from large to small, so as to reduce the attenuation and interference of the signal during the transmission process; Heat dissipation fins are arranged on the surface of the integrated circuit chip to optimize the thermal management of the chip.

3. The method for optimizing manufacturing parameters of special materials for high-performance IC chips according to claim 2, characterized in that: The optimization of the doping process parameters of the integrated circuit chip based on detecting the change in the carrier mobility of the integrated circuit chip specifically includes: Determine whether the carriers required by the integrated circuit chip are negatively charged free electrons. If so, use pentavalent impurity elements for doping and output that the chip is an N-type semiconductor. If not, use trivalent impurity elements for doping and output that the chip is a P-type semiconductor. The pentavalent impurity elements include phosphorus and arsenic elements, and the trivalent impurity elements include boron and gallium elements. On a complete silicon wafer, different doping processes are used to form an N-type semiconductor on one side and a P-type semiconductor on the other side. Setting up at least one set of experiments by adjusting the concentration of the doping source, the doping time and the temperature parameters; The carrier mobility of the semiconductor in each group of experiments was measured using the transit time method; Apply the same DC voltage to the semiconductor sample; Select pulse light with the same pulse width to stimulate the semiconductor sample through the transparent electrode to generate a thin layer of electron and hole pairs; The induced current is formed on the lower electrode due to the movement of carriers and increases with time; Monitor the voltage intensity of the semiconductor sample in real time and calculate the voltage intensity change rate of the semiconductor sample at each moment; Determine whether the voltage intensity change rate is higher than a preset change rate threshold. If so, output that the moment is a transition moment and the total power loss value at the transition moment. If not, no output is made. The carrier mobility formula was used to calculate the carrier mobility of the semiconductor in each group of experiments; The set of experiments with the highest output carrier mobility corresponds to the concentration, doping time, and temperature parameters of the doping source; The carrier mobility formula is: In the formula, μ is the carrier mobility of the semiconductor in each group of experiments, L is the thickness of the semiconductor sample, t0 is the transit time, is the total power loss value at the transition time.

4. The method for optimizing manufacturing parameters of special materials for high-performance IC chips according to claim 3, characterized in that: The optimization of the ion implantation and diffusion process parameter combination, by designing at least one set of experiments, to obtain and output the process parameter combination with the highest doping uniformity specifically includes: Obtain the doping depth and doping concentration required for integrated circuit chips; By adjusting the acceleration voltage parameters of the ion implanter, the implantation energy of the ions can be controlled to obtain the doping depth required for the integrated circuit chip; By adjusting the beam current and time of the ion implanter, the ion implantation dose can be controlled, thereby regulating the concentration of doping atoms required for the integrated circuit chip; Design at least one set of experiments by adjusting the ion implantation angle, the annealing temperature after ion implantation, the diffusion temperature and the diffusion time; Divide the integrated circuit chip in each group of experiments into at least one small cube evenly; Calculate the concentration of dopant atoms in at least one small cube respectively; Based on the concentration data of doping atoms in the small cube, the uniformity formula is used to calculate the doping uniformity of the integrated circuit chips in each group of experiments; Obtain and output the process parameter combination with the highest doping uniformity; The uniformity formula is: Where σ is the doping uniformity of the integrated circuit chip in each group of experiments, ρ i is the concentration of doping atoms in the ith small cube, is the average value of the concentration data of doping atoms in the small cubes, and n is the total number of small cubes.

5. The method for optimizing manufacturing parameters of special materials for high-performance IC chips according to claim 4, characterized in that: The method of improving the accuracy of the photolithography pattern by optimizing the photolithography process parameters of the integrated circuit chip specifically includes: By adjusting the wavelength parameters of the light source, the resolution of the corresponding photolithography patterns is calculated respectively; The wavelength of the light source that outputs the highest resolution of the photolithography pattern; Adjust the exposure time parameters and development time parameters; Determine whether there is a missing part in the photolithography pattern, if yes, output the corresponding exposure time parameter and development time parameter combination as an undesirable parameter combination, if no, output the corresponding exposure time parameter and development time parameter combination as a desirable parameter combination; Obtaining the resolution of the edge portion of the lithographic pattern; Outputting the exposure time of a group with the highest resolution of the edge portion of the photolithography pattern from the possible parameter combinations; By adjusting the thickness parameters of the photoresist, the contrast of the corresponding photolithographic patterns is calculated respectively; Output the thickness parameters of the group with the highest contrast of the photolithography pattern; The output light source wavelength parameter, exposure time parameter, development time parameter and photoresist thickness parameter are combined to obtain the optimized photolithography process parameters for the integrated circuit chip.

6. The method for optimizing manufacturing parameters of special materials for high-performance IC chips according to claim 5, characterized in that: The method of improving the accuracy of etching patterns and the verticality of sidewalls by optimizing etching process parameters of integrated circuit chips specifically includes: Obtain the required etching depth of the integrated circuit chip; By adjusting the etching solution, concentration, temperature and time parameters, the etching rate is controlled to obtain the required etching depth of the integrated circuit chip; The pattern exposed and developed on the photoresist is transferred to the integrated circuit chip material by plasma etching to form the desired design pattern; The gas in the chamber is excited by an external electromagnetic field to generate a plasma containing high-energy particles; The high-energy particles in the plasma remove substances from the surface of the integrated circuit chip material by chemical reactions to generate volatile products; The reference surface is determined to be the bottom surface of the integrated circuit chip, and at least two measuring points of the same height are selected on the side wall of the etching pattern by using a laser positioning method; Measure the distance from each measuring point along the side wall to the reference surface; Calculating the verticality of each side wall of the etching pattern using a side wall verticality formula; Determine whether the verticality of each sidewall of the etching pattern is lower than a preset verticality threshold, if so, readjust the etching process parameters, if not, combine and output the concentration of the etching solution, the etching temperature and the etching time as the optimized etching process parameters of the integrated circuit chip; The side wall verticality formula is: In the formula, is the verticality of each side wall of the etching pattern, h is the height of the measurement point, It is the average distance from each measuring point along the side wall to the reference plane.

7. The method for optimizing manufacturing parameters of special materials for high-performance IC chips according to claim 6, characterized in that: The timing paths within the integrated circuit chip are analyzed, and the paths with the longest output signal transmission delay and timing conflict points specifically include: Using static timing analysis, by traversing all transmission paths inside the integrated circuit chip, the path with the longest signal transmission delay is output; The shortest time that the data signal remains stable before the clock is triggered is the setup time; The shortest time that the data signal remains stable after the clock is triggered is the hold time; It is determined whether the setup time and hold time of each transmission path inside the integrated circuit chip exceed the preset time threshold range. If so, the transmission path is output as a timing conflict point. If not, no output is made.

8. The method for optimizing manufacturing parameters of special materials for high-performance IC chips according to claim 7, characterized in that: The method of reducing the signal delay of the path with the longest signal transmission delay and the timing conflict of the timing conflict point by adjusting the layout and wiring of the circuit in the integrated circuit chip and optimizing the logic design specifically includes: By adjusting the position of the register in the integrated circuit, the signal delay on the path with the longest signal transmission delay is balanced; Expand complex logic structures into simple logic units, reducing the number of logic layers and signal delays; By reorganizing the signal paths in the circuit and redesigning the layout and wiring of the circuit, the delay and timing conflict of signal transmission can be reduced; In chip design, additional timing constraints are used to control the logic synthesis, mapping, placement, and routing processes to reduce logic and routing delays.

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