Chip packaging structure and preparation method thereof, terminal equipment and chip packaging carrier plate

Abstract

The invention provides a chip packaging structure and a preparation method thereof, a terminal device and a chip packaging substrate, and the chip packaging structure comprises a substrate which is provided with a first side and a second side which are oppositely disposed in a first direction; the substrate comprises at least one first groove and a plurality of through holes, an opening of the first groove is located in the first side, and the through holes penetrate through the bottom wall of the first groove in the first direction; the at least one first chip is located in the first groove, and the surface, provided with pins, of the first chip faces the second side; the at least one second chip is located on the second side of the substrate, and the surface, provided with pins, of the second chip faces the first side; the first wiring layer is located on the first side of the substrate, and the first wiring layer is electrically connected with the pins of the first chip; the second wiring layer is located on the second side of the substrate, and the second wiring layer is electrically connected with the pins of the second chip; and a connection line in the through hole and electrically connected with the first wiring layer and the second wiring layer. Stacking of a plurality of chips is achieved, and holing in the chips can be avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip packaging structure and a preparation method thereof, a terminal device and a chip packaging carrier. Background Art

[0002] The recent trend in the semiconductor industry is that products are highly integrated, thin, light, fast, multifunctional and efficient, thus having high reliability. In order to cater to the above trends, chip stacking packaging technology is regarded as an important technology in the semiconductor field. At present, chips are generally stacked in the packaging structure. In the chip stacking packaging structure, multiple chips need to be electrically connected to each other. Currently, the chips are mainly electrically connected to each other using through electrodes that penetrate the chips. However, due to the limitations of related technologies, the effect of chip stacking in the existing packaging structure is not ideal. Summary of the invention

[0003] In view of this, embodiments of the present application provide a chip packaging structure and a preparation method thereof, a terminal device and a chip packaging carrier.

[0004] The first aspect of the present application provides a chip packaging structure, including: A substrate, the substrate having a first side and a second side arranged opposite to each other in a first direction; the substrate comprising at least one first groove and a plurality of through holes, the opening of the first groove being located on the first side, and the through holes penetrating through the bottom wall of the first groove along the first direction; At least one first chip is located in the first groove, and a surface of the first chip having pins faces the second side; at least one second chip, located on the second side of the substrate, with a surface of the second chip having pins facing the first side; A first wiring layer, located on a first side of the substrate, the first wiring layer being electrically connected to pins of the first chip; A second wiring layer, located on the second side of the substrate, the second wiring layer being electrically connected to the pins of the second chip; and The connecting line is located in the through hole and is electrically connected to the first wiring layer and the second wiring layer.

[0005] In one embodiment, the substrate further comprises at least one second groove, the opening of the second groove is located at the second side, and the at least one second chip is located in the second groove; The orthographic projection of the first groove on the plane where the substrate is located at least partially overlaps with the orthographic projection of the second groove on the plane where the substrate is located.

[0006] In one embodiment, the chip packaging structure further includes a filling layer located in a gap formed between the second chip and the groove wall of the second groove, and / or located in a gap formed between the first chip and the groove wall of the first groove; And / or, the substrate is made of glass.

[0007] In one embodiment, the first chip includes at least one logic chip located in the first recess; The second chip includes a plurality of memory chips respectively located in a second groove.

[0008] In one embodiment, the first wiring layer includes a first portion, a second portion, and a third portion, the first portion is electrically connected to the connection line, the second portion is electrically connected to the first portion, and the third portion is located at the first side of the substrate and is electrically connected to the second portion; The second portion is located on the groove wall of the first groove; the angle between the groove wall of the first groove and the first direction is 30° to 60°, or the groove wall of the first groove is parallel to the first direction.

[0009] In one embodiment, the first side is a signal output side, and the first chip is a logic chip.

[0010] In one embodiment, the invention further comprises: a first protective layer, located on the first side of the substrate, wherein the orthographic projection of the first protective layer on the plane where the substrate is located covers the orthographic projection of the first chip on the plane where the substrate is located; The material of the first protective layer includes at least one of polyimide, aromatic benzocyclobutane film and bismaleimide triazine resin.

[0011] In one embodiment, it further includes: a conductive structure located on a side of the third portion facing away from the substrate, the conductive structure being electrically connected to the third portion; and a portion of the conductive structure being embedded in the first protective layer.

[0012] In one embodiment, the second wiring layer further includes a fourth portion, a fifth portion and a sixth portion, the fourth portion is electrically connected to the connection line, the fifth portion is electrically connected to the fourth portion, and the sixth portion is located on the second side of the substrate and is electrically connected to the fifth portion; The fifth portion is located on the groove wall of the second groove, and the angle between the groove wall of the second groove and the first direction is 30° to 60°, or the groove wall of the second groove is parallel to the first direction.

[0013] In one embodiment, the second protective layer and the conductive structure are also included, the second protective layer is located on the second side of the substrate, and the orthographic projection of the second protective layer on the plane where the substrate is located covers the orthographic projection of the second chip on the plane where the substrate is located; the second protective layer covers the sixth portion; The conductive structure is located at a side of the sixth portion facing away from the substrate, and the conductive structure is electrically connected to the sixth portion; The conductive structure is partially embedded in the second protective layer; The material of the second protective layer includes at least one of polyimide, aromatic benzocyclobutane film and bismaleimide triazine resin.

[0014] In one embodiment, the second chip includes a first sub-chip and a second sub-chip, and the first sub-chip and the second sub-chip have different functions; The first wiring layer includes a first portion, a second portion and a third portion, the first portion is electrically connected to the connection line, the second portion is electrically connected to the first portion, the third portion is located at the first side of the substrate and is electrically connected to the second portion, and the second wiring layer includes a fourth portion; The fourth portion is electrically connected to the first sub-chip and the second sub-chip, and the first portion is electrically connected to the first chip; One second groove includes at least one first sub-chip and at least one second sub-chip; and / or one second groove includes at least one first sub-chip, and another second groove includes at least one second sub-chip.

[0015] In one embodiment, the invention further comprises: a sealing layer, which is located on a side of the second chip away from the substrate, and the sealing layer covers the second chip and is in close contact with the substrate.

[0016] In one embodiment, the substrate further comprises at least one second groove, the opening of the second groove is located at the second side, and the at least one second chip is located in the second groove; The chip packaging structure also includes a filling layer located in a gap formed by the second chip and the groove wall of the second groove, and located in a gap formed by the first chip and the groove wall of the first groove; The first wiring layer includes a first portion, a second portion and a third portion, the first portion is electrically connected to the connection line, the second portion is electrically connected to the first portion, and the third portion is located on the first side of the substrate and electrically connected to the second portion; the second portion is located on the wall of the first groove, and the angle between the wall of the first groove and the first direction is 30° to 60°; The chip packaging structure also includes a first protective layer and a conductive structure. The first protective layer is located on the first side of the substrate. The orthographic projection of the first protective layer on the plane where the substrate is located covers the orthographic projection of the first chip on the plane where the substrate is located, and the first protective layer covers the third part. The conductive structure is located on the side of the third part away from the substrate, partially embedded in the first protective layer, and the conductive structure is electrically connected to the third part.

[0017] A second aspect of the present application provides a chip packaging structure, including: A substrate, the substrate comprising at least one first groove and a plurality of through holes, wherein the through holes are connected to the first groove; At least one first chip and at least one second chip, the first chip and the second chip are located on opposite sides of the substrate; at least one first chip is located in the first groove; and the through hole is located between the first chip and the second chip; a wiring layer, located on at least one side of the substrate, the wiring layer being electrically connected to the first chip and the second chip; and The connecting wire is located in the through hole and is electrically connected to the wiring layer.

[0018] A third aspect of the present application provides a method for preparing a chip packaging structure, comprising: At least one first groove is formed on a first side of the substrate; A plurality of through holes are provided on the bottom wall of the first groove, and the through holes penetrate the bottom wall of the first groove along a first direction; preparing connecting wires in the through holes; A first wiring layer is prepared on a first side of the substrate, and a second wiring layer is prepared on a second side of the substrate, the first wiring layer and the second wiring layer are electrically connected via a connecting line, and the first side and the second side are arranged opposite to each other in a first direction; At least one first chip is arranged in the first groove, and at least one second chip is arranged on the second side of the substrate, the surface of the first chip with pins faces the second side, and the surface of the second chip with pins faces the first side; the first wiring layer is electrically connected to the pins of the first chip, and the second wiring layer is electrically connected to the pins of the second chip.

[0019] In one embodiment, the step of disposing at least one second chip on the second side of the substrate includes: opening at least one second groove on the second side of the substrate, and disposing at least one second chip in the second groove.

[0020] In one embodiment, the step of disposing at least one first chip in the first groove and disposing at least one second chip on the second side of the substrate comprises: The second chip is arranged on the second side of the substrate, and a sealing layer is prepared on the side of the second chip facing away from the substrate, wherein the sealing layer covers the second chip and is in close contact with the substrate; At least one first chip is disposed in the first groove.

[0021] A fourth aspect of the present application provides a method for preparing a chip packaging structure, comprising: At least one first groove is formed on a first side of the substrate; A plurality of through holes are provided on the bottom wall of the first groove, and the through holes penetrate the bottom wall of the first groove along a first direction; Preparing a connection line in the through hole; filling the first groove with optical glue, and preparing optical glue on a second side of the substrate that is arranged opposite to the first side in the first direction, and performing a patterning process on the optical glue; The first part and the fourth part are prepared on the surface of the optical adhesive after patterning, and the first part and the fourth part are electrically connected to the connecting wire; At least one first chip is arranged in the first groove, and at least one second chip is arranged on the second side of the substrate; the first chip is electrically connected to the first part, and the second chip is electrically connected to the fourth part; Filling the first groove with underfill glue and drilling a hole in the underfill glue; The second part and the third part are prepared on the surface of the underfill after the punching to obtain the first wiring layer.

[0022] A fifth aspect of the present application provides a terminal device, comprising the above-mentioned chip packaging structure, or comprising the chip packaging structure prepared by the above-mentioned preparation method.

[0023] A sixth aspect of the present application provides a chip packaging substrate, including: A substrate having a first side and a second side disposed opposite to each other in a first direction; at least one first groove, the opening of the first groove being located at the first side; A plurality of through holes, wherein the through holes penetrate the bottom wall of the first groove along a first direction; a connecting wire, located in the through hole; The wiring layer is located on at least one side of the substrate, and the wiring layer is electrically connected to the connecting wire.

[0024] In one embodiment, the wiring layer includes a first wiring layer and a second wiring layer, the first wiring layer is located on the first side of the substrate, the second wiring layer is located on the second side of the substrate, and the first wiring layer and the second wiring layer are both electrically connected to the connection line; The first wiring layer includes a first portion, a second portion and a third portion, the first portion is electrically connected to the connection line, the second portion is electrically connected to the first portion, and the third portion is located at the first side of the substrate and is electrically connected to the second portion; The chip package carrier also includes a first pad located on a side of the first portion away from the bottom wall of the first groove, and the first pad is electrically connected to the first portion; The chip package carrier also includes a second pad located on a side of the second wiring layer away from the substrate, and the second pad is electrically connected to the second wiring layer.

[0025] In one embodiment, it further includes: at least one second groove, the opening of the second groove being located at the second side; The through hole penetrates the bottom wall of the second groove along the first direction; The second wiring layer includes a fourth portion, a fifth portion and a sixth portion connected in sequence, the fourth portion is electrically connected to the connecting line and is located on the bottom wall of the second groove, the fifth portion is electrically connected to the fourth portion, and the sixth portion is located on the second side of the substrate and is electrically connected to the fifth portion; The chip package carrier also includes a second pad located on a side of the fourth portion away from the bottom wall of the second groove, and the second pad is electrically connected to the fourth portion; The material of the substrate is glass.

[0026] According to the packaging structure provided by the embodiment of the present application, at least one first chip is arranged in the first groove of the substrate, at least one second chip is arranged on the second side of the substrate, the first wiring layer is electrically connected to the pins of the first chip, the second wiring layer is electrically connected to the pins of the second chip, and the connecting wire is electrically connected to the first wiring layer and the second wiring layer, so that multiple chips can be stacked, and holes can be avoided in the chips, which effectively improves the yield of the packaging structure, reduces costs, and improves packaging reliability. In addition, the sizes of the first chip and the second chip can be different, which is conducive to the stacking of chips of different sizes, improves the integration of the packaging structure, and can also realize the integration of signals of different chips, so that the packaging structure has multiple functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the cross-sectional structure of a chip packaging structure in one embodiment of the present application.

[0028] Figure 2 This is a schematic cross-sectional structure diagram of a chip packaging structure in another embodiment of the present application.

[0029] Figure 3 This is a schematic cross-sectional structure diagram of a chip packaging structure in another embodiment of the present application.

[0030] Figure 4 This is a schematic cross-sectional structure diagram of a chip packaging structure in another embodiment of the present application.

[0031] Figure 5 This is a schematic cross-sectional structure diagram of a chip packaging structure in another embodiment of the present application.

[0032] Figure 6 This is a schematic cross-sectional structure diagram of a chip packaging structure in another embodiment of the present application.

[0033] Figure 7 This is a schematic cross-sectional structure diagram of a chip packaging structure in another embodiment of the present application.

[0034] Figure 8 This is a schematic cross-sectional structure diagram of a chip packaging structure in another embodiment of the present application.

[0035] Fig. 9 This is a schematic cross-sectional structure diagram of a chip packaging structure in another embodiment of the present application.

[0036] Fig.10 This is a schematic cross-sectional structure diagram of a chip packaging structure in another embodiment of the present application.

[0037] Fig.11 This is a schematic cross-sectional structure diagram of a chip packaging structure in another embodiment of the present application.

[0038] Fig.12This is a schematic cross-sectional view of a chip packaging structure in another embodiment of the present application.

[0039] Fig.13 This is a schematic cross-sectional view of a chip packaging structure in another embodiment of the present application.

[0040] Fig.14 This is a schematic cross-sectional view of a chip packaging structure in another embodiment of the present application.

[0041] Fig.15 This is a schematic cross-sectional view of a chip packaging structure in another embodiment of the present application.

[0042] Fig.16 This is a schematic flow chart of a method for preparing a chip packaging structure in one embodiment of the present application.

[0043] Fig.17 This is a schematic flow chart of a method for preparing a chip packaging structure in another embodiment of the present application.

[0044] Fig.18 It is a schematic diagram of the cross-sectional structure of a chip packaging carrier in one embodiment of the present application.

[0045] Fig.19 This is a schematic cross-sectional structure diagram of a chip packaging carrier in another embodiment of the present application.

[0046] Fig. 20 This is a schematic cross-sectional structure diagram of a chip packaging carrier in another embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0048] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods and means well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0049] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0050] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0051] The first aspect of the present application provides a chip packaging structure, referring to Figure 1 and Figure 2 The schematic diagram of the chip packaging structure shown in the figure, the chip packaging structure includes: a substrate 100, the substrate 100 has a first side 110 and a second side 140 arranged opposite to each other in a first direction x, the substrate 100 includes at least one first groove 120 and a plurality of through holes 130; the opening of the first groove 120 is located on the first side 110, and the through hole 130 passes through the bottom wall of the first groove 120 along the first direction x; at least one first chip 200 is located in the first groove 120, and the surface of the first chip 200 having the pin faces the second side 140; at least A second chip 300 is located on the second side 140 of the substrate 100, and the surface of the second chip 300 having the pins faces the first side 110; a first wiring layer 410 is located on the first side 110 of the substrate 100, and the first wiring layer 410 is electrically connected to the pins of the first chip 200; a second wiring layer 420 is located on the second side 140 of the substrate 100, and the second wiring layer 420 is electrically connected to the pins of the second chip 300; and a connecting wire 430 is located in the through hole 130 and is electrically connected to the first wiring layer 410 and the second wiring layer 420.

[0052] According to the chip packaging structure provided by the embodiment of the present application, at least one first chip 200 is arranged in the first groove 120 of the substrate 100, and at least one second chip 300 is arranged on the second side 140 of the substrate 100. The first wiring layer 410 is electrically connected to the pins of the first chip 200, the second wiring layer 420 is electrically connected to the pins of the second chip 300, and the connecting wire 430 is electrically connected to the first wiring layer 410 and the second wiring layer 420. The stacking of multiple chips can be realized, and the opening of holes in the chip can be avoided, which effectively improves the yield of the chip packaging structure, reduces the cost, and improves the packaging reliability. In addition, the sizes of the first chip 200 and the second chip 300 can be different, which is conducive to the stacking of chips of different sizes, improves the integration of the chip packaging structure, and can also realize the integration of signals of different chips, so that the chip packaging structure has multiple functions.

[0053] It is understandable that the first wiring layer 410 may be a metal wiring, or a metal pad, or may include a metal wiring and a metal pad, and the metal pad is used to be fixedly connected to the first chip 200. The second wiring layer 420 may be a metal wiring, or may be a metal pad, or may include a metal wiring and a metal pad, and the metal pad is used to be fixedly connected to the second chip 300.

[0054] It can be understood that a first groove 120 is opened in the substrate 100, a through hole 130 penetrates the bottom wall of the first groove 120 along the first direction x, and the connecting line 430 fills the through hole 130; the distance between the bottom wall of the first groove 120 and the surface of the substrate 100 located on the second side 140 is short, which is beneficial to shortening the transmission distance of signals between chips, and can improve the operating speed and sensitivity of the chip packaging structure.

[0055] For example, when the second chip 300 is located on the second side 140 of the substrate 100, refer to Figure 1 , the surface of the substrate 100 located on the second side 140 is a plane, and the second chip 300 is located on the second side 140; illustratively, referring to Figure 2 , a second groove 150 is opened on the second side 140 of the substrate 100 , and the second chip 300 is placed in the second groove 150 .

[0056] It is understandable that by respectively opening grooves on the first side 110 and the second side 140 of the substrate, the length of the connecting line 430 is shortened while ensuring that the substrate has high strength, and the signal transmission distance between the first chip 200 and the second chip 300 is shortened, thereby reducing product power consumption.

[0057] In one embodiment, referring to Figure 2 The substrate 100 further includes at least one second groove 150 , an opening of the second groove 150 is located at the second side 140 , and at least one second chip 300 is located in the second groove 150 .

[0058] In one embodiment, the orthographic projection of the first groove 120 on the plane where the substrate 100 is located overlaps at least partially with the orthographic projection of the second groove 150 on the plane where the substrate 100 is located. In one embodiment, the through hole 130 penetrates the bottom wall of the first groove 120 and the second groove 150 along the first direction x. Thus, grooves are respectively provided on opposite sides of the substrate 100, so that the thickness of the substrate 100 between the bottom walls of the grooves on both sides is thinner, and the length of the connecting wire 430 in the first direction x is shorter, which is more conducive to shortening the transmission distance of the signal between the chips, and further improving the operation speed and sensitivity of the chip packaging structure.

[0059] It is understandable that there may be more than one first groove 120 and more than one second groove 150. Optionally, at least one first chip 200 is located in one first groove 120 and at least one second chip 300 is located in one second groove 150.

[0060] In one embodiment, a first chip 200 is located in a first groove 120, and a second chip 300 is located in a second groove 150. Thus, the positioning of the chip is facilitated, and the groove has a better protection effect on the chip, thereby improving the reliability of the chip packaging structure.

[0061] In one embodiment, the first chip 200 and the second chip 300 have different sizes, which facilitates the stacking of chips of different sizes, so that the chip packaging structure has a higher degree of integration and can have the functions of multiple chips.

[0062] It should be noted that the size of the first chip 200 refers to that, in a direction parallel to the plane where the substrate 100 is located, the orthographic projection of the first chip 200 on the plane where the substrate 100 is located is a quadrilateral, and the size of the first chip 200 includes the length and width of the quadrilateral; the size of the second chip 300 refers to that, in a direction parallel to the plane where the substrate 100 is located, the orthographic projection of the second chip 300 on the plane where the substrate 100 is located is a quadrilateral, and the size of the second chip 300 includes the length and width of the quadrilateral. The difference in size between the first chip 200 and the second chip 300 refers to that the length of the orthographic projection of the first chip 200 on the plane where the substrate 100 is located is different from the length of the orthographic projection of the second chip 300 on the plane where the substrate 100 is located, and / or the width of the orthographic projection of the first chip 200 on the plane where the substrate 100 is located is different from the width of the orthographic projection of the second chip 300 on the plane where the substrate 100 is located.

[0063] In a specific embodiment, referring to Figure 2 In the schematic diagram of the chip packaging structure shown, a first chip 200 is located in a first groove 120, and a plurality of second chips 300 are located in a second groove 150, and the size of the first chip 200 is larger than the size of the second chip 300. Thus, it is convenient to stack chips of different sizes, realize the chip packaging structure with the functions of different chips, and the chip packaging structure has a high degree of integration.

[0064] In one embodiment, referring to Figure 3 and Figure 4 The schematic diagram of the chip packaging structure shown in FIG. 1 further includes a filling layer 500, which is located in the gap formed by the second chip 300 and the groove wall of the second groove 150, and / or, is located in the gap formed by the first chip 200 and the groove wall of the first groove 120. Thus, the filling layer 500 is used to fill the gap between the second chip 300 and the groove wall of the second groove 150 and the gap between the first chip 200 and the groove wall of the first groove 120, which is beneficial to improve the packaging stability of the first chip 200 and the second chip 300, and improve the reliability of the chip packaging structure.

[0065] In one embodiment, the first chip 200 includes at least one logic chip located in the first cavity 120 ; and the second chip 300 includes a plurality of memory chips.

[0066] In one embodiment, at least one memory chip is located in one second groove 150. The size of the memory chip is smaller than that of the logic chip, and multiple memory chips are located in one second groove 150 so that the chip packaging structure has a larger storage space. Exemplarily, one memory chip is located in one second groove 150, which facilitates the positioning of the memory chip, and the second groove 150 has an excellent protection effect on the memory chip.

[0067] In one embodiment, referring to Figure 1 and Figure 2 The first wiring layer 410 includes a first portion 411, a second portion 412, and a third portion 413. The first portion 411 is electrically connected to the connection line 430, the second portion 412 is electrically connected to the first portion 411, and the third portion 413 is located at the first side 110 of the substrate 100 and is electrically connected to the second portion 412. Thus, the electrical signals of different chips can be transmitted to the first side 110 through the third portion 413. The first wiring layer 410 has a simple structure, is easy to wire, and has a short transmission distance for electrical signals. The performance of the chip packaging structure is strong.

[0068] It should be noted that the first portion 411 may include a multi-layer wiring structure, and the third portion 413 may include a multi-layer wiring structure.

[0069] In one embodiment, referring to Figure 1 and Figure 2 The second portion 412 is located on the groove wall of the first groove 120, and the groove wall of the first groove 120 is parallel to the first direction x. At this time, the second portion 412 is parallel to the first direction x.

[0070] It should be noted that the first direction x is parallel to the direction from the second side 140 to the first side 110 .

[0071] In another embodiment, referring to Figure 5In the schematic diagram of the chip packaging structure shown in FIG. 1 , the second portion 412 is located on the wall of the first groove 120, and the angle α between the wall of the first groove 120 and the first direction x is 30° to 60° (for example, 30°, 40°, 50°, or 60°, etc.). Therefore, the angle between the second portion 412 and the first direction x is also 30° to 60°, which facilitates the manufacture of the second portion 412. It can be understood that in this embodiment, the second part 412 and the third part 413 can be made by electroplating. After the optical glue is filled in the first groove 120, the optical glue can be patterned to obtain the patterns corresponding to the second part 412 and the third part 413, and then electroplating is performed to obtain the second part 412 and the third part 413; since the second part 412 is located on the groove wall of the first groove 120, that is, the second part 412 is located in the first groove 120, the first groove 120 is used to accommodate the first chip 200, and the depth of the first groove 120 is relatively large relative to the thickness that the optical glue can fill. Therefore, when the angle α between the groove wall of the first groove 120 and the first direction x is 30°~60°, it is convenient for the optical glue to climb to the surface of the substrate 100 close to the first groove 120, which is convenient for the preparation of the second part 412 and the third part 413. Exemplarily, the first chip 200 is a logic chip, the first side 110 is a signal output side, and the provision of the first wiring layer 410 is beneficial to shortening the signal output distance of the logic chip, increasing the operating speed of the chip packaging structure, and thereby improving the performance of the chip packaging structure.

[0072] It should be noted that, in the direction from the second side 140 to the first side 110, the groove wall of the first groove 120 gradually moves away from the first chip 200. It can be understood that the plurality of second chips 300 are arranged along the second direction y, the second chips 300 extend along the third direction, and the second direction y intersects the third direction; each second chip 300 corresponds to a plurality of first portions 411, and the plurality of first portions 411 are arranged at intervals in the third direction. In adjacent second chips 300, some of the first portions 411 are connected to each other to realize the expansion of the chip packaging structure, and some of the first portions 411 can also be electrically connected to the first chip 200 (see for details). Figure 6 ), realize the communication of electrical signals between the first chip 200 and the second chip 300.

[0073] It should be noted that the plane formed by the second direction y and the third direction is parallel to the plane where the substrate 100 is located. The first direction x and the second direction y are perpendicular to each other.

[0074] It should be noted that the second wiring layer 420 includes a plurality of fourth portions 421 , and the fourth portions 421 are electrically connected to the pins of the second chip 300 .

[0075] In one embodiment, referring to Figure 7The structural schematic diagram of the chip packaging structure shown in the figure, the first chip 200 includes a first chip body 210 and a first conductive structure 220, the first conductive structure 220 is located on the surface of the first chip body 210, the first chip body 210 is electrically connected to the first wiring layer 410 through the first conductive structure 220, the second chip 300 includes a second chip body 310 and a second conductive structure 320, the second conductive structure 320 is located on the surface of the second chip body 310, the second chip body 310 is electrically connected to the second wiring layer 420 through the second conductive structure 320.

[0076] In one embodiment, referring to Figure 7 The schematic diagram of the chip packaging structure shown in the figure further includes: a first protective layer 600, which is located on the first side 110 of the substrate 100, and the orthographic projection of the first protective layer 600 on the plane where the substrate 100 is located covers the orthographic projection of the first chip 200 on the plane where the substrate 100 is located. This helps to improve the reliability of the chip packaging structure.

[0077] In one embodiment, the first protective layer 600 covers the third portion 413. Optionally, the material of the first protective layer includes at least one of polyimide (PI), aromatic benzocyclobutane film (ABF) and bismaleimide triazine resin (BT).

[0078] In one embodiment, referring to Figure 8 The chip packaging structure further includes: a conductive structure 700, located on a side of the third portion 413 away from the substrate 100, and the conductive structure 700 is electrically connected to the third portion 413. The conductive structure 700 may be a conductive terminal, so that the electrical signal in the chip packaging structure can be transmitted to subsequent structures through the conductive structure 700.

[0079] In one embodiment, the conductive structure 700 is partially embedded in the first protection layer 600. This helps to improve the stability of the chip packaging structure.

[0080] In one embodiment, the substrate 100 is made of glass. Therefore, glass has a strong bearing capacity, so that the chip packaging structure has a strong stability; and the price of glass is relatively low.

[0081] In one embodiment, referring to Fig. 9As shown in the schematic diagram of the structure of the chip packaging structure, the second wiring layer 420 includes a fourth portion 421, a fifth portion 422 and a sixth portion 423 connected in sequence, the fourth portion 421 is electrically connected to the connecting wire 430, the fifth portion 422 is electrically connected to the fourth portion 421, and the sixth portion 423 is located on the second side 140 of the substrate 100 and is electrically connected to the fifth portion 422. Thus, the electrical signals of different chips can be transmitted to the second side 140 through the sixth portion 423, the second wiring layer 420 has a simple structure, is easy to wire, and has a short transmission distance of the electrical signal, and the performance of the chip packaging structure is strong.

[0082] It should be noted that the fourth portion 421 may include a multi-layer wiring structure, and the sixth portion 423 may include a multi-layer wiring structure.

[0083] In one embodiment, the fifth portion 422 is located on the groove wall of the second groove 150 , and the groove wall of the second groove 150 is parallel to the first direction x. At this time, the fifth portion 422 is parallel to the first direction x.

[0084] In another embodiment, referring to Fig.10 , the fifth portion 422 is located on the groove wall of the second groove 150, and the angle β between the groove wall of the second groove 150 and the first direction x is 30° to 60° (for example, it can be 30°, 40°, 50°, or 60°, etc.). Therefore, the fifth portion 422 also has an angle of 30° to 60° with the first direction x, which facilitates the manufacture of the fifth portion 422. It can be understood that in this embodiment, the fifth part 422 and the sixth part 423 can be made by electroplating. After the optical glue is filled in the second groove 150, the optical glue is patterned to obtain the patterns corresponding to the fifth part 422 and the sixth part 423, and then electroplating is performed to obtain the fifth part 422 and the sixth part 423; since the fifth part 422 is located on the groove wall of the second groove 150, that is, the fifth part 422 is located in the second groove 150, the second groove 150 is used to accommodate the second chip 300, and the depth of the second groove 150 is relatively large relative to the thickness that the optical glue can fill. Therefore, when the angle β between the wall groove of the second groove 150 and the first direction x is 30°~60°, it is convenient for the optical glue to climb to the surface of the substrate 100 close to the second groove 150, which is convenient for the preparation of the fifth part 422 and the sixth part 423.

[0085] It should be noted that, in the direction from the first side 110 to the second side 140 , the groove wall of the second groove 150 gradually moves away from the second chip 300 .

[0086] In one embodiment, referring to Fig.11The chip packaging structure further includes a filling layer 500, which is located in the gap formed by the second chip 300 and the second groove 150, and / or in the gap formed by the first chip 200 and the first groove 120. Thus, the filling layer 500 is used to fill the gap between the second chip 300 and the second groove 150 and the gap between the first chip 200 and the first groove 120, which is beneficial to improve the packaging stability of the first chip 200 and the second chip 300, and improve the reliability of the chip packaging structure.

[0087] In one embodiment, referring to Fig.12 The chip packaging structure further includes: a second protective layer 800, which is located on the second side of the substrate 100, and the orthographic projection of the second protective layer 800 on the plane where the substrate 100 is located covers the orthographic projection of the second chip 300 on the plane where the substrate 100 is located. This helps to improve the reliability of the chip packaging structure.

[0088] In one embodiment, the second protective layer 800 covers the sixth portion 423. Optionally, the material of the second protective layer includes at least one of polyimide (PI), aromatic benzocyclobutane film (ABF) and bismaleimide triazine resin (BT).

[0089] In one embodiment, referring to Fig.13 The chip packaging structure further includes: a conductive structure 700, located on a side of the sixth portion 423 away from the substrate 100, and the conductive structure 700 is electrically connected to the sixth portion 423. Thus, the electrical signal in the chip packaging structure can be transmitted to subsequent structures through the conductive structure 700.

[0090] In one embodiment, the conductive structure 700 is partially embedded in the second protection layer 800. This helps to improve the stability of the chip packaging structure.

[0091] Exemplarily, the surface of the substrate 100 located on the second side 140 is a plane. Fig.14 The schematic diagram of the chip packaging structure shown in the figure, the chip packaging structure also includes: a sealing layer 900, which is located on the side of the second chip 300 away from the substrate 100, and the sealing layer 900 covers the second chip 300 and is in close contact with the substrate 100. Therefore, the second chip 300 can be directly arranged on the second side 140 without opening a groove on the second side 140 of the substrate 100, and the second chip 300 is packaged using the sealing layer 900, which reduces the process of opening the second groove 150 in the substrate 100 and reduces the manufacturing difficulty.

[0092] In one embodiment, referring to Fig.15In the schematic diagram of the chip packaging structure shown in FIG. 1 , the second chip 300 includes a first sub-chip 301 and a second sub-chip 302, and the first sub-chip 301 and the second sub-chip 302 have different functions. Thus, chips with different functions can be integrated into the chip packaging structure, making the chip packaging structure more powerful.

[0093] In one embodiment, the first wiring layer 410 includes a first part 411, a second part 412 and a third part 413, and the second wiring layer 420 includes a fourth part 421. The first part 411 and the fourth part 421 are electrically connected to the connecting line 430, the second part 412 is electrically connected to the first part 411, and the third part 413 is located on the first side 110 of the substrate 100 and is electrically connected to the second part 412; the fourth part 421 is electrically connected to the first sub-chip 301 and the second sub-chip 302, and the first part 411 is electrically connected to the first chip 200.

[0094] In one embodiment, one second groove 150 includes at least one first sub-chip 301 and at least one second sub-chip 302; and / or one second groove 150 includes at least one first sub-chip 301, and another second groove 150 includes at least one second sub-chip 302. Thus, it is convenient to realize the integration of different types of chips, and the arrangement of the first sub-chip 301 and the second sub-chip 302 is flexible and diverse.

[0095] In a specific embodiment, the substrate 100 further includes at least one second groove 150, the opening of the second groove 150 is located on the second side 140, at least one second chip 300 is located in the second groove 150, and the chip packaging structure further includes a filling layer 500, which is located in the gap surrounded by the second chip 300 and the groove wall of the second groove 150, and, is located in the gap surrounded by the first chip 200 and the groove wall of the first groove 120; the first wiring layer 410 includes a first portion 411, a second portion 412 and a third portion 413, the first portion 411 is electrically connected to the connecting line 430, the second portion 412 is electrically connected to the first portion 411, and the third portion 413 is located on the first side 110 of the substrate 100 and is electrically connected to the second portion 412; the second portion 412 is located on the groove wall of the first groove 120, and the angle α between the groove wall of the first groove 120 and the first direction x is 30° to 60° (specifically refer to Figure 6 ); the chip packaging structure also includes a first protective layer 600, which is located on the first side 110 of the substrate 100, and the orthographic projection of the first protective layer 600 on the plane where the substrate 100 is located covers the orthographic projection of the first chip 200 on the plane where the substrate 100 is located; the first protective layer 600 covers the third part 413; the chip packaging structure also includes a conductive structure 700, which is located on the side of the third part 413 away from the substrate 100, and the conductive structure 700 is electrically connected to the third part 413; the conductive structure 700 is partially embedded in the first protective layer 600.

[0096] The second aspect of the present application provides a chip packaging structure, referring to Figure 1 The chip packaging structure includes: a substrate 100, the substrate 100 includes at least one first groove 120 and a plurality of through holes 130, the through holes 130 are connected to the first groove 120; at least one first chip 200 and at least one second chip 300, the first chip 200 and the second chip 300 are located on opposite sides of the substrate 100; at least one first chip 200 is located in the first groove 120; the through hole 130 is located between the first chip 200 and the second chip 300; a wiring layer 400, located on at least one side of the substrate 100, the wiring layer 400 is electrically connected to the first chip 200 and the second chip 300; and a connecting wire 430, located in the through hole 130 and electrically connected to the wiring layer 400.

[0097] The third aspect of the present application provides a method for preparing a chip packaging structure, referring to Fig.16 As shown in the schematic flow chart of the preparation method, the preparation method of the chip packaging structure includes the following steps.

[0098] S110: Opening at least one first groove on a first side of the substrate.

[0099] It should be noted that the base and the first groove are consistent with the above description and will not be described in detail here.

[0100] Exemplarily, the method of forming at least one first groove on the first side of the substrate includes, but is not limited to, laser scribing, mechanical scribing, laser-induced wet etching, and the like.

[0101] S120: Opening a plurality of through holes on the bottom wall of the first groove.

[0102] The through hole penetrates the bottom wall of the first groove along the first direction.

[0103] It should be noted that the through hole is consistent with the previous description and will not be described in detail here.

[0104] Exemplarily, the method of opening a plurality of through holes on the bottom wall of the first groove includes, but is not limited to, laser scribing, mechanical scribing, laser-induced wet etching, and the like.

[0105] S130: preparing connecting wires in the through holes.

[0106] It should be noted that the connection wire is consistent with the above description, and will not be described in detail here. The preparation method of the connection wire includes but is not limited to electroplating, coating, etc.

[0107] S140: preparing a first wiring layer on the first side of the substrate, and preparing a second wiring layer on the second side of the substrate.

[0108] It should be noted that the first wiring layer and the second wiring layer are consistent with the above description and will not be described in detail here.

[0109] Exemplarily, the first wiring layer and the second wiring layer are electrically connected via a connection line.

[0110] In one embodiment, preparing a first wiring layer on a substrate and preparing a second wiring layer on a second side of the substrate includes: filling optical glue in the first groove and the second groove, and patterning the optical glue; preparing the first wiring layer and the second wiring layer on the surface of the patterned optical glue; illustratively, electroplating can be performed on the surface of the patterned optical glue to obtain the first wiring layer and the second wiring layer.

[0111] S150: Dispose at least one first chip in the first groove, and dispose at least one second chip on the second side of the substrate.

[0112] The surface of the first chip with pins faces the second side, and the surface of the second chip with pins faces the first side; the first wiring layer is electrically connected to the pins of the first chip, and the second wiring layer is electrically connected to the pins of the second chip.

[0113] It can be understood that the first chip includes a chip body and a first conductive structure located on a surface of the chip body having pins, and the first conductive structure can be connected to the first portion of the first wiring layer by welding. The second chip includes a chip body and a second conductive structure located on a surface of the chip body having pins, and the second conductive structure can be connected to the fourth portion of the second wiring layer by welding.

[0114] It should be noted that the first chip and the second chip are consistent with the above description and will not be described in detail here.

[0115] In one embodiment, the step of arranging at least one second chip on the second side of the substrate includes: opening at least one second groove on the second side of the substrate, and arranging at least one second chip in the second groove. Thus, opening the second groove is conducive to further reducing the length of the connection line and improving the signal transmission rate.

[0116] In another embodiment, the step of arranging at least one first chip in the first groove and arranging at least one second chip on the second side of the substrate includes: arranging the second chip on the second side of the substrate, preparing a sealing layer on the side of the second chip away from the substrate, the sealing layer covering the second chip and being in close contact with the substrate; arranging at least one first chip in the first groove. Thus, when the substrate is made of glass, the risk of substrate fragmentation is reduced.

[0117] The fourth aspect of the present application provides a method for preparing a chip packaging structure, referring to Fig.17As shown in the schematic flow chart of the preparation method, the preparation method of the chip packaging structure includes the following steps.

[0118] S210: Opening at least one first groove on a first side of a substrate.

[0119] It should be noted that the first groove is consistent with the previous description and will not be elaborated here.

[0120] S220: A plurality of through holes are formed on the bottom wall of the first groove, wherein the through holes penetrate the bottom wall of the first groove along a first direction.

[0121] It should be noted that the through hole is consistent with the previous description and will not be described in detail here.

[0122] S230: preparing a connection line in the through hole.

[0123] It should be noted that the connection wire is consistent with the above description, and will not be described in detail here. The preparation method of the connection wire includes but is not limited to electroplating, coating, etc.

[0124] S240: filling the first groove with optical glue, preparing optical glue on a second side of the substrate that is arranged opposite to the first side in the first direction, and performing patterning on the optical glue.

[0125] It should be noted that the optical adhesive may be patterned by laser etching, and the pattern in the optical adhesive after the patterning process corresponds to the shape of the first wiring layer.

[0126] S250: preparing a first portion and a fourth portion on the surface of the patterned optical adhesive, the first portion and the fourth portion are electrically connected to the connecting wire, and removing the first optical adhesive.

[0127] Exemplarily, electroplating may be performed on the surface of the patterned optical adhesive to obtain the first part and the fourth part.

[0128] It should be noted that the first, second, third and fourth parts are consistent with the previous description and will not be elaborated here.

[0129] S260: at least one first chip is disposed in the first groove, and at least one second chip is disposed on the second side of the substrate; the first chip is electrically connected to the first portion, and the second chip is electrically connected to the fourth portion.

[0130] It should be noted that the first chip and the second chip are consistent with the above description and will not be described in detail here.

[0131] S270: Filling the first groove with an underfill and drilling a hole in the underfill.

[0132] It should be noted that the underfill can fill the gap between the groove wall of the first groove and the first chip.

[0133] Exemplarily, holes may be punched in the underfill by mechanical scribing, and a pattern formed after the holes are punched corresponds to the patterns of the fourth portion and the fifth portion.

[0134] S280: preparing a second portion and a third portion on the surface of the underfill after the punching to obtain a first wiring layer.

[0135] The second part is electrically connected to the first part, and the third part is located on the first side of the substrate.

[0136] Exemplarily, electroplating may be performed on the bottom fill after the drilling to obtain the second part and the third part.

[0137] A fifth aspect of the present application provides a terminal device, comprising the above-mentioned chip packaging structure, or comprising the chip packaging structure prepared by the above-mentioned preparation method.

[0138] It should be noted that the terminal device may be a desktop computer, a tablet computer, a high-computing calculator, etc. It should be noted that in addition to the chip packaging structure described above, the terminal device may also include structures that a conventional terminal device should have, such as a display panel, a touch panel, a housing, etc., which will not be described in detail here.

[0139] The sixth aspect of the present application provides a chip packaging substrate, referring to Fig.18 The schematic structural diagram of the chip package carrier shown in the figure comprises: a substrate 100; the substrate has a first side 110 and a second side 140 arranged opposite to each other in a first direction x; at least one first groove 120, the opening of the first groove 120 is located on the first side 110; a plurality of through holes 130, the through holes 130 pass through the bottom wall of the first groove 120 along the first direction x; connecting wires 430, located in the through holes 130; a wiring layer 400, located on at least one side of the substrate 100, the wiring layer 400 is electrically connected to the connecting wires 430.

[0140] It should be noted that the base, the first groove, the through hole, the first side and the first direction are consistent with the previous description and will not be described in detail here.

[0141] The chip package carrier of this embodiment can carry chips of different sizes and functions, thereby realizing chip integration. Moreover, the distance between the bottom wall of the first groove and the surface located on the second side of the substrate is short, and the length of the through hole in the first direction is short, which is conducive to shortening the signal transmission distance between chips.

[0142] In one embodiment, the wiring layer 400 includes a first wiring layer 410 and a second wiring layer 420 . The first wiring layer 410 is located on the first side 110 of the substrate 100 , and the second wiring layer 420 is located on the second side 140 of the substrate 100 . Both the first wiring layer 410 and the second wiring layer 420 are electrically connected to the connection line 430 .

[0143] In one embodiment, the first wiring layer 410 includes a first portion 411, a second portion 412 and a third portion 413, the first portion 411 is electrically connected to the connecting line 430 and is located on the bottom wall of the first groove 120, the second portion 412 is electrically connected to the first portion 411, and the third portion 413 is located on the first side 110 of the substrate 100 and is electrically connected to the second portion 412.

[0144] In one embodiment, referring to Fig.19 As shown in the structural diagram of the chip package carrier, the chip package carrier further includes a first solder pad 1100 located on a side of the first portion 411 away from the bottom wall of the first groove 120 , and the first solder pad 1100 is electrically connected to the first portion 411 .

[0145] In one embodiment, the chip package carrier further includes a second pad 1200 located on a side of the second wiring layer 420 away from the substrate 100 , and the second pad 1200 is electrically connected to the second wiring layer 420 .

[0146] In one embodiment, referring to Fig. 20 The schematic diagram of the structure of the chip package carrier shown in the figure, the chip package carrier also includes: at least one second groove 150, the opening of the second groove 150 is located on the second side 140 of the substrate 100, and the first side 110 and the second side 140 are arranged opposite to each other; the through hole 130 passes through the bottom wall of the second groove 150 along the first direction x. Therefore, the distance between the bottom wall of the first groove and the bottom wall of the second groove is short, and in the first direction, the length of the through hole is further shortened, which is conducive to further shortening the signal transmission distance between chips.

[0147] In one embodiment, the second wiring layer 420 includes a fourth portion 421, a fifth portion 422 and a sixth portion 423, the fourth portion 421 is electrically connected to the connecting line 430 and is located on the bottom wall of the second groove 150, the fifth portion 422 is electrically connected to the fourth portion 421, and the sixth portion 423 is located on the second side 140 of the substrate 100 and is electrically connected to the fifth portion 422.

[0148] In one embodiment, the chip package carrier further includes a second pad 1200 located on a side of the fourth portion 421 away from the bottom wall of the second groove 150 , and the second pad 1200 is electrically connected to the fourth portion 421 .

[0149] In one embodiment, the substrate is made of glass.

[0150] It should be noted that the chip packaging carrier of this embodiment can be combined with the chip packaging carrier described above in whole or in part, which will not be described in detail here.

[0151] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0152] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A chip packaging structure, characterized in that: include: A substrate, the substrate having a first side and a second side arranged opposite to each other in a first direction; the substrate comprising at least one first groove and a plurality of through holes, the opening of the first groove being located on the first side, and the through holes penetrating through the bottom wall of the first groove along the first direction; At least one first chip is located in the first groove, and a surface of the first chip having pins faces the second side; at least one second chip, located at the second side of the substrate, wherein a surface of the second chip having pins faces the first side; A first wiring layer, located on a first side of the substrate, the first wiring layer being electrically connected to pins of the first chip; A second wiring layer, located on a second side of the substrate, the second wiring layer being electrically connected to pins of the second chip; and A connecting line is located in the through hole and is electrically connected to the first wiring layer and the second wiring layer.

2. The chip packaging structure according to claim 1, characterized in that: The substrate further comprises at least one second groove, the opening of the second groove is located at the second side, and at least one second chip is located in the second groove; An orthographic projection of the first groove on the plane where the substrate is located at least partially overlaps with an orthographic projection of the second groove on the plane where the substrate is located.

3. The chip packaging structure according to claim 2, characterized in that: The chip packaging structure further includes a filling layer located in a gap formed by the second chip and a groove wall of the second groove, and / or located in a gap formed by the first chip and a groove wall of the first groove; And / or, the substrate is made of glass.

4. The chip packaging structure according to claim 2 or 3, characterized in that: The first chip includes at least one logic chip located in the first groove; The second chip includes a plurality of memory chips respectively located in one of the second grooves.

5. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The first wiring layer includes a first portion, a second portion and a third portion, the first portion is electrically connected to the connection line, the second portion is electrically connected to the first portion, and the third portion is located at the first side of the substrate and is electrically connected to the second portion; The second portion is located on the wall of the first groove; the angle between the wall of the first groove and the first direction is 30° to 60°, or the wall of the first groove is parallel to the first direction.

6. The chip packaging structure according to claim 5, characterized in that: The first side is a signal output side, and the first chip is a logic chip.

7. The chip packaging structure according to claim 5, characterized in that: Also includes: A first protective layer, located on a first side of the substrate, wherein an orthographic projection of the first protective layer on a plane where the substrate is located covers an orthographic projection of the first chip on a plane where the substrate is located; The material of the first protective layer includes at least one of polyimide, aromatic benzocyclobutane film and bismaleimide triazine resin.

8. The chip packaging structure according to claim 7, characterized in that: Also includes: a conductive structure, located at a side of the third portion away from the substrate, the conductive structure being electrically connected to the third portion; The conductive structure is partially embedded in the first protective layer.

9. The chip packaging structure according to claim 2 or 3, characterized in that: The second wiring layer further includes a fourth portion, a fifth portion and a sixth portion, the fourth portion is electrically connected to the connecting line, the fifth portion is electrically connected to the fourth portion, and the sixth portion is located at the second side of the substrate and is electrically connected to the fifth portion; The fifth portion is located on the groove wall of the second groove, and the angle between the groove wall of the second groove and the first direction is 30° to 60°, or the groove wall of the second groove is parallel to the first direction.

10. The chip packaging structure according to claim 9, characterized in that: Also includes: a second protective layer and a conductive structure, wherein the second protective layer is located on the second side of the substrate, and the orthographic projection of the second protective layer on the plane where the substrate is located covers the orthographic projection of the second chip on the plane where the substrate is located; and the second protective layer covers the sixth portion; The conductive structure is located on a side of the sixth portion away from the substrate, and the conductive structure is electrically connected to the sixth portion; The conductive structure is partially embedded in the second protective layer; The material of the second protective layer includes at least one of polyimide, aromatic benzocyclobutane film and bismaleimide triazine resin.

11. The chip packaging structure according to claim 2, characterized in that: The second chip includes a first sub-chip and a second sub-chip, and the first sub-chip and the second sub-chip have different functions; The first wiring layer includes a first portion, a second portion and a third portion, the first portion is electrically connected to the connection line, the second portion is electrically connected to the first portion, the third portion is located at the first side of the substrate and is electrically connected to the second portion, and the second wiring layer includes a fourth portion; The fourth portion is electrically connected to the first sub-chip and the second sub-chip, and the first portion is electrically connected to the first chip; One of the second grooves includes at least one of the first sub-chips and at least one of the second sub-chips; and / or one of the second grooves includes at least one of the first sub-chips, and another of the second grooves includes at least one of the second sub-chips.

12. The chip packaging structure according to claim 1, characterized in that: Also includes: The sealing layer is located on a side of the second chip away from the substrate. The sealing layer covers the second chip and is in close contact with the substrate.

13. The chip packaging structure according to claim 1, characterized in that: The substrate further comprises at least one second groove, the opening of the second groove is located at the second side, and at least one second chip is located in the second groove; The chip packaging structure further includes a filling layer, which is located in a gap formed by the second chip and the groove wall of the second groove, and is located in a gap formed by the first chip and the groove wall of the first groove; The first wiring layer includes a first portion, a second portion and a third portion, the first portion is electrically connected to the connecting line, the second portion is electrically connected to the first portion, and the third portion is located on the first side of the substrate and electrically connected to the second portion; the second portion is located on the wall of the first groove, and the angle between the wall of the first groove and the first direction is 30° to 60°; The chip packaging structure also includes a first protective layer and a conductive structure, wherein the first protective layer is located on the first side of the substrate, the orthographic projection of the first protective layer on the plane where the substrate is located covers the orthographic projection of the first chip on the plane where the substrate is located, and the first protective layer covers the third part; the conductive structure is located on the side of the third part away from the substrate, is partially embedded in the first protective layer, and is electrically connected to the third part.

14. A chip packaging structure, characterized in that: include: A substrate, wherein the substrate comprises at least one first groove and a plurality of through holes, wherein the through holes are connected to the first groove; at least one first chip and at least one second chip, wherein the first chip and the second chip are located on opposite sides of the substrate; at least one first chip is located in the first groove; The through hole is located between the first chip and the second chip; a wiring layer, located on at least one side of the substrate, the wiring layer being electrically connected to the first chip and the second chip; and A connecting line is located in the through hole and is electrically connected to the wiring layer.

15. A method for preparing a chip packaging structure, characterized in that: include: At least one first groove is formed on a first side of the substrate; A plurality of through holes are provided on the bottom wall of the first groove, wherein the through holes penetrate the bottom wall of the first groove along a first direction; preparing a connecting wire in the through hole; A first wiring layer is prepared on the first side of the substrate, and a second wiring layer is prepared on the second side of the substrate, the first wiring layer and the second wiring layer are electrically connected through the connecting wire, and the first side and the second side are arranged opposite to each other in the first direction; At least one first chip is arranged in the first groove, and at least one second chip is arranged on the second side of the substrate, the surface of the first chip having pins faces the second side, and the surface of the second chip having pins faces the first side; the first wiring layer is electrically connected to the pins of the first chip, and the second wiring layer is electrically connected to the pins of the second chip.

16. The preparation method according to claim 15, characterized in that: The step of arranging at least one second chip on the second side of the substrate includes: opening at least one second groove on the second side of the substrate, and arranging at least one second chip in the second groove.

17. The preparation method according to claim 15, characterized in that: The step of disposing at least one first chip in the first groove and disposing at least one second chip on the second side of the substrate comprises: The second chip is arranged on the second side of the substrate, and a sealing layer is prepared on the side of the second chip away from the substrate, wherein the sealing layer covers the second chip and is in close contact with the substrate; At least one first chip is arranged in the first groove.

18. A method for preparing a chip packaging structure, characterized in that: include: At least one first groove is formed on a first side of the substrate; A plurality of through holes are provided on the bottom wall of the first groove, wherein the through holes penetrate the bottom wall of the first groove along a first direction; preparing a connecting wire in the through hole; Filling the first groove with optical glue, preparing optical glue on a second side of the substrate that is opposite to the first side in a first direction, and performing patterning on the optical glue; Preparing a first portion and a fourth portion on the surface of the optical adhesive after patterning, wherein the first portion and the fourth portion are electrically connected to the connecting wire; At least one first chip is arranged in the first groove, and at least one second chip is arranged on the second side of the substrate; the first chip is electrically connected to the first part, and the second chip is electrically connected to the fourth part; Filling the first groove with an underfill and drilling a hole in the underfill; A second portion and a third portion are prepared on the surface of the underfill after the punching to obtain a first wiring layer.

19. A terminal device, characterized in that: A chip packaging structure comprising any one of claims 1 to 14, or a chip packaging structure prepared by the preparation method of any one of claims 15 to 18.

20. A chip packaging carrier, characterized in that: include: a substrate having a first side and a second side disposed opposite to each other in a first direction; at least one first groove, the opening of the first groove being located at the first side; a plurality of through holes, wherein the through holes penetrate the bottom wall of the first groove along the first direction; A connecting wire, located in the through hole; A wiring layer is located on at least one side of the substrate, and the wiring layer is electrically connected to the connecting line.

21. The chip package carrier according to claim 20, characterized in that: The wiring layer comprises a first wiring layer and a second wiring layer, the first wiring layer is located on the first side of the substrate, the second wiring layer is located on the second side of the substrate, and the first wiring layer and the second wiring layer are both electrically connected to the connection line; The first wiring layer includes a first portion, a second portion and a third portion, the first portion is electrically connected to the connection line, the second portion is electrically connected to the first portion, and the third portion is located at the first side of the substrate and is electrically connected to the second portion; The chip package carrier further includes a first pad located on a side of the first portion away from the bottom wall of the first groove, the first pad being electrically connected to the first portion; The chip package carrier further includes a second pad located on a side of the second wiring layer away from the substrate, and the second pad is electrically connected to the second wiring layer.

22. The chip package carrier according to claim 20 or 21, characterized in that: Also includes: at least one second groove, the opening of the second groove being located at the second side; The through hole penetrates the bottom wall of the second groove along the first direction; The second wiring layer includes a fourth portion, a fifth portion and a sixth portion connected in sequence, the fourth portion is electrically connected to the connecting line and is located on the bottom wall of the second groove, the fifth portion is electrically connected to the fourth portion, and the sixth portion is located on the second side of the substrate and is electrically connected to the fifth portion; The chip package carrier further includes a second pad located on a side of the fourth portion away from the bottom wall of the second groove, the second pad being electrically connected to the fourth portion; The substrate is made of glass.

Images