Circuit determination method and device, nonvolatile storage medium and electronic equipment

Abstract

The invention discloses a circuit determination method and device, a nonvolatile storage medium and electronic equipment. The method comprises the following steps: acquiring respective current-sharing voltage of a plurality of chips; a plurality of initial circuit models are established respectively, and the number of parallel branches included in each initial circuit model is the same; according to the respective current-sharing voltage of the plurality of chips, a plurality of groups are determined in the plurality of chips, the number of chips included in the plurality of groups is the same, and the number of parallel branches included in the plurality of initial circuit models is the same; and according to the plurality of groups, chips are matched for the plurality of initial circuit models to obtain a plurality of target circuit models, so that currents in a plurality of parallel branches included in the target circuit models are uniform. According to the invention, the technical problem of unbalanced current in a multi-chip parallel circuit is solved.

Description

Technical Field

[0001] The present invention relates to the field of parallel circuit current balancing, and in particular to a circuit determination method, device, non-volatile storage medium and electronic equipment. Background Art

[0002] At present, the current level of a single silicon carbide chip is generally less than 100A. In order to meet the needs of higher power applications, multiple discrete devices are usually connected in parallel. However, when used in parallel, the chip parameters, packaging parameters, and drive parameters will cause unbalanced current distribution in parallel devices. Unbalanced current will produce unbalanced electrical stress and thermal stress. In severe cases, the device with excessive current distribution will fail, thereby endangering the operating reliability of other parallel devices and even the entire parallel circuit.

[0003] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0004] The embodiments of the present invention provide a circuit determination method, device, non-volatile storage medium and electronic device to at least solve the technical problem of current imbalance in a circuit with multiple chips connected in parallel.

[0005] According to one aspect of an embodiment of the present invention, a circuit determination method is provided, including: obtaining a current sharing voltage of each of a plurality of chips; establishing a plurality of initial circuit models respectively, wherein the plurality of initial circuit models each include the same number of parallel branches; determining a plurality of groups among the plurality of chips according to the current sharing voltage of each of the plurality of chips, wherein the plurality of groups each include the same number of chips and the same number of parallel branches as the plurality of initial circuit models; matching chips for the plurality of initial circuit models according to the plurality of groups to obtain a plurality of target circuit models, so that the currents in the plurality of parallel branches included in the target circuit models are uniform.

[0006] Optionally, obtaining the current sharing voltage of each of the multiple chips includes: when the drain-source voltage is a fixed value, gradually increasing the voltage between the gate and the source on the multiple chips according to a fixed step size until the drain current of each of the multiple chips is a predetermined current value, thereby obtaining the current sharing voltage of each of the multiple chips, wherein the predetermined current value is the minimum drain current value after the current sharing voltages of the multiple chips are fixed in order.

[0007] Optionally, multiple groups are determined among the multiple chips based on the respective current sharing voltages of the multiple chips, including: sorting the multiple chips according to the magnitude of the respective current sharing voltages of the multiple chips to obtain a chip sequence; determining that the number of parallel branches included in each of the multiple initial circuit models is the number of chips included in each of the multiple groups; determining a multiple relationship between the total number of chips of the multiple chips and the number of chips included in each of the multiple groups; and determining multiple groups among the multiple chips based on the multiple relationship and the chip sequence.

[0008] Optionally, multiple groups are determined from the multiple chips based on the multiple relationship and the chip sequence; including: when the multiple relationship is that the total number of chips is an integer multiple of the number of chips included in each of the multiple groups, adjacent chips in the sorting of the multiple chips are grouped according to the number of chips included in each of the multiple groups to determine the multiple groups; if the multiple relationship is that the total number of chips is not an integer multiple of the number of chips included in each of the multiple groups, some chips are removed from the chip sequence until the number of chips included in the chip sequence after removal is an integer multiple of the number of chips included in each of the multiple groups, and adjacent chips in the sorting of the multiple chips are grouped according to the number of chips included in each of the multiple groups to determine the multiple groups.

[0009] Optionally, some chips are removed from the chip sequence until the number of chips included in the chip sequence after the removal is an integer multiple of the number of chips included in each of the multiple groups, and adjacent chips in the arrangement of the multiple chips are grouped according to the number of chips included in each of the multiple groups to determine multiple groups, including: determining the remainder obtained by dividing the total number of chips by the number of chips included in each of the multiple groups; in the chip sequence, removing chips arranged at the head or end whose number is the same as the remainder to obtain a chip sequence after the removal; and grouping adjacent chips in the chip sequence after the removal to determine multiple groups.

[0010] Optionally, according to multiple groups, chips are matched for multiple initial circuit models to obtain multiple target circuit models, so that the currents in the multiple parallel branches included in the target circuit model are uniform, including: matching the multiple groups with the multiple initial circuit models one by one; placing the chips included in each of the multiple groups into the corresponding initial circuit model to obtain multiple target circuit models, so that the currents in the multiple parallel branches included in the target circuit model are uniform.

[0011] According to another aspect of an embodiment of the present invention, a circuit determination device is provided, comprising: an acquisition module for acquiring the respective current sharing voltages of a plurality of chips; an establishment module for respectively establishing a plurality of initial circuit models, wherein the plurality of initial circuit models each include the same number of parallel branches; a determination module for determining a plurality of groups among the plurality of chips according to the respective current sharing voltages of the plurality of chips, wherein the plurality of groups each include the same number of chips and the same number of parallel branches as the plurality of initial circuit models; a matching module for matching chips for the plurality of initial circuit models according to the plurality of groups to obtain a plurality of target circuit models, so that the currents in the plurality of parallel branches included in the target circuit models are uniform.

[0012] According to another aspect of an embodiment of the present invention, a non-volatile storage medium is provided. The non-volatile storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor and executing any one of the circuit determination methods.

[0013] According to another aspect of an embodiment of the present invention, there is provided an electronic device, comprising: one or more processors and a memory, the memory being used to store one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement any one of the circuit determination methods.

[0014] According to yet another aspect of an embodiment of the present invention, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the circuit determination method described above is implemented.

[0015] In an embodiment of the present invention, by obtaining the respective current sharing voltages of a plurality of chips; establishing a plurality of initial circuit models respectively, wherein the plurality of initial circuit models each include the same number of parallel branches; determining a plurality of groups among the plurality of chips according to the respective current sharing voltages of the plurality of chips, wherein the plurality of groups each include the same number of chips and the same number of parallel branches as the plurality of initial circuit models; matching chips for the plurality of initial circuit models according to the plurality of groups, and obtaining a plurality of target circuit models, so that the currents in the plurality of parallel branches included in the target circuit model are uniform, thereby solving the technical problem of current imbalance in a circuit with multiple chips in parallel, achieving the purpose of current balance in a circuit with multiple chips in parallel, and further realizing the technical effect of improving the reliability of a circuit with multiple chips in parallel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0017] Figure 1is a flow chart of a circuit determination method provided according to an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of an optional method for testing the gate-source voltage of a power semiconductor chip according to an embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of a circuit determination device provided according to an embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of an electronic device provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0022] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0023] According to an embodiment of the present invention, a circuit determination method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0024] Figure 1 is a flow chart of a circuit determination method according to an embodiment of the present invention. Figure 1 As shown, the method comprises the following steps:

[0025] Step S102, obtaining the current sharing voltage of each of the multiple chips.

[0026] In this step, during the screening and grouping of power semiconductor chips, each chip is tested and its current sharing voltage is determined, that is, the voltage value between the gate and source of the chip when a predetermined current passes through the chip.

[0027] In an optional embodiment, obtaining the current sharing voltage of each of the plurality of chips includes:

[0028] When the drain-source voltage is a fixed value, the voltage between the gate and the source on multiple chips is gradually increased according to a fixed step size until the drain current of each of the multiple chips is a predetermined current value, thereby obtaining a current sharing voltage for each of the multiple chips, wherein the predetermined current value is the minimum drain current value after the current sharing voltages of each of the multiple chips are fixed in order.

[0029] Optionally, the gate-source voltage of each chip refers to the gate-source voltage of each chip corresponding to the smallest drain current when the drain current continues to increase and the order of the gate-source voltage of each chip no longer changes. The gate-source voltage of each chip at this time is the current-sharing voltage of each chip. For example, when the drain current is 5A, the gate-source voltages of the parallel chips are sorted, and when the drain current continues to increase, the order of the gate-source voltages of the parallel chips no longer changes. The smallest drain current is selected because the drain current increases from 0, and the larger the drain current, the longer the test time required, so selecting the smallest drain current can reduce the test time.

[0030] The specific test steps are as follows: record the total number of power semiconductor chip samples n, where the total number of samples n is the total number of power semiconductor chips to be applied; number the power semiconductor chip samples from 1 to n; start the power analyzer, select the gate-source voltage and drain current test module, and set the parameter values ​​of the test data points. The drain current of the data point can be 5A, and the drain-source voltage can be 10V. Figure 2 As shown, the gate-source voltage of the power semiconductor chip is tested. The gate-source voltage test process is that the drain-source voltage is fixed at 10V, and the gate-source voltage increases from 0V, with a step size of 0.1V, until the drain current of the power semiconductor chip is 5A, the test is stopped, and the gate-source voltage corresponding to the drain current of 5A is recorded. According to the above gate-source voltage test process, the gate-source voltage test of power semiconductor chips No. 1 to No. n is performed in sequence, and the gate-source voltage of each chip obtained by the test is the current-sharing voltage of each chip. Current-sharing voltage V ct The expression is:

[0031]

[0032] In the formula, i d The drain current is 5A, g fsis the transconductance corresponding to a drain current of 5A, V th is the threshold voltage of the power semiconductor chip.

[0033] Step S104: establishing a plurality of initial circuit models respectively, wherein the plurality of initial circuit models each include a same number of parallel branches.

[0034] In this step, when designing and analyzing the parallel application of power semiconductor chips, multiple initial circuit models can be created, and the number of parallel branches in each model is the same.

[0035] Step S106, determining a plurality of groups from the plurality of chips according to the respective current sharing voltages of the plurality of chips, wherein the plurality of groups each include the same number of chips and the same number of parallel branches as the plurality of initial circuit models;

[0036] In this step, when screening and grouping power semiconductor chips, ensure that the number of chips in each group matches the number of parallel branches in the initial circuit model. At the same time, use the current sharing voltage as a key parameter to make the current sharing voltage of the chips in each group as consistent as possible to achieve a more balanced distribution of current among the chips.

[0037] In an optional embodiment, multiple groups are determined among the multiple chips based on the respective current sharing voltages of the multiple chips, including: sorting the multiple chips according to the magnitude of the respective current sharing voltages of the multiple chips to obtain a chip sequence; determining the number of parallel branches included in each of the multiple initial circuit models as the number of chips included in each of the multiple groups; determining a multiple relationship between the total number of chips of the multiple chips and the number of chips included in each of the multiple groups; and determining multiple groups among the multiple chips based on the multiple relationship and the chip sequence.

[0038] Optionally, the number of parallel branches contained in the initial circuit model is the number of chips contained in each group. Since each initial circuit model contains the same number of parallel branches, the number of groups can be determined by dividing all chips equally. Assuming that there are n chips in total, the number of parallel branches contained in the initial circuit model is m, that is, the number of chips in each group is also m. Test the current sharing voltage of each of the n chips separately, sort the n chips according to their respective current sharing voltages, and group the sorted n chips according to the rule of m chips per group to obtain the number of groups. The current sharing voltage of each group of chips is basically the same.

[0039] In an optional embodiment, multiple groups are determined from multiple chips based on a multiple relationship and a chip sequence; including: when the multiple relationship is that the total number of chips is an integer multiple of the number of chips included in each of the multiple groups, adjacent chips in the sorting of the multiple chips are grouped according to the number of chips included in each of the multiple groups to determine the multiple groups; if the multiple relationship is that the total number of chips is not an integer multiple of the number of chips included in each of the multiple groups, some chips are removed from the chip sequence until the number of chips included in the chip sequence after removal is an integer multiple of the number of chips included in each of the multiple groups, and adjacent chips in the sorting of the multiple chips are grouped according to the number of chips included in each of the multiple groups to determine the multiple groups.

[0040] Optionally, assuming that the total number of chips is n and each group contains m chips, if n is an integer multiple of m, the n chips are divided equally according to the chip sequence, and the adjacent m chips are grouped together. If n is not an integer multiple of m, r chips are removed until nr is an integer multiple of m, and the nr chips are grouped together according to the chip sequence.

[0041] In an optional embodiment, some chips are removed from a chip sequence until the number of chips included in the chip sequence after the removal is an integer multiple of the number of chips included in each of the multiple groups, and adjacent chips in the arrangement of the multiple chips are grouped according to the number of chips included in each of the multiple groups to determine multiple groups, including: determining the remainder obtained by dividing the total number of chips by the number of chips included in each of the multiple groups; in the chip sequence, removing chips at the head or end whose number is the same as the remainder to obtain a chip sequence after the removal; and grouping adjacent chips in the chip sequence after the removal to determine multiple groups.

[0042] Optionally, assuming that the total number of chips is n, each group contains m chips, and n is not an integer multiple of m, then determine the remainder r obtained by dividing n by m, remove the r chips with the largest current sharing voltage or the r chips with the smallest current sharing voltage, until nr is an integer multiple of m, and group the m adjacent chips among the nr chips. The reason for removing the r chips with the largest current sharing voltage or the r chips with the smallest current sharing voltage is that all chips are sorted according to the size of the current sharing voltage, and the current sharing voltage difference between adjacent chips is small. If other chips are removed, the current sharing voltage difference between adjacent chips may be large, which may easily lead to unbalanced current distribution in the parallel circuit.

[0043] Step S108, matching chips for the multiple initial circuit models according to the multiple groups to obtain multiple target circuit models, so that the currents in the multiple parallel branches included in the target circuit models are uniform.

[0044] In this step, a group of chips is allocated to each initial circuit model to form a target circuit model. The m chips (i.e., m parallel branches) of each target circuit model have similar current sharing voltages, and the current can be evenly distributed among the chips.

[0045] In an optional embodiment, chips are matched for multiple initial circuit models according to multiple groups to obtain multiple target circuit models so that the currents in multiple parallel branches included in the target circuit models are uniform, including: matching multiple groups with multiple initial circuit models one by one; placing the chips included in each of the multiple groups into the corresponding initial circuit models to obtain multiple target circuit models so that the currents in multiple parallel branches included in the target circuit models are uniform.

[0046] Optionally, m chips with the largest current sharing voltage or the smallest current sharing voltage are selected from all the chips as a group according to the sorting of the current sharing voltage, and the group of chips is applied to an initial circuit model to obtain a target circuit model. The current sharing voltages of the m chips included in the target circuit model are basically consistent, so that the current allocated to each branch of the target circuit model can be basically consistent.

[0047] The above method obtains the current sharing voltage of each of the multiple chips; establishes multiple initial circuit models respectively, wherein the multiple initial circuit models each include the same number of parallel branches; determines multiple groups among the multiple chips according to the current sharing voltage of each of the multiple chips, wherein the multiple groups each include the same number of chips and the same number of parallel branches as the multiple initial circuit models; matches chips for the multiple initial circuit models according to the multiple groups, and obtains multiple target circuit models, so that the currents in the multiple parallel branches included in the target circuit model are uniform, thereby solving the technical problem of current imbalance in the circuit of multiple chips in parallel, achieving the purpose of current balance in the circuit of multiple chips in parallel, and further realizing the technical effect of improving the reliability of the circuit of multiple chips in parallel.

[0048] Based on the above embodiments and optional embodiments, the present invention proposes an optional implementation mode:

[0049] Step S1, obtaining the current sharing voltage of each of the multiple chips, including: when the drain-source voltage is a fixed value, gradually increasing the voltage between the gate and the source on the multiple chips according to a fixed step size until the drain current of each of the multiple chips is a predetermined current value, and obtaining the current sharing voltage of each of the multiple chips, wherein the predetermined current value is the minimum drain current value after the current sharing voltages of the multiple chips are fixed in order.

[0050] Optionally, the gate-source voltage of each chip refers to the gate-source voltage of each chip corresponding to the smallest drain current when the drain current continues to increase and the order of the gate-source voltage of each chip no longer changes. The gate-source voltage of each chip at this time is the current-sharing voltage of each chip. For example, when the drain current is 5A, the gate-source voltages of the parallel chips are sorted, and when the drain current continues to increase, the order of the gate-source voltages of the parallel chips no longer changes. The smallest drain current is selected because the drain current increases from 0, and the larger the drain current, the longer the test time required, so selecting the smallest drain current can reduce the test time.

[0051] The specific test steps are as follows: record the total number of power semiconductor chip samples n, where the total number of samples n is the total number of power semiconductor chips to be applied; number the power semiconductor chip samples from 1 to n; start the power analyzer, select the gate-source voltage and drain current test module, and set the parameter values ​​of the test data points. The drain current of the data point can be 5A, and the drain-source voltage can be 10V. Figure 2 As shown, the gate-source voltage of the power semiconductor chip is tested. The test process of the gate-source voltage is that the drain-source voltage is fixed at 10V, and the gate-source voltage increases from 0V, with a step size of 0.1V, until the drain current of the power semiconductor chip is 5A, the test is stopped, and the gate-source voltage corresponding to the drain current of 5A is recorded. According to the above gate-source voltage test process, the gate-source voltage test of power semiconductor chips No. 1 to No. n is performed in sequence, and the gate-source voltage of each chip obtained by the test is the current-sharing voltage of each chip, that is, the current-sharing voltage V ct The expression is:

[0052]

[0053] In the formula, i d The drain current is 5A, g fs is the transconductance corresponding to a drain current of 5A, V th is the threshold voltage of the power semiconductor chip.

[0054] Step S2, establishing a plurality of initial circuit models respectively, wherein the plurality of initial circuit models each include the same number of parallel branches.

[0055] In this step, when designing and analyzing the parallel application of power semiconductor chips, multiple initial circuit models can be created. The multiple initial circuit models can be multi-chip parallel circuits with symmetrical layouts, and the number of parallel branches in each model is the same. Multi-chip parallel circuits with symmetrical layouts refer to devices in parallel in the circuit that have mirror symmetry or the same parameters in electrical and physical layouts, which helps reduce the impact of inconsistent electrical parameters on current distribution.

[0056] Step S3, determining a plurality of groups from the plurality of chips according to the respective current sharing voltages of the plurality of chips, including: sorting the plurality of chips according to the magnitude of the respective current sharing voltages of the plurality of chips to obtain a chip sequence; determining the number of parallel branches contained in each of the plurality of initial circuit models as the number of chips included in each of the plurality of groups; determining a multiple relationship between the total number of chips of the plurality of chips and the number of chips included in each of the plurality of groups; determining a plurality of groups from the plurality of chips according to the multiple relationship and the chip sequence.

[0057] Optionally, the number of parallel branches contained in the initial circuit model is the number of chips contained in each group. Since each initial circuit model contains the same number of parallel branches, the number of groups can be determined by dividing all chips equally. Assuming that there are n chips in total, the number of parallel branches contained in the initial circuit model is m, that is, the number of chips in each group is also m. Test the current sharing voltage of each of the n chips separately, sort the n chips according to their respective current sharing voltages, and group the sorted n chips according to the rule of m chips per group to obtain the number of groups. The current sharing voltage of each group of chips is basically the same.

[0058] Step S31, determining multiple groups from multiple chips according to the multiple relationship and the chip sequence; including: when the multiple relationship is that the total number of chips is an integer multiple of the number of chips included in each of the multiple groups, grouping adjacent chips in the sorting of the multiple chips according to the number of chips included in each of the multiple groups, and determining multiple groups; if the multiple relationship is that the total number of chips is not an integer multiple of the number of chips included in each of the multiple groups, removing some chips from the chip sequence until the number of chips included in the chip sequence after removal is an integer multiple of the number of chips included in each of the multiple groups, and grouping adjacent chips in the sorting of the multiple chips according to the number of chips included in each of the multiple groups, and determining multiple groups.

[0059] Optionally, assuming that the total number of chips is n and each group contains m chips, if n is an integer multiple of m, the n chips are divided equally according to the chip sequence, and the adjacent m chips are grouped together. If n is not an integer multiple of m, r chips are removed until nr is an integer multiple of m, and the nr chips are grouped together according to the chip sequence.

[0060] Step S32, removing some chips from the chip sequence until the number of chips included in the chip sequence after the removal is an integer multiple of the number of chips included in each of the multiple groups, and grouping adjacent chips in the arrangement of the multiple chips according to the number of chips included in each of the multiple groups to determine multiple groups, including: determining the remainder obtained by dividing the total number of chips by the number of chips included in each of the multiple groups; in the chip sequence, removing chips arranged at the head or end whose number is the same as the remainder to obtain a chip sequence after the removal; grouping adjacent chips in the chip sequence after the removal to determine multiple groups.

[0061] Optionally, assuming that the total number of chips is n, each group contains m chips, and n is not an integer multiple of m, then determine the remainder r obtained by dividing n by m, remove the r chips with the largest current sharing voltage or the r chips with the smallest current sharing voltage, until nr is an integer multiple of m, and group the m adjacent chips among the nr chips. The reason for removing the r chips with the largest current sharing voltage or the r chips with the smallest current sharing voltage is that all chips are sorted according to the size of the current sharing voltage, and the current sharing voltage difference between adjacent chips is small. If other chips are removed, the current sharing voltage difference between adjacent chips may be large, which may easily lead to unbalanced current distribution in the parallel circuit.

[0062] Step S4, matching chips for multiple initial circuit models according to multiple groups to obtain multiple target circuit models, so that the currents in the multiple parallel branches included in the target circuit model are uniform, including: matching the multiple groups with the multiple initial circuit models one by one; placing the chips included in each of the multiple groups into the corresponding initial circuit model to obtain multiple target circuit models, so that the currents in the multiple parallel branches included in the target circuit model are uniform.

[0063] Optionally, m chips with the largest current sharing voltage or the smallest current sharing voltage are selected from all the chips as a group according to the sorting of the current sharing voltage, and the group of chips is applied to an initial circuit model to obtain a target circuit model. The current sharing voltages of the m chips included in the target circuit model are basically consistent, so that the current allocated to each branch of the target circuit model can be basically consistent.

[0064] The above optional implementation achieves at least the following effects: solves the technical problem of current imbalance in a multi-chip parallel circuit, achieves the purpose of current balance in a multi-chip parallel circuit, and further achieves the technical effect of improving the reliability of a multi-chip parallel circuit.

[0065] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0066] In this embodiment, a circuit determination device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the terms "module" and "device" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0067] According to an embodiment of the present invention, a device embodiment for implementing the circuit determination method is also provided. Figure 3 A schematic diagram of a circuit determination device according to an embodiment of the present invention is shown in FIG. Figure 3 As shown, the circuit determination device includes an acquisition module 31, an establishment module 32, a determination module 33, and a matching module 34. The device is described below.

[0068] An acquisition module 31 is used to acquire the current sharing voltage of each of the multiple chips;

[0069] An establishing module 32, connected to the acquiring module 31, for establishing a plurality of initial circuit models respectively, wherein the plurality of initial circuit models respectively include the same number of parallel branches;

[0070] A determination module 33, connected to the establishment module 32, is used to determine a plurality of groups among the plurality of chips according to the respective current sharing voltages of the plurality of chips, wherein the plurality of groups each include the same number of chips and the same number of parallel branches as the plurality of initial circuit models;

[0071] The matching module 34 is connected to the determination module 33 and is used to match chips for multiple initial circuit models according to multiple groups to obtain multiple target circuit models so that the currents in multiple parallel branches included in the target circuit models are uniform.

[0072] In a circuit determination device provided by an embodiment of the present invention, an acquisition module is set to obtain the current sharing voltage of each of multiple chips; an establishment module is used to respectively establish multiple initial circuit models, wherein the multiple initial circuit models each include the same number of parallel branches; a determination module is used to determine multiple groups in the multiple chips according to the current sharing voltage of each of the multiple chips, wherein the multiple groups each include the same number of chips and the same number of parallel branches as the multiple initial circuit models; a matching module is used to match chips for the multiple initial circuit models according to the multiple groups to obtain multiple target circuit models, so that the currents in the multiple parallel branches included in the target circuit model are uniform, thereby solving the technical problem of current imbalance in a circuit with multiple chips in parallel, achieving the purpose of current balance in a circuit with multiple chips in parallel, and further realizing the technical effect of improving the reliability of a circuit with multiple chips in parallel.

[0073] It should be noted that the above modules can be implemented by software or hardware. For example, for the latter, it can be implemented in the following ways: the above modules can be located in the same processor; or the above modules can be located in different processors in any combination.

[0074] It should be noted that the acquisition module 31, the establishment module 32, the determination module 33, and the matching module 34 correspond to steps S102 to S108 in the embodiment, and the examples and application scenarios implemented by the modules and the corresponding steps are the same, but are not limited to the contents disclosed in the above embodiment. It should be noted that the modules as part of the device can be run in a computer terminal.

[0075] It should be noted that the optional or preferred implementation of this embodiment can refer to the relevant description in the embodiment, which will not be repeated here.

[0076] The above-mentioned circuit determination device may also include a processor and a memory. The acquisition module 31, the establishment module 32, the determination module 33, the matching module 34, etc. are all stored in the memory as program units, and the processor executes the above-mentioned program units stored in the memory to realize the corresponding functions.

[0077] The processor includes a kernel, which retrieves the corresponding program unit from the memory. There can be one or more kernels. The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one storage chip.

[0078] An embodiment of the present invention provides a non-volatile storage medium on which a program is stored. When the program is executed by a processor, a circuit determination method is implemented.

[0079] like Figure 4 It is shown that an embodiment of the present invention provides an electronic device, the electronic device 10 includes a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, the following steps are implemented: the memory is used to store a computer program, wherein, when the computer program is executed by the processor, the processor implements the above-mentioned circuit determination method. The device in this article may be a server, a PC, etc.

[0080] The present invention also provides a computer program product, which, when executed on a data processing device, is suitable for executing a program initialized with the following method steps: computer instructions are executed by a processor to perform the above-mentioned circuit determination method.

[0081] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0082] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0083] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0084] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0085] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0086] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0087] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0088] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0089] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0090] The above are only embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A circuit determination method, characterized in that: include: Obtain the current sharing voltage of multiple chips; Establishing a plurality of initial circuit models respectively, wherein the plurality of initial circuit models each include the same number of parallel branches; Determine a plurality of groups among the plurality of chips according to the respective current sharing voltages of the plurality of chips, wherein the plurality of groups each include the same number of chips and the same number of parallel branches as the plurality of initial circuit models; According to the multiple groups, chips are matched for the multiple initial circuit models to obtain multiple target circuit models, so that the currents in the multiple parallel branches included in the target circuit models are uniform.

2. The method according to claim 1, characterized in that The obtaining of the current sharing voltages of the plurality of chips includes: When the drain-source voltage is a fixed value, the voltage between the gate and the source on the multiple chips is gradually increased according to a fixed step size until the drain current of each of the multiple chips is a predetermined current value, thereby obtaining a current sharing voltage for each of the multiple chips, wherein the predetermined current value is the minimum drain current value after the current sharing voltages of each of the multiple chips are fixed in order.

3. The method according to claim 1, characterized in that Determining a plurality of groups among the plurality of chips according to respective current sharing voltages of the plurality of chips includes: Sorting the multiple chips according to the magnitude of the current sharing voltages of the multiple chips to obtain a chip sequence; Determine that the number of parallel branches included in each of the plurality of initial circuit models is the number of chips included in each of the plurality of groups; Determine a multiple relationship between a total number of chips of the plurality of chips and a number of chips included in each of the plurality of groups; The plurality of groups are determined in the plurality of chips according to the multiple relationship and the chip sequence.

4. The method according to claim 3, characterized in that The step of determining the plurality of groups in the plurality of chips according to the multiple relationship and the chip sequence comprises: When the multiple relationship is that the total number of chips is an integer multiple of the number of chips included in each of the multiple groups, adjacent chips in the arrangement of the multiple chips are grouped according to the number of chips included in each of the multiple groups to determine the multiple groups; If the multiple relationship is that the total number of chips is not an integer multiple of the number of chips included in each of the multiple groups, some chips are eliminated from the chip sequence until the number of chips included in the chip sequence after elimination is an integer multiple of the number of chips included in each of the multiple groups, and adjacent chips in the arrangement of the multiple chips are grouped according to the number of chips included in each of the multiple groups to determine the multiple groups.

5. The method according to claim 4, characterized in that The removing some chips from the chip sequence until the number of chips included in the chip sequence after the removal is an integer multiple of the number of chips included in each of the multiple groups, and grouping adjacent chips in the sequence of the multiple chips into one group according to the number of chips included in each of the multiple groups, and determining the multiple groups, including: Determine a remainder obtained by dividing the total number of chips by the number of chips included in each of the plurality of groups; In the chip sequence, the chips arranged at the head end or the tail end whose number is the same as the remainder are eliminated to obtain the chip sequence after elimination; The adjacent chips in the chip sequence after being eliminated are grouped into one group to determine the multiple groups.

6. The method according to any one of claims 1 to 5, characterized in that The step of matching chips for the multiple initial circuit models according to the multiple groups to obtain multiple target circuit models so that currents in multiple parallel branches included in the target circuit models are uniform includes: Matching the multiple groups with the multiple initial circuit models in a one-to-one correspondence; The chips included in each of the multiple groups are respectively placed into the corresponding initial circuit models to obtain the multiple target circuit models, so that the currents in the multiple parallel branches included in the target circuit models are uniform.

7. A circuit determination device, characterized in that: include: An acquisition module is used to obtain the current sharing voltage of multiple chips; An establishing module, used to establish a plurality of initial circuit models respectively, wherein the plurality of initial circuit models each include the same number of parallel branches; A determination module, configured to determine a plurality of groups among the plurality of chips according to respective current sharing voltages of the plurality of chips, wherein the plurality of groups each include the same number of chips and the same number of parallel branches as the plurality of initial circuit models; A matching module is used to match chips for the multiple initial circuit models according to the multiple groups to obtain multiple target circuit models so that the currents in the multiple parallel branches included in the target circuit models are uniform.

8. A non-volatile storage medium, characterized in that: The non-volatile storage medium stores a plurality of instructions, wherein the instructions are suitable for being loaded by a processor and executing the circuit determination method according to any one of claims 1 to 6.

9. An electronic device, characterized in that: include: One or more processors and a memory, wherein the memory is used to store one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the circuit determination method described in any one of claims 1 to 6.

10. A computer program product comprising computer instructions, characterized in that The computer instructions are executed by a processor to execute the circuit determination method according to any one of claims 1 to 6.

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