Automatic time offset compensation method for ultra-wideband chip baseband

Abstract

The invention belongs to the technical field of integrated circuits, and discloses an automatic time offset compensation method for an ultra-wideband chip baseband, which comprises the following steps: dividing Symbol signals entering an SHR into I-path real part signals and Q-path imaginary part signals, and outputting a compensation phase to adjust an interpolation position by adopting an interpolation algorithm and through a time offset compensation module; judging the number of Preamble synchronization, estimating the amplitude of a signal, carrying out low-pass filtering, and selecting time offset compensation with different precisions; phase compensation is dynamically adjusted; and when an SFD frame synchronization signal is detected, the time offset phase difference of the current Symbol is locked, tracking compensation is carried out, and the compensated signal is sent to a decoding module for decoding. According to the invention, time offset compensation modes with different precisions can be flexibly selected according to the current channel condition, and the interference problem caused by noise is overcome; by dynamically adjusting the compensation precision, the communication reliability is remarkably improved while the power consumption is reduced, so that the overall performance of the system is comprehensively improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to an automatic time deviation compensation method for an ultra-wideband chip baseband. Background Art

[0002] Ultra Wide Band (UWB) communication technology is a short-range wireless communication technology that uses nanosecond non-sinusoidal narrow pulses to transmit data. It has many advantages, such as strong anti-interference performance, high positioning accuracy, and ultra-low power consumption. With the continuous development of UWB technology, UWB communication chips have been widely used in the fields of smart communication devices and smart cars, and also have considerable application prospects in other consumer markets.

[0003] The existing UWB technology adopts the IEEE 802.15.4a protocol, which is a revised version of IEEE 802.15.4 and supports higher data rates, extended communication range, and enhanced anti-interference capabilities. According to the provisions of the UWB communication system in the IEEE 802.15.4a protocol, a UWB data frame is divided into three parts, namely the SHR part for synchronization, the PHR part for indicating basic information of the data frame and ranging, and the Payload part containing specific data loads, such as Figure 1 As shown. The synchronous SHR specified in IEEE 802.15.4a is divided into two parts, including the preamble that occupies the vast majority of the total length of the SHR, and the separator SFD used to separate the SHR and PHR. For the preamble, according to the IEEE 802.15.4a protocol, 24 different sequences can be used, of which the length of sequences 1 to 8 is 31, and the length of sequences 9 to 24 is 127; and 8 different synchronization numbers can be selected, the minimum synchronization number is 256, and the maximum synchronization number is 2048.

[0004] When communicating at the data part bit rate of 6.8Mb / s specified in the IEEE 802.15.4a protocol, a synchronization sequence of length 127 should be selected according to the protocol; and when communicating at this data rate, the average number of pulses contained in each Symbol of the data part is 2, and the average number of pulses contained in each Symbol of the SHR part is 508. The typical value of the pulse repetition frequency (MPRF) of the preamble part is 62.89MHz, and the corresponding MPRF of the PHR and Payload part is 15.6MHz. A higher MPRF means a higher transmission rate, which means that the signal will be affected by the multipath effect and distorted. If there is no good time offset compensation auxiliary channel estimation response to match the filter to maximize the output signal-to-noise ratio, it will cause unpacking errors and affect normal communication.

[0005] The traditional time offset compensation process is as follows: Figure 2 As shown, the traditional time offset compensation processing mode has the following problems:

[0006] 1. In order to adapt to the real-time changing complex channels, the number of preamble synchronizations will also be adjusted accordingly, and the time deviation convergence bandwidth coefficient will change with the change of the preamble duration; however, in the traditional time deviation compensation module, the convergence bandwidth of the loop filter is usually a fixed value, which is difficult to effectively cope with the complex and changing channel conditions in the actual communication environment.

[0007] 2. For UWB chips, the time offset compensation module needs to select the time offset correction with corresponding accuracy according to different signal-to-noise ratio levels; however, the traditional time offset compensation module uses a fixed loop filter coefficient accuracy, and usually estimates and compensates the phase by roughly comparing the energy values ​​of the previous and next sampling points; in complex environments, this method is difficult to resist the influence of noise, resulting in the sampling moment cannot be accurately adjusted, which easily causes inter-code crosstalk.

[0008] Therefore, if you want to ensure that the UWB chip works normally in complex and changeable channels, it is impossible to continue to use traditional time deviation compensation. At the same time, it will also cause the system to be unable to meet the requirements of adaptability and real-time performance, resulting in non-convergence or unpacking errors, seriously degrading the overall performance of the UWB communication baseband. Summary of the invention

[0009] In order to solve the above technical problems, the present invention provides an automatic time deviation compensation method for ultra-wideband chip baseband, which flexibly selects time deviation compensation methods of different precisions according to the current channel conditions, combines the time division of coarse convergence mode and fine convergence mode, ensures higher adaptability in the process of coping with channel changes, significantly improves communication reliability while reducing power consumption, thereby comprehensively improving the overall performance of the system.

[0010] The automatic time deviation compensation method for ultra-wideband chip baseband described in the present invention comprises the following steps:

[0011] Step 1, a Symbol signal entering the SHR symbol detection module is divided into an I-way real signal of the in-phase component and a Q-way imaginary signal of the orthogonal component, and an interpolation algorithm is used to adjust the interpolation position through the output compensation phase of the time offset compensation module to obtain the impulse response values ​​of the I and Q signals of the current phase P, the first three phases E1 / E2 / E3, and the last three phases L1 / L2 / L3;

[0012] Step 2: Determine the number of Preamble synchronizations and compare it with the experimental value, set the amplitude estimation time, perform correlation accumulation operations on the received I-channel real signal and Q-channel imaginary signal within the amplitude estimation time to estimate the signal amplitude; input the obtained amplitude signal into the alpha filter for low-pass filtering, and select time offset compensation of different precisions according to the signal-to-noise ratio level;

[0013] Step 3: Synchronize the number counter T through Preamble update Determine the Preamble length in real time to dynamically adjust the phase compensation;

[0014] Step 4: After the SFD frame synchronization signal is detected, the time offset phase difference of the current Symbol is locked, and the time offset compensation module is entered for tracking compensation. The compensated signal is sent to the decoding module for decoding, and the original baseband data is decoded to complete the communication.

[0015] Furthermore, in step 1, the interpolation algorithm uses a piecewise parabolic interpolator, and the mathematical expression is:

[0016]

[0017] Among them, C -1 (μ) is the interpolation phase of the previous sampling point, C0(μ) is the interpolation phase of the current sampling point, C1(μ) is the estimated interpolation phase of the next sampling point, and μ is the compensation phase output by the time offset compensation module. The present invention adopts the value of 1 / 2, which is relatively simple to implement on the hardware platform. Only shift operations need to be performed during calculation, avoiding multiplication operations to simplify the calculation complexity.

[0018] Furthermore, in step 2, the mathematical expression of the alpha filter is:

[0019] s[t+1]=(1-α)*s[t]+x[t+1]

[0020] Wherein, s[t+1] is the output at the current sampling moment, s[t] is the sampling output at the previous moment, α is the alpha filter coefficient, and x[t+1] is the input at the current sampling moment. The present invention simplifies the expression of the alpha filter, and compared with the filter in the prior art, the present invention makes the hardware implementation more efficient and the implementation complexity is lower.

[0021] Furthermore, step 3 is specifically as follows:

[0022] When the estimated signal-to-noise ratio is high, the synchronization number counter 0 < T update <512, the loop filter coefficient C0 is expanded by 32 times, and the loop filter coefficient C1 remains unchanged; the synchronous number counter 512<T update <1024, the loop filter coefficient C0 is enlarged by 16 times, and the loop filter coefficient C1 is reduced by 4 times; when the synchronous number counter is 1024<T update When , the loop filter coefficient C0 is enlarged by 8 times, and the loop filter coefficient C1 is reduced by 16 times;

[0023] When the estimated signal-to-noise ratio is low, the synchronization number counter 0 < T update <512, the loop filter coefficient C0 is enlarged by 16 times, and the loop filter coefficient C1 is reduced by 4 times; the synchronous number counter 512<T update <1024, the loop filter coefficient C0 is enlarged by 8 times, and the loop filter coefficient C1 is reduced by 16 times; when the synchronous number counter is 1024<T update When , the loop filter coefficient C0 is enlarged by 4 times, and the loop filter coefficient C1 is reduced by 32 times;

[0024] C0 is the gain coefficient of the feedback path, which determines the contribution of the feedback path to the output signal. The larger the value, the more significant the impact. C1 is the gain coefficient of the forward transmission path, which determines the amplification degree of the input signal in the forward transmission path. The selection of these two parameters can achieve filtering and enhancement of signals of different frequencies, and improve signal quality and reliability. The loop filter coefficient will transition from coarse convergence mode to fine convergence mode as the synchronization number counter increases.

[0025] After receiving the input signal, the phase detection module samples it and performs a convolution operation on the sampled signal with the fractional phase waveform pre-stored in the waveform lookup table to obtain the E-path real part E_i and imaginary part E_q of the previous sampling point, as well as the L-path real part L_i and imaginary part L_q of the next sampling point, for subsequent phase difference analysis; when there is a phase difference in the signal, the phase difference Δy1 formula of the current input signal is as follows:

[0026] Δy1=(L_i+L_q / 4)-(E_i+E_q / 4)

[0027] If Δy1>2, it enters the loop filter for phase correction 8, if Δy1>1.5, it makes a phase correction 4, if Δy1>1.25, it makes a phase correction 2, otherwise it makes a phase correction 0.

[0028] The coarse convergence mode is used for preliminary adjustments to quickly eliminate large time offsets. The phase difference obtained in this mode is often relatively large, basically belonging to the stage of Δy1>2, for phase correction; the fine convergence mode is used for refined adjustments to further reduce the convergence error and make the synchronization process reach a high-precision level. In this mode, the phase difference obtained will be relatively small, and fine-tuning will be performed slowly to make the phase difference 0.

[0029] Furthermore, in step 4, when the SFD frame synchronization signal is detected, the system immediately locks the time offset phase difference of the current Symbol, enters the demodulation time offset compensation module, and accumulates the pulse signals in the current Symbol of the E-path, P-path and L-path through the early and late gates to obtain an overall energy value in the Symbol;

[0030] By obtaining the difference Δy2 between the energy of the E path and the energy of the L path, the system will dynamically adjust the phase correction; if Δy2>4, the loop filter will be entered for phase correction 7, if Δy2>2, the phase correction will be 4, if Δy2>1.5, the phase correction will be 2, when Δy2>1.25, the phase correction will be 1, otherwise the phase correction will be 0;

[0031] The system phase is adjusted in real time through the detected phase difference to ensure that the signal and the reference benchmark are optimally matched; after completing the timing compensation and phase synchronization, the compensated signal is sent to the decoding module for decoding, and finally the original baseband data is decoded to complete the entire communication process.

[0032] The beneficial effects of the present invention are:

[0033] 1) The present invention proposes an adaptive synchronization method suitable for complex and changeable channels, in which the number of preamble synchronizations will change dynamically according to the channel conditions, and the bandwidth coefficient of the time deviation convergence will also be adjusted accordingly with the duration of the preamble. In order to ensure that the convergence process will neither take too long nor lead to too slow convergence, the present invention designs a time deviation compensation control strategy based on the length of the preamble, combining the time division of the coarse convergence mode and the fine convergence mode to ensure higher adaptability in the process of coping with channel changes. The operation modes of coarse convergence and fine convergence are controlled by real-time judgment of the length of the preamble. The coarse convergence mode is suitable for preliminary adjustment and rapid elimination of large time offsets, thereby achieving rapid adaptation to complex channels; the fine convergence mode is used for refined adjustment to further reduce the convergence error and achieve a high level of precision in the synchronization process. This two-stage convergence control strategy can flexibly respond to real-time fluctuations in channel status and ensure that better synchronization effects can be achieved under different channel conditions. In addition, another significant advantage of the present invention is the significant reduction in power consumption. Due to the time division of coarse convergence and fine convergence and their adaptive adjustment, long-term high-bandwidth operation that may occur in the traditional single mode is avoided, thereby effectively reducing unnecessary energy consumption.

[0034] 2) The present invention provides an adaptive time offset compensation scheme for different signal-to-noise ratio (SNR) levels, which can flexibly select time offset compensation methods with different precisions according to the current channel conditions, thereby effectively overcoming the interference problem caused by noise. In this design, by dynamically adjusting the compensation precision, the system can be adjusted in the best way under various noise environments, achieving significant improvement in communication reliability while reducing power consumption, thereby comprehensively improving the overall performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a schematic diagram of the UWB frame structure specified by the IEEE 802.15.4a protocol;

[0036] Figure 2 It is a flow chart of time deviation tracking and compensation in traditional design;

[0037] Figure 3 is a flow chart of the method of the present invention;

[0038] Figure 4 It is a flow chart of the time deviation tracking, compensation and demodulation part adopted by the present invention;

[0039] Figure 5 is the flow chart of the interpolation algorithm;

[0040] Figure 6 It is the waveform diagram of impulse response lookup table;

[0041] Figure 7is a schematic diagram of the phase detector structure in an embodiment;

[0042] Figure 8 : is a diagram of the energy accumulation process of the early and late gate E-path, P-path, and L-path in the embodiment;

[0043] Fig. 9 is a flow chart of time deviation tracking and compensation of a demodulation module in an embodiment;

[0044] Fig.10 This is a schematic diagram of the convergence curve before the improvement when the number of Preamble synchronization is 256;

[0045] Fig.11 This is a schematic diagram of the convergence curve after the number of preamble synchronization is improved to 256;

[0046] Fig.12 This is a schematic diagram of the convergence curve before the improvement when the number of Preamble synchronization is 2048;

[0047] Fig.13 This is a schematic diagram of the convergence curve after the number of preamble synchronization is improved to 2048;

[0048] Fig.14 This is a schematic diagram comparing the packet error rates under two time-skew modules;

[0049] Fig.15 This is a schematic diagram comparing the bit error rates of the two time-skew modules. DETAILED DESCRIPTION

[0050] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments in conjunction with the accompanying drawings.

[0051] like Figure 3 He Ru Figure 4 As shown, the automatic time deviation compensation method for ultra-wideband chip baseband described in the present invention comprises the following steps:

[0052] Step 1: The present invention is aimed at the case where the length of the UWB system synchronization preamble sequence specified in the IEEE 802.15.4a protocol is 127. When the MPRF of the preamble part is 62.89 MHZ, there are 508 valid pulses in a symbol, and the number of preamble synchronization is set to 2048, and the signal-to-noise ratio is -5 db. When the signal enters the SHR symbol detection module, the relevant energy Where n represents the number of symbols, r is the baseband signal, and r * is the local scrambling sequence, p is the starting phase of the received signal, k is the summation coefficient, and ΔL is the UWB spreading coefficient specified in the protocol. Start calculating the impulse response value h of each Symbol iand h q ,like Figure 5 ,like Figure 6 As shown; time deviation will cause the loss of amplitude or phase information of the signal during the interpolation process, affecting the restoration or accumulation result of the signal. The impulse response lookup table provides a predefined interpolation filter response, which can accurately interpolate and compensate for the error of the fractional phase, thereby minimizing the impact of time deviation on the signal; the interpolation position is adjusted by the compensation phase output by the time deviation compensation module to change the starting phase p of the received signal in real time. Figure 6 The envelope of the impulse response values ​​corresponding to the stored different fractional delays is represented, and the impulse response value required for the corresponding fractional delay value is found through the lookup table for interpolation processing. The lookup table design can not only be directly mapped to the hardware, reducing the implementation complexity, but also reducing the computational complexity.

[0053] Step 2: Determine the number of Preamble synchronizations. The IEEE 802.15.4a protocol specifies eight different numbers of Preamble synchronizations, with the minimum being 64 and the maximum being 4096. If the number of Preamble synchronizations is less than the experimental value of 512, the amplitude estimation will continue for 16 Symbol times to indicate the signal-to-noise ratio level and select the loop coefficient accuracy. Otherwise, the amplitude estimation will continue for 512 Symbol times. During the amplitude estimation, the I / Q symbols are correlated and accumulated to obtain the amplitude, and then the amplitude is low-pass filtered in the alpha filter to reduce the impact of noise.

[0054] If the number of Preamble synchronizations is 2048>512, a longer amplitude estimation time is used, which is set to 512 Symbol times. During the amplitude estimation, the received I-channel real signal and Q-channel imaginary signal are correlated and accumulated to estimate the amplitude of the signal. The accumulation process is to square and sum the I-channel component and Q-channel component of each sampling point, and then calculate their amplitude values:

[0055]

[0056] Among them, A(t) is the amplitude at the current sampling moment, I(t) and Q(t) represent the I-path component and Q-path component at the current moment respectively. The obtained amplitude signal is input into the alpha filter for low-pass filtering to reduce the influence of noise.

[0057] The mathematical expression of the alpha filter is: s[t+1]=(1-α)*s[t]+x[t+1], where s[t+1] is the output at the current sampling moment, s[t] is the sampling output at the previous moment, α is the alpha filter coefficient, and x[t+1] is the input at the current sampling moment; substitute the A(t) value into x[t+1] to obtain s[t+1].

[0058] Step 3: Obtain the impulse response values ​​of the I / Q signals of the current (Present) phase P path, the first three (Earlier) phase E1 / E2 / E3 paths and the last three (Later) phase L1 / L2 / L3 paths according to step 1, and enter the chip time offset compensation module. At the same time, through the monitoring module, according to s[t+1] obtained in step 2, it is used to characterize the signal-to-noise ratio (SNR) level, that is, it is judged that -5db is a high signal-to-noise ratio level. The system uses a lower precision time offset compensation to reduce the complexity and energy consumption of the calculation. In the time offset compensation module, it is known that the signal-to-noise ratio is a high signal-to-noise ratio, and the number of Preamble synchronizations is 2048, and the synchronization number counter 0<T update When <512, the loop filter coefficient C0 is expanded by 32 times, and the loop filter coefficient C1 remains unchanged. Synchronous number counter 512<T update When <1024, the loop filter coefficient C0 is enlarged by 16 times, and the loop filter coefficient C1 is reduced by 4 times. Synchronous number counter 1024<T update When the signal-to-noise ratio is low, the synchronous number counter 0 < T update When <512, the loop filter coefficient C0 is enlarged by 16 times, and the loop filter coefficient C1 is reduced by 4 times. Synchronous number counter 512<T update When <1024, the loop filter coefficient C0 is enlarged by 8 times, and the loop filter coefficient C1 is reduced by 16 times. Synchronous number counter 1024<T update When the loop filter coefficient C0 is increased by 4 times, the loop filter coefficient C1 is reduced by 32 times. This dynamic adjustment mechanism ensures finer phase adjustment under signal-to-noise ratio conditions to ensure the accuracy and stability of system synchronization.

[0059] After receiving the input signal, the phase detector module first performs specific sampling on these signals. Figure 7. The phase detection module collects the current phase (Present) P-channel signal, as well as the impulse response values ​​of the first three phases (Earlier) E1, E2, E3 and the last three phases (Later) L1, L2, L3 as inputs, so as to track the phase changes of the signal more accurately. These sampling point signals are convolved with the envelope value of the fractional phase waveform pre-stored in the waveform lookup table (RRC memory) at the previous sampling point and the next sampling point to ensure the accuracy of the calculation results. After this process, the real part (E_i) and imaginary part (E_q) of the E-channel of the previous sampling point, as well as the real part (L_i) and imaginary part (L_q) of the L-channel of the next sampling point are obtained, and these data are used for subsequent phase difference analysis. The pre-stored waveform lookup table stores the designed waveform envelope signal R(τ), which is actually the inverse of the input signal X(τ), but its inverse does not change the envelope shape. The envelope is matched with the envelope of the input signal for filtering, and the maximum amplitude can be obtained in the time domain. When there is no phase difference in the signal, the convolution formula in the time domain is: Y(τ)=X(τ)*R(τ+τ0), X(μ) is the input signal, R(τ) is the signal of the pre-stored phase waveform RRC, Yiτ) is the output signal, v is the phase sampling point, τ0 is the phase offset point, if there is no fractional phase difference at the ideal sampling moment, then Y(τ+τ0)=X(τ)*R(τ+τ0) and Y(τ-τ0)=X(τ)*R(τ-τ0) have equal peak values ​​at the offset fractional sampling points of τ=-τ0 and τ=τ0 and are symmetrical around the phase difference of 0. In actual situations, there may be a certain phase difference between the signals, which will cause the sampling points to offset. Over time, the phase difference accumulates, causing a change in the match between the output signal and the reference signal.

[0060] When there is a phase difference in the signal, the result of the convolution will change in the time domain. The difference between the two, Δy1 = (L_i + L_q / 4) - (E_i + e_q / 4), can be used to approximate the phase difference of the current input signal. When Δy1>2, the loop filter is used for phase correction 8, when Δy1>1.5, the phase correction is 4, when Δy1>1.25, the phase correction is 2, otherwise the phase correction is 0. Then the phase is compensated by adjusting the starting phase p of the received signal in step 1. The system uses the loop filter to feedback and adjust the currently detected phase error, thereby gradually reducing the phase difference and making it approach zero.

[0061] Step 4: When the SFD frame synchronization signal is detected, the system immediately locks the time offset phase difference of the current Symbol and enters the demodulation time offset compensation module to continue tracking and compensation. Time offset compensation: Accumulate the pulses in the current Symbol of the E path (representing the phase information of the previous time point), the P path (representing the phase information of the current Symbol) and the L path (representing the phase information of the next time point), such as Figure 8 . Get the overall energy value within a Symbol to maximize the peak value. When the signal has no phase difference, the P-path energy is the ideal peak value, then the E-path energy and the L-path energy are equal; when the signal has a phase difference, the difference Δy2 between the E-path energy and the L-path energy approximately represents the phase difference of the current signal. When Δy2>4, enter the loop filter for phase correction 7, when Δy2>2, the phase correction 4, when Δy2>1.5, the phase correction 2, when Δy2>1.25, the phase correction 1, otherwise the phase correction 0. The phase of the system is adjusted in real time through the detected phase difference, so that the phase difference continues to shrink until it is close to zero, ensuring that the signal and the reference benchmark achieve the best matching state and reducing the bit error rate. After completing the time deviation compensation and phase synchronization, the compensated signal is sent to the decoding module for decoding, and finally the original baseband data is decoded, successfully completing the entire communication process. The time deviation tracking and compensation process is as follows Fig. 9 shown.

[0062] So far, step 1 to step 4 constitute a complete automatic time offset compensation cycle. By repeating step 1 to step 4, the time offset tracking and compensation of the UWB signal in the current channel environment can be completed.

[0063] The method of the present invention is used to conduct simulation experiments in the algorithm simulation system of the UWB chip, and the simulation system includes a frame generation module, a pulse formation module, a simulation channel module, an AD module, a synchronization module, a time offset compensation module and an unpacking module. The real effect of the method of the present invention is verified by simulating the sending and receiving of data packets.

[0064] (1) Simulation experiment to verify the effectiveness of the time offset compensation algorithm

[0065] According to the provisions of the IEEE 802.15.4a protocol for the HRP-UWB communication system, the transmitter of the simulation system is configured to work in BPRF mode with a data rate of 6.80Mbps. At this time, the MPRF of the preamble part is 62.89MHz, and the MPRF of the data part is 15.60MHz. In order to simulate a complex channel environment with a high noise level, the signal-to-noise ratio SNR is configured to be -5dB in the simulation channel, the time offset is 10PPM (Percent Per Million), the data packet length is 60 bytes, and the sequence number of 18 and the length of 127 bits in the IEEE802.15.4a protocol are used as the preamble sequence. The minimum value of the Preamble synchronization is 256 and the maximum value is 2048. The simulation with this configuration is typical, and the SFD sequence with the sequence number of 2 and the length of 8 bits is used for simulation testing.

[0066] In the digital baseband time offset compensation simulation test, the ultimate purpose of configuring the extreme value of the Preamble synchronization times is to cope with interference in different complex environments. The convergence curve it shows indicates the working condition of the module in the current environment.

[0067] Since the time deviation has the cumulative characteristic, if it is not compensated in time, it will accumulate to a certain extent and cause serious signal misalignment and constellation rotation, which will cause the convergence curve to fail to converge normally. Fig.10 The convergence process of the traditional time deviation module when the number of preamble synchronization is 256 is shown. Due to the accumulation of a large amount of time deviation, synchronization failure and convergence failure are eventually caused. Fig.11 The convergence curve of the method of the present invention is shown. By dynamically controlling the time offset compensation process according to the Preamble length and combining the coarse convergence and fine convergence modes, the problem of failure to converge when the number of Preamble synchronizations is small in the traditional method is effectively solved.

[0068] However, this also raises another issue, namely the control of convergence time. In order to ensure that the UWB chip works normally in a complex and changing channel environment while meeting the low power consumption requirements, the convergence time must be strictly controlled. Too long convergence time will lead to increased power consumption. Fig.12 The fine convergence process of the traditional time deviation module when the number of preamble synchronization is 2048 is shown. Although it finally converges, it takes a long time and increases power consumption. Fig.13 The method of the present invention is demonstrated, which avoids the problem of too long convergence time by combining the dual adjustment of coarse convergence and fine convergence, thereby reducing power consumption.

[0069] Simulation results show that the method of the present invention can not only prevent the convergence failure problem caused by too long or too fast convergence time by dynamically adjusting the time deviation convergence bandwidth coefficient within the duration of the preamble code, but also effectively cope with the real-time changes of complex channels, thereby improving the robustness of the chip baseband in complex channels.

[0070] (2) Verify the performance of the time offset compensation algorithm under different signal-to-noise ratios

[0071] Another beneficial effect of the method of the present invention compared with the traditional time offset compensation method is that by judging different signal-to-noise ratio levels, time offset compensation schemes with different precisions are selected, which overcomes the influence of noise, reduces power consumption and improves the reliability of communication, thereby further improving the overall performance of the system. According to the provisions of the IEEE 802.15.4a protocol for the HRP-UWB communication system, the simulation system transmitter is configured to work in BPRF mode with a data rate of 6.80 Mbps. At this time, the MPRF of the preamble part is 62.89 MHz and the MPRF of the data part is 15.60 MHz. To simulate a complex channel environment with a high noise level, the initial signal-to-noise ratio is configured to -5dB in the simulation channel, the step value is -1dB, and the end value is -15dB. The time offset is 10PPM (Percent Per Million). The IEEE 802.15.4a protocol is used as the preamble sequence with a sequence number of 18 and a length of 127 bits, and the SFD sequence with a sequence number of 2 and a length of 8 bits is used for simulation testing. The data packet length is 60 bytes, and 1000 data packets are tested each time.

[0072] Fig.14 , Fig.15 The performance comparison between the traditional time offset compensation method and the time offset compensation method of the present invention when the UWB transmitter sends signals in BPRF mode is demonstrated. It can be seen that the time offset compensation method of the present invention has obvious performance improvement compared with the traditional time offset compensation method. When the signal-to-noise ratio is greater than -12dB, no packet or bit errors occur in receiving 1000 data packets. When the signal-to-noise ratio is less than -13dB, the overall performance of the system deteriorates significantly. Compared with the traditional frequency offset and time offset compensation method, there is a 7-8dB performance improvement, which enables the UWB communication baseband to work normally even in a high-noise complex environment.

[0073] The above description is only a preferred embodiment of the present invention and is not intended to be a further limitation of the present invention. All equivalent changes made using the contents of the present specification and drawings are within the protection scope of the present invention.

Claims

1. An automatic time offset compensation method for ultra-wideband chip baseband, characterized in that: The following steps are involved: Step 1, a Symbol signal entering the SHR symbol detection module is divided into an I-way real signal of the in-phase component and a Q-way imaginary signal of the orthogonal component, and an interpolation algorithm is used to adjust the interpolation position through the output compensation phase of the time offset compensation module to obtain the impulse response values ​​of the I and Q signals of the current phase P, the first three phases E1 / E2 / E3, and the last three phases L1 / L2 / L3; Step 2: Determine the number of Preamble synchronizations and compare it with the experimental value, set the amplitude estimation time, perform correlation accumulation operations on the received I-channel real signal and Q-channel imaginary signal within the amplitude estimation time to estimate the signal amplitude; input the obtained amplitude signal into the alpha filter for low-pass filtering, and select time offset compensation of different precisions according to the signal-to-noise ratio level; Step 3: Synchronize the number counter T through Preamble update Determine the Preamble length in real time to dynamically adjust the phase compensation; Step 4: After the SFD frame synchronization signal is detected, the time offset phase difference of the current Symbol is locked, and the time offset compensation module is entered for tracking compensation. The compensated signal is sent to the decoding module for decoding, and the original baseband data is decoded to complete the communication.

2. The automatic time offset compensation method for ultra-wideband chip baseband according to claim 1, characterized in that: In step 1, the interpolation algorithm uses a piecewise parabolic interpolator, and the mathematical expression is: Among them, C -1 (μ) is the interpolation phase of the previous sampling point, C0(μ) is the interpolation phase of the current sampling point, C1(μ) is the estimated interpolation phase of the next sampling point, and μ is the compensation phase output by the time offset compensation module.

3. The automatic time offset compensation method for ultra-wideband chip baseband according to claim 1, characterized in that: In step 2, the mathematical expression of the alpha filter is: s[t+1]=(1-α)*s[t]+x[t+1] Among them, s[t+1] is the output at the current sampling time, s[t] is the sampling output at the previous time, α is the alpha filter coefficient, and x[t+1] is the input at the current sampling time.

4. The automatic time offset compensation method for ultra-wideband chip baseband according to claim 1, characterized in that: Step 3 is as follows: When the estimated signal-to-noise ratio is high, the synchronization number counter 0 < T update When <512, the loop filter coefficient C o Expanded 32 times, loop filter coefficient C1 remains unchanged; synchronous number counter 512 < T update <1024, the loop filter coefficient C0 is enlarged by 16 times, and the loop filter coefficient C1 is reduced by 4 times; when the synchronous number counter is 1024<T update When , the loop filter coefficient C0 is enlarged by 8 times, and the loop filter coefficient C1 is reduced by 16 times; When the estimated signal-to-noise ratio is low, the synchronization number counter 0 < T update <512, the loop filter coefficient C0 is enlarged by 16 times, and the loop filter coefficient C1 is reduced by 4 times; the synchronous number counter 512<T update <1024, the loop filter coefficient C0 is enlarged by 8 times, and the loop filter coefficient C1 is reduced by 16 times; when the synchronous number counter is 1024<T update When , the loop filter coefficient C0 is enlarged by 4 times, and the loop filter coefficient C1 is reduced by 32 times; After receiving the input signal, the phase detection module samples it and performs a convolution operation on the sampled signal with the fractional phase waveform pre-stored in the waveform lookup table to obtain the E-path real part E_i and imaginary part E_q of the previous sampling point, as well as the L-path real part L_i and imaginary part L_q of the next sampling point, for subsequent phase difference analysis; when there is a phase difference in the signal, the phase difference Δy1 formula of the current input signal is as follows: Δy1=(L_i+L_q / 4)-(E_i+E_q / 4) If Δy1>2, it enters the loop filter for phase correction 8, if Δy1>1.5, it makes a phase correction 4, if Δy1>1.25, it makes a phase correction 2, otherwise it makes a phase correction 0.

5. The automatic time offset compensation method for ultra-wideband chip baseband according to claim 1, characterized in that: In step 4, when the SFD frame synchronization signal is detected, the system immediately locks the time offset phase difference of the current Symbol, enters the demodulation time offset compensation module, and accumulates the pulse signals in the current Symbol of the E, P and L channels through the early and late gates to obtain the overall energy value in the Symbol; By obtaining the difference Δy2 between the energy of E path and the energy of L path, the system will dynamically adjust the phase correction; if Δy2>4, the loop filter will be entered for phase correction 7, if Δy2>2, the phase correction will be 4, if Δy2>1.5, the phase correction will be 2, when Δy2>1.25, the phase correction will be 1, otherwise the phase correction will be 0; The system phase is adjusted in real time based on the detected phase difference to ensure the best match between the signal and the reference benchmark; After completing the timing offset compensation and phase synchronization, the compensated signal is sent to the decoding module for decoding, and finally the original baseband data is decoded to complete the entire communication process.

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