General security platform communication data equalization processing method, apparatus and device, and medium

Abstract

The invention provides a universal security platform communication data equalization processing method, device and equipment and a medium. The method comprises the following steps: controlling an I-system A machine, an I-system B machine, an II-system A machine and an II-system B machine to respectively receive first input data, second input data, third input data and fourth input data sent by an external interface; controlling the two-system two-machine to perform data verification based on the first input data, the second input data, the third input data and the fourth input data to obtain two-system input data; controlling the two-system two-machine to perform data processing based on the two-system input data to obtain two-system output data; and controlling the two-system two-machine to perform data verification based on the two-system output data to obtain target output data output by the two-system two-machine. According to the communication data equalization processing method provided by the invention, the input data and the output data are respectively subjected to equalization processing by controlling the double-system A machine and the double-system B machine, and the maintainability of the system is effectively improved while the availability and the safety of the system are ensured.

Description

Technical Field

[0001] The present invention relates to the field of communication network technology, and in particular to a method, device, equipment and medium for balancing communication data on a universal security platform. Background Art

[0002] A universal security platform is an integrated security solution designed to provide multiple security services. It is typically used to protect networks and applications, ensuring the security of data during transmission and storage.

[0003] The general safety platform is a safety platform system that reaches Safety Integrity Level 4 (SIL4) based on a 2x2x2 safety redundant architecture built by 6 general-purpose computers. Among them, the 2x2x2 safety redundant architecture adopts two-mode comparison to achieve two-take, dual-system redundancy, and two-times, so as to design a communication architecture that meets the SIL4 safety level requirements. Therefore, a communication architecture that meets the SIL4 functional safety level includes system I and system II, and one system includes three devices A, B, and C.

[0004] The three devices A, B, and C in the same system (A<->B, A<->C, B<->C) and the corresponding devices between the two systems (IA<->II-A, IB<->II-B, IC<->II-C) are all connected to each other via Ethernet.

[0005] Machines A and B are safety devices whose logic operation units must assume safety functions, while machine C is a non-safety device. Machine C, as a communication front-end unit, is connected to external interface devices via Ethernet. All communications with external interfaces are realized through machine C to send and receive data.

[0006] However, as a communication front-end unit, the C machine does not assume security functions and is a non-security device. From the perspective of system architecture, the existence of non-security devices within the system reduces the overall security of the system. In other words, the security of the C machine is low and it is vulnerable to attacks, which may lead to damage to the integrity and consistency of the data, which further affects the effect of data balancing processing. Summary of the invention

[0007] The present invention provides a method, device, equipment and medium for balancing processing communication data on a universal security platform, so as to solve the problem in the prior art that the security of data transmission and reception is low and the effect of data balancing processing is affected.

[0008] In a first aspect, the present invention provides a communication data equalization processing method, comprising: Controlling the I series A machine, the I series B machine, the II series A machine and the II series B machine to respectively receive the first input data, the second input data, the third input data and the fourth input data sent by the external interface; Control the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data verification based on the first input data, the second input data, the third input data and the fourth input data to obtain dual-series input data; the dual-series input data is used by the I series A machine, the I series B machine, the II series A machine and the II series B machine; Control the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data processing based on the dual-series input data to obtain dual-series output data; Control the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data verification based on the dual-system output data to obtain the target output data output by the I series A machine, the I series B machine, the II series A machine and the II series B machine respectively.

[0009] In one embodiment, the dual-system input data includes I-system input data; when controlling the I-system A machine, the I-system B machine, the II-system A machine, and the II-system B machine to perform data verification based on the first input data, the second input data, the third input data, and the fourth input data to obtain the dual-system input data, the following steps are performed for the I-system A machine: Control the I-series A machine to receive the second input data sent by the I-series B machine; Controlling the I-series A machine to perform data verification on the first input data and the second input data; After the data verification is successful, controlling the I-series A machine to splice the first input data and the second input data according to a first preset splicing order to obtain first intra-series splicing data; Control the I series A machine to use a fast scheduling cycle to calculate a cyclic redundancy check value corresponding to the spliced ​​data in the first series; Controlling the I-series A machine to receive the second intra-series splicing data sent by the I-series B machine; the second intra-series splicing data is obtained by the I-series B machine splicing the first input data and the second input data according to the first preset splicing order; Controlling the I-series A machine to perform data consistency comparison on the first-series spliced ​​data and the second-series spliced ​​data based on a cyclic redundancy check value corresponding to the first-series spliced ​​data; If the data consistency is successful, the I series A machine is controlled to perform data verification based on the first series splicing data, the third input data and the fourth input data to obtain the I series input data.

[0010] In one embodiment, the controlling the I series A machine to perform data verification based on the first series internal splicing data, the third input data, and the fourth input data to obtain the I series input data includes: Control the I series A machine to receive the third intra-system splicing data sent by the II series A machine using a system period; the third intra-system splicing data is obtained by the II series A machine splicing the third input data and the fourth input data according to the first preset splicing order; Control the I-series A machine to perform data verification on the first-series splicing data and the third-series splicing data; After the data verification is successful, controlling the I-series A machine to splice the first-series splicing data and the third-series splicing data according to a second preset splicing order to obtain first-series splicing data; Control the I-series A machine to generate a corresponding cyclic redundancy check value based on the first inter-series splicing data; Control the I series A machine to receive the second inter-system splicing data sent by the I series B machine; the second inter-system splicing data is obtained by the I series B machine splicing the second intra-system splicing data and the fourth intra-system splicing data according to the second preset splicing order; the fourth intra-system splicing data is obtained by the II series B machine splicing the third input data and the fourth input data according to the first preset splicing order; Controlling the I-series A machine to perform data consistency comparison on the first inter-series splicing data and the second inter-series splicing data based on a cyclic redundancy check value corresponding to the first inter-series splicing data; If the data consistency is relatively successful, the first inter-system splicing data is determined as the I system input data.

[0011] In one embodiment, the dual-system output data includes the I-system output data; when controlling the I-system A machine, the I-system B machine, the II-system A machine and the II-system B machine to perform data verification based on the dual-system output data to obtain target output data outputted by the I-system A machine, the I-system B machine, the II-system A machine and the II-system B machine respectively, the following steps are performed for the I-system A machine: Controlling the I series A machine to use a fast scheduling cycle to calculate a cyclic redundancy check value corresponding to the I series output data of the I series A machine; Control the I series A machine to receive the I series output data sent by the I series B machine; Controlling the I series A machine to perform data consistency comparison between the I series output data of the I series A machine and the I series output data of the I series B machine based on a cyclic redundancy check value corresponding to the I series output data of the I series A machine; If the data consistency comparison is successful, the I series A machine is controlled to generate corresponding target output data.

[0012] In one embodiment, after controlling the I series A machine to generate corresponding target output data, the method further includes: Control the I series A machine to receive the target output data sent by the I series B machine and the target output data sent by the II series A machine; Controlling the I series A machine to compare the I series output data of the I series A machine with the target output data of the I series B machine and the target output data of the II series A machine for data consistency based on the cyclic redundancy check value corresponding to the I series output data of the I series A machine; If the data consistency comparison is successful, the I system A machine is controlled to generate corresponding pair system output data.

[0013] In one embodiment, the universal security platform can support multiple virtual boards; each virtual board supports multiple tasks; each task includes a first channel and a second channel; the communication data balancing processing method also includes: The first channel of each task supported by each virtual board is configured on machine A; the machine A includes the series I machine A and the series II machine A; The second channel of each task supported by each virtual board is configured on the B machine; the B machine includes the I series B machine and the II series B machine; After the configuration is completed, a corresponding communication Internet protocol IP is configured for each first channel and each second channel.

[0014] In one embodiment, the universal security platform can support multiple virtual boards; each virtual board supports multiple tasks; the communication data balancing processing method also includes: Allocate each task supported by the virtual board with an odd virtual board index number on machine A; the machine A includes the series I A machine and the series II A machine; Allocate each task supported by the virtual board with an even-numbered virtual board index number on the B machine; the B machine includes the I series B machine and the II series B machine; After the configuration is completed, configure the corresponding communication IP for each task.

[0015] In a second aspect, the present invention further provides a communication data equalization processing device, comprising: A data receiving module, used for controlling the I series A machine, the I series B machine, the II series A machine and the II series B machine to respectively receive the first input data, the second input data, the third input data and the fourth input data sent by the external interface; An input data verification module is used to control the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data verification based on the first input data, the second input data, the third input data and the fourth input data to obtain dual-series input data; the dual-series input data is used by the I series A machine, the I series B machine, the II series A machine and the II series B machine; An input data processing module, used for controlling the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data processing based on the dual-series input data to obtain dual-series output data; The output data verification module is used to control the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data verification based on the dual-system output data to obtain the target output data output by the I series A machine, the I series B machine, the II series A machine and the II series B machine respectively.

[0016] In a third aspect, the present invention provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of any of the above-mentioned communication data equalization processing methods are implemented.

[0017] In a fourth aspect, the present invention further provides a storage medium, comprising a non-transitory computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of any of the communication data equalization processing methods described above are implemented.

[0018] The method, device, equipment and medium for balancing communication data of a universal security platform provided by the present invention balance the functions of sending and receiving data with external interface devices to the dual-system A machine and B machine, thereby eliminating the time-consuming internal interaction with the original equipment and effectively improving the system response capability. While transferring the external interaction function to the dual-system A machine and B machine, the balanced processing method of the input data and output data inside the universal security platform is redesigned, that is, the input data and output data are balancedly processed respectively by controlling the dual-system A machine and B machine, thereby effectively improving the system maintainability while ensuring the system availability and security. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 It is a flow chart of the communication data equalization processing method provided by the present invention.

[0021] Figure 2 It is a schematic diagram of the internal interface connection of the universal security platform provided by the present invention.

[0022] Figure 3 It is a topological connection diagram of the universal security platform and the external Ethernet interface provided by the present invention.

[0023] Figure 4 It is a schematic diagram of the process of processing the universal security platform and external interface input data provided by the present invention.

[0024] Figure 5 It is a flow chart of the processing of the universal security platform and external interface output data provided by the present invention.

[0025] Figure 6 This is one of the configuration structure diagrams of the universal security platform and the external interface channel mode provided by the present invention.

[0026] Figure 7 It is one of the planning distribution diagrams of the universal security platform and the external interface channel mode provided by the present invention.

[0027] Figure 8 This is the second configuration structure diagram of the universal security platform and external interface channel mode provided by the present invention.

[0028] Fig. 9 This is the second planning distribution diagram of the universal security platform and the external interface channel mode provided by the present invention.

[0029] Fig.10 It is a structural schematic diagram of the communication data equalization processing device provided by the present invention.

[0030] Fig.11 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] The terms "first", "second", etc. in the present invention are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein.

[0033] Combine the following Figure 1-Figure 11 The invention describes a method, device, equipment and medium for balancing communication data of a universal security platform.

[0034] The communication data balancing processing method provided in the embodiment of the present invention is implemented based on the communication data balancing processing device, and the communication data balancing processing device is configured in the universal security platform and can be used to control the I series A machine, the I series B machine, the II series A machine and the II series B machine in the universal security platform. Therefore, the embodiment of the present invention takes the communication data balancing processing device as an example to describe the communication data balancing processing method.

[0035] Figure 1 It is a flow chart of the communication data equalization processing method provided by the present invention.

[0036] like Figure 1 As shown, the method includes the following: Step 101, control the I series A machine, the I series B machine, the II series A machine and the II series B machine to respectively receive the first input data, the second input data, the third input data and the fourth input data sent by the external interface; Step 102, controlling the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data verification based on the first input data, the second input data, the third input data and the fourth input data to obtain dual-series input data; Step 103, controlling the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data processing based on the dual-series input data to obtain dual-series output data; Step 104, control the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data verification based on the dual-system output data to obtain the target output data output by the I series A machine, the I series B machine, the II series A machine and the II series B machine respectively.

[0037] It should be noted that the general safety platform built by four general-purpose computers is a safety platform system that reaches SIL4 level based on a 2x2-out-of-2 safety architecture. The four general-purpose computers in the general safety platform include machine A of series I, machine B of series I, machine A of series II and machine B of series II. Machine A and machine B can be considered as general-purpose computer devices in the general safety platform, which are used for balanced processing of input data and output data between external interfaces. Ultimately, a dual-machine balanced processing method for communication in a general safety platform can be realized in a safety platform system that reaches SIL4 level with a 2x2-out-of-2 safety architecture built by four general-purpose computers.

[0038] The two computer devices A and B in the same system (A<->B, I system A interacts with I system B), and the corresponding computer devices between the two systems (IA<->II-A, IB<->II-B, I system A interacts with II system A, I system B interacts with II system B) are connected through Ethernet dual network redundancy. The two systems A and B are cross-connected with external interface devices through Ethernet. Figure 2 , Figure 2 This is a schematic diagram of the internal interface connection of the universal security platform provided by the present invention. Figure 2 It can be seen that there is an interactive relationship between machine A and machine B in the same system, and between the corresponding computer devices in the two systems.

[0039] The external interface devices are all dual-system redundant architectures, and each system will expose two Internet Protocol (IP) addresses. In a single system cycle, the two systems send a maximum of 8 copies of input data to the general security platform through the A network Ethernet switch and the B network Ethernet switch, and receive a maximum of 8 copies of output data from the general security platform. The output data must be compared and consistent by the AB machine in the system before it can be output. Figure 3 , Figure 3 This is a topological connection diagram of the universal security platform and the external Ethernet interface provided by the present invention. Figure 3 It can be seen that the Ethernet switch of network A is mainly used to realize the interaction between machine A and machine B of series I and the external Ethernet interface, and the Ethernet switch of network B is mainly used to realize the interaction between machine A and machine B of series II and the external Ethernet interface.

[0040] After configuring the internal and external architecture of the universal security platform, the universal security platform can control the I series A machine, I series B machine, II series A machine and II series B machine through the communication data balancing processing device, and perform operations such as load balancing transmission and security verification within the platform for the received external interface input data and the external interface output data sent to the outside, and further perform dual-system and dual-machine communication balancing processing.

[0041] Both the A and B machines of the dual system use a combination of system cycles (such as 250ms) and fast scheduling cycles (such as 25ms) to realize balanced communication processing of input data and output data within the platform. The system cycle is used to ensure the timing processing of input data and output of the external interface; the fast scheduling cycle is used to receive and temporarily store input data from the external interface and to splice and store the temporarily stored external interface input data at the specified base cycle, that is, when a single system cycle is reached, to form the external interface data received in this system cycle. At the same time, the fast scheduling cycle is also responsible for the verification and comparison of input data and output data for interaction within and between systems.

[0042] In particular, when sending input data or output data within or between systems during the system cycle, in order to ensure the system data processing capability and effectively improve the system data availability, data transmission is performed in units of virtual boards. The general security platform supports up to N virtual board types, each of which can support M tasks. The N and M values ​​can be flexibly configured according to the actual scale of use. Each board type is oriented to different business needs and can be specifically divided into general Ethernet type (normal Transmission Control Protocol (TCP) or User Data Protocol (UDP) mode), multi-connection TCP type (TCP server uses one socket to process multiple external sockets at the same time) and multi-connection UDP type (UDP server uses one socket to process multiple external sockets at the same time). The platform software can obtain and set the communication data of the specified node through the virtual board index, task index or channel index.

[0043] When data is transmitted in units of virtual boards, not all virtual board data are spliced ​​together and sent at once, which avoids the normal use of other virtual board data due to the unusability of a certain virtual board data. If the current virtual board data packet is too long, it should be actively sent and received according to the communication restrictions of the operating system.

[0044] Specifically, the control unit I series A, the unit I series B, the unit II series A and the unit II series B all use a fast scheduling cycle to traverse all task objects managed locally in all virtual boards to obtain the external interface data of the communication node associated with the current virtual board and temporarily store it. When a single system cycle is reached, the temporarily stored external interface input data is spliced ​​and stored to form the external interface input data D_IA, D_IB, D_IIA, D_IIB received in this system cycle.

[0045] Therefore, it can be understood that the control system I series A machine adopts the logic of combining the system cycle and the fast scheduling cycle to receive the first input data D_IA sent by the external interface, the control system I series B machine adopts the logic of combining the system cycle and the fast scheduling cycle to receive the second input data D_IB sent by the external interface, the control system II series A machine adopts the logic of combining the system cycle and the fast scheduling cycle to receive the third input data D_IIA sent by the external interface, and the control system II series B machine adopts the logic of combining the system cycle and the fast scheduling cycle to receive the fourth input data D_IIB sent by the external interface.

[0046] Further, the I series A machine, the I series B machine, the II series A machine and the II series B machine are controlled to perform data verification based on the first input data D_IA, the second input data D_IB, the third input data D_IIA and the fourth input data D_IIB to obtain dual-series input data, wherein the dual-series input data includes the I series input data and the II series input data, the I series input data can be used directly or indirectly by the I series A machine and the I series B machine, and the II series input data can be used directly or indirectly by the II series A machine and the II series B machine.

[0047] Furthermore, the I series A machine, the I series B machine, the II series A machine and the II series B machine are controlled to perform data processing based on the dual-system input data to obtain dual-system output data, wherein the dual-system output data includes the I series output data and the II series output data.

[0048] It can be understood that the I series A machine and the I series B machine are controlled to process the I series input data to obtain the I series output data, and at the same time, the II series A machine and the II series B machine are controlled to process the II series input data to obtain the II series output data.

[0049] Furthermore, the I series A machine, the I series B machine, the II series A machine and the II series B machine are controlled to perform data verification based on the dual-system output data, i.e., the I series output data and the II series output data, to obtain the target output data O_IA output by the I series A machine, the target output data O_IB output by the I series B machine, the target output data O_IIA output by the II series A machine, and the target output data O_IIB output by the II series B machine.

[0050] The communication data balanced processing method provided by the present invention evenly distributes the functions of receiving and sending data with the external interface device to the dual-system A machine and B machine, eliminating the time-consuming internal interaction with the original device, effectively improving the system response capability, and while transferring the external interaction function to the dual-system A machine and B machine, redesigns the balanced processing method of the input data and output data inside the universal security platform, that is, by controlling the dual-system A machine and B machine to balance the input data and the output data respectively, effectively improving the system maintainability while ensuring the system availability and security.

[0051] The specific process of balancing the input data and the output data will be described below. Since the processing processes of the I series A machine, the I series B machine, the II series A machine and the II series B machine are consistent, the embodiment of the present invention uses the example of controlling the I series A machine to perform data balancing processing to illustrate, and the same applies to the other machines.

[0052] In some embodiments, based on step 102, when controlling the I series A machine, the I series B machine, the II series A machine, and the II series B machine to perform data verification based on the first input data, the second input data, the third input data, and the fourth input data to obtain dual-series input data, the following steps are performed for the I series A machine: Control the I series A machine to receive the second input data sent by the I series B machine; control the I series A machine to perform data verification on the first input data and the second input data; after the data verification is successful, control the I series A machine to splice the first input data and the second input data according to a first preset splicing order to obtain first intra-system splicing data; control the I series A machine to use a fast scheduling cycle to calculate the cyclic redundancy check value corresponding to the first intra-system splicing data; control the I series A machine to receive the second intra-system splicing data sent by the I series B machine; the second intra-system splicing data is obtained by the I series B machine splicing the first input data and the second input data according to the first preset splicing order; control the I series A machine to perform data consistency comparison on the first intra-system splicing data and the second intra-system splicing data based on the cyclic redundancy check value corresponding to the first intra-system splicing data; if the data consistency comparison is successful, control the I series A machine to perform data verification based on the first intra-system splicing data, the third input data and the fourth input data to obtain the I series input data.

[0053] The following balanced processing of input data can be referred to Figure 4 , Figure 4 It is a schematic diagram of the process of processing the universal security platform and external interface input data provided by the present invention.

[0054] Specifically, the I series B machine is controlled to use the system cycle to send the second input data D_IB to the I series A machine.

[0055] Furthermore, after the I series A machine receives the first input data D_IA and the second input data D_IB sent to the local machine, the I series A machine is controlled to perform data verification on the first input data D_IA and the second input data D_IB. This verification process includes but is not limited to dual network de-redundancy operations, security verification, serial number verification, integrity verification, consistency verification and other operation processes.

[0056] It should be noted that dual-network de-redundancy operation mainly refers to improving the reliability and availability of the system by using two different network connections in the network architecture; security verification is to ensure that the data has not been tampered with or damaged during transmission and storage; sequence number verification is used to ensure that the data packets are received in the correct order; integrity verification is to ensure that the data has not been damaged or changed during transmission; consistency verification is used to ensure the consistency of multiple data copies in different locations.

[0057] Furthermore, after the data verification is successful, the A machine of the I series is controlled to splice the first input data D_IA and the second input data D_IB according to the first preset splicing order, that is, in the order of A machine first and then B machine in the same series, and perform a source data de-redundancy operation, which can remove the consistent duplicate data in the spliced ​​data packet, thereby generating the first intra-system splicing data D_IAIB.

[0058] Furthermore, the control system A machine uses a fast scheduling cycle to calculate a cyclic redundancy check value (CRC) corresponding to the first intra-system splicing data D_IAIB at this moment, and a CRC32 algorithm can be used to generate a 32-bit check value.

[0059] Furthermore, the I series B machine is controlled to use the system cycle to send the second intra-system splicing data D_IAIB to the I series A machine, wherein the second intra-system splicing data is calculated by the I series B machine according to the above-mentioned processes of intra-system reception, intra-system verification, and intra-system splicing, and is specifically obtained based on the first input data D_IA and the second input data D_IB being spliced ​​in the order of first machine A and then machine B in the same system.

[0060] Further, the I-series A machine is controlled to perform a data consistency comparison on the first intra-series splicing data D_IAIB and the second intra-series splicing data D_IAIB based on a cyclic redundancy check value corresponding to the first intra-series splicing data.

[0061] Furthermore, if the data consistency is relatively successful, the I series A machine is controlled to perform data verification based on the first intra-system splicing data D_IAIB, the third input data D_IIA and the fourth input data D_IIB to obtain the I series input data. At the same time, the I series A machine is controlled to use the system cycle to send the first intra-system splicing data D_IAIB to the inter-system machine, that is, the II series A machine.

[0062] The embodiment of the present invention combines the system cycle and the fast scheduling cycle to enable the external communication interface input data to be processed by the system cycle and the fast scheduling cycle within the platform to achieve balanced internal communication of the dual-system AB machines. This balanced processing method improves the overall performance of the system, enhances the reliability of communication, and ultimately effectively improves the maintainability of the system while ensuring the availability and security of the system.

[0063] Further, in the above embodiment, the controlling the I series A machine to perform data verification based on the first series internal splicing data, the third input data and the fourth input data to obtain the I series input data includes: Control the I series A machine to receive the third intra-system splicing data sent by the II series A machine using a system cycle; the third intra-system splicing data is obtained by the II series A machine splicing the third input data and the fourth input data according to the first preset splicing order; control the I series A machine to perform data verification on the first intra-system splicing data and the third intra-system splicing data; after the data verification is successful, control the I series A machine to splice the first intra-system splicing data and the third intra-system splicing data according to a second preset splicing order to obtain the first inter-system splicing data; control the I series A machine to generate a corresponding cyclic redundancy check value based on the first inter-system splicing data; control the I series Machine A receives the second inter-system splicing data sent by the I-system B machine; the second inter-system splicing data is obtained by the I-system B machine splicing the second intra-system splicing data and the fourth intra-system splicing data according to the second preset splicing order; the fourth intra-system splicing data is obtained by the II-system B machine splicing the third input data and the fourth input data according to the first preset splicing order; the I-system A machine is controlled to perform a data consistency comparison on the first inter-system splicing data and the second inter-system splicing data based on the cyclic redundancy check value corresponding to the first inter-system splicing data; if the data consistency comparison is successful, the first inter-system splicing data is determined as the I-system input data.

[0064] Specifically, the control unit A of the II series adopts the system cycle to send the third intra-system splicing data D_IIAIIB to the unit A of the I series, wherein the third intra-system splicing data is calculated by the unit A of the II series according to the above-mentioned processes of intra-system reception, intra-system verification, and intra-system splicing, and is specifically obtained by splicing the third input data D_IIA and the fourth input data D_IIB in the order of first unit A and then unit B in the same system.

[0065] Furthermore, after the I series A machine receives the third system splicing data D_IIAIIB sent to this machine, the I series A machine is controlled to perform data verification on the first system splicing data D_IAIB and the third system splicing data D_IIAIIB. This verification process includes but is not limited to dual network de-redundancy operations, security verification, serial number verification, integrity verification, consistency verification and other operation processes.

[0066] Furthermore, after the data verification is successful, the A machine of series I is controlled to splice the first intra-system splicing data D_IAIB and the third intra-system splicing data D_IIAIIB in the order of A machine of series I, B machine of series II, and A machine of series II, B machine, and perform the source data de-redundancy operation again. This operation can remove the consistent duplicate data in the spliced ​​data packet, thereby generating the first inter-system splicing data D_IAIBIIAIIB.

[0067] Further, the control I series A machine generates a corresponding cyclic redundancy check value based on the first inter-system splicing data D_IAIBIIAIIB, which can be a CRC32 value.

[0068] Further, the I series B machine is controlled to use the system cycle to send the second inter-system splicing data D_IAIBIIAIIB to the I series A machine, wherein the second inter-system splicing data is calculated by the I series B machine according to the above-mentioned processes of inter-system reception, inter-system splicing, etc. after the data consistency is successfully compared, and is specifically obtained based on the second intra-system splicing data D_IAIB and the fourth intra-system splicing data D_IIAIIB, which are spliced ​​in the order of I series A machine, B machine and then II series A machine, B machine between different systems, and the fourth intra-system splicing data is obtained by the II series B machine based on the third input data D_IIA and the fourth input data D_IIB, which are spliced ​​in the order of first machine A and then machine B in the same system.

[0069] Further, the control I system A machine performs data consistency comparison on the first inter-system splicing data D_IAIBIIAIIB and the second inter-system splicing data D_IAIBIIAIIB based on the cyclic redundancy check value corresponding to the first intra-system splicing data D_IAIBIIAIIB.

[0070] Furthermore, if the data consistency is relatively successful, it means that both the I series A machine and the I series B machine will pass the data consistency. Therefore, the first inter-system splicing data D_IAIBIIAIIB and the second inter-system splicing data D_IAIBIIAIIB are both determined as the first inter-system splicing data are determined as the I series input data, which can be used directly or indirectly by the I series A machine and the I series B machine.

[0071] Through the above-described process, data verification can also be achieved between the II series A machine and the II series B machine, and ultimately the II series output data can be obtained, which can be used directly or indirectly by the II series A machine and the II series B machine.

[0072] At this point, the dual-system input data (D_IAIBIIAIIB) available for Series I A machines, Series I B machines, Series II A machines, and Series II B machines can be directly acquired by application software through the Application Programming Interface (API), and can also be adapted at the platform software level according to its associated task attributes to execute the Railway Signal Safety Protocol (RSSP), including RSSP-I, RSSP-II, and user-defined protocols to specify header operations, and then provide the processed actual valid data area to the application software in the form of an API interface.

[0073] If there are abnormal situations such as intra-system or inter-system interruptions, serial number verification failure, transmission data integrity verification failure, etc. in the above process, the associated receiving data storage area should be set to the safe side, and during the data verification process through the fast scheduling cycle, each virtual board data area should be kept from being overwritten and tampered with within a single system cycle and directed to the safe side before the next system cycle. Only the comparison area data that is relatively strictly consistent can be used. The real-time comparison area should transfer data in time after the comparison is completed, and the transferred data area should be promptly directed to the safe side.

[0074] The embodiment of the present invention combines the system cycle and the fast scheduling cycle to enable the external communication interface input data to be processed by the system cycle and the fast scheduling cycle within the platform to achieve balanced internal communication of the dual-system AB machines. This balanced processing method improves the overall performance of the system, enhances the reliability of communication, and ultimately effectively improves the maintainability of the system while ensuring the availability and security of the system.

[0075] In some embodiments, based on step 104, when controlling the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data verification based on the dual-system output data to obtain target output data outputted by the I series A machine, the I series B machine, the II series A machine and the II series B machine respectively, the following steps are performed for the I series A machine: Controlling the I series A machine to use a fast scheduling cycle to calculate a cyclic redundancy check value corresponding to the I series output data of the I series A machine; Control the I series A machine to receive the I series output data sent by the I series B machine; Controlling the I series A machine to perform data consistency comparison between the I series output data of the I series A machine and the I series output data of the I series B machine based on a cyclic redundancy check value corresponding to the I series output data of the I series A machine; If the data consistency comparison is successful, the I series A machine is controlled to generate corresponding target output data.

[0076] The following balanced processing of output data can be referred to Figure 5 , Figure 5 It is a flow chart of the processing of the universal security platform and external interface output data provided by the present invention.

[0077] Specifically, the I series A machine is controlled to use a fast scheduling cycle to calculate the cyclic redundancy check value corresponding to the I series output data O_I of the I series A machine, which may be a CRC32 value.

[0078] Furthermore, the I series B machine is controlled to use the system cycle to send the I series output data O_I to the I series A machine.

[0079] Furthermore, after the I series A machine receives the I series output data O_I sent by the I series B machine, the I series A machine is controlled to perform a data consistency comparison between the I series output data O_I of the I series A machine and the I series output data O_I of the I series B machine based on the cyclic redundancy check value corresponding to the I series output data O_I of the I series A machine.

[0080] Furthermore, if the data consistency comparison is successful, the A machine of the I system is controlled to generate the corresponding target output data O_IA.

[0081] Similarly, the I series B machine, the II series A machine and the II series B machine can only generate the usable target output data O_IB, O_IIA and O_IIB sent by the external interface after following the above data verification process.

[0082] After the available target output data O_IA, O_IB, O_IIA, O_IIB sent by the external interface is successfully generated, the communication node associated with the current virtual board is obtained according to the task object locally managed in the virtual board to send the output data to the external interface.

[0083] The embodiment of the present invention combines the system cycle and the fast scheduling cycle so that the output data output to the external communication interface can be processed by the system cycle and the fast scheduling cycle within the platform to achieve balanced internal communication of the dual-system AB machines. This balanced processing method improves the overall performance of the system, enhances the reliability of communication, and ultimately effectively improves the maintainability of the system while ensuring the availability and security of the system.

[0084] Furthermore, after controlling the I series A machine to generate corresponding target output data, it also includes: Control the I series A machine to receive the target output data sent by the I series B machine and the target output data sent by the II series A machine; control the I series A machine to perform data consistency comparison on the I series output data of the I series A machine, the target output data of the I series B machine, and the target output data of the II series A machine based on the cyclic redundancy check value corresponding to the I series output data of the I series A machine; if the data consistency comparison is successful, control the I series A machine to generate corresponding pair output data.

[0085] Specifically, the I series B machine and the II series A machine are controlled to respectively use the system cycle to send the corresponding target output data O_IB and O_IIA to the I series A machine.

[0086] Furthermore, the I-series A machine is controlled to receive the target output data O_IB sent by the I-series B machine and the target output data O_IIA sent by the II-series A machine.

[0087] Furthermore, the I series A machine is controlled to compare the I series output data O_I of the I series A machine with the target output data O_IB of the I series B machine and the target output data O_IIA of the II series A machine based on the cyclic redundancy check value corresponding to the I series output data of the I series A machine.

[0088] Furthermore, if the data consistency is successful, the I-series A machine is controlled to generate the corresponding pair output data O_II. Similarly, the I-series B machine can also generate the corresponding pair output data O_II.

[0089] Similarly, the II series A machine and the II series B machine can generate the corresponding pair output data O_I only after following the above data verification process.

[0090] After the system output data O_II and O_I are successfully generated, an API interface can be provided for use by the application program according to the application usage scenario.

[0091] The embodiment of the present invention combines the system cycle and the fast scheduling cycle so that the output data output to the external communication interface can be processed by the system cycle and the fast scheduling cycle within the platform to achieve balanced internal communication of the dual-system AB machines. This balanced processing method improves the overall performance of the system, enhances the reliability of communication, and ultimately effectively improves the maintainability of the system while ensuring the availability and security of the system.

[0092] It should be noted that before the general security platform receives and processes the input data from the external interface, in order to maintain the load balance and system stability of the general security platform, it is necessary to scientifically and reasonably disperse the dual-system communication IP in the dual-system AB machines, and design a communication configuration structure to uniformly manage the communication nodes. For this purpose, the following two configuration structures and dual-machine communication IP balanced setting methods are provided.

[0093] In some embodiments, the communication data equalization processing method further includes: The first channel of each task supported by each virtual board is configured on machine A; the machine A includes the I series A machine and the II series A machine; the second channel of each task supported by each virtual board is configured on machine B; the B machine includes the I series B machine and the II series B machine; after the configuration is completed, the corresponding communication Internet interconnection protocol IP is configured for each first channel and each second channel.

[0094] The following content describes the first configuration structure and the dual-machine communication IP balancing setting method under this configuration.

[0095] refer to Figure 6 , Figure 6 This is one of the configuration diagrams of the universal security platform and the external interface channel provided by the present invention. Figure 6 As shown, each virtual board contains M tasks, each task contains two channels, namely the first channel and the second channel, each channel is responsible for a communication link node, and the attributes of the communication link node are the same as the usage type of the virtual board to which it belongs. Among them, there are N virtual boards, and their corresponding indexes are represented as virtual board-0, virtual board-1,..., virtual board-N, and there are M tasks, and their corresponding indexes are represented as task-0, task-1,..., task-M. The index number of the first channel is represented as channel 0, and the index number of the second channel is represented as channel 1.

[0096] refer to Figure 7 , Figure 7 It is one of the planning distribution diagrams of the universal security platform and the external interface channel mode provided by the present invention.

[0097] Specifically, the first channel of each task supported by each virtual board is configured on machine A, wherein machine A specifically includes series I A machines and series II A machines.

[0098] At the same time, the second channel of each task supported by each virtual board is configured on the B machine, wherein the B machine specifically includes the I series B machine and the II series B machine.

[0099] It can be understood that all channel 0 nodes associated with task M of the virtual board are set on machine A, and all channel 1 nodes associated with task M are set on machine B, that is, the A network task nodes are set on machine A, and the B network task nodes are set on machine B.

[0100] Furthermore, after the configuration is completed, a corresponding communication Internet Protocol IP is configured for each first channel and each second channel.

[0101] The embodiment of the present invention realizes balanced setting of dual-machine communication IP by setting all channel 0 nodes associated with the tasks of the virtual board on machine A and all channel 1 nodes associated with task M on machine B, and can scientifically and reasonably disperse the dual-system communication IP in the dual-system A and B machines, thereby maintaining load balancing and system stability of the general security platform and enhancing the stability of the overall system.

[0102] In some embodiments, the communication data equalization processing method further includes: Each task supported by the virtual board with an odd virtual board index number is configured on machine A; the A machine includes the I series A machine and the II series A machine; each task supported by the virtual board with an even virtual board index number is configured on machine B; the B machine includes the I series B machine and the II series B machine; after the configuration is completed, a corresponding communication IP is configured for each task.

[0103] The following content describes the second configuration structure and the dual-machine communication IP balancing setting method under this configuration.

[0104] refer to Figure 8 , Figure 8 This is the second configuration diagram of the general security platform and external interface channel mode provided by the present invention. Figure 8 As shown, each virtual board contains M tasks, and network channels are no longer distinguished. Each task is a communication link node, and the attributes of the communication link node are the same as the usage type of the virtual board to which it belongs. Among them, there are N virtual boards, and their corresponding indexes are represented by virtual board-0, virtual board-1, ..., virtual board-N, and there are M tasks, and their corresponding indexes are represented by task-0, task-1, ..., task-M.

[0105] refer to Fig. 9 , Fig. 9 This is the second planning distribution diagram of the universal security platform and the external interface channel mode provided by the present invention.

[0106] Specifically, each task supported by a virtual board with an odd virtual board index number is configured on machine A, wherein machine A specifically includes series I A machines and series II A machines.

[0107] At the same time, each task supported by the virtual board with an even-numbered virtual board index number is configured on the B machine, wherein the B machine specifically includes the I series B machine and the II series B machine.

[0108] It can be understood that all tasks M with even virtual board index numbers are set on machine A, and all tasks M with odd virtual board index numbers are set on machine B, that is, they are set on machine A and machine B respectively according to the odd and even conditions of the virtual board index numbers.

[0109] Furthermore, after the configuration is completed, configure the corresponding communication IP for each task

[0110] In particular, for channels or tasks under the concept of virtual boards, their associated communication IPs will no longer be strongly bound to physical network cards or physical network ports. The IP addresses can be flexibly configured on designated network ports according to actual needs. Virtual boards focus on the tasks under their management rather than physical network cards or network port devices.

[0111] The embodiment of the present invention realizes balanced setting of dual-machine communication IP by setting all tasks with even-numbered virtual board index numbers on machine A and all tasks with odd-numbered virtual board index numbers on machine B, and can scientifically and reasonably disperse the dual-system communication IP in the dual-system A and B machines, thereby maintaining load balancing and system stability of the general security platform and enhancing the stability of the overall system.

[0112] The communication data equalization processing device provided by the present invention is described below. The communication data equalization processing device described below and the communication data equalization processing method described above can be referred to each other.

[0113] Reference Fig.10 , Fig.10 It is a structural schematic diagram of the communication data equalization processing device provided by the present invention.

[0114] The communication data equalization processing device comprises: The data receiving module 1010 is used to control the I series A machine, the I series B machine, the II series A machine and the II series B machine to respectively receive the first input data, the second input data, the third input data and the fourth input data sent by the external interface.

[0115] The input data verification module 1020 is used to control the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data verification based on the first input data, the second input data, the third input data and the fourth input data to obtain dual-series input data; the dual-series input data is used by the I series A machine, the I series B machine, the II series A machine and the II series B machine.

[0116] The input data processing module 1030 is used to control the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data processing based on the dual-series input data to obtain dual-series output data.

[0117] The output data verification module 1040 is used to control the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data verification based on the dual-system output data to obtain the target output data output by the I series A machine, the I series B machine, the II series A machine and the II series B machine respectively.

[0118] The communication data balancing processing device provided by the present invention distributes the functions of receiving and sending data with the external interface device to the dual-system A machine and B machine in a balanced manner, thereby eliminating the time-consuming internal interaction with the original equipment and effectively improving the system response capability. While transferring the external interaction function to the dual-system A machine and B machine, the balanced processing method of the input data and output data inside the universal security platform is redesigned, that is, by controlling the dual-system A machine and B machine to balance the input data and the output data respectively, effectively improving the system maintainability while ensuring the system availability and security.

[0119] Furthermore, the input data verification module 1020 is also used for: Control the I-series A machine to receive the second input data sent by the I-series B machine; Controlling the I-series A machine to perform data verification on the first input data and the second input data; After the data verification is successful, controlling the I-series A machine to splice the first input data and the second input data according to a first preset splicing order to obtain first intra-series splicing data; Control the I series A machine to use a fast scheduling cycle to calculate a cyclic redundancy check value corresponding to the spliced ​​data in the first series; Controlling the I-series A machine to receive the second intra-series splicing data sent by the I-series B machine; the second intra-series splicing data is obtained by the I-series B machine splicing the first input data and the second input data according to the first preset splicing order; Controlling the I-series A machine to perform data consistency comparison on the first-series spliced ​​data and the second-series spliced ​​data based on a cyclic redundancy check value corresponding to the first-series spliced ​​data; If the data consistency is successful, the I series A machine is controlled to perform data verification based on the first series splicing data, the third input data and the fourth input data to obtain the I series input data.

[0120] Furthermore, the input data verification module 1020 is also used for: Control the I series A machine to receive the third intra-system splicing data sent by the II series A machine using a system period; the third intra-system splicing data is obtained by the II series A machine splicing the third input data and the fourth input data according to the first preset splicing order; Control the I-series A machine to perform data verification on the first-series splicing data and the third-series splicing data; After the data verification is successful, controlling the I-series A machine to splice the first-series splicing data and the third-series splicing data according to a second preset splicing order to obtain first-series splicing data; Control the I-series A machine to generate a corresponding cyclic redundancy check value based on the first inter-series splicing data; Control the I series A machine to receive the second inter-system splicing data sent by the I series B machine; the second inter-system splicing data is obtained by the I series B machine splicing the second intra-system splicing data and the fourth intra-system splicing data according to the second preset splicing order; the fourth intra-system splicing data is obtained by the II series B machine splicing the third input data and the fourth input data according to the first preset splicing order; Controlling the I-series A machine to perform data consistency comparison on the first inter-series splicing data and the second inter-series splicing data based on a cyclic redundancy check value corresponding to the first inter-series splicing data; If the data consistency is relatively successful, the first inter-system splicing data is determined as the I system input data.

[0121] Furthermore, the output data verification module 1040 is also used for: Controlling the I series A machine to use a fast scheduling cycle to calculate a cyclic redundancy check value corresponding to the I series output data of the I series A machine; Control the I series A machine to receive the I series output data sent by the I series B machine; Controlling the I series A machine to perform data consistency comparison between the I series output data of the I series A machine and the I series output data of the I series B machine based on a cyclic redundancy check value corresponding to the I series output data of the I series A machine; If the data consistency comparison is successful, the I series A machine is controlled to generate corresponding target output data.

[0122] Furthermore, the output data verification module 1040 is also used for: Control the I series A machine to receive the target output data sent by the I series B machine and the target output data sent by the II series A machine; Controlling the I series A machine to compare the I series output data of the I series A machine with the target output data of the I series B machine and the target output data of the II series A machine for data consistency based on the cyclic redundancy check value corresponding to the I series output data of the I series A machine; If the data consistency comparison is successful, the I system A machine is controlled to generate corresponding pair system output data.

[0123] Furthermore, the communication data equalization processing device is also used for: The first channel of each task supported by each virtual board is configured on machine A; the machine A includes the series I machine A and the series II machine A; The second channel of each task supported by each virtual board is configured on the B machine; the B machine includes the I series B machine and the II series B machine; After the configuration is completed, a corresponding communication Internet protocol IP is configured for each first channel and each second channel.

[0124] Furthermore, the communication data equalization processing device is also used for: Allocate each task supported by the virtual board with an odd virtual board index number on machine A; the machine A includes the series I A machine and the series II A machine; Allocate each task supported by the virtual board with an even-numbered virtual board index number on the B machine; the B machine includes the I series B machine and the II series B machine; After the configuration is completed, configure the corresponding communication IP for each task.

[0125] It should be noted that the communication data equalization processing device provided by the present invention can execute the communication data equalization processing method described in any of the above embodiments during specific operation, which will not be described in detail in this embodiment.

[0126] Fig.11 is a schematic diagram of the structure of the electronic device provided by the present invention, such as Fig.11As shown, the electronic device may include: a processor 1110, a communications interface 1120, a memory 1130 and a communications bus 1140, wherein the processor 1110, the communications interface 1120 and the memory 1130 communicate with each other through the communications bus 1140. The processor 1110 may call the logic instructions in the memory 1130 to execute a communication data equalization processing method, the method comprising: controlling the I series A machine, the I series B machine, the II series A machine and the II series B machine to respectively receive the first input data, the second input data, the third input data and the fourth input data sent by the external interface; controlling the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data verification based on the first input data, the second input data, the third input data and the fourth input data to obtain dual-system input data. ; The dual-system input data is used by the I-system A machine, the I-system B machine, the II-system A machine and the II-system B machine; the I-system A machine, the I-system B machine, the II-system A machine and the II-system B machine are controlled to perform data processing based on the dual-system input data to obtain dual-system output data; the I-system A machine, the I-system B machine, the II-system A machine and the II-system B machine are controlled to perform data verification based on the dual-system output data to obtain target output data outputted by the I-system A machine, the I-system B machine, the II-system A machine and the II-system B machine respectively.

[0127] In addition, the logic instructions in the above-mentioned memory 1130 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0128] On the other hand, the present invention also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the communication data equalization processing method provided in the above-mentioned embodiments, and the method includes: controlling the I series A machine, the I series B machine, the II series A machine and the II series B machine to respectively receive the first input data, the second input data, the third input data and the fourth input data sent by the external interface; ... The input data, the third input data and the fourth input data are subjected to data verification to obtain dual-series input data; the dual-series input data is used by the I-series A machine, the I-series B machine, the II-series A machine and the II-series B machine; the I-series A machine, the I-series B machine, the II-series A machine and the II-series B machine are controlled to perform data processing based on the dual-series input data to obtain dual-series output data; the I-series A machine, the I-series B machine, the II-series A machine and the II-series B machine are controlled to perform data verification based on the dual-series output data to obtain target output data outputted by the I-series A machine, the I-series B machine, the II-series A machine and the II-series B machine respectively.

[0129] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the communication data equalization processing method provided in the above-mentioned embodiments is implemented, and the method includes: controlling the I series A machine, the I series B machine, the II series A machine and the II series B machine to respectively receive the first input data, the second input data, the third input data and the fourth input data sent by the external interface; controlling the I series A machine, the I series B machine, the II series A machine and the II series B machine to respectively receive the first input data, the second input data, the third input data and the fourth input data sent by the external interface; and controlling the I series A machine, the I series B machine, the II series A machine and the II series B machine to respectively receive the first input data, the second input data, the third input data and the fourth input data sent by the external interface. The input data is verified to obtain dual-series input data; the dual-series input data is used by the I-series A machine, the I-series B machine, the II-series A machine and the II-series B machine; the I-series A machine, the I-series B machine, the II-series A machine and the II-series B machine are controlled to perform data processing based on the dual-series input data to obtain dual-series output data; the I-series A machine, the I-series B machine, the II-series A machine and the II-series B machine are controlled to perform data verification based on the dual-series output data to obtain target output data outputted by the I-series A machine, the I-series B machine, the II-series A machine and the II-series B machine respectively.

[0130] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. Those of ordinary skill in the art may understand and implement the present invention without creative effort.

[0131] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A communication data equalization processing method, characterized in that: Applied to common security platforms, including: Controlling the I series A machine, the I series B machine, the II series A machine and the II series B machine to respectively receive the first input data, the second input data, the third input data and the fourth input data sent by the external interface; Control the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data verification based on the first input data, the second input data, the third input data and the fourth input data to obtain dual-series input data; the dual-series input data is used by the I series A machine, the I series B machine, the II series A machine and the II series B machine; Control the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data processing based on the dual-series input data to obtain dual-series output data; Control the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data verification based on the dual-system output data to obtain the target output data output by the I series A machine, the I series B machine, the II series A machine and the II series B machine respectively.

2. The communication data equalization processing method according to claim 1, characterized in that: The dual-system input data includes the I-system input data; when controlling the I-system A machine, the I-system B machine, the II-system A machine, and the II-system B machine to perform data verification based on the first input data, the second input data, the third input data, and the fourth input data to obtain the dual-system input data, the following steps are performed for the I-system A machine: Control the I-series A machine to receive the second input data sent by the I-series B machine; Controlling the I-series A machine to perform data verification on the first input data and the second input data; After the data verification is successful, controlling the I-series A machine to splice the first input data and the second input data according to a first preset splicing order to obtain first intra-series splicing data; Control the I series A machine to use a fast scheduling cycle to calculate a cyclic redundancy check value corresponding to the spliced ​​data in the first series; Controlling the I-series A machine to receive the second intra-series splicing data sent by the I-series B machine; the second intra-series splicing data is obtained by the I-series B machine splicing the first input data and the second input data according to the first preset splicing order; Controlling the I-series A machine to perform data consistency comparison on the first-series spliced ​​data and the second-series spliced ​​data based on a cyclic redundancy check value corresponding to the first-series spliced ​​data; If the data consistency is successful, the I series A machine is controlled to perform data verification based on the first series splicing data, the third input data and the fourth input data to obtain the I series input data.

3. The communication data equalization processing method according to claim 2, characterized in that: The controlling the I series A machine to perform data verification based on the first series internal splicing data, the third input data, and the fourth input data to obtain the I series input data includes: Control the I series A machine to receive the third intra-system splicing data sent by the II series A machine using a system period; the third intra-system splicing data is obtained by the II series A machine splicing the third input data and the fourth input data according to the first preset splicing order; Control the I-series A machine to perform data verification on the first-series splicing data and the third-series splicing data; After the data verification is successful, controlling the I-series A machine to splice the first-series splicing data and the third-series splicing data according to a second preset splicing order to obtain first-series splicing data; Control the I-series A machine to generate a corresponding cyclic redundancy check value based on the first inter-series splicing data; Control the I series A machine to receive the second inter-system splicing data sent by the I series B machine; the second inter-system splicing data is obtained by the I series B machine splicing the second intra-system splicing data and the fourth intra-system splicing data according to the second preset splicing order; the fourth intra-system splicing data is obtained by the II series B machine splicing the third input data and the fourth input data according to the first preset splicing order; Controlling the I-series A machine to perform data consistency comparison on the first inter-series splicing data and the second inter-series splicing data based on a cyclic redundancy check value corresponding to the first inter-series splicing data; If the data consistency is relatively successful, the first inter-system splicing data is determined as the I system input data.

4. The communication data equalization processing method according to claim 1, characterized in that: The dual-system output data includes the I-system output data; when controlling the I-system A machine, the I-system B machine, the II-system A machine and the II-system B machine to perform data verification based on the dual-system output data to obtain the target output data outputted by the I-system A machine, the I-system B machine, the II-system A machine and the II-system B machine respectively, the following steps are performed for the I-system A machine: Controlling the I series A machine to use a fast scheduling cycle to calculate a cyclic redundancy check value corresponding to the I series output data of the I series A machine; Control the I series A machine to receive the I series output data sent by the I series B machine; Controlling the I series A machine to perform data consistency comparison between the I series output data of the I series A machine and the I series output data of the I series B machine based on a cyclic redundancy check value corresponding to the I series output data of the I series A machine; If the data consistency comparison is successful, the I series A machine is controlled to generate corresponding target output data.

5. The communication data equalization processing method according to claim 4, characterized in that: After controlling the I series A machine to generate corresponding target output data, the method further includes: Control the I series A machine to receive the target output data sent by the I series B machine and the target output data sent by the II series A machine; Controlling the I series A machine to compare the I series output data of the I series A machine with the target output data of the I series B machine and the target output data of the II series A machine for data consistency based on the cyclic redundancy check value corresponding to the I series output data of the I series A machine; If the data consistency comparison is successful, the I system A machine is controlled to generate corresponding pair system output data.

6. The communication data equalization processing method according to claim 1, characterized in that: The universal security platform can support multiple virtual boards; Each virtual board supports multiple tasks; Each task consists of a first channel and a second channel; The communication data equalization processing method also includes: The first channel of each task supported by each virtual board is configured on machine A; the machine A includes the series I A machine and the series II A machine; The second channel of each task supported by each virtual board is configured on the B machine; the B machine includes the I series B machine and the II series B machine; After the configuration is completed, a corresponding communication Internet Protocol IP is configured for each first channel and each second channel.

7. The communication data equalization processing method according to claim 1, characterized in that: The universal security platform can support multiple virtual boards; Each virtual board supports multiple tasks; The communication data equalization processing method also includes: Allocate each task supported by the virtual board with an odd virtual board index number on machine A; the machine A includes the series I A machine and the series II A machine; Allocate each task supported by the virtual board with an even-numbered virtual board index number on the B machine; the B machine includes the I series B machine and the II series B machine; After the configuration is completed, configure the corresponding communication IP for each task.

8. A communication data equalization processing device, characterized in that: include: A data receiving module, used for controlling the I series A machine, the I series B machine, the II series A machine and the II series B machine to respectively receive the first input data, the second input data, the third input data and the fourth input data sent by the external interface; An input data verification module is used to control the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data verification based on the first input data, the second input data, the third input data and the fourth input data to obtain dual-series input data; the dual-series input data is used by the I series A machine, the I series B machine, the II series A machine and the II series B machine; An input data processing module, used for controlling the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data processing based on the dual-series input data to obtain dual-series output data; The output data verification module is used to control the I series A machine, the I series B machine, the II series A machine and the II series B machine to perform data verification based on the dual-system output data to obtain the target output data output by the I series A machine, the I series B machine, the II series A machine and the II series B machine respectively.

9. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the communication data equalization processing method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium, the computer-readable storage medium comprising a non-transitory computer-readable storage medium, having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the communication data equalization processing method according to any one of claims 1 to 7 are implemented.

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