Method for converting AXI protocol data stream interface and storage mapping interface
In the conversion method of the AXI protocol data flow interface and the storage mapping interface, the user logic controls the conversion of the data flow and the storage mapping interface according to custom rules, solving the problems of high resource consumption, high development costs, poor flexibility and low fault tolerance in the prior art, and realizing data transmission effects of resource saving, low development costs, high flexibility and high fault tolerance.
Patent Information
- Application Number
- CN202411682719.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-22
- Publication Date
- 2025-02-28
AI Technical Summary
When the existing AXI-DMA IP core realizes the conversion of the AXI data stream interface to the AXI storage mapping interface, it consumes a lot of resources, has high development costs, poor flexibility and low fault tolerance, and cannot meet the usage requirements in complex scenarios.
By providing a conversion method between the AXI protocol data stream interface and the storage mapping interface, the user logic resets and completes the initial configuration. After detecting valid data, the data type and exception are checked according to the custom rules. The control interface issues a write request signal, a write address signal, a write length signal and a status code signal to realize the conversion between the data stream and the storage mapping interface without the participation of the microcontroller.
This method consumes less resources, has low development costs, and has high flexibility and fault tolerance. User logic can parse and control the write address and length according to custom rules, capture data errors in real time and feedback, and improve system stability.
Smart Images
Figure CN119544838A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of data transmission, and in particular to a method for converting an AXI protocol data stream interface and a storage mapping interface. Background Art
[0002] AXI (Advanced eXtensible Interface), advanced extensible interface, is part of the AMBA (Advanced Microcontroller Bus Architecture) protocol proposed by ARM. Xilinx has used the AXI protocol to connect various IP cores since the Spartan-6 and Virtex-6 series FPGAs. The AXI protocol is a high-performance, high-bandwidth, low-latency on-chip bus. The AXI protocol has two types of interfaces: storage mapping and non-storage mapping (data stream). The storage mapping interface is used to communicate with storage IP cores such as DDR and BRAM, and the data stream interface is used to communicate with data stream IP cores such as ADC and Ethernet.
[0003] In actual engineering applications, both AXI interfaces are used extensively. External data is transmitted to the FPGA in the form of data streams, and after internal processing, it is transferred to the memory for subsequent operations. This process inevitably brings about the conversion problem from the AXI data stream interface to the AXI memory mapping interface.
[0004] Xilinx provides an AXI-DMA IP core that can realize the conversion function from AXI data stream interface to AXI memory mapping interface. The AXI-DMA IP core implements interface conversion, data handling and logic control functions, and provides a set of control registers. It has three groups of interfaces, namely AXI data stream interface, AXI memory mapping interface and control interface. In engineering applications, the AXI-DMA IP core often needs to be used with a microcontroller. The microcontroller configures the internal registers of the AXI-DMA IP core through the control interface to achieve the purpose of controlling data transmission behavior.
[0005] See also Figure 5 , the working principle of the AXI-DMA IP core in the prior art is as follows:
[0006] The microcontroller acts as the control center during the transmission process. The microcontroller pre-configures the registers inside the AXI-DMA IP core through the control interface, sets the write address and write length. When the AXI data stream interface has data, the AXI-DMA IP core automatically receives the data stream and initiates a write operation through the AXI storage mapping interface according to the set write address and length, and moves the data stream to the storage mapping IP core. The microcontroller obtains the write completion signal in real time through the control interface. As needed, the transmission configuration of the AXI-DMA IP core remains unchanged or the write address and write length are reconfigured, and a new transmission process is started.
[0007] The AXI-DMA IP core cannot complete the work independently. An additional microcontroller is required to control the transmission behavior. The microcontroller runs C / C++ code and requires a certain amount of memory space. The more complex the transmission behavior is, the more resources are needed. In resource-constrained FPGA applications, these additional resource consumption will become a key technical bottleneck. FPGA development uses Veri log language, while microcontroller development uses C / C++ language. Microcontrollers require additional software engineers to develop and debug, which will undoubtedly increase the development cost of the entire technical solution.
[0008] At the same time, this method has poor flexibility. The AXI-DMA IP core is suitable for moving video images, ADC and other data with relatively fixed storage addresses and relatively simple formats. Since there is no communication link between the microcontroller and the data stream IP core, after the AXI-DMA IP core starts a transmission, it needs to complete the current transmission before it can start the next transmission again. In the data writing process, when there are different data types, different data lengths and storage at different addresses in the data stream, the microcontroller is completely unable to obtain these data stream characteristics in time, so it is impossible to control the AXI-DMA IP core to complete the matching transmission behavior, and it cannot meet the use requirements in complex scenarios.
[0009] In addition, this method has low fault tolerance, and the microcontroller and data stream IP core are independent of each other and have no communication link. After the AXI-DMA IP core starts a transmission, it needs to complete the current transmission before it can start the next transmission again. When data errors, data loss and other abnormal conditions occur in the data stream, the microcontroller cannot monitor the data stream abnormalities in time, which will cause the AXI-DMA IP core to write erroneous or invalid data into the memory, and other modules in the system cannot obtain this error. In this case, the entire system will be seriously affected. Summary of the invention
[0010] In view of the above problems, the present invention provides a method for converting an AXI protocol data stream interface to a storage mapping interface for overcoming the above problems or at least partially solving the above problems. The problem of AXI-DMA IP core + microcontroller consuming a lot of resources and having high development costs is solved. The problem of poor flexibility of AXI-DMA IP core + microcontroller is solved. The problem of low fault tolerance of AXI-DMA IP core + microcontroller is solved.
[0011] The present invention provides the following scheme:
[0012] A method for converting an AXI protocol data stream interface to a storage mapping interface, comprising:
[0013] Step 1: User logic reset to complete initialization configuration;
[0014] Step 2, the user logic executes step 3 after detecting that there is valid data in the AXI protocol data stream interface through the data stream IP core;
[0015] Step 3: The user logic checks the data type and data anomaly according to the custom rules to see whether it is normal;
[0016] Step 4: If the inspection is normal, proceed to step 5; if the inspection is abnormal, proceed to step 8;
[0017] Step 5, the user logic sends a write request signal, a write address signal, a write length signal and a status code signal to the AXI data stream and storage mapping interface conversion IP core through the control interface;
[0018] Step 6, waiting for the AXI data stream and storage mapping interface conversion IP core to complete the data stream data writing according to the write request signal, the write address signal, the write length signal and the status code signal, and then proceeding to step 7;
[0019] Step 7: Return to step 2 and wait for valid data from the data stream interface again;
[0020] Step 8: The user logic writes the exception address and the status code.
[0021] Preferably: step 6 comprises:
[0022] Step 61, the AXI data stream and storage mapping interface conversion IP core is reset to complete the IP core initialization configuration;
[0023] Step 62: receiving the write request signal from the control interface;
[0024] Step 63, check whether the input write address signal, the write length signal and the status code signal are normal; if the check is normal, proceed to step 64; if the check is abnormal, proceed to step 610;
[0025] Step 64: the AXI data stream and storage mapping interface conversion IP core controls the AXI storage mapping interface to issue a write address operation;
[0026] Step 65, the AXI data stream and storage mapping interface conversion IP core waits for valid data from the AXI data stream interface;
[0027] Step 66, the AXI data stream and storage mapping interface conversion IP core checks whether the write address signal and the status code signal are normal, and if the check is normal, it goes to step 67, and if the check is abnormal, it goes to step 610;
[0028] Step 67: the AXI data stream and storage mapping interface conversion IP core controls the AXI storage mapping interface to issue a write data operation;
[0029] Step 68: After the data is written, the AXI data stream and storage mapping interface conversion IP core waits for a write response signal from the AXI storage mapping interface;
[0030] Step 69: After receiving the write response signal, return to step 62 and continue to wait for the write request signal;
[0031] Step 610: Control the AXI storage mapping interface to issue a write exception address operation and a write status code operation.
[0032] Preferably, the AXI data stream interface and the AXI storage mapping interface are standard interfaces that comply with the AXI protocol.
[0033] Preferably: the control code of the write request signal, the write address signal, the write length signal and the status code signal are integrated into the user logic.
[0034] Preferably, the control codes of the write address signal and the write length signal are signal control codes input by the user according to different data types.
[0035] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:
[0036] The embodiment of the present application provides a method for converting an AXI protocol data stream interface to a storage mapping interface, which consumes few resources and has low development costs. The control code is integrated in the user logic to realize the conversion from the AXI data stream interface to the AXI storage mapping interface, without the involvement of a microcontroller or a software engineer in the development of C / C++ code. It has high flexibility. Whether it is transmitting fixed-type data or transmitting different types of data, the user logic can parse according to custom rules and flexibly control the write address and write length. It has high fault tolerance. During any transmission process, the user logic can capture abnormal situations such as data errors and data loss in real time, immediately feedback to the IP core, and write the status code to the memory to mark invalid data, thereby improving the stability of the entire system.
[0037] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0039] Figure 1 It is a flow chart of a method for converting an AXI protocol data stream interface and a storage mapping interface provided by an embodiment of the present invention;
[0040] Figure 2 is a schematic diagram of an input signal provided by an embodiment of the present invention;
[0041] Figure 3 It is a working principle diagram of the IP core provided by an embodiment of the present invention;
[0042] Figure 4 It is a schematic diagram of an application process provided by an embodiment of the present invention;
[0043] Figure 5 The prior art includes a working principle diagram of a microcontroller AXI-DMA IP core. DETAILED DESCRIPTION
[0044] The technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present invention.
[0045] See also Figure 1, a method for converting an AXI protocol data stream interface and a storage mapping interface provided by an embodiment of the present invention, such as Figure 1 As shown, the method may include:
[0046] Step 1: User logic reset to complete initialization configuration;
[0047] Step 2, the user logic executes step 3 after detecting that there is valid data in the AXI protocol data stream interface through the data stream IP core;
[0048] Step 3: The user logic checks the data type and data anomaly according to the custom rules to see whether it is normal;
[0049] Step 4: If the inspection is normal, proceed to step 5; if the inspection is abnormal, proceed to step 8;
[0050] Step 5, the user logic sends a write request signal, a write address signal, a write length signal and a status code signal to the AXI data stream and storage mapping interface conversion IP core through the control interface;
[0051] Step 6, waiting for the AXI data stream and storage mapping interface conversion IP core to complete the data stream data writing according to the write request signal, the write address signal, the write length signal and the status code signal, and then proceeding to step 7;
[0052] Step 7: Return to step 2 and wait for valid data from the data stream interface again;
[0053] Step 8: The user logic writes the exception address and the status code.
[0054] In specific implementation, the step 6 includes:
[0055] Step 61, the AXI data stream and storage mapping interface conversion IP core is reset to complete the IP core initialization configuration;
[0056] Step 62: receiving the write request signal from the control interface;
[0057] Step 63, check whether the input write address signal, the write length signal and the status code signal are normal; if the check is normal, proceed to step 64; if the check is abnormal, proceed to step 610;
[0058] Step 64: the AXI data stream and storage mapping interface conversion IP core controls the AXI storage mapping interface to issue a write address operation;
[0059] Step 65, the AXI data stream and storage mapping interface conversion IP core waits for valid data from the AXI data stream interface;
[0060] Step 66, the AXI data stream and storage mapping interface conversion IP core checks whether the write address signal and the status code signal are normal, and if the check is normal, it goes to step 67, and if the check is abnormal, it goes to step 610;
[0061] Step 67: the AXI data stream and storage mapping interface conversion IP core controls the AXI storage mapping interface to issue a write data operation;
[0062] Step 68: After the data is written, the AXI data stream and storage mapping interface conversion IP core waits for a write response signal from the AXI storage mapping interface;
[0063] Step 69: After receiving the write response signal, return to step 62 and continue to wait for the write request signal;
[0064] Step 610: Control the AXI storage mapping interface to issue a write exception address operation and a write status code operation.
[0065] Furthermore, the AXI data stream interface and the AXI storage mapping interface are standard interfaces that comply with the AXI protocol.
[0066] The control code of the write request signal, the write address signal, the write length signal, and the status code signal are integrated into the user logic.
[0067] In order to facilitate the user to adjust each signal according to needs, the embodiment of the present application can also provide the control code of the write address signal and the write length signal as a signal control code input by the user according to different data types.
[0068] The conversion method of the AXI protocol data stream interface and the storage mapping interface provided by the present application includes a set of control signals, which can realize the conversion of the AXI data stream-AXI storage mapping interface, consume less resources, and have low application development cost. During the AXI data stream transmission process, when there are different data types, the write address and write length can be effectively controlled to improve flexibility. During the AXI data stream transmission process, when there is data abnormality, the transmission can be terminated in time, and a data error flag can be set in the memory to improve the system fault tolerance rate.
[0069] The method provided by this application is introduced in detail below.
[0070] like Figure 2 As shown in the figure, the AXI data stream-storage mapping interface conversion IP core implements interface conversion, data handling and logic control functions internally, and its external core contains three groups of signals, namely the control interface, AXI storage mapping interface and AXI data stream interface. The control interface contains four input signals, namely write request, write address, write length and status code. The AXI data stream interface and AXI storage mapping interface are standard interfaces that comply with the AXI protocol.
[0071] AXI data stream - storage mapping interface conversion IP core working principle, such as Figure 3 As shown:
[0072] 1. Reset the AXI data stream-storage mapping interface conversion IP core and complete the IP core initialization configuration.
[0073] 2. Wait for the write request signal from the control interface.
[0074] 3. Check the input write address, write length and status code signal.
[0075] 4. Check if everything is normal and control the AXI storage mapping interface to issue a write address operation.
[0076] 5. Wait for valid data from the AXI data stream interface.
[0077] 6. Check the write address and status code signals.
[0078] 7. Control the AXI storage mapping interface to issue a write data operation.
[0079] 8. After writing the data, wait for the write response signal from the AXI storage mapping interface.
[0080] 9. Return to step 2 and continue waiting for the write request signal.
[0081] 10. Control the AXI storage mapping interface to issue a write exception address operation.
[0082] 11. Control the AXI storage mapping interface to issue a write status code operation.
[0083] 12. In step 3, after checking for errors, proceed to step 10.
[0084] 13. In step 6, after checking for errors, proceed to step 10.
[0085] The AXI data stream-memory mapping interface conversion IP core needs to be used in conjunction with user logic, which controls the data transmission process. Figure 1 The application process is as follows. Figure 4 shown.
[0086] 1. User logic reset to complete initialization configuration;
[0087] 2. Wait for valid data from the data stream interface;
[0088] 3. Check data types and data anomalies according to custom rules;
[0089] 4. Check if it is normal, and the control interface sends the write address and write length;
[0090] 5. The control interface issues a write request;
[0091] 6. Wait for the data stream to be written to completion;
[0092] 7. Return to step 2 and wait for valid data from the data stream interface again;.
[0093] 8. Check the exception, write the exception address and status code;
[0094] 9. In step 3, if the inspection is abnormal, go to step 8.
[0095] In short, the conversion method of the AXI protocol data stream interface and the storage mapping interface provided by this application consumes less resources and has low development cost. The control code is integrated in the user logic to realize the conversion of the AXI data stream interface to the AXI storage mapping interface. There is no need for the participation of a microcontroller, and there is no need for a software engineer to participate in the development of C / C++ code. It has high flexibility. Whether it is transmitting fixed type data or transmitting different types of data, the user logic can be parsed according to custom rules, and the write address and write length can be flexibly controlled. It has high fault tolerance. During any transmission process, the user logic can capture abnormal situations such as data errors and data loss in real time, and immediately feedback to the IP core, and write the status code to the memory to mark invalid data, thereby improving the stability of the entire system.
[0096] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0097] It can be known from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product can be stored in a storage medium such as ROM / RAM, a disk, an optical disk, etc., and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application or certain parts of the embodiments.
[0098] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can refer to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without creative work.
[0099] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims
1. A method for converting an AXI protocol data stream interface to a storage mapping interface, characterized in that: include: Step 1: User logic reset to complete initialization configuration; Step 2, the user logic executes step 3 after detecting that there is valid data in the AXI protocol data stream interface through the data stream IP core; Step 3: The user logic checks the data type and data anomaly according to the custom rules to see whether it is normal; Step 4: If the inspection is normal, proceed to step 5; if the inspection is abnormal, proceed to step 8; Step 5, the user logic sends a write request signal, a write address signal, a write length signal and a status code signal to the AXI data stream and storage mapping interface conversion IP core through the control interface; Step 6, waiting for the AXI data stream and storage mapping interface conversion IP core to complete the data stream data writing according to the write request signal, the write address signal, the write length signal and the status code signal, and then proceeding to step 7; Step 7: Return to step 2 and wait for valid data from the data stream interface again; Step 8: The user logic writes the exception address and the status code.
2. The method for converting an AXI protocol data stream interface to a storage mapping interface according to claim 1, characterized in that: The step 6 comprises: Step 61, the AXI data stream and storage mapping interface conversion IP core is reset to complete the IP core initialization configuration; Step 62: receiving the write request signal from the control interface; Step 63, check whether the input write address signal, the write length signal and the status code signal are normal; if the check is normal, proceed to step 64; if the check is abnormal, proceed to step 610; Step 64: the AXI data stream and storage mapping interface conversion IP core controls the AXI storage mapping interface to issue a write address operation; Step 65, the AXI data stream and storage mapping interface conversion IP core waits for valid data from the AXI data stream interface; Step 66, the AXI data stream and storage mapping interface conversion IP core checks whether the write address signal and the status code signal are normal, and if the check is normal, it goes to step 67, and if the check is abnormal, it goes to step 610; Step 67: the AXI data stream and storage mapping interface conversion IP core controls the AXI storage mapping interface to issue a write data operation; Step 68: After writing the data, the AXI data stream and storage mapping interface conversion IP core waits for a write response signal from the AXI storage mapping interface. Step 69: After receiving the write response signal, return to step 62 and continue to wait for the write request signal; Step 610: Control the AXI storage mapping interface to issue a write exception address operation and a write status code operation.
3. The method for converting an AXI protocol data stream interface to a storage mapping interface according to claim 2, characterized in that: The AXI data stream interface and the AXI storage mapping interface are standard interfaces that comply with the AXI protocol.
4. The method for converting an AXI protocol data stream interface to a storage mapping interface according to claim 1, characterized in that: The control code of the write request signal, the write address signal, the write length signal, and the status code signal are integrated into the user logic.
5. The method for converting an AXI protocol data stream interface to a storage mapping interface according to claim 4, characterized in that: The control codes of the write address signal and the write length signal are signal control codes input by a user according to different data types.