Thin embedded capacitor circuit board with high capacitance value and manufacturing method thereof

Abstract

The invention discloses a thin embedded capacitor circuit board with a high capacitance value and a manufacturing method thereof, and the method comprises the steps: providing a flexible substrate, and manufacturing a first electrode layer at a first side of the flexible substrate; forming a first insulating medium layer on one side, far away from the first flexible base material, of the first electrode layer by adopting a physical deposition or chemical deposition method; forming a second electrode layer on one side, far away from the first electrode layer, of the first insulating dielectric layer by adopting a vacuum sputtering method to obtain an initial embedded capacitor circuit board; wherein the projection of the second electrode layer on the first insulating dielectric layer is overlapped with the projection of the first electrode layer on the first insulating dielectric layer; and performing outer surface treatment on the initial capacitor-embedded circuit board to obtain a target capacitor-embedded circuit board. According to the invention, the capacitor circuit board which simultaneously meets the requirements of high-capacitance and low-thickness capacitor products can be formed.

Description

Technical Field

[0001] The invention relates to the field of flexible circuit board manufacturing, and in particular to a thin buried capacitance circuit board with high capacitance and a manufacturing method thereof. Background Art

[0002] Capacitors are common electronic components in circuit boards. Their basic structure consists of two conductors with a certain area placed opposite to each other and an insulating medium between the two conductors. The most important indicator of capacitance is the capacitance value, which is proportional to the area of ​​the two conductors facing each other and the dielectric constant of the insulating medium, and inversely proportional to the thickness of the insulating medium.

[0003] Capacitors play an important role in circuits and have many functions and uses, including but not limited to energy storage, filtering, coupling, and voltage regulation. At present, the most common methods of setting capacitors on circuit boards are surface mounting and plug-in mounting. Both methods can only install capacitors on the surface of the circuit board. Depending on the circuits and functions in the circuit board, the number of capacitor components on the circuit board ranges from 1-2 to hundreds. A large number of capacitor components need to occupy a very large area, which increases the size of the circuit board.

[0004] In order to overcome the problem of increased circuit board area caused by capacitor components, there are some methods to place capacitors in the middle (inner layer) of the circuit board. For example, 3M has developed a buried capacitance film material. The material consists of a ceramic-filled epoxy insulating medium and copper foils arranged on both sides of the insulating medium. The minimum thickness of the insulating medium is 3μm, and the dielectric constant of the insulating medium is 22. The capacitance density of this material can reach 6.2nF / cm 2 However, it is not possible to form capacitors with large capacitance (such as μF, mF, etc.) on a circuit board with a smaller area using this material. Another way is to directly embed the capacitor components in the middle of the circuit board using laminated materials, so that a larger capacitance can be obtained in a smaller area. However, since the minimum thickness of the capacitor components currently available for installation is still more than 0.15mm, this embedding method cannot be used in very thin circuit boards (especially flexible circuit boards). Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a thin embedded capacitor circuit board with high capacitance and a manufacturing method thereof, so as to solve the problem that the existing embedded capacitor technology cannot form a capacitor circuit board with both high capacitance and low thickness.

[0006] The present invention provides a method for manufacturing a thin buried capacitance circuit board with high capacitance, the method comprising:

[0007] Providing a flexible substrate, and manufacturing a first electrode layer on a first side of the flexible substrate;

[0008] Forming a first insulating dielectric layer on a side of the first electrode layer away from the first flexible substrate by a physical deposition method or a chemical deposition method;

[0009] A second electrode layer is formed on a side of the first insulating dielectric layer away from the first electrode layer by vacuum sputtering to obtain an initial buried capacitance circuit board; wherein a projection of the second electrode layer on the first insulating dielectric layer overlaps with a projection of the first electrode layer on the first insulating dielectric layer;

[0010] The initial embedded capacitance circuit board is subjected to external surface treatment to obtain a target embedded capacitance circuit board.

[0011] Optionally, before forming the first insulating dielectric layer on the side of the first electrode layer away from the first flexible substrate by the physical deposition or chemical deposition method, the method further comprises:

[0012] According to the preset capacitor design data, attaching a first mask to a side of the first electrode layer away from the first flexible substrate;

[0013] Correspondingly, a first insulating dielectric layer is formed on the first side of the first electrode layer by a physical deposition method or a chemical deposition method, specifically:

[0014] Based on the first mask, forming the first insulating medium layer on the side of the first electrode layer away from the first flexible substrate by magnetron sputtering;

[0015] After forming the first insulating medium layer, the first mask attached to the first electrode layer is removed.

[0016] Optionally, the first mask is any one of a metal cover plate, a polymer film and a photosensitive cover film.

[0017] Optionally, the first insulating dielectric layer is composed of any one of barium titanate, strontium titanate, barium strontium titanate, lead zirconate titanate, and calcium titanate, or a mixture of any of the above.

[0018] Optionally, the thickness of the first insulating dielectric layer is in the range of 10 nm to 3 μm.

[0019] Optionally, the thickness of the first insulating dielectric layer is in the range of 300 nm to 1 μm.

[0020] Optionally, the method of using a vacuum sputtering method to form a second electrode layer on a side of the first insulating dielectric layer away from the first electrode layer to obtain an initial buried capacitance circuit board includes:

[0021] forming a metal seed layer on a side of the first insulating dielectric layer away from the first electrode layer by vacuum sputtering;

[0022] According to the preset capacitor design data, the exposure and development process and the etching process are sequentially adopted to perform patterning on the first metal seed layer, so that the first metal seed layer forms the second electrode layer to obtain the initial buried capacitor circuit board.

[0023] Optionally, the method of using a vacuum sputtering method to form a second electrode layer on a side of the first insulating dielectric layer away from the first electrode layer to obtain an initial buried capacitance circuit board includes:

[0024] According to the preset capacitor design data, attaching a second mask to a side of the first insulating medium layer away from the first electrode layer;

[0025] Based on the second mask, a metal seed layer having a pattern is formed on a side of the first insulating medium layer away from the first electrode layer by a vacuum sputtering method, so that the metal seed layer having the pattern forms the second electrode layer;

[0026] After forming the second electrode layer, the second mask plate attached to the first insulating medium layer is removed to obtain the initial buried capacitance circuit board.

[0027] Optionally, when the thickness of the formed metal seed layer is less than or equal to a preset threshold, the method further includes:

[0028] The formed metal seed layer is thickened by electroplating or chemical plating.

[0029] Optionally, before performing external surface treatment on the initial embedded capacitance circuit board, the method further comprises:

[0030] The first electrode layer and the second electrode layer are respectively led out through lines.

[0031] Optionally, after forming the second electrode layer on a side of the first insulating dielectric layer away from the first electrode layer by vacuum sputtering, the method further comprises:

[0032] Forming a second insulating dielectric layer on a side of the second electrode layer away from the first insulating dielectric layer by a physical deposition method or a chemical deposition method;

[0033] A third electrode layer is formed on a side of the second insulating dielectric layer away from the second electrode layer by using a vacuum sputtering method; wherein a projection of the third electrode layer on the second insulating dielectric layer overlaps with a projection of the second electrode layer on the second insulating dielectric layer, and the third electrode layer is electrically connected to the first electrode layer.

[0034] Optionally, the flexible substrate is any one of a single-sided board, a double-sided board or a multi-layer board.

[0035] In addition, the present invention also provides a thin buried capacitance circuit board with high capacitance, which is manufactured by the aforementioned manufacturing method.

[0036] The beneficial effects of the present invention are as follows: a first electrode layer is made of a flexible substrate, a second electrode layer is formed by a vacuum sputtering method, and a first insulating dielectric layer is formed between the first electrode layer and the second electrode layer by a physical deposition or chemical deposition method, so that a first electrode layer, a second electrode layer and a first insulating dielectric layer with a large paving area and a thin thickness can be formed respectively; wherein the projection of the second electrode layer on the first insulating dielectric layer overlaps with the projection of the first electrode layer on the first insulating dielectric layer, which means that the first electrode layer and the second electrode layer are completely or partially opposite to each other, and then based on the first insulating dielectric layer between the two (i.e., the first electrode layer and the second electrode layer), an initial buried capacitance circuit board with a large capacitance per unit area and a thin thickness can be formed, and finally, through the outer surface treatment of the initial buried capacitance circuit board, the target buried capacitance circuit board obtained can simultaneously meet the requirements of high capacitance and low thickness capacitor products. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The features and advantages of the present invention will be more clearly understood by referring to the accompanying drawings, which are schematic and should not be construed as limiting the present invention in any way. In the accompanying drawings:

[0038] Figure 1 A flow chart showing a method for manufacturing a thin buried capacitance circuit board with high capacitance in the first embodiment of the present invention is shown;

[0039] Figure 2 The cross-sectional structure diagram of the double-sided board in the first embodiment of the present invention is shown;

[0040] Figure 3 The cross-sectional structure diagram of the flexible substrate with the first electrode layer in the first embodiment of the present invention is shown;

[0041] Figure 4 The cross-sectional structure diagram of the first insulating dielectric layer formed by directly using a magnetron sputtering method in the first embodiment of the present invention is shown;

[0042] Figure 5 A cross-sectional structural diagram of a first mask plate attached in the first embodiment of the present invention is shown;

[0043] Figure 6 A cross-sectional structural diagram showing a first insulating dielectric layer formed by magnetron sputtering based on a first mask in Embodiment 1 of the present invention is shown;

[0044] Figure 7 A cross-sectional structural diagram of the first embodiment of the present invention without the first mask is shown;

[0045] Figures 8A to 8C A schematic diagram showing a first optional embodiment of forming a second electrode layer in Embodiment 1 of the present invention;

[0046] Figures 9A to 9D A schematic diagram showing a second optional embodiment of forming a second electrode layer in the first embodiment of the present invention;

[0047] Fig.10 The cross-sectional structure diagram of the flexible substrate after the connection layer and the interlayer via holes are manufactured on the double-sided board in the first embodiment of the present invention is shown;

[0048] Fig.11 A schematic diagram showing the circuit lead-out of the second electrode layer based on a single-sided board and copper-plated holes in the first embodiment of the present invention is shown;

[0049] Fig. 12A The cross-sectional structure diagram of the target embedded capacitance circuit board obtained after the external surface treatment of the initial embedded capacitance circuit board after the circuit lead-out in the first embodiment of the present invention is shown;

[0050] Fig. 12B The cross-sectional structure diagram of the target embedded capacitance circuit board obtained after the external surface treatment of the initial embedded capacitance circuit board after the circuit is led out when the second electrode layer is led out by a wire in the first embodiment of the present invention;

[0051] Fig.13 A schematic diagram showing a second insulating dielectric layer formed by using a mask after the second electrode layer is manufactured in the first embodiment of the present invention;

[0052] Fig.14 A schematic diagram showing the formation of a third electrode layer using a mask after the second insulating dielectric layer is manufactured in the first embodiment of the present invention.

[0053] The description of each reference numeral is as follows:

[0054] 1. Base copper, 2. Insulating layer, 3. First electrode layer, 4. First insulating dielectric layer, 5. First mask, 6. Metal seed layer, 7. Second electrode layer, 8. Second mask, 9. Connecting layer, 10. Single-sided board, 11. Glue layer, 12. Protective film, 13. Third mask, 14. Second insulating dielectric layer, 15. Fourth mask, 16. Third electrode layer, 91. Interlayer via hole, 101. Copper-plated hole, 121. Protective film PI layer, 122. Protective film glue layer. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0056] Embodiment 1

[0057] This embodiment provides a method for manufacturing a thin embedded capacitance circuit board with high capacitance. Figure 1 As shown, including:

[0058] S1: providing a flexible substrate, and manufacturing a first electrode layer on a first side of the flexible substrate;

[0059] S2: forming a first insulating dielectric layer on a side of the first electrode layer away from the first flexible substrate by a physical deposition method or a chemical deposition method;

[0060] S3: forming a second electrode layer on a side of the first insulating dielectric layer away from the first electrode layer by a vacuum sputtering method to obtain an initial buried capacitance circuit board; wherein a projection of the second electrode layer on the first insulating dielectric layer overlaps with a projection of the first electrode layer on the first insulating dielectric layer;

[0061] S4: performing external surface treatment on the initial embedded capacitance circuit board to obtain a target embedded capacitance circuit board.

[0062] In this embodiment, a first electrode layer is made of a flexible substrate, a second electrode layer is formed by vacuum sputtering, and a first insulating dielectric layer is formed between the first electrode layer and the second electrode layer by physical deposition or chemical deposition. A first electrode layer, a second electrode layer and a first insulating dielectric layer with a large paving area and a thin thickness can be formed respectively; wherein the projection of the second electrode layer on the first insulating dielectric layer overlaps with the projection of the first electrode layer on the first insulating dielectric layer, which means that the first electrode layer and the second electrode layer are completely or partially opposite to each other, and then based on the first insulating dielectric layer between the two (i.e., the first electrode layer and the second electrode layer), an initial buried capacitance circuit board with a large capacitance per unit area and a thin thickness can be formed. Finally, through the external surface treatment of the initial buried capacitance circuit board, the target buried capacitance circuit board can simultaneously meet the requirements of high capacitance and low thickness capacitor products.

[0063] The following describes in detail each step of the manufacturing method of this embodiment.

[0064] In the present embodiment S1, the flexible substrate is any one of a single-sided board, a double-sided board or a multi-layer board.

[0065] For a single-sided board, it has a layer of base copper and an insulating layer, and the material of the insulating layer can be PI (i.e., polyimide), PET (i.e., polyethylene terephthalate), PEN (i.e., polyethylene naphthalate), etc. For the single-sided board, the first electrode layer is made on the side of the single-sided board having the base copper.

[0066] For a double-sided board, it has two layers of substrate copper and an insulating layer, the insulating layer is located between the two layers of substrate copper, and the material of the insulating layer is the same as that of a single-sided board. For the double-sided board, a first electrode layer is made on any one of the substrate coppers of the double-sided board.

[0067] For a multi-layer board, it is composed of a plurality of single-sided boards and / or double-sided boards. For the multi-sided board, a copper substrate of the outermost layer is selected to make the first electrode layer.

[0068] For the convenience of explanation, this embodiment takes a double-sided board as an example for explanation as a flexible substrate. The cross-sectional structure of the double-sided board provided in this embodiment is as follows: Figure 2 As shown, in Figure 2 In the figure, 1 is the base copper, and 2 is the insulating layer. It should be noted that the first side of the present embodiment refers to the upper side of the double-sided board.

[0069] In the present embodiment S1, a first electrode layer is fabricated on the first side of the flexible substrate, including:

[0070] The first side of the flexible substrate is processed by sequentially adopting an exposure and development process and an etching process to form a first electrode layer on the first side of the flexible substrate.

[0071] The exposure and development process and the etching process are conventional circuit processes in the field of flexible circuit board manufacturing. By adopting the conventional circuit process, a first electrode layer that meets the design requirements can be manufactured on the first side of the flexible substrate (specifically, the upper side of the flexible substrate), and the manufacturing process is simple. The specific operation methods of the exposure and development process and the etching process are not repeated here.

[0072] The cross-sectional structure of the flexible substrate with the first electrode layer manufactured in this embodiment is as follows: Figure 3 As shown, in Figure 3 In the embodiment, the copper substrate after exposure, development and etching is the first electrode layer 3.

[0073] In an optional embodiment, S2 includes:

[0074] The first insulating medium layer is formed on a side of the first electrode layer away from the first flexible substrate by magnetron sputtering.

[0075] When there is no pattern requirement for the first insulating dielectric layer between the first electrode layer and the second electrode layer, the first insulating dielectric layer is directly formed on the side of the first electrode layer away from the first flexible substrate (specifically, the upper side of the first electrode layer) by magnetron sputtering. This can make the formed first insulating dielectric layer more uniform in thickness, have stronger bonding force with the first electrode layer and the subsequently formed second electrode layer, and simplify the manufacturing process.

[0076] The above optional embodiment directly uses magnetron sputtering to form the cross-sectional structure of the first insulating dielectric layer. Figure 4 As shown, in Figure 4 4 is the first insulating dielectric layer.

[0077] In another optional embodiment, before S2, the method further includes:

[0078] According to preset capacitor design data, a first mask is attached to a side of the first electrode layer away from the first flexible substrate.

[0079] Correspondingly, in this embodiment S2 is specifically:

[0080] S21: Based on the first mask, using a magnetron sputtering method, forming the first insulating medium layer on a side of the first electrode layer away from the first flexible substrate;

[0081] S22: After forming the first insulating dielectric layer, removing the first mask attached to the first electrode layer.

[0082] When the first insulating dielectric layer between the first electrode layer and the second electrode layer has pattern requirements, the first mask is firstly attached to the side of the first electrode layer away from the first flexible substrate (specifically the upper side of the first electrode layer) according to the preset capacitor design data (including the pattern shape, pattern size and pattern position of the first electrode layer, the second electrode layer and the first insulating dielectric layer), and then based on the attached first mask, the first insulating dielectric layer is formed on the side of the first electrode layer away from the first flexible substrate by magnetron sputtering. On the one hand, it can ensure that the first insulating dielectric layer is formed at the required position on the first electrode layer, thereby forming a capacitor that meets the design requirements; on the other hand, similar to the method of directly forming the first insulating dielectric layer by magnetron sputtering, the thickness of the formed first insulating dielectric layer can be more uniform, the bonding force between the first electrode layer and the subsequently formed second electrode layer is stronger, and the manufacturing process is simple.

[0083] The cross-sectional structure of the first mask in the above optional embodiment is as follows: Figure 5 As shown, the cross-sectional structure of the first insulating dielectric layer formed by magnetron sputtering based on the first mask is as follows Figure 6 As shown, the cross-sectional structure after removing the first mask is as follows Figure 7 As shown, in Figure 5 and Figure 6 In the figure, 5 is the first mask. Figure 6 and Figure 7 In the figure, 4 is a first insulating dielectric layer.

[0084] Preferably, the first insulating dielectric layer is composed of any one of barium titanate, strontium titanate, barium strontium titanate, lead zirconate titanate, and calcium titanate, or a mixture of any of the above.

[0085] The first insulating medium layer of the above material is an insulating medium of an inorganic material, and its dielectric constant can reach more than 1000, which is convenient for forming a high-capacitance capacitor product.

[0086] Preferably, the thickness of the first insulating dielectric layer is in the range of 10 nm to 3 μm.

[0087] Furthermore, the thickness of the first insulating dielectric layer is in the range of 300 nm to 1 μm.

[0088] By using the magnetron sputtering method of this embodiment, a first insulating dielectric layer within the above-mentioned thickness range can be formed. Through the first insulating dielectric layer within the above-mentioned thickness range, good conductivity of the dielectric layer can be ensured, and it is also convenient to simultaneously form a capacitor product with high capacitance and low thickness.

[0089] In traditional technology, the insulating dielectric layer is made of polymer + high dielectric filler, and its dielectric constant is usually only about 20. In addition, the traditional process makes it impossible to make the thickness of the insulating dielectric layer of this material less than 3μm, which makes it difficult for the capacitance per unit area in traditional technology to exceed 10nF / cm. 2 In this embodiment, the first insulating medium layer is an inorganic insulating medium, and its dielectric constant can reach more than 1000, so that the capacitance per unit area of ​​the manufactured capacitor can reach 1000-2000nF / cm 2 .

[0090] Preferably, the first mask is any one of a metal cover plate, a polymer film and a photosensitive cover film.

[0091] The cover plates made of the above materials can play an on-demand shielding role on the side of the first electrode layer away from the flexible substrate (specifically the upper side of the first electrode layer), thereby conveniently ensuring that the first insulating medium layer is sputtered at the required position on the first electrode layer, and is not sputtered at the unnecessary position.

[0092] In an optional embodiment, S3 includes:

[0093] S3A1: forming a metal seed layer on a side of the first insulating dielectric layer away from the first electrode layer by a vacuum sputtering method;

[0094] S3A2: According to the preset capacitor design data, an exposure and development process and an etching process are sequentially used to perform patterning on the first metal seed layer, so that the first metal seed layer forms the second electrode layer to obtain the initial buried capacitor circuit board.

[0095] The above optional embodiment specifically forms the second electrode layer by first sputtering the metal seed layer and then patterning, that is, firstly sputtering the metal seed layer on the side of the first insulating dielectric layer away from the first electrode layer (specifically the upper side of the first insulating dielectric layer), and then patterning the sputtered metal seed layer according to the conventional circuit manufacturing method to form the second electrode layer that meets the design requirements. This method can make the formed second electrode layer more uniform in thickness, have a stronger bonding force with the first insulating dielectric layer, and be simple and efficient to manufacture.

[0096] The schematic diagram of forming the second electrode layer by the above process is as follows Figures 8A-8B As shown, in Fig. 8A In the figure, 6 is a metal seed layer. Figure 8B In the process, the metal seed layer with a pattern formed by sequentially adopting the exposure and development process and the etching process is the second electrode layer 7.

[0097] In another optional embodiment, S3 includes:

[0098] S3B1: attaching a second mask to a side of the first insulating dielectric layer away from the first electrode layer according to preset capacitor design data;

[0099] S3B2: Based on the second mask, a metal seed layer having a pattern is formed on a side of the first insulating medium layer away from the first electrode layer by a vacuum sputtering method, so that the metal seed layer having the pattern forms the second electrode layer;

[0100] S3B3: After forming the second electrode layer, removing the second mask adhered to the first insulating dielectric layer to obtain the initial buried capacitance circuit board.

[0101] The above optional embodiment specifically forms the second electrode layer by first patterning and then sputtering the metal seed layer, that is, a second mask is attached to the side of the first insulating dielectric layer away from the first electrode layer (specifically the upper side of the first insulating dielectric layer), and the second mask has the same function as the first mask, and can play a shielding role as needed, and then the second mask is used to sputter the metal seed layer on the upper part of the first insulating dielectric layer, and the formed metal seed layer has a pattern that meets the design requirements, and finally the second mask is removed, and the metal seed layer with the pattern forms the second electrode layer that meets the design requirements. This method can also make the formed second electrode layer more uniform in thickness, and the bonding force between it and the first insulating dielectric layer is stronger, and the production is simple and efficient.

[0102] The schematic diagram of forming the second electrode layer by the above process is as follows Figures 9A to 9C As shown, in Figures 9A to 9B In the figure, 8 is the second mask. Figures 9B to 9C In the process, the metal seed layer with a pattern formed is the second electrode layer 7.

[0103] Of course, in actual production, the above two methods of forming the second electrode layer can also be used in combination. By combining the two methods, it can be further ensured that the second electrode layer meets the design requirements and the manufacturing accuracy of the second electrode layer is improved. In the process of combining the two methods, the order of executing the two methods is not limited.

[0104] Preferably, when the thickness of the formed metal seed layer is less than or equal to a preset threshold, the method further comprises:

[0105] The formed metal seed layer is thickened by electroplating or chemical plating.

[0106] The metal seed layer is thickened by electroplating or chemical plating, so that the thickness of the metal seed layer reaches a required thickness, thereby forming a second electrode layer that meets the design requirements.

[0107] It should be understood that when the second electrode layer is formed by first sputtering the metal seed layer and then patterning, the thickening of the metal seed layer can be performed before patterning (i.e., before step S3A2) or after patterning (i.e., after step S3A2). In this embodiment, it is specifically performed before step S3A2, and its schematic diagram is shown in FIG. Figure 8C When the second electrode layer is formed by first patterning and then sputtering the metal seed layer, the thickening of the metal seed layer can be performed before removing the second mask (i.e., before step S3B3) or after removing the second mask (i.e., after step S3B3). In this embodiment, the thickening is performed before step S3B3, as shown in the schematic diagram. Fig.9D shown.

[0108] It should be understood that the overlapping area between the projection of the second electrode layer on the first insulating medium layer and the projection of the first electrode layer on the first insulating medium layer can be determined according to the actual capacitor design, and this embodiment does not limit this.

[0109] Preferably, in this implementation S4, before performing external surface treatment on the initial embedded capacitance circuit board, the method further comprises:

[0110] The first electrode layer and the second electrode layer are respectively led out through lines.

[0111] The first electrode layer and the second electrode layer are respectively led out to realize the connection between the first electrode layer and the second electrode layer and external devices, thereby ensuring the functionality of the final target buried capacitance circuit board.

[0112] Among them, the line lead-out of the first electrode layer can be performed after the initial buried capacitance circuit board is manufactured (that is, it can be performed after S3), or after the first electrode layer is manufactured (that is, it can be performed after S1). This embodiment specifically selects to be performed after the first electrode layer is manufactured. After the first electrode layer is manufactured, in order to facilitate the connection between the first electrode layer and the external components or the external circuit board, the line lead-out of the first electrode layer is required. At this time, for the double-sided board, the base copper on the second side of the double-sided board (specifically the lower side of the double-sided board) can be directly made into a connecting layer, and interlayer conductive holes are made on the connecting layer, and the line lead-out of the first electrode layer is realized by using the connecting layer and the interlayer conductive holes. Among them, when the base copper on the second side of the double-sided board is made into a connecting layer, based on the pattern of the first electrode layer, the base copper on the second side of the double-sided board can be processed by the exposure and development process and the etching process in sequence, so that the base copper on the second side of the double-sided board after exposure, development and etching forms a connecting layer. As for the interlayer via holes, a drilling process can be used to penetrate the connection layer and the insulating layer to form blind holes, and then the blind holes can be processed by electroplating to form interlayer via holes on the connection layer. In this embodiment, for a double-sided board, the cross-sectional structure of the flexible substrate after the connection layer and the interlayer via holes are made is as follows: Fig.10 As shown, in Fig.10 In the embodiment, the copper of the substrate on the second side of the flexible substrate after exposure, development and etching is the connection layer 9, and an interlayer conductive hole 91 is formed on the connection layer 9.

[0113] In order to lead out the first electrode layer, for a single-sided board or a multi-layer board, the first electrode layer can be directly led out with a wire. This method is a conventional line leading method and will not be shown here.

[0114] The circuit lead-out of the second electrode layer is directly carried out after the initial embedded circuit board is made. It can be achieved by laminating a single-sided board (which plays a similar role) on the upper side of the second electrode layer. Fig.10 The copper-plated holes are formed on the single-sided board (the holes are first drilled and then electroplated, and the copper-plated holes play a similar role). Fig.10 The circuit lead-out of the second electrode layer is realized based on a single-sided board and a copper-plated hole, and its schematic diagram is shown as follows: Fig.11 As shown, in Fig.11 In the figure, 10 is a single-sided board, 101 is a copper-plated hole formed on the single-sided board, and 11 is a glue layer used for laminating the single-sided board. The second electrode layer can also be directly led out by a wire, similar to the first electrode layer being led out by a wire, which is not shown here.

[0115] In the present embodiment S4, the initial embedded capacitance circuit board is subjected to external surface treatment, which specifically includes processes such as chemical cleaning and applying a protective film.

[0116] for Fig.11 The cross-sectional structure diagram of the target buried capacitance circuit board obtained after the external surface treatment is shown in FIG. Fig. 12A When the second electrode layer is led out by a wire, the cross-sectional structure of the target buried capacitance circuit board obtained after the initial buried capacitance circuit board with the circuit led out is processed on the outer surface is as shown in FIG. Fig. 12B As shown (wherein, the wire used to lead out the second electrode layer is located at the same horizontal plane as the second electrode layer, which is not shown in the figure). Fig. 12A and Fig. 12B In the figure, 12 is a protective film, 121 is a protective film PI layer on the protective film, and 122 is a protective film adhesive layer on the protective film.

[0117] It should be added that the forming of the first insulating dielectric layer in step S2 and the forming of the second electrode layer in step S3 of this embodiment can be performed alternately for multiple times to produce a capacitor circuit board with a multi-layer structure, which can further increase the capacitance per unit area. For the convenience of explanation, this embodiment is described by taking S2 and S3 as an example after S3, that is, after S3, the method further includes:

[0118] S4: forming a second insulating dielectric layer on a side of the second electrode layer away from the first insulating dielectric layer by a physical deposition method or a chemical deposition method;

[0119] S5: A third electrode layer is formed on a side of the second insulating dielectric layer away from the second electrode layer by using a vacuum sputtering method; wherein a projection of the third electrode layer on the second insulating dielectric layer overlaps with a projection of the second electrode layer on the second insulating dielectric layer, and the third electrode layer is electrically connected to the first electrode layer.

[0120] Similar to the preparation of the first insulating dielectric layer, a physical deposition or chemical deposition method (specifically, a magnetron sputtering method) is used to prepare the second insulating dielectric layer on the side of the second electrode layer away from the first insulating dielectric layer (specifically, the upper side of the second electrode layer); similar to the second electrode layer, a vacuum sputtering method is used to prepare the third electrode layer on the side of the second insulating dielectric layer away from the second electrode layer (specifically, the upper side of the second insulating dielectric layer), while ensuring that the projection of the third electrode layer on the second insulating dielectric layer overlaps with the projection of the second electrode layer on the second insulating dielectric layer, and ensuring that the first electrode layer and the third electrode layer are electrically connected, so that the facing area between the capacitor electrode layers can be further expanded on the basis of the original capacitance, thereby further expanding the capacitance.

[0121] It should be understood that only the first electrode layer and the third electrode layer are electrically connected, while the first electrode layer and the second electrode layer are separated by the first insulating medium layer, and the second electrode layer and the third electrode layer are separated by the second insulating medium layer, and both are not conductive.

[0122] In this embodiment, the specific method for forming the second insulating dielectric layer is the same as the method for forming the first insulating dielectric layer, and the specific method for forming the third electrode layer is the same as the method for forming the second electrode layer, which will not be described in detail here. After the third electrode layer is formed, the circuit of the third electrode layer is led out in the same way as the circuit of the second electrode layer, which will not be described in detail here.

[0123] In this embodiment, after the second electrode layer is formed, a schematic diagram of using a mask to form a second insulating dielectric layer is shown in FIG. Fig.13 As shown, the schematic diagram of using the mask to form the third electrode layer is as shown Fig.14 As shown. Fig.13 In the figure, 13 is a third mask, 14 is a second insulating dielectric layer; Fig.14 In the figure, 15 is a fourth mask, and 16 is a third electrode layer. Similarly, the third electrode layer 16 can be thickened according to actual needs.

[0124] Embodiment 2

[0125] This embodiment provides a thin embedded-capacitance circuit board with high capacitance, which is manufactured by using the manufacturing method of the thin embedded-capacitance circuit board with high capacitance described in the first embodiment.

[0126] The thin embedded capacitor circuit board with high capacitance manufactured in this embodiment can simultaneously meet the requirements of capacitor products with high capacitance and low thickness.

[0127] The manufacturing method of the thin buried capacitance circuit board with high capacitance in this embodiment is the same as the method steps described in the first embodiment. Therefore, for details not provided in this embodiment, please refer to the first embodiment and the second embodiment. Figure 1 to Figure 14 The specific description of this embodiment will not be repeated in detail.

[0128] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for manufacturing a thin buried capacitance circuit board with high capacitance, characterized in that: The method comprises: Providing a flexible substrate, and manufacturing a first electrode layer on a first side of the flexible substrate; Forming a first insulating dielectric layer on a side of the first electrode layer away from the first flexible substrate by a physical deposition method or a chemical deposition method; A second electrode layer is formed on a side of the first insulating dielectric layer away from the first electrode layer by vacuum sputtering to obtain an initial buried capacitance circuit board; wherein a projection of the second electrode layer on the first insulating dielectric layer overlaps with a projection of the first electrode layer on the first insulating dielectric layer; The initial embedded capacitance circuit board is subjected to external surface treatment to obtain a target embedded capacitance circuit board.

2. The method according to claim 1, characterized in that: The method using physical deposition or chemical deposition, before forming the first insulating dielectric layer on the side of the first electrode layer away from the first flexible substrate, the method further comprises: According to the preset capacitor design data, attaching a first mask to a side of the first electrode layer away from the first flexible substrate; Correspondingly, a first insulating dielectric layer is formed on the first side of the first electrode layer by a physical deposition method or a chemical deposition method, specifically: Based on the first mask, forming the first insulating medium layer on the side of the first electrode layer away from the first flexible substrate by magnetron sputtering; After forming the first insulating medium layer, the first mask attached to the first electrode layer is removed.

3. The method according to claim 2, characterized in that: The first mask is any one of a metal cover plate, a polymer film and a photosensitive cover film.

4. The method according to claim 1, characterized in that: The first insulating dielectric layer is composed of any one of barium titanate, strontium titanate, barium strontium titanate, lead zirconate titanate, and calcium titanate, or a mixture of any of the above.

5. The method according to claim 1, characterized in that: The thickness of the first insulating dielectric layer ranges from 10 nm to 3 μm.

6. The method according to claim 1, characterized in that: The thickness of the first insulating dielectric layer is in the range of 300 nm to 1 μm.

7. The manufacturing method according to claim 1, characterized in that: The method of using vacuum sputtering to form a second electrode layer on a side of the first insulating dielectric layer away from the first electrode layer to obtain an initial buried capacitance circuit board includes: forming a metal seed layer on a side of the first insulating dielectric layer away from the first electrode layer by vacuum sputtering; According to the preset capacitor design data, the exposure and development process and the etching process are sequentially adopted to perform patterning on the first metal seed layer, so that the first metal seed layer forms the second electrode layer to obtain the initial buried capacitor circuit board.

8. The manufacturing method according to claim 1, characterized in that: The method of using vacuum sputtering to form a second electrode layer on a side of the first insulating dielectric layer away from the first electrode layer to obtain an initial buried capacitance circuit board includes: According to the preset capacitor design data, attaching a second mask to a side of the first insulating medium layer away from the first electrode layer; Based on the second mask, a metal seed layer having a pattern is formed on a side of the first insulating medium layer away from the first electrode layer by a vacuum sputtering method, so that the metal seed layer having the pattern forms the second electrode layer; After forming the second electrode layer, the second mask plate attached to the first insulating medium layer is removed to obtain the initial buried capacitance circuit board.

9. The production method according to claim 7 or 8, characterized in that: When the thickness of the formed metal seed layer is less than or equal to a preset threshold, the method further includes: The formed metal seed layer is thickened by electroplating or chemical plating.

10. The manufacturing method according to claim 1, characterized in that: Before performing external surface treatment on the initial embedded capacitance circuit board, the method further comprises: The first electrode layer and the second electrode layer are respectively led out through lines.

11. The manufacturing method according to claim 1, characterized in that: After forming the second electrode layer on the side of the first insulating medium layer away from the first electrode layer by the vacuum sputtering method, the method further comprises: Forming a second insulating dielectric layer on a side of the second electrode layer away from the first insulating dielectric layer by a physical deposition method or a chemical deposition method; A third electrode layer is formed on a side of the second insulating dielectric layer away from the second electrode layer by using a vacuum sputtering method; wherein a projection of the third electrode layer on the second insulating dielectric layer overlaps with a projection of the second electrode layer on the second insulating dielectric layer, and the third electrode layer is electrically connected to the first electrode layer.

12. The manufacturing method according to claim 1, characterized in that: The flexible substrate is any one of a single-sided board, a double-sided board or a multi-layer board.

13. A thin buried capacitance circuit board with high capacitance, characterized in that: The method is produced according to any one of claims 1 to 12.

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