Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a substrate; forming a gate structure protruding out of the substrate; an ion implantation process is executed on the substrate on the two sides of the gate structure, ion implantation regions are formed in the substrate on the two sides of the gate structure, and implanted ions of the ion implantation process comprise carbon ions; and after executing the ion implantation process, executing a source-drain implantation process on the ion implantation region, and forming a source-drain doped region in the ion implantation region. According to the technical scheme in the embodiment of the invention, the product yield and performance of the formed semiconductor structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Flash memory, also known as flash memory, has become the mainstream of non-volatile memory (NVM). According to different structures, flash memory can be divided into two types: NOR Flash and NAND Flash. The main feature of flash memory is that it can keep the stored information for a long time without power supply, and it has the advantages of high integration, fast access speed, easy erasure and rewriting, so it has been widely used in many fields such as microcomputers and automation control.

[0003] However, the product yield and electrical performance of semiconductor devices including flash memory still need to be improved. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which can improve the product yield and performance of the formed semiconductor structure.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, the method comprising:

[0006] providing a substrate, the substrate comprising a backing;

[0007] forming a gate structure protruding from the substrate;

[0008] Performing an ion implantation process on the substrate at both sides of the gate structure to form ion implantation regions in the substrate at both sides of the gate structure, wherein the implanted ions in the ion implantation process include carbon ions;

[0009] After the ion implantation process is performed, a source-drain implantation process is performed on the ion implantation region to form a source-drain doped region in the ion implantation region.

[0010] Optionally, the process parameters of the ion implantation process include: an implantation dose of 1E14 atoms / cm 2 To 9E15atoms / cm 2 , the implantation energy is 5KeV to 50KeV.

[0011] Optionally, the step of performing an ion implantation process on the substrate at both sides of the gate structure includes:

[0012] forming a patterned layer on the substrate, wherein the patterned layer has openings exposing the substrate at both sides of the gate structure;

[0013] Using the patterned layer as a mask, an ion implantation process is performed on the substrate to form the ion implantation regions in the substrate at both sides of the gate structure.

[0014] Optionally, before performing an ion implantation process on the substrate at both sides of the gate structure, the method for forming the semiconductor structure further comprises: forming a sidewall structure on the sidewall of the gate structure.

[0015] Optionally, the substrate includes a storage area and a peripheral area;

[0016] The gate structure on the substrate in the storage area is a first gate structure, the gate structure on the substrate in the peripheral area is a second gate structure, and the base also includes an isolation structure in the substrate in the storage area and the peripheral area;

[0017] The steps of forming the isolation structure, the first gate structure and the second gate structure include: forming a liner layer on the substrate; patterning the liner layer and a portion of the thickness of the substrate to form a first trench; filling the first trench with an isolation material layer; removing the liner layer so that the exposed substrate between adjacent isolation material layers forms a second trench; forming a first gate insulating film on the bottom of the second trench, and forming a floating gate material layer filling the second trench on the first gate insulating film; removing a portion of the thickness of the isolation material layer so that the isolation material layer forms an isolation structure; forming a gate dielectric material layer conformally covering the floating gate material layer and the isolation structure on the substrate of the storage area; forming a gate dielectric material layer conformally covering the floating gate material layer on the substrate of the storage area The invention relates to a method for manufacturing a floating gate material layer and an inter-gate dielectric layer of an isolation structure on both sides of the floating gate material layer; removing the first gate insulating film and the floating gate material layer on the substrate in the peripheral area, and retaining only the first gate insulating film and the floating gate material layer on the substrate in the storage area as the first gate insulating layer and the floating gate layer, respectively; forming a second gate insulating film covering the substrate and the isolation structure in the peripheral area; forming a control gate material layer covering the second gate insulating film and the inter-gate dielectric material layer; patterning the control gate material layer, the second gate insulating film and the inter-gate dielectric material layer, forming an inter-gate dielectric layer on the substrate in the storage area, a first control gate layer located on the inter-gate dielectric layer and crossing the floating gate layer, and forming a second gate insulating layer and a second control gate layer located on the second gate insulating layer on the substrate in the peripheral area.

[0018] Accordingly, an embodiment of the present invention further provides a semiconductor structure, including:

[0019] a substrate, the substrate comprising a backing;

[0020] A gate structure protruding from the substrate;

[0021] An ion implantation region is located in the substrate on both sides of the gate structure, and the implanted ions in the ion implantation region include carbon ions;

[0022] The source-drain doping region is located in the ion implantation region.

[0023] Optionally, the carbon ion implantation dose in the ion implantation region is 1E14 atoms / cm 2 To 9E15atoms / cm 2 .

[0024] Optionally, the semiconductor structure further includes: a sidewall structure located on a sidewall of the gate structure.

[0025] Optionally, the sidewall structure is an ONO structure.

[0026] Optionally, the substrate includes a storage area and a peripheral area;

[0027] The gate structure on the substrate in the storage area is a first gate structure, the gate structure on the substrate in the peripheral area is a second gate structure, and the base also includes an isolation structure in the substrate in the storage area and the peripheral area;

[0028] The first gate structure includes a first gate insulating layer, a floating gate layer located on the first gate insulating layer, an intergate dielectric layer located on the floating gate layer, and a first control gate layer located on the intergate dielectric layer. The second gate structure includes a second gate insulating layer and a second control gate layer located on the second gate insulating layer.

[0029] Optionally, the material of the first gate insulating layer and the second gate insulating layer includes silicon oxide.

[0030] Optionally, the material of the floating gate layer includes polysilicon.

[0031] Optionally, the inter-gate dielectric layer is an ONO structure.

[0032] Optionally, the material of the first control gate layer and the second control gate layer is polysilicon.

[0033] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0034] The method for forming a semiconductor structure provided by an embodiment of the present invention first performs an ion implantation process on the substrate on both sides of the gate structure to form ion implantation regions in the substrate on both sides of the gate structure, and then performs a source-drain implantation process on the ion implantation regions to form source-drain doped regions in the ion implantation regions on both sides of the gate structure. The ion implantation regions include carbon ions, which can prevent the aggregation of defect points formed in the source-drain doped regions during the source-drain implantation process, and can reduce the stress of the substrate in the ion implantation regions, thereby avoiding the generation of leakage between the source region and the drain region formed subsequently, thereby avoiding the generation of lattice dislocation, which correspondingly helps to improve the product yield and performance of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figures 1 to 17 A schematic diagram of an intermediate structure formed by each step of a method for forming a semiconductor structure provided by an embodiment of the present invention is shown;

[0036] Fig.18 A schematic diagram showing a performance comparison between a semiconductor structure formed by a method for forming a semiconductor structure provided by an embodiment of the present invention and a semiconductor structure formed by a conventional process is shown. DETAILED DESCRIPTION

[0037] As can be seen from the background technology, the product yield and performance of existing semiconductor structures still need to be improved.

[0038] In order to solve the above-mentioned technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a base, wherein the base comprises a substrate; forming a gate structure protruding from the substrate; performing an ion implantation process on the substrate on both sides of the gate structure to form ion implantation regions in the substrate on both sides of the gate structure, wherein the implanted ions of the ion implantation process comprise carbon ions; after performing the ion implantation process, performing a source-drain implantation process on the ion implantation region to form a source-drain doped region in the ion implantation region.

[0039] The method for forming a semiconductor structure provided by an embodiment of the present invention first performs an ion implantation process on the substrate on both sides of the gate structure to form ion implantation regions in the substrate on both sides of the gate structure, and then performs a source-drain implantation process on the ion implantation regions to form source-drain doped regions in the ion implantation regions on both sides of the gate structure. The ion implantation regions include carbon ions, which can prevent the aggregation of defect points formed in the source-drain doped regions during the source-drain implantation process, and can reduce the stress of the substrate in the ion implantation regions, thereby avoiding the generation of leakage between the source region and the drain region formed subsequently, thereby avoiding the generation of lattice dislocation, which correspondingly helps to improve the product yield and performance of the formed semiconductor structure.

[0040] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 1 to 17 A schematic diagram of an intermediate structure formed by each step of a method for forming a semiconductor structure provided by an embodiment of the present invention is shown.

[0042] See also Figure 1 , a base (not shown) is provided, wherein the base includes a substrate 100 .

[0043] The substrate 100 provides a process platform for the subsequent formation of a flash memory. In this embodiment, the substrate 100 is used to provide a process platform for the subsequent formation of a NOR Flash device.

[0044] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. In some other embodiments, the substrate may also include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, the first semiconductor layer is used to provide a process basis for the subsequent formation of the substrate, and the second semiconductor layer is used to provide a process basis for the subsequent formation of the fin. In other embodiments, the substrate may also include other functional layers to be etched, and the target pattern is formed by etching the functional layers to be etched.

[0045] In this embodiment, the substrate 100 includes a storage region I and a peripheral region II. Specifically, the storage region I and the peripheral region II are adjacent to or isolated from each other.

[0046] Combined with reference Figures 2 to 12 , forming a gate structure 200 protruding from the substrate 100 .

[0047] In this embodiment, the substrate 100 includes a storage region I and a peripheral region II. Accordingly, the gate structure 200 of the substrate 100 protruding from the storage region I is a first gate structure 210 , and the gate structure 200 of the substrate 100 protruding from the peripheral region II is a second gate structure 220 .

[0048] The first gate structure 210 is used as a storage gate structure. Specifically, the first gate structure 210 includes a first gate insulating layer 211 , a floating gate layer 212 on the first gate insulating layer 211 , an inter-gate dielectric layer 213 on the floating gate layer 212 , and a first control gate layer 214 on the inter-gate dielectric layer 213 .

[0049] The first gate insulating layer 211 serves as a tunnel oxide (TO) layer of the NOR flash memory device, and is used to achieve electrical isolation between the substrate 100 and the floating gate layer 212, thereby preventing electrons from entering the substrate 100 and further reducing the loss of electrons. That is, the first gate insulating layer 211 is used to prevent the data stored in the NOR flash memory device from being lost.

[0050] In this embodiment, the material of the first gate insulating layer 211 is silicon oxide. In other embodiments, the first gate insulating layer can also be made of other suitable materials.

[0051] The floating gate layer 212 is used to store electrons during the operation of the NOR flash memory device.

[0052] In this embodiment, the floating gate layer 212 is made of polysilicon.

[0053] The inter-gate dielectric layer 213 is used as an insulating layer between the floating gate layer 212 and the first control gate layer 214 , and is used to achieve electrical isolation between the floating gate layer 212 and the first control gate layer 214 .

[0054] In this embodiment, the inter-gate dielectric layer 213 is a stacked structure. Specifically, the inter-gate dielectric layer 213 is an oxide layer-nitride layer-oxide layer (Oxide-Nitride-Oxide, ONO) structure. The oxide layer is a silicon oxide layer, and the nitride layer is a silicon nitride layer. In other embodiments, the inter-gate dielectric layer can also be a single-layer structure.

[0055] The first control gate layer 214 is used as a part of a word line of a NOR flash memory device.

[0056] In this embodiment, the material of the first control gate layer 214 is the same as that of the floating gate layer 212 , that is, the material of the first control gate layer 214 is polysilicon.

[0057] The second gate structure 220 is used to form a logic gate structure on the substrate 100 in the peripheral region II.

[0058] The second gate structure 220 includes a second gate insulating layer 221 and a second control gate layer 224 located on the second gate insulating layer 221 .

[0059] The second gate insulating layer 221 is used to achieve electrical isolation between the second control gate layer 214 and the substrate 100 .

[0060] In this embodiment, the material of the second gate insulating layer 221 is the same as that of the first gate insulating layer 211 , that is, the material of the second gate insulating layer 221 is silicon oxide.

[0061] In this embodiment, the material of the second control gate layer 224 is the same as that of the first control gate layer 214 , that is, the material of the second control gate layer 224 is polysilicon.

[0062] In this embodiment, the base further includes an isolation structure 105 located in the substrate 100 of the storage area I and the peripheral area II.

[0063] The isolation structure 105 is used to achieve electrical isolation between the storage areas I and between the storage area I and the peripheral area II.

[0064] In this embodiment, the isolation structure 105 is a shallow trench isolation (STI) structure. Specifically, the material of the isolation structure 105 is silicon oxide. In other embodiments, the material of the isolation structure can also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0065] In this embodiment, the isolation structure 105, the first gate structure 210 and the second gate structure 220 are formed in the same process step to simplify the process steps and save process costs. Figures 2 to 11 .

[0066] See also Figure 2 , a liner layer 250 is formed on the substrate 100 .

[0067] In this embodiment, the pad layer 250 includes a first sub-pad layer 250 a and a second sub-pad layer 250 b located on the first sub-pad layer 250 a .

[0068] The first sub-pad layer 250 a is used to protect the active region formed in the substrate 100 during the subsequent removal of the second sub-pad layer 250 b , so that the active region formed in the substrate 100 is protected from chemical contamination.

[0069] In this embodiment, the material of the first subpad layer 250 a includes silicon oxide.

[0070] In this embodiment, the first sub-pad layer 250a is formed by a thermal oxidation process. In other embodiments, the first sub-pad layer can be formed by at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process.

[0071] The thickness of the first sub-pad layer 250a can be set according to actual needs. As an example, the thickness of the first sub-pad layer 250a is 50 angstroms to 200 angstroms.

[0072] The second sub-pad layer 250 b is used to protect the active area formed in the substrate 100 in the subsequent process of forming the isolation structure 105 in the substrate 100 , and is also used as an etching hard mask for forming the first trench.

[0073] In this embodiment, the material of the second subpad layer 250 b includes silicon nitride.

[0074] In this embodiment, the second sub-pad layer 250b is formed by a low pressure chemical vapor deposition process. In other embodiments, the second sub-pad layer can be formed by at least one of a chemical vapor deposition process, a physical vapor deposition process and an atomic layer deposition process.

[0075] The thickness of the second sub-pad layer 250b can be set according to actual needs. As an example, the thickness of the second sub-pad layer 250b is 600 angstroms to 1500 angstroms.

[0076] See also Figure 3 , patterning the liner layer 250 and a partial thickness of the substrate 100 to form a first trench 252 .

[0077] The first trench 252 is used to provide a foundation for subsequently forming an isolation material layer therein, and is also used to define the location of an active area (Active Area, AA).

[0078] In this embodiment, the liner layer 250 and a portion of the thickness of the substrate 100 are patterned by a dry etching process to form a first trench 252. The dry etching process has the characteristic of anisotropic etching, so by selecting the dry etching process, the etching is more directional, which is beneficial to improving the dimensional accuracy of the formed first trench 252, and further to improving the dimensional accuracy of the isolation material layer subsequently formed in the first trench 252.

[0079] Specifically, the step of patterning the liner layer 250 and a portion of the thickness of the substrate 100 to form the first groove 252 includes: forming an anti-reflection layer (not shown) on the liner layer 250; forming a patterned photoresist layer (not shown) on the anti-reflection layer; using the patterned photoresist layer as a mask to sequentially etch the anti-reflection layer, the liner layer 250 and a portion of the thickness of the substrate 100 to form the first groove 252; after forming the first groove 252, removing the remaining photoresist layer and anti-reflection layer. The anti-reflection layer is a dielectric anti-reflection layer (DARC).

[0080] In other embodiments, the grooves may be formed by a wet etching process or a dry etching process combined with a wet etching process. Those skilled in the art may make a selection according to actual needs, and no limitation is made here.

[0081] See also Figure 4 , filling the first trench 252 with an isolation material layer 105 a .

[0082] An isolation material layer 105 a is filled in the first trench 252 to prepare for the subsequent formation of an isolation structure.

[0083] In this embodiment, the step of forming the isolation material layer 105a includes: forming an initial isolation material layer (not shown) on the liner layer 250, and the initial isolation material layer also fills the first groove 252; flattening the initial isolation material layer until the top surface of the liner layer 250 is exposed to form the isolation material layer 105a.

[0084] In this embodiment, the process for forming the initial isolation material layer is a high-density plasma chemical vapor deposition process. In other embodiments, other deposition processes can also be used to form the initial isolation material layer, such as a physical vapor deposition process, an atomic layer deposition process, or a furnace process.

[0085] In this embodiment, the process for planarizing the initial isolation material layer is a chemical mechanical polishing (CMP) process. In other embodiments, the initial isolation material layer can also be planarized using an etch-back process.

[0086] See also Figure 5 , remove the liner layer 250, so that the exposed substrate 100 between adjacent isolation material layers 105a and adjacent isolation material layers 105a forms a second trench (not marked); form a first gate insulating film 211a on the bottom of the second trench, and form a floating gate material layer 212a filling the second trench on the first gate insulating film 211a.

[0087] The second trench is used to provide a space for subsequently forming a first gate insulating film 211 a and a floating gate material layer 212 a therein.

[0088] The liner layer 250 is removed by a wet etching process, so that the exposed substrate 100 between adjacent isolation material layers 105 a and adjacent isolation material layers 105 a forms a second trench.

[0089] The wet etching process has the characteristic of isotropic etching, which is beneficial to cleanly remove the liner layer 250. Moreover, the cost of the wet etching process is relatively low, the operation steps are simple, and a larger etching selectivity ratio can be achieved, which is beneficial to reduce damage to other film layers during the removal of the liner layer 250.

[0090] In other embodiments, the second trench may be formed by using a dry etching process or a dry etching process combined with a wet etching process.

[0091] The first gate insulating film 211 a provides a basis for subsequently forming a first gate insulating layer on the substrate 100 in the storage region I.

[0092] In this embodiment, the material of the first gate insulating film 211a is silicon oxide. In other embodiments, the material of the first gate insulating film 211a can also be a dielectric material such as silicon nitride, silicon carbide, or silicon carbonitride.

[0093] In this embodiment, the process of forming the first gate insulating film 211 a is a chemical vapor deposition process.

[0094] The floating gate material layer 212a provides a basis for the subsequent formation of a floating gate layer.

[0095] In this embodiment, the step of forming the floating gate material layer 212a includes: forming an initial floating gate material layer (not shown) covering the isolation material layer 105a and the substrate 100 exposed by the isolation material layer 105a, the initial floating gate material layer also filling the second groove; planarizing the initial floating gate material layer until the top surface of the isolation material layer 105a is exposed, so that the initial floating gate material layer forms the floating gate material layer 212a.

[0096] The formation process of the initial floating gate material layer includes at least one of a chemical vapor deposition process, a physical vapor deposition process, an atomic layer substrate process, and the like.

[0097] In this embodiment, the process for planarizing the initial floating gate material layer is a chemical mechanical polishing process.

[0098] See also Figure 6 , removing a portion of the thickness of the isolation material layer 105 a so that the isolation material layer 105 a forms an isolation structure 105 .

[0099] In this embodiment, an etch-back process is used to remove the isolation material layer 105 a protruding above the surface of the substrate 100 , and the top surface of the isolation material layer 105 a is flush with the top surface of the substrate 100 , thereby forming an isolation structure 105 .

[0100] In other embodiments, other suitable processes may be used to remove the isolation material layer protruding above the substrate surface.

[0101] See also Figure 7 , a gate dielectric material layer 213a is formed on the substrate 100 of the storage area I to conformally cover the floating gate material layer 212a and the isolation structure 105.

[0102] In this embodiment, an inter-gate dielectric material layer 213 a conformally covering the floating gate material layer 212 a and the isolation structure 105 is formed on the substrate 100 of the storage area I by an atomic layer deposition process.

[0103] The atomic layer deposition process has good step coverage capability, which is beneficial to improving the conformal coverage of the inter-gate dielectric material layer 213a on the top and sidewalls of the floating gate material layer 212a and the top of the isolation structure 105. The use of the atomic layer deposition process is also beneficial to accurately control the thickness of the formed inter-gate dielectric material layer 213a, thereby achieving accurate control of the thickness of the subsequently formed inter-gate dielectric layer.

[0104] See also Figure 8 After forming the inter-gate dielectric material layer 213a, the first gate insulating film 211a and the floating gate material layer 212a on the substrate 100 located in the peripheral area II are removed, and only the first gate insulating film 211a and the floating gate material layer 212a on the substrate 100 located in the storage area I are retained as the first gate insulating layer 211 and the floating gate layer 212, respectively.

[0105] In this embodiment, a wet etching process is used to remove the first gate insulating film 211 a and the floating gate material layer 212 a on the substrate 100 located in the peripheral region II.

[0106] In other embodiments, other suitable processes such as an etch-back process may be used to remove the first gate insulating film and the floating gate material layer on the substrate in the peripheral region.

[0107] See also Fig. 9 After removing the first gate insulating film 211a and the floating gate material layer 212a on the substrate 100 in the peripheral region II, a second gate insulating film 221a is formed covering the substrate 100 and the isolation structure 105 in the peripheral region II.

[0108] The second gate insulating film 221 a is used for subsequent patterning to form a second gate insulating layer on the substrate 100 in the peripheral region II.

[0109] In this embodiment, the material of the second gate insulating film 221a is the same as that of the first gate insulating film 211a. Specifically, the material of the second gate insulating film 221a is silicon oxide.

[0110] In this embodiment, the second gate insulating film 221a is formed by an atomic layer deposition process. In other embodiments, the process for forming the second gate insulating film can also be at least one of a thermal oxidation process, a chemical vapor deposition process, a physical vapor deposition process or a furnace process.

[0111] See also Fig.10 , forming a control gate material layer 214a covering the second gate insulating film 221a and the inter-gate dielectric material layer 213a.

[0112] The control gate material layer 214a is used for subsequent patterning to form a first control gate layer 214 on the inter-gate dielectric layer 213 on the substrate 100 in the storage area I and a second control gate layer 224 on the substrate 100 in the peripheral area II.

[0113] The process of forming the control gate material layer 214a includes at least one of an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process and a furnace process. In this embodiment, the control gate material layer 214a is formed by a chemical vapor deposition process.

[0114] See also Fig.11 , Fig.11 (b) is related to Fig.10 (b) A cross-sectional view in a perpendicular direction, wherein a control gate material layer 214a, a second gate insulating film 221a and the inter-gate dielectric material layer 213a are patterned, an inter-gate dielectric layer 213a and a first control gate layer 214 located on the inter-gate dielectric layer 213a and spanning the floating gate layer 212 are formed on the substrate 100 in the storage area I, and a second gate insulating layer 221 and a second control gate layer 224 located on the second gate insulating layer 221 are formed on the substrate 100 in the peripheral area II.

[0115] In this embodiment, the step of patterning the control gate material layer 214a, the second gate insulating film 221a and the inter-gate dielectric material layer 213a includes: forming a first patterned layer (not shown) on the control gate material layer 214a, the first patterned layer having a plurality of first openings, the bottom of the first openings exposing a portion of the control gate material layer 214a; sequentially etching the control gate material layer 214a, the second gate insulating film 221a and the inter-gate dielectric material layer 213a using the first patterned layer as a mask, forming an inter-gate dielectric layer 213a and a first control gate layer 214 located on the inter-gate dielectric layer 213a and spanning the floating gate layer 212 on the substrate 100 of the storage area I, and forming a second gate insulating layer 221 and a second control gate layer 224 located on the second gate insulating layer 221 on the substrate 100 of the peripheral area II; after forming the first control gate layer 214, the second control gate layer 224 and the second gate insulating layer 221, removing the remaining first patterned layer.

[0116] In this embodiment, the first patterned layer is a photoresist layer. Accordingly, the process of forming the first patterned layer on the control gate material layer 214a includes a spin coating process.

[0117] In this embodiment, the first patterned layer is a photoresist layer. Accordingly, an ashing process or a wet resist stripping process can be used to remove the remaining first patterned layer.

[0118] See also Fig.12After forming the gate structure 200 , the method for forming the semiconductor structure further includes: forming a spacer structure 260 on the sidewall of the gate structure 200 .

[0119] The spacer structure 260 is used to protect the sidewall of the gate structure 200 , and is also used to define the area and position of subsequent ion implantation processes and source / drain doping processes.

[0120] In this embodiment, the gate structure 200 includes a first gate structure 210 protruding from the substrate 100 in the storage area I and a second gate structure 220 protruding from the substrate 100 in the peripheral area II. Accordingly, the spacer structure 260 is located on the sidewalls of the first gate structure 210 and the second gate structure 220, respectively.

[0121] In this embodiment, the sidewall structure 260 is a stacked structure. Specifically, the sidewall structure 260 is an ONO structure.

[0122] In other embodiments, the spacer structure can also be a single-layer structure. Accordingly, the material of the spacer structure can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

[0123] Specifically, the step of forming the sidewall structure 260 includes: forming a dielectric material layer (not shown) that conformally covers the top and sidewalls of the gate structure 200 and the substrate 100; using a maskless etching process to etch away the dielectric material layer located on the top of the gate structure 200 and the substrate 100, and retaining the dielectric material layer located on the sidewalls of the gate structure 200 as the sidewall structure 260.

[0124] See also Fig.13 An ion implantation process is performed on the substrate 100 at both sides of the gate structure 200 to form ion implantation regions 110 in the substrate 100 at both sides of the gate structure 200 , wherein the implanted ions in the ion implantation regions 110 include carbon ions.

[0125] The implanted ions in the ion implantation area 110 include carbon ions. During the source-drain implantation process, the carbon ions in the ion implantation area 110 can prevent the aggregation of defect points formed in the subsequently formed source-drain doping area, and make the stress of the formed ion implantation area 110 smaller, which can avoid the breakage of the ion implantation area 110 caused by the source-drain implantation process, thereby avoiding the leakage between the subsequently formed source area and drain area, and further avoiding the occurrence of lattice dislocation, which correspondingly helps to improve the product yield and performance of the formed semiconductor structure.

[0126] It should be noted that the carbon ion implantation dose should not be too large or too small. If the carbon ion implantation dose is too large, it is easy to cause the carbon ion concentration in the formed ion implantation area 110 to be too large, which will cause the local electrical characteristics of the ion implantation area 110 to change, resulting in the electrical performance of the formed semiconductor structure to deteriorate, and will also cause excessive wear and tear of the machine equipment; if the carbon ion concentration is too small, it is easy to cause the carbon ion concentration in the ion implantation area 110 to be too small, which will correspondingly lead to poor formation quality of the ion implantation area 110, which is not conducive to suppressing the aggregation of defect points formed in the subsequently formed source and drain doping areas, and is not conducive to reducing the stress of the substrate 100 in the ion implantation area 110, so it is less helpful to improve the performance of the formed semiconductor structure. For this reason, in this embodiment, the carbon ion implantation dose is 1E14atoms / cm 2 To 9E15 atoms / cm 2 .

[0127] It should be noted that the carbon ion injection energy should not be too large or too small. If the carbon ion injection energy is too large, more defects will be generated in the ion injection area 110, causing secondary damage; if the carbon ion injection energy is too small, it will not be conducive to improving the electrical properties of the semiconductor structure. For this reason, in this embodiment, the carbon ion injection energy is 5KeV to 50KeV.

[0128] In this embodiment, the step of forming the ion implantation area 110 includes: forming a second patterned layer covering the gate structure 200 on the substrate 100, the second patterned layer having a second opening exposing the substrate 100 on both sides of the gate structure 200; using the second patterned layer as a mask, performing an ion implantation process on the substrate 100 on both sides of the gate structure 200 to form the ion implantation area 110 in the substrate 100 on both sides of the gate structure 200; after the ion implantation area 110 is formed, removing the second patterned layer.

[0129] In this embodiment, the gate structure 200 of the substrate 100 protruding from the storage area I is a first gate structure 210, and the gate structure 200 of the substrate 100 protruding from the peripheral area II is a second gate structure 220. Accordingly, ion implantation areas 110 are formed in the substrate 100 on both sides of the first gate structure 210 and in the substrate 100 on both sides of the second gate structure 220, respectively.

[0130] See also Fig.14 After the ion implantation region 110 is formed, source-drain doped regions 115 are formed in the ion implantation region 110 on both sides of the gate structure 200 .

[0131] The source-drain doped region 115 is used to subsequently form a source region and a drain region located on both sides of the gate structure 200 .

[0132] In this embodiment, the gate structure 200 protruding from the substrate 100 of the storage area I is a first gate structure 210, and the gate structure 200 protruding from the substrate 100 of the peripheral area II is a second gate structure 220. Accordingly, source-drain doped regions 115 are formed in the substrate 100 on both sides of the first gate structure 210 and in the substrate 100 on both sides of the second gate structure 220, respectively.

[0133] In this embodiment, the source-drain doping region 115 is located in the ion implantation region 110 . In other words, the coverage area of ​​the ion implantation region 110 is greater than or equal to the coverage area of ​​the source-drain doping region 115 .

[0134] The source-drain doping region 115 is formed in the ion implantation region 110, so that the ion implantation region 110 can effectively suppress the aggregation of defect points formed during the source-drain implantation process, and the stress of the ion implantation region 110 is relatively small, which can reduce the risk of fracture of the ion implantation region 110 during the source-drain implantation process, thereby avoiding the generation of leakage between the source region and the drain region formed, and further helping to avoid the generation of lattice dislocation, which correspondingly helps to improve the product yield and performance of the formed semiconductor structure.

[0135] According to the different conductivity types of the formed semiconductor structure, the doping type of the source-drain doping region 115 is different accordingly. Specifically, when the formed semiconductor structure is an NMOS device, the doping type of the source-drain doping region 115 is N-type; when the formed semiconductor structure is a PMOS device, the doping type of the source-drain doping region 115 is P-type doping ions. Among them, the doping ions used for N-type doping are phosphorus (P), arsenic (As) or antimony (Sb), and the doping ions used for P-type doping are boron (B), gallium (Ga) or indium (In).

[0136] In this embodiment, after the source-drain doping regions 115 are formed, a step of removing the remaining second patterned layer is also included.

[0137] In this embodiment, the second patterned layer is a photoresist layer, and accordingly, an ashing process is used to remove the remaining second patterned layer. In other embodiments, the process for removing the remaining second patterned layer can also be a wet stripping process, etc.

[0138] In this embodiment, after forming the source-drain doping region 115, the method for forming the semiconductor structure further includes: annealing the source-drain doping region 115 to repair lattice damage in the source-drain doping region 115, activate the doped ions in the source-drain doping region 115, and promote further isotropic diffusion of the doped ions.

[0139] Combined with reference Fig.15In this embodiment, after the source / drain doping region 115 is annealed, the method for forming the semiconductor structure further includes: performing a metal silicide process to convert the top of the gate structure 200 into a first metal silicide layer (Salicide Layer) 270 .

[0140] In this embodiment, the gate structure 200 of the substrate 100 protruding from the storage area I is a first gate structure 210, and the gate structure 200 of the substrate 100 protruding from the peripheral area II is a second gate structure 220. After the metal silicide process, the first metal silicide layer 270 located in the storage area I is used as a word line of the NOR flash memory device.

[0141] Among them, the first metal silicide layer 270 is used to reduce the gate resistance of the NOR flash memory device, thereby improving the programming operation capability and efficiency of the NOR flash memory device, improving the repeated read and write capability of the NOR flash memory device, and improving the resistance capacitance (RC) delay, thereby improving the performance of the NOR flash memory device.

[0142] In this embodiment, during the process of converting the top of the gate structure 200 into the first metal silicide layer 270 , a second metal silicide layer (not shown) is also formed on the source / drain doped regions 115 on both sides of the gate structure 200 .

[0143] The second metal silicide layer can improve the adhesion between the subsequently formed source-drain plug and the source-drain doped region 115 , and reduce the contact resistance between the subsequently formed source-drain plug and the source-drain doped region 115 .

[0144] In this embodiment, the steps of forming the first metal silicide layer 270 and the second metal silicide layer include: forming a barrier layer (not shown) between adjacent gate structures 200, wherein the barrier layer exposes the top of the gate structure 200 and the source-drain doped regions 115 on both sides of the gate structure 200; forming a metal layer (not shown) on the barrier layer to cover the exposed top of the gate structure 200 and the source-drain doped regions 115 on both sides of the gate structure 200; after forming the metal layer, performing a first annealing process on the metal layer so that the metal layer and the exposed The top of the gate structure 200 and the source-drain doped regions 115 on both sides of the gate structure 200 react to form an initial metal silicide layer (not shown); after the initial metal silicide layer is formed, the unreacted remaining metal layer is removed; after the unreacted remaining metal layer is removed, a second annealing process is performed to convert the initial metal silicide layer on the top of the gate structure 200 into the first metal silicide layer 270, and convert the initial metal silicide layer on the source-drain doped regions 115 on both sides of the gate structure 200 into the second metal silicide layer.

[0145] In this embodiment, the material of the metal layer is nickel, and accordingly, the materials of the first metal silicide layer 270 and the second metal silicide layer are nickel silicon compounds. In another embodiment, the material of the metal layer is titanium, and the materials of the first metal silicide layer and the second metal silicide layer are titanium silicon compounds. In other embodiments, the material of the metal layer can also be cobalt, and the materials of the first metal silicide layer and the second metal silicide layer are cobalt silicon compounds.

[0146] Combined with reference Fig.16 In this embodiment, after forming the first metal silicide layer 270 , the method for forming the semiconductor structure further includes: forming a dielectric layer 300 covering the substrate 100 , the isolation structure 105 and the gate structure 200 .

[0147] The dielectric layer 300 is used to achieve electrical isolation between conductive structures formed therein and between the conductive structures and other electrical connection structures.

[0148] The material of the dielectric layer 300 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the material of the dielectric layer 300 is silicon oxide.

[0149] In this embodiment, the gate structure 200 of the substrate 100 protruding from the storage area I is a first gate structure 210, and the gate structure 200 of the substrate 100 protruding from the peripheral area II is a second gate structure 220. Accordingly, the dielectric layer 300 covers the first gate structure 210 and the second gate structure 220.

[0150] In this embodiment, sidewall structures 260 are respectively formed on the side walls of the first gate structure 210 of the substrate 100 protruding from the storage area I and the second gate structure 220 of the substrate 100 protruding from the peripheral area II. Accordingly, after the dielectric layer 300 is formed, the dielectric layer 300 also covers the sidewall structure 260.

[0151] In this embodiment, a chemical vapor deposition process is used to form the dielectric layer 300. In other embodiments, the dielectric layer can also be formed by a physical vapor deposition process, an atomic layer deposition process, a furnace process, or the like.

[0152] refer to Fig.17 In this embodiment, after the dielectric layer 300 is formed, the method further includes: forming a source-drain plug 310 penetrating the dielectric layer 300 at the top of the source-drain doped region 115 , wherein the source-drain plug 310 is in contact with the source-drain doped region 115 .

[0153] The source-drain plugs 310 are used to electrically lead out the source-drain doped regions 115 .

[0154] In this embodiment, the gate structure 200 of the substrate 100 protruding from the storage area I is a first gate structure 210, and the gate structure 200 of the substrate 100 protruding from the peripheral area II is a second gate structure 220. Accordingly, the source-drain plugs 310 are in contact with the source-drain doped regions 115 located on both sides of the first gate structure 210 and the second gate structure 220, respectively.

[0155] In this embodiment, the material of the source-drain plug 310 is tungsten (W). In other embodiments, the material of the source-drain plug 310 may also be cobalt (Co) or ruthenium (Ru).

[0156] In this embodiment, the steps of forming the source-drain plug 310 include: forming a third patterned layer (not shown) on the dielectric layer 300, the third patterned layer having a third opening exposing the top surface of the dielectric layer 300 at the top of the source-drain doped region 115; using the third patterned layer as a mask, etching the dielectric layer 300 to form a contact hole (not shown) penetrating the dielectric layer 300 at the top of the source-drain doped region 115; after forming the contact hole, filling the contact hole with a conductive material to form the source-drain plug 310; after forming the source-drain plug 310, removing the remaining third patterned layer.

[0157] In this embodiment, the source-drain plug 310 penetrates the dielectric layer 300 on the top of the source-drain doped region 115 . Accordingly, the height of the source-drain plug 310 is equivalent to the thickness of the dielectric layer 300 .

[0158] Regarding the third graphic layer, please refer to the corresponding content of the first graphic layer, which will not be repeated here.

[0159] The method for forming a semiconductor structure provided by an embodiment of the present invention first performs an ion implantation process on the substrate on both sides of the gate structure to form ion implantation regions in the substrate on both sides of the gate structure, and then performs a source-drain implantation process on the ion implantation regions to form source-drain doped regions in the ion implantation regions on both sides of the gate structure. The ion implantation regions include carbon ions, which can prevent the aggregation of defect points formed in the source-drain doped regions during the source-drain implantation process, and can reduce the stress of the substrate in the ion implantation regions, thereby avoiding the generation of leakage between the source region and the drain region formed subsequently, thereby avoiding the generation of lattice dislocation, which correspondingly helps to improve the product yield and performance of the formed semiconductor structure.

[0160] Fig.18 It shows a schematic diagram of the comparison results of CP test and common emitter current amplification factor β of bipolar transistors of the semiconductor structure formed by the semiconductor structure forming method in the embodiment of the present invention and the semiconductor structure formed by the prior art.

[0161] like Fig.18 As shown, compared with the existing process, the semiconductor structure formed by the method for forming a semiconductor structure in the embodiment of the present invention (such as Fig.18 The number of black dots in (a) is small, indicating that the product yield of the semiconductor structure formed by the method for forming the semiconductor structure in the embodiment of the present invention is significantly improved. Fig.18 (b) As shown), the semiconductor structure bipolar transistor common emitter current amplification factor β (as shown) formed by the semiconductor structure forming method in the embodiment of the present invention Fig.18 (b) This indicates that the electrical performance of the semiconductor structure formed by the method for forming a semiconductor structure in the embodiment of the present invention has been significantly improved.

[0162] It should be noted that this embodiment takes a NOR flash memory device as an example to describe the method for forming a semiconductor structure in the embodiment of the present invention. Those skilled in the art can understand that the method for forming a semiconductor structure in the embodiment of the present invention can also be used to form other types of device structures, such as a NAND flash memory device, etc., which is not limited here.

[0163] Accordingly, an embodiment of the present invention further provides a semiconductor structure.

[0164] Please continue to see Fig.17A semiconductor structure in an embodiment of the present invention may include: a substrate (not shown), the substrate including a substrate 100; a gate structure 200 protruding from the substrate 100; an ion implantation region 110 located in the substrate 100 on both sides of the gate structure 200, and the implanted ions in the ion implantation region 110 include carbon ions; and a source-drain doping region 115 located in the ion implantation region 110.

[0165] The substrate 100 is used to provide a process platform for forming a flash memory. In this embodiment, the substrate 100 is used to provide a process platform for forming a NOR Flash device.

[0166] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. In some other embodiments, the substrate may also include a first semiconductor layer and a second semiconductor layer epitaxially grown on the first semiconductor layer, the first semiconductor layer is used to provide a process basis for the subsequent formation of the substrate, and the second semiconductor layer is used to provide a process basis for the subsequent formation of the fin. In other embodiments, the substrate may also include other functional layers to be etched, and the target pattern is formed by etching the functional layers to be etched.

[0167] In this embodiment, the substrate 100 includes a storage region I and a peripheral region II. Specifically, the storage region I and the peripheral region II are adjacent to or isolated from each other.

[0168] In this embodiment, the gate structure 200 of the substrate 100 protruding from the storage area I is a first gate structure 210 , and the gate structure 200 of the substrate 100 protruding from the peripheral area II is a second gate structure 220 .

[0169] The first gate structure 210 is used as a storage gate structure. Specifically, the first gate structure 210 includes a first gate insulating layer 211 , a floating gate layer 212 on the first gate insulating layer 211 , an inter-gate dielectric layer 213 on the floating gate layer 212 , and a first control gate layer 214 on the inter-gate dielectric layer 213 .

[0170] The first gate insulating layer 211 serves as a tunnel oxide layer (TO) of the NOR flash memory device, and is used to achieve electrical isolation between the substrate 100 and the floating gate layer 212 formed on the substrate 100 in the storage area I, thereby preventing electrons from entering the substrate 100, thereby reducing the loss of electrons, that is, the first gate insulating layer 211 is used to prevent the data stored in the NOR flash memory device from being lost.

[0171] In this embodiment, the material of the first gate insulating layer 211 is silicon oxide. In other embodiments, the first gate insulating layer can also be made of other suitable materials.

[0172] The floating gate layer 212 is used to store electrons during the operation of the NOR flash memory device.

[0173] In this embodiment, the floating gate layer 212 is made of polysilicon.

[0174] The inter-gate dielectric layer 213 is used as an insulating layer between the floating gate layer 212 and the first control gate layer 214 , and is used to achieve electrical isolation between the floating gate layer 212 and the first control gate layer 214 .

[0175] In this embodiment, the inter-gate dielectric layer 213 is a stacked structure. Specifically, the inter-gate dielectric layer 213 is an oxide layer-nitride layer-oxide layer (Oxide-Nitride-Oxide, ONO) structure. The oxide layer is a silicon oxide layer, and the nitride layer is a silicon nitride layer. In other embodiments, the inter-gate dielectric layer can also be a single-layer structure.

[0176] The first control gate layer 214 is used as a part of a word line of a NOR flash memory device.

[0177] In this embodiment, the material of the first control gate layer 214 is the same as that of the floating gate layer 212 , that is, the material of the first control gate layer 214 is polysilicon.

[0178] The second gate structure 220 is used to form a logic gate structure on the substrate 100 in the peripheral region II.

[0179] The second gate structure 220 includes a second gate insulating layer 221 and a second control gate layer 224 located on the second gate insulating layer 221 .

[0180] The second gate insulating layer 221 is used to achieve electrical isolation between the second control gate layer 214 and the substrate 100 .

[0181] In this embodiment, the material of the second gate insulating layer 221 is the same as that of the first gate insulating layer 211 , that is, the material of the second gate insulating layer 221 is silicon oxide.

[0182] In this embodiment, the material of the second control gate layer 224 is the same as that of the first control gate layer 214 , that is, the material of the second control gate layer 224 is polysilicon.

[0183] In this embodiment, the base further includes an isolation structure 105 located in the substrate 100 of the storage area I and the peripheral area II.

[0184] The isolation structure 105 is used to achieve electrical isolation between the storage areas I and between the storage area I and the peripheral area II.

[0185] In this embodiment, the isolation structure 105 is a shallow trench isolation (STI) structure. Specifically, the material of the isolation structure 105 is silicon oxide. In other embodiments, the material of the isolation structure can also be other dielectric materials such as silicon nitride or silicon oxynitride.

[0186] In this embodiment, the semiconductor structure further includes: a spacer structure 260 located on the sidewall of the gate structure 200 .

[0187] The spacer structure 260 is used to protect the sidewall of the gate structure 200 and is also used to define the area and position of the ion implantation process and the source / drain doping process.

[0188] In this embodiment, the gate structure 200 includes a first gate structure 210 protruding from the substrate 100 in the storage area I and a second gate structure 220 protruding from the substrate 100 in the peripheral area II. Accordingly, the spacer structure 260 is located on the sidewalls of the first gate structure 210 and the second gate structure 220, respectively.

[0189] In this embodiment, the sidewall structure 260 is a stacked structure. Specifically, the sidewall structure 260 is an ONO structure.

[0190] In other embodiments, the spacer structure can also be a single-layer structure. Accordingly, the material of the spacer structure can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride and boron carbonitride.

[0191] The implanted ions in the ion implantation area 110 include carbon ions. During the source-drain implantation process, the carbon ions in the ion implantation area 110 can prevent the aggregation of defect points formed in the source-drain doping area, and make the stress of the formed ion implantation area 110 smaller, which can avoid the breakage of the ion implantation area 110 caused by the source-drain implantation process, thereby avoiding the leakage between the source area and the drain area formed subsequently, and further avoiding the occurrence of lattice dislocation, which correspondingly helps to improve the product yield and performance of the formed semiconductor structure.

[0192] In this embodiment, the implantation dose of carbon ions in the ion implantation region 110 is 1E14 atoms / cm 2 To 9E15atoms / cm 2 .

[0193] In this embodiment, the gate structure 200 of the substrate 100 protruding from the storage area I is a first gate structure 210, and the gate structure 200 of the substrate 100 protruding from the peripheral area II is a second gate structure 220. Accordingly, the ion implantation area 110 is respectively located in the substrate 100 on both sides of the first gate structure 210 and in the substrate 100 on both sides of the second gate structure 220.

[0194] The source-drain doped regions 115 are used as source regions and drain regions located at two sides of the gate structure 200 , respectively.

[0195] In this embodiment, the gate structure 200 protruding from the substrate 100 of the storage area I is a first gate structure 210, and the gate structure 200 protruding from the substrate 100 of the peripheral area II is a second gate structure 220. Correspondingly, the source-drain doped regions 115 are respectively located in the substrate 100 on both sides of the first gate structure 210 and in the substrate 100 on both sides of the second gate structure 220.

[0196] In this embodiment, the source-drain doping region 115 is located in the ion implantation region 110 . In other words, the coverage area of ​​the ion implantation region 110 is greater than or equal to the coverage area of ​​the source-drain doping region 115 .

[0197] The source-drain doping region 115 is formed in the ion implantation region 110, so that the ion implantation region 110 can effectively suppress the aggregation of defect points formed during the source-drain implantation process, and the stress of the ion implantation region 110 is relatively small, which can reduce the risk of fracture of the ion implantation region 110 during the source-drain implantation process, thereby avoiding the generation of leakage between the source region and the drain region formed, and further helping to avoid the generation of lattice dislocation, which correspondingly helps to improve the product yield and performance of the formed semiconductor structure.

[0198] According to the different conductivity types of the formed semiconductor structure, the doping type of the source-drain doping region 115 is different accordingly. Specifically, when the formed semiconductor structure is an NMOS device, the doping type of the source-drain doping region 115 is N-type; when the formed semiconductor structure is a PMOS device, the doping type of the source-drain doping region 115 is P-type doping ions. Among them, the doping ions of N-type doping are phosphorus (P), arsenic (As) or antimony (Sb), and the doping ions used for P-type doping are boron (B), gallium (Ga) or indium (In).

[0199] In this embodiment, the semiconductor structure further includes: a first metal silicide layer 270 located on the top of the gate structure 200 .

[0200] In this embodiment, the gate structure 200 of the substrate 100 protruding from the storage area I is a first gate structure 210 , and the gate structure 200 of the substrate 100 protruding from the peripheral area II is a second gate structure 220 .

[0201] Accordingly, the first control gate 214 and the top first metal silicide layer 270 in the storage area I are used as word lines of the NOR flash memory device.

[0202] Among them, the first metal silicide layer 270 is used to reduce the gate resistance of the NOR flash memory device, thereby improving the programming operation capability and efficiency of the NOR flash memory device, improving the repeated read and write capability of the NOR flash memory device, and improving the resistance and capacitance delay, thereby improving the performance of the NOR flash memory device.

[0203] In this embodiment, the material of the first metal silicide layer 270 is nickel silicon compound. In another embodiment, the material of the first metal silicide layer is titanium silicon compound. In other embodiments, the material of the first metal silicide layer is cobalt silicon compound.

[0204] In this embodiment, the semiconductor structure further includes: a second metal silicide layer (not shown) located on the source and drain doping regions 115 on both sides of the gate structure 200 .

[0205] The second metal silicide layer is used to improve the adhesion between the subsequently formed source-drain plug and the source-drain doped region 115 , and to reduce the contact resistance between the subsequently formed source-drain plug and the source-drain doped region 115 .

[0206] In this embodiment, the semiconductor structure further includes: a dielectric layer 300 covering the substrate 100 , the isolation structure 105 and the gate structure 200 .

[0207] The dielectric layer 300 is used to achieve electrical isolation between conductive structures formed therein and between the conductive structures and other electrical connection structures.

[0208] The material of the dielectric layer 300 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the material of the dielectric layer 300 is silicon oxide.

[0209] In this embodiment, the gate structure 200 of the substrate 100 protruding from the storage area I is a first gate structure 210, and the gate structure 200 of the substrate 100 protruding from the peripheral area II is a second gate structure 220. Accordingly, the dielectric layer 300 covers the first gate structure 210 and the second gate structure 220.

[0210] In this embodiment, sidewall structures 260 are respectively formed on the side walls of the first gate structure 210 of the substrate 100 protruding from the storage area I and the second gate structure 220 of the substrate 100 protruding from the peripheral area II. Accordingly, after the dielectric layer 300 is formed, the dielectric layer 300 also covers the sidewall structure 260.

[0211] In this embodiment, the semiconductor structure further includes: a source-drain plug 310 , which penetrates the dielectric layer 300 on the top of the source-drain doped region 115 and contacts the source-drain doped region 115 .

[0212] The source-drain plugs 310 are used to electrically lead out the source-drain doped regions 115 .

[0213] In this embodiment, the gate structure 200 of the substrate 100 protruding from the storage area I is a first gate structure 210, and the gate structure 200 of the substrate 100 protruding from the peripheral area II is a second gate structure 220. Accordingly, the source-drain plugs 310 are in contact with the source-drain doped regions 115 located on both sides of the first gate structure 210 and the second gate structure 220, respectively.

[0214] In this embodiment, the material of the source-drain plug 310 is tungsten (W). In other embodiments, the material of the source-drain plug 310 may also be cobalt (Co) or ruthenium (Ru).

[0215] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate, the substrate comprising a backing; forming a gate structure protruding from the substrate; Performing an ion implantation process on the substrate at both sides of the gate structure to form ion implantation regions in the substrate at both sides of the gate structure, wherein the implanted ions in the ion implantation process include carbon ions; After the ion implantation process is performed, a source-drain implantation process is performed on the ion implantation region to form a source-drain doped region in the ion implantation region.

2. The method for forming a semiconductor structure according to claim 1, wherein: The process parameters of the ion implantation process include: the implantation dose is 1E14atoms / cm 2 To 9E15 atoms / cm 2 , the implantation energy is 5KeV to 50KeV.

3. The method for forming a semiconductor structure according to claim 1, wherein: Before performing the ion implantation process on the substrate at both sides of the gate structure, the method further includes: forming a sidewall structure on the sidewall of the gate structure.

4. The method for forming a semiconductor structure according to claim 1, wherein: The substrate includes a storage area and a peripheral area; The gate structure on the substrate in the storage area is a first gate structure, the gate structure on the substrate in the peripheral area is a second gate structure, and the base also includes an isolation structure in the substrate in the storage area and the peripheral area; The steps of forming the isolation structure, the first gate structure and the second gate structure include: forming a liner layer on the substrate; patterning the liner layer and a portion of the thickness of the substrate to form a first trench; filling the first trench with an isolation material layer; removing the liner layer so that the exposed substrate between adjacent isolation material layers forms a second trench; forming a first gate insulating film on the bottom of the second trench, and forming a floating gate material layer filling the second trench on the first gate insulating film; removing a portion of the thickness of the isolation material layer so that the isolation material layer forms an isolation structure; forming a gate dielectric material layer conformally covering the floating gate material layer and the isolation structure on the substrate of the storage area; forming a gate dielectric material layer conformally covering the floating gate material layer on the substrate of the storage area The invention relates to a method for manufacturing a floating gate material layer and an inter-gate dielectric layer of an isolation structure on both sides of the floating gate material layer; removing the first gate insulating film and the floating gate material layer on the substrate in the peripheral area, and retaining only the first gate insulating film and the floating gate material layer on the substrate in the storage area as the first gate insulating layer and the floating gate layer, respectively; forming a second gate insulating film covering the substrate and the isolation structure in the peripheral area; forming a control gate material layer covering the second gate insulating film and the inter-gate dielectric material layer; patterning the control gate material layer, the second gate insulating film and the inter-gate dielectric material layer, forming an inter-gate dielectric layer on the substrate in the storage area, a first control gate layer located on the inter-gate dielectric layer and crossing the floating gate layer, and forming a second gate insulating layer and a second control gate layer located on the second gate insulating layer on the substrate in the peripheral area.

5. A semiconductor structure, characterized in that: include: a substrate, the substrate comprising a backing; A gate structure protruding from the substrate; An ion implantation region is located in the substrate on both sides of the gate structure, and the implanted ions in the ion implantation region include carbon ions; The source and drain doping regions are located in the ion implantation region.

6. The semiconductor structure according to claim 5, characterized in that: The carbon ion implantation dose in the ion implantation area is 1E14 atoms / cm 2 To 9E15 atoms / cm 2 .

7. The semiconductor structure according to claim 5, characterized in that: Also includes: The sidewall structure is located on the sidewall of the gate structure.

8. The semiconductor structure according to claim 7, characterized in that: The side wall structure is an ONO structure.

9. The semiconductor structure according to claim 5, characterized in that: The substrate includes a storage area and a peripheral area; The gate structure on the substrate in the storage area is a first gate structure, the gate structure on the substrate in the peripheral area is a second gate structure, and the base also includes an isolation structure in the substrate in the storage area and the peripheral area; The first gate structure includes a first gate insulating layer, a floating gate layer located on the first gate insulating layer, an intergate dielectric layer located on the floating gate layer, and a first control gate layer located on the intergate dielectric layer. The second gate structure includes a second gate insulating layer and a second control gate layer located on the second gate insulating layer.

10. The semiconductor structure according to claim 9, characterized in that: The material of the first gate insulating layer and the second gate insulating layer includes silicon oxide.

11. The semiconductor structure according to claim 9, characterized in that: The material of the floating gate layer includes polysilicon.

12. The semiconductor structure according to claim 9, characterized in that: The inter-gate dielectric layer is an ONO structure.

13. The semiconductor structure according to claim 9, characterized in that: The material of the first control gate layer and the second control gate layer is polysilicon.

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