Memristor and method for realizing binary Boolean logic based on memristor

Abstract

The memristor comprises a substrate and a resistance change unit arranged above the substrate, and the resistance change unit comprises a bottom electrode, a second resistance change layer, a middle electrode layer, a first resistance change layer and a top electrode which are sequentially arranged from bottom to top. The invention also discloses a method for realizing the binary Boolean logic based on the memristor, and the method comprises the steps: setting a logic state table which is provided with different logic codes; initializing the memristor according to the logic state table; writing the variable into the memristor according to the logic state table; according to the logic state table, the variables of the memristor are read, the variables in the memristor are changed while reading is conducted, and a logic result is obtained. According to the memristor and the method for realizing the binary Boolean logic disclosed by the invention, the preparation method is simple in operation, low in cost, easy to realize miniaturization and integration, simple in operation and simple in steps, and all 16 binary Boolean logic functions can be realized.

Description

Technical Field

[0001] The invention relates to a method for realizing binary Boolean logic based on a memristor, and belongs to the technical field of memory. Background Art

[0002] As the basic unit of neural learning, memristor is considered to be one of the most promising electronic devices for building high-density circuits and realizing neuromorphic computing, which can effectively perform parallel computing. It has the advantages of simple structure, high integration, fast operation speed, low power consumption, and can realize synaptic bionic functions. Its efficient computing power has brought changes to traditional computing systems.

[0003] However, most of the existing memristor-based logic circuits remain at the simulation level. The ideality of the simulation results makes it impossible to simulate the environment in which the device actually works. How to use physical memristors with stable performance to construct and implement circuit functions remains to be solved.

[0004] In addition, existing memristor-based logic circuits also use IMP logic gates as the basis, using resistors as logic states to implement IMP logic. In this way, the inputs and outputs stored in the memristor array perform basic Boolean functions through IMP and False operations, where the False operation is a zeroing operation, thereby implementing various logic gates of the adder and their cascade methods. However, this structure requires two sequential voltages to perform logical functions and an additional resistor in each row of the array, resulting in a complex control circuit and huge power consumption. In addition, when implementing logical functions, there is no specific memristor for output, but the output information is stored in the input memristor, which greatly limits its application.

[0005] A memristor-assisted (MAGIC) logic structure has also been proposed in the prior art. In the MAGIC logic architecture, the input and output memristors are separated, and the output results of the logic function are stored in a dedicated memristor without the need for additional resistors. However, since it uses resistors as input and output of the logic state, it is difficult to realize the cascading of gate circuits.

[0006] Therefore, there is an urgent need to provide a more convenient and simpler logic circuit implementation method to solve the problem of complex operation of existing memristor logic circuits. Summary of the invention

[0007] In order to overcome the above problems, the inventors have conducted in-depth research and designed a memristor, which is characterized by comprising a substrate 1 and a resistive switching unit arranged above the substrate 1.

[0008] The resistive switching unit 2 includes a bottom electrode 21, a second resistive switching layer 22, an intermediate electrode layer 23, a first resistive switching layer 24 and a top electrode 25 arranged in sequence from bottom to top;

[0009] The top electrode 25, the first resistive switching layer 24, and the middle electrode layer 23 constitute an upper bipolar resistive switching memory BRS1;

[0010] The middle electrode layer 23 , the second resistive switching layer 22 , and the bottom electrode 21 constitute a lower bipolar resistive switching memory BRS2 .

[0011] In a preferred embodiment, the bottom electrode 21 is partially exposed, and a signal access line T1 is arranged on it;

[0012] A signal access line T2 is disposed on the top electrode 25 .

[0013] In a preferred embodiment, a plurality of resistive switching units 2 are disposed on the substrate 1 , and the plurality of resistive switching units 2 share a bottom electrode 21 , a second resistive switching layer 22 , an intermediate electrode layer 23 and a first resistive switching layer 24 .

[0014] In a preferred embodiment, the bottom electrode 21 is ITO glass;

[0015] The second resistive layer 22 is made of GO:Au NPs;

[0016] The intermediate electrode layer 23 is made of aluminum;

[0017] The first resistive layer 24 is made of GO:Au NPs (graphene oxide: gold nanoparticles);

[0018] The top electrode 25 is made of silver.

[0019] The present invention also provides a method for manufacturing a memristor, comprising the following steps:

[0020] S1, using ITO on a glass substrate as a bottom electrode;

[0021] S2, preparing GO: Au NPs solution, and spin coating it on the bottom electrode to form the second resistive switching layer;

[0022] S3, evaporating aluminum on the second resistive layer to form a central electrode layer;

[0023] S4, spin coating the GO:Au NPs solution on the central electrode layer to form a first resistive switching layer;

[0024] S5. Evaporate silver on the first resistive layer to form a top electrode.

[0025] The present invention also provides a method for implementing binary Boolean logic based on a memristor, using one of the above-mentioned memristors, comprising the following steps:

[0026] Set a logic state table, in which different logic codes are set;

[0027] Initialize the memristor according to the logic state table;

[0028] According to the logic state table, write the variables into the memristor;

[0029] According to the logic state table, the variables of the memristor are read, and the variables in the memristor are changed at the same time to obtain the logic result.

[0030] In a preferred embodiment, the logic state table includes four variables and one output, the four variables are initial state S, T1 write state, T2 write state, read voltage state r, and each variable or output has two states;

[0031] The initial state S is used to characterize the high and low configuration states of the memristor, including the HRS / LRS state and the LRS / HRS state.

[0032] In a preferred embodiment, the memristor is initialized by connecting a voltage signal to T1 and T2 to determine the value of the initial state S.

[0033] When |V T1 -V T2 |>2|V reset |, the initial state S is the HRS / LRS state, represented by S = 1;

[0034] When |V T2 -V T1 |>2|V reset |, the initial state S is the LRS / HRS state, represented by S = 0;

[0035] Among them, V T1 is the input voltage of the signal access line T1, V T2 is the input voltage of the signal access line T2, V reset It is the sum of the reset voltages of the upper bipolar resistive memory and the lower bipolar resistive memory.

[0036] In a preferred embodiment, when writing into the memristor, by connecting T1 and / or T2 to a high level, the write state of T1 and the write state of T2 are written into the memristor.

[0037] When the voltage of the signal access line T1 is higher than 2|V reset |, the state written to T1 is 1, otherwise the state written to T1 is 0;

[0038] When the access voltage of the signal access line T2 is higher than 2|V reset |, the state written to T2 is 1, otherwise the state written to T2 is 0.

[0039] In a preferred embodiment, when reading the state of the memristor, the voltage state r is read according to the logic state table, and the access voltages of the signal access line T1 and the signal access line T2 are set. When r=1, the following is set:

[0040] 2|V reset |>|V T1 -V T2 |>|V set |

[0041] When r=0, set:

[0042] 2|V reset |>|V T2 -V T1 |>|V set

[0043] Among them, V T1 is the input voltage of the signal access line T1, V T2 is the input voltage of the signal access line T2, V set is the sum of the set voltages of the upper bipolar resistive memory and the lower bipolar resistive memory;

[0044] The logical result obtained is:

[0045]

[0046] Among them, S represents the initial state, T1 represents the T1 write state, T2 represents the T2 write state, r represents the read voltage state, and the superscript one represents the Boolean value inversion.

[0047] The beneficial effects of the present invention include:

[0048] (1) The obtained memristor has good cycling stability;

[0049] (2) The preparation method is simple to operate, low in cost, and easy to achieve miniaturization and integration;

[0050] (3) This method adopts a reconfigurable timing operation scheme and can realize all 16 binary Boolean logic functions by utilizing the characteristics of complementary resistive switch memristors;

[0051] (4) The operation is simple, the steps are concise, the cost is low, and it is easy to implement logical operations based on resistive memory, which provides a new idea for its physical implementation and is suitable for large-scale industrial applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A schematic diagram of a memristor structure according to a preferred embodiment of the present invention is shown;

[0053] Figure 2A schematic diagram of a top view structure of a memristor according to a preferred embodiment of the present invention is shown;

[0054] Figure 3 A schematic flow chart of a method for implementing binary Boolean logic based on a memristor according to a preferred embodiment of the present invention is shown;

[0055] Figure 4 shows the scans obtained in Experimental Example 1;

[0056] Figure 5 The characteristic curve obtained by performing multiple repeated scanning tests on the memristor in Example 1 is shown;

[0057] Figure 6 The distribution diagram of the memristor in Example 1 in high and low resistance states is shown;

[0058] Figure 7 The figure shows the change of the current switching ratio of the memristor in Example 1 with the voltage;

[0059] Figure 8 The resistance state change of the upper and lower bipolar resistive memory in Experimental Example 2 is shown;

[0060] Fig. 9 The resistance state change of the upper and lower bipolar resistive memory in Experimental Example 3 is shown;

[0061] Fig.10 The resistance state change of the upper and lower bipolar resistive memory in Experimental Example 4 is shown.

[0062] Description of Figure Numbers

[0063] 1- substrate;

[0064] 2-resistive switching unit;

[0065] 21- bottom electrode;

[0066] 22- a second resistive switching layer;

[0067] 23-intermediate electrode layer;

[0068] 24-a first resistive switching layer;

[0069] 25-top electrode;

[0070] BRS1-upper bipolar resistive random access memory;

[0071] BRS2-Bottom bipolar resistive random access memory. DETAILED DESCRIPTION

[0072] The present invention will be further described in detail below through the accompanying drawings and embodiments. Through these descriptions, the characteristics and advantages of the present invention will become more clear and distinct.

[0073] The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise noted.

[0074] According to a memristor provided by the present invention, Figure 1 As shown, it includes a substrate 1 and a resistive switching unit arranged above the substrate 1.

[0075] The resistive switching unit 2 includes a bottom electrode 21, a second resistive switching layer 22, an intermediate electrode layer 23, a first resistive switching layer 24 and a top electrode 25 arranged in sequence from bottom to top;

[0076] The top electrode 25, the first resistive switching layer 24, and the middle electrode layer 23 constitute an upper bipolar resistive switching memory BRS1;

[0077] The middle electrode layer 23 , the second resistive switching layer 22 , and the bottom electrode 21 constitute a lower bipolar resistive switching memory BRS2 .

[0078] According to the present invention, the upper bipolar resistive random access memory BRS1 and the lower bipolar resistive random access memory BRS2 form a structure with complementary resistive switching characteristics.

[0079] In a preferred embodiment, the bottom electrode 21 is partially exposed, and a signal access line T1 is arranged on it;

[0080] A signal access line T2 is disposed on the top electrode 25 .

[0081] In a preferred embodiment, Figure 2 As shown, a plurality of resistive switching units 2 are arranged on a substrate 1 , and the plurality of resistive switching units 2 share a bottom electrode 21 , a second resistive switching layer 22 , an intermediate electrode layer 23 and a first resistive switching layer 24 .

[0082] Furthermore, when a plurality of resistive switching units 2 are provided on the substrate 1, the plurality of resistive switching units 2 are arranged in rows and columns to form a cross array structure, and a signal access line T1 of each resistive switching unit 2 is set on a bit line, and a signal access line T2 is set on a word line. The bit line and the word line are suspended and are not connected to other resistive switching units 2.

[0083] In the present invention, a crossbar array structure is used to allow input operations to be performed on multiple devices simultaneously.

[0084] Preferably, the substrate 1 is made of semiconductor materials such as glass or silicon wafer, preferably conductive glass, which is inexpensive and has stable and reliable performance.

[0085] In a preferred embodiment,

[0086] The bottom electrode 21 is ITO glass;

[0087] The second resistive layer 22 is made of GO:Au NPs;

[0088] The intermediate electrode layer 23 is made of aluminum;

[0089] The first resistive layer 24 is made of GO:Au NPs;

[0090] The top electrode 25 is made of silver.

[0091] The resistive random access memory made of the above materials has good cycle stability. It can complete two switchings in one half axis, which can effectively solve the problem of sneak path current in unselected cells in the Crossbar array. Furthermore, the structure can produce the smallest theoretical cell size, i.e. 4F 2 / n , where F is the minimum feature size and n is the number of layers when using three-dimensional stacking, which can improve integration and performance and reduce power consumption.

[0092] In the present invention, GO: Au NPs is used as the dielectric layer material, which is easy to prepare a solution, easy to prepare a film through the solution, and easy to adjust the performance of the memristor.

[0093] In addition, the switching current ratio of the device with GO:Au NPs as the dielectric layer material is significantly improved compared with the device with only GO as the dielectric layer. The addition of Au NPs effectively increases the selection window of the device and reduces the misreading rate of the device in the application.

[0094] The present invention also provides a method for manufacturing a memristor, comprising the following steps:

[0095] S1, using ITO on a glass substrate as a bottom electrode;

[0096] S2, preparing GO: Au NPs solution, and spin coating it on the bottom electrode to form the second resistive switching layer;

[0097] S3, evaporating aluminum on the second resistive layer to form a central electrode layer;

[0098] S4, spin coating the GO:Au NPs solution on the central electrode layer to form a first resistive switching layer;

[0099] S5. Evaporate silver on the first resistive layer to form a top electrode.

[0100] In S1, the substrate is conductive glass.

[0101] Before placing the ITO glass on the substrate, the substrate and the ITO glass are cleaned.

[0102] Preferably, the cleaning is performed using a variety of solutions, and more preferably, cleaning is performed sequentially using acetone solution, ethanol solution, and deionized water solution to improve the cleaning effect.

[0103] More preferably, the cleaning time in each solution is not less than 15 minutes to improve the cleaning effect.

[0104] More preferably, ultrasound is performed during cleaning to improve the cleaning effect.

[0105] Preferably, masking is done at the ITO edge to lead out the T2 electrode.

[0106] In S2, the preparation of GO:Au NPs solution comprises the following sub-steps:

[0107] S21, preparing Au NPs solution;

[0108] S22. Configure GO:Au NPs.

[0109] S21 includes:

[0110] S211, adding chloroauric acid to deionized water and heating to boiling, preferably the mass ratio of chloroauric acid to deionized water is 1:100;

[0111] S212, adding sodium citrate aqueous solution to obtain a mixed solution;

[0112] Preferably, the mass fraction of sodium citrate in the sodium citrate aqueous solution is 1%, and the mass ratio of the sodium citrate aqueous solution to chloroauric acid is 1:1.

[0113] Preferably, stirring is continued during the process of adding the sodium citrate aqueous solution. The stirring speed is not limited and can be freely set by those skilled in the art. For example, stirring at 600 rpm can accelerate the mixing effect.

[0114] Preferably, the mixed solution is also boiled continuously, more preferably, the boiling is continued for not less than 20 minutes.

[0115] According to experience, the temperature and duration of the reaction will affect the size and yield of the prepared gold nanoparticles. As the reaction time increases, the concentration of the generated Au NPs continues to increase. Under the control of variables, samples with higher reaction temperatures will reach the concentration threshold and size threshold faster. It can be seen that the reaction temperature and time affect each other, and a higher reaction temperature is conducive to rapid preparation.

[0116] In S212, GO powder is dissolved in deionized water to obtain a GO solution, and the GO solution is mixed with the Au NPs solution to obtain a GO:Au NPs solution.

[0117] Preferably, the GO solution is a GO solution with a concentration of 0.5 wt%.

[0118] Preferably, the GO solution and the Au NPs solution are mixed in a mass ratio of 10:1.

[0119] Preferably, the ultrasonication is continued after mixing. More preferably, the ultrasonication is not less than 20 minutes.

[0120] Preferably, before mixing the GO solution with the Au NPs solution, the GO solution is also sonicated.

[0121] In S2, the obtained GO:Au NPs solution is spin-coated on the surface of the bottom electrode. Preferably, during the spin-coating process, the rotation speed of the coating machine is set at 1000 r / s and the spin-coating time is 60 s.

[0122] Preferably, after spin coating, the coating is placed in a drying oven for heating and curing. More preferably, the drying temperature is 100° C. and the curing time is not less than 10 minutes.

[0123] In S3, preferably, the vacuum degree of the evaporation is 2.0×10 -3 Pa.

[0124] Preferably, after evaporation, the film is placed in a drying oven for heating and curing. More preferably, the drying temperature is 100° C. and the curing time is not less than 10 minutes.

[0125] In S4, the GO:Au NPs solution used was the same as that in S2.

[0126] Preferably, the rotation speed of the coating machine during the spin coating process is set at 1000 r / s, and the spin coating time is 60 s.

[0127] Preferably, after spin coating, the coating is placed in a drying oven for heating and curing. More preferably, the drying temperature is 100° C. and the curing time is not less than 10 minutes.

[0128] In S5, preferably, the vacuum degree of the evaporation is 2.0×10 -3 Pa.

[0129] Preferably, after evaporation, the film is placed in a drying oven for heating and curing. More preferably, the drying temperature is 100° C. and the curing time is not less than 10 minutes.

[0130] The present invention also provides a method for realizing binary Boolean logic based on a memristor, using the above memristor, such as Figure 3 As shown, the following steps are included:

[0131] Set a logic state table, in which different logic codes are set;

[0132] Initialize the memristor according to the logic state table;

[0133] According to the logic state table, write the variables into the memristor;

[0134] According to the logic state table, the variables of the memristor are read, and the logic variables in the memristor are changed at the same time to obtain the logic result.

[0135] In a preferred embodiment, the logic state table includes four variables and one output, the four variables are initial state S, T1 write state, T2 write state, read voltage state r, each variable or output has two states, that is, Boolean values;

[0136] Among them, the initial state S is used to characterize the high and low configuration states of the memristor, including the HRS / LRS state and the LRS / HRS state. For the convenience of description, in the present invention, the HRS / LRS state is represented as S=1, and the LRS / HRS state is represented as S=0. Of course, it should be pointed out that the above representation is only for the convenience of description and is not a specific limitation.

[0137] The T1 write state and the T2 write state are respectively the high and low level signals of the signal access line T1 and the signal access line T2 during the writing process. For example, when the access signal is at a high level, the write state is 1; otherwise, the write state is 0.

[0138] The read voltage state r is the power supply level signal of the signal access line T1 and the signal access line T2 during the reading process, and during the reading process, one of the signal access line T1 and the signal access line T2 is connected to a low level signal and the other is connected to a Vr voltage signal. The voltage of the Vr voltage signal is different from that of the high level signal. Exemplarily, when the signal access line T1 is grounded and the signal access line T2 is connected to the Vr voltage signal during the reading process, the read voltage state r==0; when the signal access line T1 is connected to the Vr voltage signal and the signal access line T2 is grounded during the reading process, the read voltage state r=1.

[0139] The output is a realized Boolean logic value.

[0140] Exemplarily, the logic state table is shown in Table 1.

[0141] Table 1

[0142]

[0143]

[0144] According to the present invention, the logic state table includes four variables, each of which is a Boolean value, corresponding to 16 output values, which can respectively correspond to "AND", "OR", "XOR", "XOR", "TRUE", "FALSE", "LOGICAL p", "LOGICAL q", "LOGICAL NOT p", "LOGICAL NOT q", "NAND", "NOR", "substantial implication", "Negative substantive implication", "Anti-substantive implication" and "Anti-negative substantive implication". Through the logic state table, the setting and query of binary Boolean logic can be realized.

[0145] According to the present invention, the purpose of initializing the memristor is to set the initial state S in the memristor to a certain logic state.

[0146] In a preferred embodiment, the memristor is initialized by connecting a voltage signal to T1 and T2 to determine the value of the initial state S.

[0147] For example,

[0148] When |V T1 -V T2 |>2|V reset |, the initial state S is the HRS / LRS state, represented by S = 1;

[0149] When |V T2 -V T1 |>2|V reset |, the initial state S is the LRS / HRS state, represented by S = 0;

[0150] Among them, V T1 is the level signal input voltage of signal access line T1, V T2 is the level signal input voltage of signal access line T2, V reset It is the sum of the reset voltages of the upper bipolar resistive memory and the lower bipolar resistive memory.

[0151] According to the present invention, by applying different external voltages to the memristor, variables are written into the memristor, and the variables are T1 write state and T2 write state.

[0152] In a preferred embodiment, when writing into the memristor, by connecting T1 and / or T2 to a high level, the write state of T1 and the write state of T2 are written into the memristor.

[0153] For example,

[0154] When the voltage of the signal access line T1 is higher than 2|V reset |, the state written to T1 is 1, otherwise the state written to T1 is 0;

[0155] When the access voltage of the signal access line T2 is higher than 2|V reset|, the state written to T2 is 1, otherwise the state written to T2 is 0.

[0156] According to the present invention, the state of the memristor is read through a read operation, and the logical state of the memristor is output. Meanwhile, the read operation can also change the state of the memristor, thereby affecting the output result.

[0157] In a preferred embodiment, when reading the state of the memristor, the voltage state r is read according to the logic state table, and the access voltages of the signal access line T1 and the signal access line T2 are set.

[0158] For example,

[0159] When r=1, set:

[0160] 2|V reset |>|V T1 -V T2 |>|V set |

[0161] When r=0, set:

[0162] 2|V reset |>|V T2 -V T1 |>|V set

[0163] Among them, V T1 is the input voltage of the signal access line T1, V T2 is the input voltage of the signal access line T2, V set is the sum of the set voltages of the upper bipolar resistive memory and the lower bipolar resistive memory;

[0164] The logical result obtained is:

[0165]

[0166] The superscript - indicates the negation of a Boolean value.

[0167] According to the present invention, whether it is initialization, writing or reading of the memristor, its signal is completed by the voltage T1 and T2 applied to the two ends of the memristor. Since the combination of different variables in the logic state table corresponds to a unique output, and the state of the memristor can be changed by the reading operation, any Boolean logic can be realized by changing the state of the four variables, as shown in Table 2.

[0168] Table 2

[0169]

[0170] Example

[0171] Example 1

[0172] The operation of binary Boolean logic is realized based on memristor to realize "AND gate".

[0173] The memristor includes a substrate 1 and a resistive switching unit arranged above the substrate 1.

[0174] The resistive switching unit 2 includes a bottom electrode 21, a second resistive switching layer 22, an intermediate electrode layer 23, a first resistive switching layer 24 and a top electrode 25 arranged in sequence from bottom to top;

[0175] The top electrode 25, the first resistive switching layer 24, and the middle electrode layer 23 constitute an upper bipolar resistive switching memory BRS1;

[0176] The middle electrode layer 23 , the second resistive switching layer 22 , and the bottom electrode 21 constitute a lower bipolar resistive switching memory BRS2 .

[0177] The logical operation is performed as follows:

[0178] A logic state table is set, and different logic codes are set in the logic table. The specific logic codes are shown in Table 1; the four variables S, T1, T2, and r corresponding to the AND gate have amplitudes of p, q, 1, and 0, respectively.

[0179] Initialize the memristor according to the logic state table;

[0180] Specifically, let S=p. When p=1, T1 is connected to a high level, T2 is grounded, and the state of the memristor is set to HRS / LRS. When p=0, T1 is grounded, T2 is connected to a high level, and the state of the memristor is set to LRS / HRS.

[0181] According to the logic state table, write the variables into the memristor;

[0182] Specifically, T2 is connected to a high level, T1 = q, when q = 1, T1 is connected to a high level with an amplitude of VDD, and since T2 is also connected to a high level at this time, there is no voltage difference between the upper and lower ends, so the state of the device remains unchanged at this time, and is still p (when p = 1, it is HRS / LRS; when p = 0, it is LRS / HRS). When q = 0, since T2 is connected to a high level, a voltage from bottom to top is generated at this time, so the state of the device switches or remains at LRS / HRS.

[0183] According to the logic state table, the variables of the memristor are read, and the variables in the memristor are changed at the same time to obtain the logic result.

[0184] The logical result is:

[0185]

[0186] Specifically, r=0, T1 is grounded, and T2 is connected to a high level with an amplitude of Vr, where 2|V reset |>Vr>|V set |, if the previous state of the memristor is in LRS / HRS, the switching of the memristor cannot be completed due to the polarity of the voltage, so the state of the memristor remains unchanged and the output logic is "0";

[0187] If the device is previously in the HRS / LRS state, the device's overall state switches to LRS / LRS, and at this point, the output is logic "1".

[0188] Since the memristor can only output a low-resistance logic "1" when both p and q are logic "1", the device is in a high-resistance logic "0" state in other cases. That is, the input and output results conform to the operation of "AND" logic, realizing an "AND gate" (AND).

[0189] Example 2

[0190] The same memristor as in Example 1 is used to implement the operation of binary Boolean logic and realize an "OR gate" (OR).

[0191] The logical operation is performed as follows:

[0192] A logic state table is set, and different logic codes are set in the logic table. The specific logic codes are shown in Table 1; the four variables S, T1, T2, and r corresponding to the AND gate have amplitudes of p, q, 0, and 0, respectively.

[0193] Initialize the memristor according to the logic state table;

[0194] Specifically, let S=p. When p=1, T1 is connected to a high level, T2 is grounded, and the state of the memristor is set to HRS / LRS. When p=0, T1 is grounded, T2 is connected to a high level, and the state of the memristor is set to LRS / HRS.

[0195] According to the logic state table, write the variables into the memristor;

[0196] Specifically, T2 is grounded, that is, T2=0, T1=q. When q=1, since T2 is grounded, a voltage from top to bottom is generated at this time, so the state of the device switches or remains at HRS / LRS. When q=0, both T1 and T2 are grounded, and there is no voltage difference between the upper and lower ends. Therefore, the state of the memristor remains unchanged and is still p (when p=1, it is HRS / LRS; when p=0, it is LRS / HRS).

[0197] According to the logic state table, the variables of the memristor are read, and the variables in the memristor are changed at the same time to obtain the logic result.

[0198] The logical result is:

[0199]

[0200] Specifically, r=0, T1 is grounded, and T2 is connected to a high level with an amplitude of Vr, where 2|V reset |>Vr>|V set |, if the previous state of the memristor is in LRS / HRS, the switching of the memristor cannot be completed due to the polarity of the voltage, so the state of the memristor remains unchanged and the output logic is "0";

[0201] If the device is previously in the HRS / LRS state, the overall state of the memristor switches to LRS / LRS, and at this time, the output is logic "1".

[0202] Since the memristor can only output the high-resistance logic "0" when p and q are both logic "0", the memristor is in the logic "1" state with a lower resistance value in other cases. That is, the input and output results conform to the "OR" logic operation, realizing the "OR gate" (OR).

[0203] Example 3

[0204] The same memristor as in Example 1 is used to implement the operation of binary Boolean logic and realize an "exclusive OR gate" (XOR).

[0205] The logical operation is performed as follows:

[0206] Set a logic state table. Different logic codes are set in the logic table. The specific logic codes are shown in Table 1. The amplitudes of the four variables S, T1, T2, and r corresponding to the XOR gate are 0, p, 0, and q respectively.

[0207] Initialize the memristor according to the logic state table;

[0208] Specifically, let S=0, that is, T1 is grounded, T2 is connected to a high level, and the state of the memristor is set to LRS / HRS.

[0209] According to the logic state table, write the variables into the memristor;

[0210] Specifically, T2 = 0, that is, T2 is grounded, T1 = p, when p = 0, since T2 is also grounded, there is no voltage difference between the upper and lower ends, so the state of the memristor remains unchanged, still LRS / HRS. When p = 1, T1 is connected to a high level with an amplitude of VDD, and a voltage from top to bottom is generated, and |V T1 -V T2 |>2|V reset |, so the state of the memristor changes and switches to HRS / LRS, S=1.

[0211] According to the logic state table, the variables of the memristor are read, and the variables in the memristor are changed at the same time to obtain the logic result.

[0212] The logical result is:

[0213]

[0214] Specifically, r=q, when q=0, T1 is grounded, and T2 is connected to a high level with an amplitude of Vr. If the previous state of the memristor is in LRS / HRS, the switching of the memristor cannot be completed due to the polarity of the voltage, so the state of the memristor remains unchanged and the output is logic "0";

[0215] If the previous state of the memristor is in HRS / LRS, since the applied Vr satisfies: |V set |<|Vr|<2|V reset |, therefore, the read operation will set the upper RRAM, and the state of the memristor as a whole will switch to LRS / LRS, at which point the output logic is "1";

[0216] When q=1, T1 is connected to a high level with an amplitude of Vr, and T2 is grounded. If the previous state of the memristor is LRS / HRS, the memristor will switch to LRS / LRS and output logic "1".

[0217] If the previous state of the memristor is in HRS / LRS, the state of the memristor will remain unchanged and the output is logic "0".

[0218] That is, the input and output results conform to the "XOR" logic operation, realizing the "XOR gate".

[0219] Experimental Example 1

[0220] The electrical characteristics of the memristor in Example 1 were tested using a Keithley 4200-SCA semiconductor parameter test system, with a ground probe connected to the surface of the bottom electrode and another probe connected to the Ag top electrode.

[0221] Apply a positive voltage V1 (V1>2V) to the memristor. set ), and perform initialization settings. Then test its electrical characteristics, such as Figure 4 As shown, the scanning direction first scans negatively along the directions marked by 1→2→3→4 in the figure, and then scans positively along the directions of 5→6→7→8.

[0222] Figure 5 The characteristic curve obtained by performing multiple repeated scanning tests on the memristor in Example 1 is shown, and it can be seen that the memristor in Example 1 has good cycle stability.

[0223] Figure 6 The memristor in Example 1 is shown to be distributed in high and low resistance states; Figure 7 The figure shows the change of the current switching ratio of the memristor of Example 1 with the voltage. It can be seen from the figure that the memristor can complete two switchings in one half axis, showing a complementary resistive switching characteristic.

[0224] Experimental Example 2

[0225] The "AND gate" process in Example 1 is tested by measuring the overall current of the memristor, reading the resistance state of the memristor, and recording the resistance state of the bipolar resistive memory at the upper and lower ends during the process. Figure 8 As shown, it can be seen that only when the two inputs p and q input logic "1" at the same time, the overall resistance of the memristor is low and the output logic "1", otherwise the output logic "0" satisfies the operation of the "AND" gate.

[0226] Experimental Example 3

[0227] The "AND gate" process in Example 2 is tested by measuring the overall current of the memristor, reading the resistance state of the memristor, and recording the resistance state of the upper and lower bipolar resistive memory during the process, such as Fig. 9 As shown in the figure, only when p and q are both logic "0" can the device output high-impedance logic "0", and in other cases the device is in a low-resistance logic "1" state. Its input and output results conform to the operation of "OR" logic.

[0228] Experimental Example 4

[0229] The "XOR gate" process in Example 3 is tested by measuring the current of the entire memristor, reading the resistance state of the memristor, and recording the resistance state of the upper and lower bipolar resistive memory during the process, such as Fig.10 As shown, when the input is "01" or "10", the output is logic "1", otherwise the output is logic "0", satisfying the operation of the XOR gate.

[0230] In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", "front", "rear", etc. indicate positions or positional relationships based on the working state of the present invention, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", and "fourth" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0231] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integrated ordinary connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediate medium, or the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0232] The present invention has been described above in conjunction with preferred embodiments, but these embodiments are only exemplary and serve only as an illustration. On this basis, the present invention may be subjected to a variety of substitutions and improvements, all of which fall within the scope of protection of the present invention.

Claims

1. A memristor, characterized in that: It comprises a substrate (1) and a resistive switching unit arranged above the substrate (1). The resistive switching unit (2) comprises a bottom electrode (21), a second resistive switching layer (22), an intermediate electrode layer (23), a first resistive switching layer (24) and a top electrode (25) which are arranged in sequence from bottom to top; The top electrode (25), the first resistive switching layer (24), and the middle electrode layer (23) constitute an upper bipolar resistive switching memory (BRS1); The middle electrode layer (23), the second resistive switching layer (22) and the bottom electrode (21) form a lower bipolar resistive switching memory (BRS2).

2. The memristor according to claim 1, characterized in that The bottom electrode (21) is partially exposed to the outside, and a signal access line T1 is arranged on it; A signal access line T2 is arranged on the top electrode (25).

3. The memristor according to claim 1, characterized in that A plurality of resistive switching units (2) are arranged on a substrate (1); the plurality of resistive switching units (2) share a bottom electrode (21), a second resistive switching layer (22), an intermediate electrode layer (23) and a first resistive switching layer (24).

4. The memristor according to claim 1, characterized in that The bottom electrode (21) is ITO glass; The second resistive layer (22) is made of GO:Au NPs; The intermediate electrode layer (23) is made of aluminum; The first resistive switching layer (24) is made of GO:Au NPs; The top electrode (25) is made of silver.

5. A method for manufacturing a memristor, characterized in that: The following steps are involved: S1, using ITO on a glass substrate as a bottom electrode; S2, preparing GO:Au NPs solution, and spin coating it on the bottom electrode to form a second resistive switching layer; S3, evaporating aluminum on the second resistive layer to form a central electrode layer; S4, spin coating the GO:Au NPs solution on the central electrode layer to form a first resistive switching layer; S5. Evaporate silver on the first resistive layer to form a top electrode.

6. A method for implementing binary Boolean logic based on a memristor, using the memristor as claimed in any one of claims 1 to 5, characterized in that: The following steps are involved: Set a logic state table, in which different logic codes are set; Initialize the memristor according to the logic state table; According to the logic state table, write the variables into the memristor; According to the logic state table, the variables of the memristor are read, and the variables in the memristor are changed at the same time to obtain the logic result.

7. The method for implementing binary Boolean logic based on memristor according to claim 6, characterized in that: The logic state table includes four variables and one output, the four variables are initial state S, T1 write state, T2 write state, read voltage state r, and each variable or output has two states; The initial state S is used to characterize the high and low configuration states of the memristor, including the HRS / LRS state and the LRS / HRS state.

8. The method for implementing binary Boolean logic based on memristor according to claim 7, characterized in that: By connecting voltage signals to T1 and T2, the memristor is initialized and the value of the initial state S is determined. When |V T1 -V T2 |>2|V reset |, the initial state S is the HRS / LRS state, represented by S = 1; When |V T2 -V T1 |>2|V reset |, the initial state S is the LRS / HRS state, represented by S = 0; Among them, V T1 is the input voltage of the signal access line T1, V T2 is the input voltage of the signal access line T2, V reset It is the sum of the reset voltages of the upper bipolar resistive memory and the lower bipolar resistive memory.

9. The method for implementing binary Boolean logic based on memristor according to claim 7, characterized in that: When writing to the memristor, by connecting T1 and / or T2 to a high level, the write state of T1 and the write state of T2 are written into the memristor. When the voltage of the signal access line T1 is higher than 2|V reset |, the state written to T1 is 1, otherwise the state written to T1 is 0; When the access voltage of the signal access line T2 is higher than 2|V reset |, the state written to T2 is 1, otherwise the state written to T2 is 0.

10. The method for implementing binary Boolean logic based on memristor according to claim 7, characterized in that: When reading the state of the memristor, the voltage state r is read according to the logic state table, and the access voltages of the signal access line T1 and the signal access line T2 are set. When r=1, the following is set: 2|V reset |>|V T1 -V T2 |>|V set | When r=0, set: 2|V reset |>|V T2 -V T1 |>|V set Among them, V T1 is the input voltage of the signal access line T1, V T2 is the input voltage of the signal access line T2, V set is the sum of the set voltages of the upper bipolar resistive memory and the lower bipolar resistive memory; The logical result obtained is: Among them, S represents the initial state, T1 represents the T1 write state, T2 represents the T2 write state, r represents the read voltage state, and the superscript - represents the Boolean value inversion.

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