Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof, and relates to the technical field of integrated circuit design and manufacturing. The supporting layer is in direct contact with the side walls of the plurality of lower electrodes, and the supporting layer comprises a wavy side wall; the plurality of openings are located between the adjacent lower electrodes, the openings are arranged at intervals in the first direction and the second direction to form an array, and the openings have a first size; from a top view, the wavy side wall comprises a plurality of wave crests and wave troughs, a second size is formed between every two adjacent wave crests, the second size is larger than the first size, and at least the morphology quality of the array area edge unit pattern can be improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] With the rapid development of semiconductor technology, the market has higher and higher requirements for the integration, performance and reliability of integrated circuits. Moore's Law has promoted the development of the semiconductor industry, making the performance of memory continuously improved and the cost gradually reduced.

[0003] However, the increasing integration requires that the volume of a single memory cell in the memory and the distance between the memory array area and the peripheral logic circuit area continue to shrink, resulting in a continuous decrease in the yield and reliability of memory cells at the edge of the memory array area. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the problems in the above-mentioned background technology, which can at least improve the morphology quality of the edge unit pattern of the array area while ensuring that the volume of the semiconductor structure does not increase and the unit density does not decrease, thereby improving the yield, performance and reliability of the semiconductor structure.

[0005] According to various embodiments of the present disclosure, a first aspect of the present disclosure provides a semiconductor structure, comprising: a substrate, a plurality of lower electrodes, a supporting layer and a plurality of openings, wherein the plurality of lower electrodes are located on the substrate; the supporting layer directly contacts the side walls of the plurality of lower electrodes, and the supporting layer comprises a wavy side wall; the plurality of openings are located between adjacent lower electrodes, the openings are arranged in an array at intervals along a first direction and a second direction, and the openings have a first size; wherein, from a top view, the wavy side wall comprises a plurality of peaks and troughs, and a second size is provided between adjacent peaks, and the second size is greater than the first size.

[0006] The semiconductor structure in the above-mentioned embodiment can increase the distance between the wave peak of the supporting layer and the nearest opening, and improve the morphology quality of the opening pattern at the edge of the lower electrode array area, while ensuring that the volume of the semiconductor structure does not increase and the density of the lower electrode unit and the support degree of the supporting layer do not decrease, thereby improving the yield, performance and reliability of the semiconductor structure.

[0007] In some embodiments, the wavy sidewall includes a first wavy sidewall extending along a first direction, and a second wavy sidewall extending along a second direction.

[0008] In some embodiments, the second dimension spans across three lower electrodes in the first direction.

[0009] In some embodiments, there is a second size between the wave crests of adjacent first wavy sidewalls; there is a third size between the wave crests of adjacent second wavy sidewalls; wherein the first size<the third size<the second size.

[0010] In some embodiments, there is a first spacing between adjacent openings along the second direction; wherein, in the second direction, a minimum spacing between the wavy sidewall and the most adjacent opening is greater than the first spacing.

[0011] In some embodiments, there is a first spacing between adjacent openings along the second direction; and the maximum spacing between the wavy sidewall and the opening most adjacent to it along the first direction is greater than the first spacing.

[0012] In some embodiments, a first preset distance exists between the wave valley and the most adjacent opening; and a second preset distance exists between the wave valley and the most adjacent lower electrode.

[0013] The second aspect of the present disclosure provides a semiconductor structure, comprising: a substrate, a plurality of lower electrodes, a support layer and a plurality of openings, wherein the plurality of lower electrodes are located on the substrate; the support layer directly contacts the side walls of the plurality of lower electrodes, and the support layer comprises a wavy side wall; the plurality of openings are located between adjacent lower electrodes, and the openings are arranged in an array at intervals along a first direction and a second direction; wherein, from a top view, the wavy side wall comprises a plurality of crests and troughs, and a first preset spacing exists between the trough and the nearest opening; and a second preset spacing exists between the trough and the nearest lower electrode.

[0014] The semiconductor structure in the above-mentioned embodiment can increase the distance between the wave peak of the supporting layer and the nearest opening, and improve the pattern morphology quality of the edge opening of the lower electrode array area and the lower electrode, while ensuring that the volume of the semiconductor structure does not increase and the density of the lower electrode unit and the support degree of the supporting layer do not decrease, thereby improving the yield, performance and reliability of the semiconductor structure.

[0015] In some embodiments, the opening has a first dimension along the first direction; and adjacent wave crests have a second dimension along the first direction, and the second dimension is greater than the first dimension.

[0016] In some embodiments, adjacent openings have a first spacing along the second direction; in the second direction, a minimum spacing between the wavy sidewall and the most adjacent opening is greater than the first spacing.

[0017] The third aspect of the present disclosure provides a semiconductor structure, including: a substrate, a plurality of lower electrodes, a supporting layer and a plurality of openings, wherein the plurality of lower electrodes are located on the substrate; the supporting layer directly contacts the side walls of the plurality of lower electrodes, and the supporting layer includes a wavy side wall; the plurality of openings are located between adjacent lower electrodes, the openings are arranged in an array at intervals along a first direction and a second direction, and there is a first spacing between adjacent openings; wherein, in the second direction, the minimum spacing between the wavy side wall and the most adjacent opening is greater than the first spacing.

[0018] The semiconductor structure in the above-mentioned embodiment can increase the distance between the wave peak of the supporting layer and the nearest opening, and improve the pattern morphology quality of the edge opening of the lower electrode array area and the lower electrode, while ensuring that the volume of the semiconductor structure does not increase and the density of the lower electrode unit and the support degree of the supporting layer do not decrease, thereby improving the yield, performance and reliability of the semiconductor structure.

[0019] In some embodiments, the opening has a first dimension along a first direction; from a top view, the wavy sidewall includes a plurality of crests and troughs; adjacent crests have a second dimension along the first direction, and the second dimension is greater than the first dimension.

[0020] In some embodiments, from a top view, the wavy sidewall includes a plurality of crests and troughs, and a first preset distance exists between the trough and the most adjacent opening; and a second preset distance exists between the trough and the most adjacent lower electrode.

[0021] A fourth aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0022] Providing a substrate, the substrate comprising a stacked structure, the stacked structure comprising a first sacrificial layer, a first supporting layer, a second sacrificial layer and a second supporting layer stacked in sequence in a direction away from the substrate;

[0023] forming a plurality of lower electrodes penetrating the stacked structure in a direction perpendicular to the substrate;

[0024] Removing part of the first supporting layer and part of the second supporting layer to obtain a supporting layer including a plurality of openings, wherein the remaining first supporting layer and the remaining second supporting layer are used to constitute a supporting layer, the supporting layer directly contacts the side walls of the plurality of lower electrodes, and the supporting layer includes a wavy side wall; the plurality of openings are located between adjacent lower electrodes, and the openings are arranged in an array along a first direction and a second direction at intervals;

[0025] The first sacrificial layer and the second sacrificial layer are removed.

[0026] The semiconductor structure preparation method in the above-mentioned embodiment can obtain a support layer that directly contacts the side walls of multiple lower electrodes after removing the first sacrificial layer and the second sacrificial layer, and use the support layer to support the multiple lower electrodes to ensure that the lower electrode array including multiple openings stands firmly on the substrate; by setting the support layer to include a wavy side wall, it is convenient to increase the distance between the wave peak of the support layer and the nearest opening while ensuring that the volume of the semiconductor structure does not increase and the density of the lower electrode unit and the support degree of the support layer do not decrease, thereby improving the morphology quality of the opening pattern at the edge of the lower electrode array area, thereby improving the yield, performance and reliability of the semiconductor structure.

[0027] In some embodiments, the opening has a first dimension along a first direction; from a top view, the wavy sidewall includes a plurality of crests and troughs, and adjacent crests have a second dimension along the first direction, the second dimension being greater than the first dimension.

[0028] In some embodiments, there is a first spacing between adjacent openings along the second direction; wherein, in the second direction, a minimum spacing between the wavy sidewall and the most adjacent opening is greater than the first spacing.

[0029] In some embodiments, from a top view, the wavy sidewall includes a plurality of crests and troughs; a first preset distance exists between the trough and the most adjacent opening; and a second preset distance exists between the trough and the most adjacent lower electrode.

[0030] In some embodiments, the wavy sidewall includes a first wavy sidewall extending along a first direction and a second wavy sidewall extending along a second direction.

[0031] In some embodiments, the second dimension spans across three lower electrodes in the first direction.

[0032] In some embodiments, there is a second size between the wave crests of adjacent first wavy sidewalls; there is a third size between the wave crests of adjacent second wavy sidewalls; wherein the first size<the third size<the second size. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] FIG. 1a is a schematic top view of a semiconductor structure in an embodiment of the present application;

[0035] FIG1b is a schematic diagram of a cross-sectional structure of the semiconductor structure in FIG1a along a direction perpendicular to the top surface of the substrate;

[0036] Figure 2 A schematic diagram of a memory manufacturing method provided in an embodiment of the present disclosure;

[0037] FIG3 a is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained in step S20 of a memory manufacturing method according to an embodiment of the present disclosure;

[0038] FIG3b is a schematic top view of FIG3a;

[0039] FIG4 a is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after a lower electrode is formed in step S40 in a memory manufacturing method according to an embodiment of the present disclosure;

[0040] FIG4b is a schematic top view of FIG4a;

[0041] 5a is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after a support layer having a wavy sidewall is formed in step S60 in a memory manufacturing method according to an embodiment of the present disclosure;

[0042] FIG5b is a schematic top view of FIG5a;

[0043] 6a is a schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure obtained after the first sacrificial layer and the second sacrificial layer are removed in step S80 in a memory manufacturing method according to an embodiment of the present disclosure;

[0044] FIG. 6 b is a schematic top view of FIG. 6 a .

[0045] Description of reference numerals:

[0046] 1000, semiconductor structure; 20, supporting layer; 101, crest; 102, trough; 11, lower electrode; 12, opening; 21, first supporting layer; 22, second supporting layer; 201, first sacrificial layer; 202, second sacrificial layer; 100, substrate; S1, first size; S2, second size; S3, third size; P0, first spacing; P1, second spacing; P2, third spacing; P3, fourth spacing; SP1, first preset spacing; SP2, second preset spacing. DETAILED DESCRIPTION

[0047] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used in the specification of the present disclosure herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0049] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0050] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0051] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or components may be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0052] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0053] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0054] Please refer to Figures 1a-1b. In some embodiments, a semiconductor structure 1000 is provided, including: a substrate 100, a plurality of lower electrodes 11, a support layer 20 and a plurality of openings 12, wherein the plurality of lower electrodes 11 are located on the substrate 100; the support layer 20 directly contacts the sidewalls of the plurality of lower electrodes 11, and the support layer 20 includes a wavy sidewall; the plurality of openings 12 are located between adjacent lower electrodes 11, and the openings 12 are arranged in an array at intervals along a first direction (e.g., an X-axis direction) and a second direction (e.g., a Y-axis direction), and the openings 12 have a first dimension S1 along the first direction; wherein, from a top view, for example, on a cross section parallel to the Z-axis direction, the wavy sidewall includes a plurality of crests 101 and troughs 102, and a second dimension S2 is provided between adjacent crests 101 along the first direction, and the second dimension S2 is greater than the first dimension S1.

[0055] For example, please continue to refer to Figures 1a-1b. The support layer 20 is used to support multiple lower electrodes 11 to ensure that the array of lower electrodes 11 including multiple openings 12 stands firmly on the substrate 100; the support layer 20 is provided with a wavy side wall. From a top view, the wavy side wall includes multiple crests 101 and troughs 102, and there is a second size S2 between adjacent crests 101 along the first direction, and the second size S2 is greater than the first size S1, so as to facilitate increasing the distance between the crest 101 of the support layer 20 and the nearest opening 12 while ensuring that the volume of the semiconductor structure 1000 does not increase and the unit density of the lower electrode 11 and the support degree of the support layer 20 do not decrease, thereby improving the morphology quality of the pattern of the edge openings 12 in the array area of ​​the lower electrode 11, thereby improving the yield, performance and reliability of the semiconductor structure 1000.

[0056] In some embodiments, a semiconductor structure is provided, further comprising an upper electrode located on the side of the lower electrode facing away from the substrate, and a dielectric layer located between the upper electrode and the lower electrode. The lower electrode, the dielectric layer and the upper electrode are used to form a capacitor together. The materials of the lower electrode and the upper electrode may be the same or different. The material of the lower electrode may include, but is not limited to, at least one of indium tin oxide, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, tantalum nitride, etc. The material of the upper electrode may include, but is not limited to, at least one of indium tin oxide, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, tantalum nitride, etc. The material of the dielectric layer may be formed of a material with a high k (k ≥ 3.9) dielectric constant. For example, the material of the dielectric layer may include, but is not limited to, at least one of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3).

[0057] It should be noted that the first direction in the embodiment of the present application may be the X-axis direction, and the second direction may be the Y-axis direction. Ignoring that the top surface of the substrate is not absolutely flat, the X-axis direction and the Y-axis direction are parallel to the top surface of the substrate, and the Z-axis is perpendicular to the top surface of the substrate.

[0058] Please continue to refer to Figure 1a. In some embodiments, the wavy sidewall includes a first wavy sidewall extending along a first direction, and a second wavy sidewall extending along a second direction, so as to facilitate setting the sidewalls of the support layer 20 surrounding the lower electrode 11 array area into wavy sidewalls, thereby improving the morphology quality of the adjacent opening 12 of the sidewall of the support layer 20 surrounding the lower electrode 11 array area.

[0059] Please continue to refer to Figure 1a. In some embodiments, the second dimension S2 spans across three lower electrodes 11 in the first direction, so that two centers of the openings 12 are correspondingly set at the peak areas of the wave peaks 101 of two adjacent support layers 20 along the first direction, thereby increasing the spacing between the wave peaks 101 of the support layer 20 and the nearest opening 12 while ensuring that the volume of the semiconductor structure 1000 is not increased and the unit density of the lower electrode 11 and the support degree of the support layer 20 are not reduced, thereby improving the morphology quality of the pattern of the openings 12 at the edge of the array area of ​​the lower electrode 11 and reducing the complexity of the design of the wavy sidewall morphology of the support layer 20.

[0060] Please continue to refer to FIG. 1a. In some embodiments, the crests 101 of the first wavy sidewalls adjacent to each other along the first direction have a second dimension S2; the crests 101 of the second wavy sidewalls adjacent to each other along the second direction have a third dimension S3; wherein the first dimension S1<the third dimension S3<the second dimension S2. This facilitates setting the morphology of the wavy sidewalls of the support layer 20 according to the distribution of the openings 12 in the array region of the lower electrodes 11, so that the adjacent crests 101 of the first wavy sidewalls extending along the first direction span across three lower electrodes 11, and the adjacent crests 101 of the second wavy sidewalls extending along the second direction span across three lower electrodes 11.

[0061] Please continue to refer to FIG. 1a. In some embodiments, there is a first spacing P0 between adjacent openings 12 along the second direction; the first spacing P0 may be the minimum spacing between adjacent openings 12 along the second direction. In the second direction, the minimum spacing between the wavy sidewall of the support layer 20 and the nearest opening 12 is greater than the first spacing P0. For example, there is a second spacing P1 between the trough 102 of the first wavy sidewall and the nearest opening 12 along the second direction, P1 may be the minimum spacing between the trough 102 of the first wavy sidewall and the nearest opening 12, P1>P0; there is a third spacing P2 between the crest 101 of the first wavy sidewall and the nearest opening 12 along the second direction, P2 may be the minimum spacing between the crest 101 of the first wavy sidewall and the nearest opening 12, P2>P0. The spacing between the crest 101 of the wavy sidewall of the support layer 20 and the nearest opening 12 is greater than the spacing between adjacent openings 12, thereby ensuring the morphology quality of all edge openings 12 patterns in the array area of ​​the lower electrode 11.

[0062] Please continue to refer to FIG. 1a. In some embodiments, there is a fourth spacing P3 between the crest 101 of the second wavy sidewall and the nearest opening 12 along the first direction. P3 may be the maximum spacing between the second wavy sidewall and the nearest opening 12 along the first direction, and P3>P0. The spacing between the crest 101 of the second wavy sidewall extending along the second direction and the nearest opening 12 along the first direction is greater than the first spacing P0, thereby increasing the spacing between the crest 101 of the second wavy sidewall of the support layer 20 and the nearest opening 12 while ensuring that the volume of the semiconductor structure 1000 does not increase and the unit density of the lower electrode 11 and the support degree of the support layer 20 do not decrease, thereby improving the morphology quality of the pattern of the edge opening 12 of the array region of the lower electrode 11.

[0063] Please continue to refer to Figure 1a. In some embodiments, a first preset spacing SP1 is provided between the trough 102 and the nearest opening 12; a second preset spacing SP2 is provided between the trough 102 and the nearest lower electrode 11, so as to ensure the morphology quality of the opening 12 pattern at the edge of the array area of ​​the lower electrode 11 while ensuring the morphology quality of the lower electrode 11 at the edge of the array area of ​​the lower electrode 11.

[0064] In some embodiments, the first preset interval SP1 may be smaller than the second preset interval SP2.

[0065] In some other embodiments, the first preset interval SP1 may be greater than the second preset interval SP2.

[0066] Please refer to Figures 1a-1b. In some embodiments, a semiconductor structure 1000 is provided, including: a substrate 100, a plurality of lower electrodes 11, a support layer 20 and a plurality of openings 12, wherein the plurality of lower electrodes 11 are located on the substrate 100; the support layer 20 directly contacts the side walls of the plurality of lower electrodes 11, and the support layer 20 includes a wavy side wall; the plurality of openings 12 are located between adjacent lower electrodes 11, and the openings 12 are arranged in an array at intervals along a first direction and a second direction; wherein, from a top view, the wavy side wall includes a plurality of crests 101 and troughs 102, and a first preset spacing SP1 is present between the trough 102 and the nearest opening 12; and a second preset spacing SP2 is present between the trough 102 and the nearest lower electrode 11.

[0067] Please continue to refer to Figures 1a-1b. The support layer 20 is used to support the multiple lower electrodes 11 to ensure that the array of lower electrodes 11 including multiple openings 12 stands firmly on the substrate 100; the support layer 20 is provided with a wavy side wall. From a top view, the wavy side wall includes multiple crests 101 and troughs 102, and there is a first preset spacing SP1 between the trough 102 and the nearest opening 12; there is a second preset spacing SP2 between the trough 102 and the nearest lower electrode 11, so as to facilitate increasing the spacing between the crest 101 of the support layer 20 and the nearest opening 12 while ensuring that the volume of the semiconductor structure 1000 does not increase and the unit density of the lower electrode 11 and the support degree of the support layer 20 do not decrease, thereby improving the pattern morphology quality of the edge openings 12 and the lower electrode 11 in the array area of ​​the lower electrode 11, thereby improving the yield, performance and reliability of the semiconductor structure 1000.

[0068] Please continue to refer to Figure 1a. In some embodiments, the opening 12 has a first dimension S1 along the first direction; adjacent wave crests 101 have a second dimension S2 along the first direction, and the second dimension S2 is greater than the first dimension S1, so that the peak area of ​​adjacent wave crests 101 of the wavy side wall of the support layer 20 is as close to the edge opening 12 of the array area of ​​the nearest lower electrode 11 as possible. Under the condition that the volume of the semiconductor structure 1000 is not increased and the unit density of the lower electrode 11 and the support degree of the support layer 20 are not reduced, the distance between the wave crest 101 of the support layer 20 and the nearest opening 12 is increased, thereby improving the morphology quality of the pattern of the edge opening 12 of the array area of ​​the lower electrode 11.

[0069] Please continue to refer to FIG. 1a. In some embodiments, there is a first spacing P0 between adjacent openings 12 along the second direction; the minimum spacing between the wavy sidewall and the opening 12 closest to the wavy sidewall along the second direction is greater than the first spacing P0. For example, there is a second spacing P1 between the trough 102 of the first wavy sidewall and the closest opening 12 along the second direction, P1 can be the minimum spacing between the trough 102 of the first wavy sidewall and the closest opening 12, P1>P0; there is a third spacing P2 between the crest 101 of the first wavy sidewall and the closest opening 12 along the second direction, P2 can be the minimum spacing between the crest 101 of the first wavy sidewall and the closest opening 12, P2>P0. The spacing between the crest 101 of the wavy sidewall of the support layer 20 and the closest opening 12 is greater than the spacing between adjacent openings 12, thereby ensuring the morphology quality of the patterns of all edge openings 12 in the array area of ​​the lower electrode 11.

[0070] Please refer to Figures 1a-1b. In some embodiments, a semiconductor structure 1000 is provided, including: a substrate 100, a plurality of lower electrodes 11, a support layer 20 and a plurality of openings 12, wherein the plurality of lower electrodes 11 are located on the substrate 100; the support layer 20 directly contacts the side walls of the plurality of lower electrodes 11, and the support layer 20 includes a wavy sidewall; the plurality of openings 12 are located between adjacent lower electrodes 11, the openings 12 are arranged in an array at intervals along a first direction and a second direction, and a first spacing P0 is provided between adjacent openings 12; wherein the minimum spacing between the wavy sidewall and the opening 12 most adjacent to the wavy sidewall along the second direction is greater than the first spacing P0.

[0071] For example, please continue to refer to Figures 1a-1b. The support layer 20 is used to support multiple lower electrodes 11 to ensure that the array of lower electrodes 11 including multiple openings 12 stands firmly on the substrate 100; by setting the support layer 20 to include a wavy sidewall, the minimum spacing between the wavy sidewall and the opening 12 closest to the second direction is greater than the first spacing P0, thereby facilitating the increase of the spacing between the wave crest 101 of the support layer 20 and the closest opening 12 while ensuring that the volume of the semiconductor structure 1000 does not increase and the unit density of the lower electrode 11 and the support degree of the support layer 20 do not decrease, thereby improving the pattern morphology quality of the edge openings 12 and the lower electrodes 11 in the array area of ​​the lower electrode 11, thereby improving the yield, performance and reliability of the semiconductor structure 1000.

[0072] Please continue to refer to Figure 1a. In some embodiments, the opening 12 has a first dimension S1 along the first direction; from a top view, the wavy sidewall includes a plurality of crests 101 and troughs 102; adjacent crests 101 have a second dimension S2 along the first direction, and the second dimension S2 is greater than the first dimension S1, so that the peak area of ​​adjacent crests 101 of the wavy sidewall of the support layer 20 is as close to the edge opening 12 of the array area of ​​the nearest lower electrode 11 as possible. While ensuring that the volume of the semiconductor structure 1000 does not increase and the unit density of the lower electrode 11 and the support degree of the support layer 20 do not decrease, the distance between the crest 101 of the support layer 20 and the nearest opening 12 is increased, thereby improving the morphology quality of the pattern of the edge opening 12 of the array area of ​​the lower electrode 11.

[0073] Please continue to refer to Figure 1a. In some embodiments, from a top view, the wavy sidewall includes a plurality of crests 101 and troughs 102. The trough 102 has a first preset spacing SP1 from the nearest opening 12. The trough 102 has a second preset spacing SP2 from the nearest lower electrode 11. While ensuring the morphology quality of the opening 12 pattern at the edge of the array area of ​​the lower electrode 11, the morphology quality of the lower electrode 11 at the edge of the array area of ​​the lower electrode 11 is also ensured.

[0074] See also Figure 2In some embodiments, a method for preparing a semiconductor device is provided, comprising the following steps:

[0075] Step S20: providing a substrate, the substrate comprising a laminated structure, the laminated structure comprising a first sacrificial layer, a first supporting layer, a second sacrificial layer and a second supporting layer sequentially laminated in a direction away from the substrate;

[0076] Step S40: forming a plurality of lower electrodes penetrating the stacked structure in a direction perpendicular to the substrate;

[0077] Step S60: removing part of the first supporting layer and part of the second supporting layer to obtain a supporting layer including a plurality of openings, wherein the remaining first supporting layer and the remaining second supporting layer are used to constitute a supporting layer, the supporting layer directly contacts the side walls of the plurality of lower electrodes, and the supporting layer includes a wavy side wall; the plurality of openings are located between adjacent lower electrodes, and the openings are arranged in an array along the first direction and the second direction at intervals;

[0078] Step S80: removing the first sacrificial layer and the second sacrificial layer.

[0079] As an example, see Figure 2 In step S20, FIG. 3a and FIG. 3b, a substrate 100 is provided. The substrate 100 may be made of a semiconductor material, an insulating material, a conductor material or any combination thereof. The substrate 100 is a semiconductor structure that provides mechanical support and electrical properties for manufacturing semiconductor devices. The substrate 100 may be a single-layer structure or a multi-layer structure. For example, the substrate 100 may be a III / V semiconductor substrate 100 or a II / VI semiconductor substrate 100. Those skilled in the art may select the type of substrate 100 according to the type of transistor or semiconductor structure formed on the substrate 100, and therefore the type of substrate 100 should not limit the scope of protection of the present disclosure.

[0080] Continuing to refer to FIG. 3a and FIG. 3b, a deposition process and / or a spin on glass coating (SOG) process may be used to form a first sacrificial layer 201 on the top surface of the substrate 100. A deposition process is then used to form a first supporting layer 21 on the first sacrificial layer 201. The preparation process of the first sacrificial layer 201 may be repeated to form a second sacrificial layer 202 on the first supporting layer 21. The preparation process of the first supporting layer 21 may be repeated to form a second supporting layer 22 on the second sacrificial layer 202.

[0081] For example, the material of the first sacrificial layer 201 may include silicon oxide, silicon nitride (SiN x ), aluminum oxide (AlO x), silicon carbide (SiC), or the like. For example, the material of the first sacrificial layer 201 may include silicon oxide. The material of the second sacrificial layer 202 may include silicon oxide, silicon nitride (SiN x ), aluminum oxide (AlO x ), silicon carbide (SiC), or the like. For example, the material of the second sacrificial layer 202 may include silicon oxide.

[0082] For example, the material of the first support layer 21 may include at least one of silicon nitride, silicon oxynitride or silicon carbide nitride, etc. The material of the second support layer 22 may include at least one of silicon nitride, silicon oxynitride or silicon carbide nitride, etc. The materials of the first support layer 21 and the second support layer 22 may be the same or different.

[0083] As an example, see Figure 2 In step S40, FIG. 4a and FIG. 4b, in step S40, a patterned mask layer (not shown) may be formed on the second supporting layer 22 first, and the patterned mask layer includes a pattern for defining parameters such as the shape, position and size of the lower electrode. Based on the patterned mask layer, the second supporting layer 22, the second sacrificial layer 202, the first supporting layer 21 and the first sacrificial layer 201 are etched to obtain a plurality of through holes (not shown) that penetrate the stacked structure in a direction perpendicular to the substrate 100. Then, a deposition process may be used to form the lower electrodes 11 in the plurality of through holes to obtain a plurality of lower electrodes 11 that penetrate the stacked structure in a direction perpendicular to the substrate 100. The material of the lower electrode 11 may be selected from titanium, tungsten, nickel, cobalt, silver, cobalt silicide, aluminum, palladium, copper or metal silicide, and combinations thereof.

[0084] As an example, see Figure 2 In step S60, Figure 5a and Figure 5b, in step S60, a graphic mask covering the top surface of the second supporting layer 22 and the top surface of the lower electrode 11 can be first formed, and the graphic mask includes a pattern for defining parameters such as the shape, position and size of the opening and the wavy side wall. Based on the graphic mask, the stacked structure is etched to remove part of the first supporting layer 21 and part of the second supporting layer 22 to obtain a supporting layer 20 including a plurality of openings 12, wherein the remaining first supporting layer 21 and the remaining second supporting layer 22 are used to constitute a supporting layer, and the supporting layer directly contacts the side walls of the plurality of lower electrodes 11, and the supporting layer 20 includes a wavy side wall; the plurality of openings 12 are located between adjacent lower electrodes 11, and the openings 12 are arranged in an array at intervals along the first direction and the second direction.

[0085] As an example, see Figure 2 In step S80, FIG6a and FIG6b, a wet etching solution may be used in step S80 to remove the first sacrificial layer 201 and the second sacrificial layer 202. The wet etching solution may include a diluted hydrofluoric acid solution.

[0086] Please continue to refer to Figures 6a and 6b. In some embodiments, the opening 12 has a first dimension S1 along the first direction; from a top view, the wavy sidewall includes a plurality of crests 101 and troughs 102, and a second dimension S2 along the first direction is provided between adjacent crests 101, and the second dimension S2 is greater than the first dimension S1, so that the peak area of ​​adjacent crests 101 of the wavy sidewall of the support layer 20 is as close to the edge opening 12 of the array area of ​​the nearest lower electrode 11 as possible. While ensuring that the volume of the semiconductor structure 1000 is not increased and the unit density of the lower electrode 11 and the support degree of the support layer 20 are not reduced, the distance between the crest 101 of the support layer 20 and the nearest opening 12 is increased, thereby improving the morphology quality of the pattern of the edge opening 12 of the array area of ​​the lower electrode 11.

[0087] Please continue to refer to Figures 6a and 6b. In some embodiments, there is a first spacing P0 along the second direction between adjacent openings 12; wherein the minimum spacing between the wavy sidewall and the opening 12 closest to the second direction is greater than the first spacing P0, so that the spacing between the crest 101 of the wavy sidewall of the support layer 20 and the closest opening 12 is greater than the spacing between adjacent openings 12, thereby ensuring the morphology quality of the pattern of all edge openings 12 in the array area of ​​the lower electrode 11.

[0088] Please continue to refer to Figures 6a and 6b. In some embodiments, from a top view, the wavy sidewall includes a plurality of crests 101 and troughs 102; a first preset spacing SP1 is provided between the trough 102 and the nearest opening 12; a second preset spacing SP2 is provided between the trough 102 and the nearest lower electrode 11, thereby facilitating increasing the spacing between the crest 101 of the support layer 20 and the nearest opening 12 while ensuring that the volume of the semiconductor structure 1000 does not increase and the unit density of the lower electrode 11 and the support degree of the support layer 20 do not decrease, thereby improving the pattern morphology quality of the edge opening 12 of the array area of ​​the lower electrode 11 and the lower electrode 11, thereby improving the yield, performance and reliability of the semiconductor structure 1000.

[0089] Please continue to refer to Figures 6a and 6b. In some embodiments, the wavy sidewall includes a first wavy sidewall extending along a first direction and a second wavy sidewall extending along a second direction, so as to facilitate setting the sidewalls of the support layer 20 surrounding the array area of ​​the lower electrode 11 into wavy sidewalls, thereby improving the morphology quality of the adjacent openings 12 of the sidewalls of the support layer 20 surrounding the array area of ​​the lower electrode 11.

[0090] Please continue to refer to Figures 6a and 6b. In some embodiments, the second size S2 spans across three lower electrodes 11 in the first direction, so that two centers of the openings 12 are correspondingly set at the peak areas of the wave peaks 101 of two adjacent support layers 20 along the first direction, thereby increasing the spacing between the wave peaks 101 of the support layer 20 and the nearest opening 12 while ensuring that the volume of the semiconductor structure 1000 is not increased and the unit density of the lower electrode 11 and the support degree of the support layer 20 are not reduced, thereby improving the morphology quality of the pattern of the openings 12 at the edge of the array area of ​​the lower electrode 11 and reducing the complexity of the design of the wavy sidewall morphology of the support layer 20.

[0091] Please continue to refer to FIG. 6a and FIG. 6b. In some embodiments, the crests 101 of the adjacent first wavy sidewalls have a second dimension S2; the crests 101 of the adjacent second wavy sidewalls have a third dimension S3; wherein the first dimension S1<the third dimension S3<the second dimension S2. This facilitates setting the morphology of the wavy sidewall of the support layer 20 according to the distribution of the openings 12 in the array region of the lower electrode 11, so that the adjacent crests 101 of the first wavy sidewall extending in the first direction span across the three lower electrodes 11, and the adjacent crests 101 of the second wavy sidewall extending in the second direction span across the three lower electrodes 11.

[0092] The semiconductor structure preparation method in the above embodiment forms a plurality of lower electrodes 11 penetrating the stacked structure in a direction perpendicular to the substrate 100, wherein the stacked structure includes a first sacrificial layer 201, a first supporting layer 21, a second sacrificial layer 202 and a second supporting layer 22 stacked in sequence in a direction away from the substrate 100; then a plurality of openings 12 are formed between adjacent lower electrodes 11, and the openings 12 are arranged in an array at intervals along the first direction and the second direction; thus, after removing the first sacrificial layer 201 and the second sacrificial layer 202, a supporting layer directly contacting the side walls of the plurality of lower electrodes 11 is obtained. 20, the support layer 20 is used to support the plurality of lower electrodes 11, so as to ensure that the array of lower electrodes 11 including the plurality of openings 12 stands firmly on the substrate 100; by arranging the support layer 20 to include a wavy side wall, it is convenient to increase the distance between the wave crest 101 of the support layer 20 and the nearest opening 12 while ensuring that the volume of the semiconductor structure 1000 does not increase and the unit density of the lower electrode 11 and the support degree of the support layer 20 do not decrease, thereby improving the morphology quality of the pattern of the opening 12 at the edge of the array area of ​​the lower electrode 11, thereby improving the yield, performance and reliability of the semiconductor structure 1000.

[0093] It should be understood that although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, although Figure 2At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0094] Please note that for the sake of simplicity of the specification, in the structural schematic diagrams given in the embodiments below, unless the corresponding cross-sectional structural schematic diagrams are given separately, other structural schematic diagrams of different perspectives of structures related to the inventive points of the embodiments of the present disclosure can refer to each other.

[0095] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A plurality of lower electrodes, located on the substrate; A support layer directly contacts the sidewalls of the plurality of lower electrodes, wherein the support layer comprises a wavy sidewall; A plurality of openings are located between adjacent lower electrodes, the openings are arranged in an array along a first direction and a second direction, and the openings have a first size; Wherein, as seen from the top view, the wavy side wall includes a plurality of wave crests and wave troughs, and there is a second size between adjacent wave crests, and the second size is greater than the first size.

2. The semiconductor structure according to claim 1, characterized in that: The wavy sidewall includes a first wavy sidewall extending along the first direction, and a second wavy sidewall extending along the second direction.

3. The semiconductor structure according to claim 1, characterized in that: The second dimension spans across three of the lower electrodes in the first direction.

4. The semiconductor structure according to claim 2, characterized in that: The second dimension is located between the wave crests of adjacent first wavy side walls; and There is a third dimension between the wave crests of adjacent second wavy side walls; wherein the first dimension<the third dimension<the second dimension.

5. The semiconductor structure according to claim 1, characterized in that: There is a first spacing along the second direction between adjacent openings; Wherein, in the second direction, the minimum distance between the wavy side wall and the most adjacent opening is greater than the first distance.

6. The semiconductor structure according to claim 1, characterized in that There is a first spacing along the second direction between adjacent openings; The maximum distance between the wavy sidewall and the opening most adjacent to it along the first direction is greater than the first distance.

7. The semiconductor structure according to claim 1, characterized in that: There is a first preset distance between the wave trough and the most adjacent opening; A second preset distance exists between the wave valley and the most adjacent lower electrode.

8. A semiconductor structure, characterized in that: include: substrate; A plurality of lower electrodes, located on the substrate; A support layer directly contacts the sidewalls of the plurality of lower electrodes, wherein the support layer comprises a wavy sidewall; A plurality of openings are located between adjacent lower electrodes, and the openings are arranged in an array at intervals along a first direction and a second direction; Wherein, from a top view, the wavy side wall includes a plurality of wave crests and wave troughs, and a first preset spacing exists between the wave trough and the most adjacent opening; A second preset distance exists between the wave valley and the most adjacent lower electrode.

9. The semiconductor structure according to claim 8, characterized in that: The opening has a first dimension along the first direction; There is a second dimension between adjacent wave crests along the first direction, and the second dimension is greater than the first dimension.

10. The semiconductor structure according to claim 8, characterized in that There is a first spacing along the second direction between adjacent openings; In the second direction, the minimum distance between the wavy sidewall and the most adjacent opening is greater than the first distance.

11. A semiconductor structure, characterized in that: include: substrate; A plurality of lower electrodes, located on the substrate; A support layer directly contacts the sidewalls of the plurality of lower electrodes, wherein the support layer comprises a wavy sidewall; A plurality of openings are located between adjacent lower electrodes, the openings are arranged in an array along a first direction and a second direction, and there is a first spacing between adjacent openings; Wherein, in the second direction, the minimum distance between the wavy side wall and the most adjacent opening is greater than the first distance.

12. The semiconductor structure according to claim 11, characterized in that: The opening has a first dimension along the first direction; From a top view, the wavy sidewall includes a plurality of crests and troughs; There is a second dimension between adjacent wave crests along the first direction, and the second dimension is greater than the first dimension.

13. The semiconductor structure according to claim 11, characterized in that: From a top view, the wavy side wall includes a plurality of wave crests and wave troughs, and a first preset spacing exists between the wave trough and the most adjacent opening; A second preset distance exists between the wave valley and the most adjacent lower electrode.

14. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a stacked structure, the stacked structure comprising a first sacrificial layer, a first supporting layer, a second sacrificial layer and a second supporting layer stacked in sequence in a direction away from the substrate; forming a plurality of lower electrodes penetrating the stacked structure in a direction perpendicular to the substrate; Removing part of the first supporting layer and part of the second supporting layer to obtain a supporting layer including a plurality of openings, wherein the remaining first supporting layer and the remaining second supporting layer are used to constitute the supporting layer, the supporting layer directly contacts the side walls of the plurality of lower electrodes, and the supporting layer includes a wavy side wall; the plurality of openings are located between adjacent lower electrodes, and the openings are arranged in an array at intervals along the first direction and the second direction; The first sacrificial layer and the second sacrificial layer are removed.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that: The opening has a first dimension along the first direction; Seen from a top view, the wavy side wall includes a plurality of wave crests and wave troughs, and a second dimension along the first direction exists between adjacent wave crests, and the second dimension is greater than the first dimension.

16. The method for preparing a semiconductor structure according to claim 14, characterized in that: There is a first spacing along the second direction between adjacent openings; Wherein, in the second direction, the minimum distance between the wavy side wall and the most adjacent opening is greater than the first distance.

17. The method for preparing a semiconductor structure according to claim 14, characterized in that: From a top view, the wavy sidewall includes a plurality of crests and troughs; There is a first preset distance between the wave trough and the most adjacent opening; A second preset distance exists between the wave valley and the most adjacent lower electrode.

18. The method for preparing a semiconductor structure according to claim 15, characterized in that: The wavy sidewall includes a first wavy sidewall extending along the first direction, and a second wavy sidewall extending along the second direction.

19. The method for preparing a semiconductor structure according to claim 15, characterized in that: The second dimension spans across three of the lower electrodes in the first direction.

20. The method for preparing a semiconductor structure according to claim 18, characterized in that: The second dimension is located between the wave crests of adjacent first wavy side walls; and There is a third dimension between the wave crests of adjacent second wavy side walls; wherein the first dimension<the third dimension<the second dimension.

Images