Semiconductor element, composite semiconductor element, and drive circuit

Abstract

The invention relates to a semiconductor element, a composite semiconductor element, and a drive circuit. Even if a power supply having a relatively high voltage is used, a gate insulating film of a semiconductor element to be driven can be thinned, and stable operation can be performed. A p + layer is formed on a surface between the drain electrode and an end portion of the gate electrode or the n layer on the gate electrode side, and an auxiliary electrode is connected to the p + layer. The depletion layer gradually expands from a pn junction interface between the n-layer and the p-layer when a drain electrode-source electrode voltage is gradually increased at an off-state. When the voltage between the drain electrode and the source electrode is further increased, the depletion layer reaches the p + layer, when the voltage is further increased, the depletion layer in the n layer expands, but the p + layer is not completely depleted, and the potential of the p + layer is saturated. When an auxiliary electrode is connected to a gate of a switching element driven by an n-channel element (1), a gate oxide film of the switching element can be thinned.

Description

Technical Field

[0001] The present invention relates to a semiconductor element used in a drive circuit for driving a switching element or the like, a composite semiconductor element in which the semiconductor element is combined, and a drive circuit using the semiconductor element or the composite semiconductor element. Background Art

[0002] In order to control the on and off of high-power loads such as motors, power semiconductor elements (power control semiconductor elements) such as power MOSFET and IGBT are used. The control of the switching action of the power semiconductor element is controlled by the gate voltage applied to the gate. In order to optimally control the action, the gate voltage is controlled by a drive circuit provided separately from the power semiconductor element. The rated voltage of the power semiconductor element (such as IGBT) is, for example, about 600V.

[0003] On the other hand, the voltage used for controlling such a power semiconductor element (gate voltage of the power semiconductor element) is set to a relatively high voltage (for example, approximately 20 V) to prevent erroneous operation associated with induced noise and a floating component of the LCR component and to allow a relatively large current to flow, and a drive circuit is provided in the control of the power semiconductor element.

[0004] Therefore, generally speaking, as described in Patent Document 1, the gate oxide film of the semiconductor element used for controlling the power semiconductor element is thickened to improve the gate withstand voltage. However, in this way, the thicker gate oxide film also has many disadvantages. For example, since punch-through is easy to occur when the gate oxide film is thick, it is necessary to increase the gate length to cope with this situation. Alternatively, since the current driving capability is reduced when the gate oxide film is thick, it is necessary to increase the gate width to compensate for this defect.

[0005] In addition, Patent Document 2 describes a driving circuit that uses a CMOS level shift circuit to form two voltages for driving a MOSFET. In addition, Patent Document 3 describes a circuit in which a p-type semiconductor region for an intermediate contact is provided in a p-type drain region of a semiconductor element (p-channel MOSFET P3) in a level shift circuit, and the intermediate contact is connected to the gate of the power semiconductor element. According to the circuit of Patent Document 3, it is disclosed that the gate oxide film of the switching element can be made thinner.

[0006] Patent Document 1: Japanese Patent Application Publication No. 2004-96083

[0007] Patent Document 2: Japanese Patent Application Laid-Open No. 5-308274

[0008] Patent Document 3: Japanese Patent Application Laid-Open No. 9-270699

[0009] In the technology described in Patent Document 3, although the potential extracted from the intermediate contact electrode is lower than the potential directly extracted from the power supply voltage, the potential extracted from the intermediate contact electrode rises in accordance with the increase in the drain-source voltage of the MOSFET provided with the intermediate contact.

[0010] Therefore, a driving circuit or a semiconductor element used in the driving circuit is desired, which can make the gate insulating film of the semiconductor element to be driven thinner and can perform stable operation even when a relatively high voltage power supply is used. Summary of the invention

[0011] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide an invention that solves the above-mentioned problems.

[0012] The present invention has the following configurations in order to solve the above-mentioned problems.

[0013] The semiconductor element (first) of the present invention is characterized in that, on the surface of a semiconductor substrate, there is: a p-type first semiconductor region; an n-type second semiconductor region, which is formed on the surface within the first semiconductor region; an n-type third semiconductor region, which is formed separately from the second semiconductor region; an n-type fourth semiconductor region, which is formed in a manner that the local impurity concentration is high on the side of the third semiconductor region away from the second semiconductor region; a gate electrode, which is formed above the semiconductor substrate between the second semiconductor region and the third semiconductor region through an insulating film; a first main electrode, which is connected to the second semiconductor region; and a second main electrode, which is connected to the fourth semiconductor region, and the current flowing between the first main electrode and the second main electrode is controlled by the potential of the gate electrode, and the semiconductor element has: a p-type fifth semiconductor region, which is locally formed at the surface of the third semiconductor region, between the fourth semiconductor region and the gate electrode; and an auxiliary electrode, which is connected to the fifth semiconductor region.

[0014] The semiconductor element (second) of the present invention is characterized in that it has on the surface of a semiconductor substrate: an n-type first semiconductor region; a p-type second semiconductor region, which is formed on the surface within the first semiconductor region; a p-type third semiconductor region, which is formed separately from the second semiconductor region; a p-type fourth semiconductor region, which is formed in a manner that the local impurity concentration is high on the side of the third semiconductor region away from the second semiconductor region; a gate electrode, which is formed above the semiconductor substrate between the second semiconductor region and the third semiconductor region through an insulating film; a first main electrode, which is connected to the second semiconductor region; and a second main electrode, which is connected to the fourth semiconductor region, and the current flowing between the first main electrode and the second main electrode is controlled by the potential of the gate electrode, and the semiconductor element has: an n-type fifth semiconductor region, which is locally formed on the surface of the third semiconductor region, between the fourth semiconductor region and the gate electrode; and an auxiliary electrode, which is connected to the fifth semiconductor region.

[0015] The composite semiconductor element of the present invention is characterized in that the composite semiconductor element is formed by connecting the second main electrode in the semiconductor element (first) and the second main electrode in the semiconductor element (second).

[0016] The driving circuit of the present invention is characterized in that the auxiliary electrode in the semiconductor element is electrically connected to a gate electrode in another semiconductor element.

[0017] The driving circuit of the present invention controls the power supply to a load connected to a location connecting the low voltage side of a first power control element on the high side and the high voltage side of a second power control element on the low side, and is characterized in that the auxiliary electrode of the semiconductor element is connected to the gate of a switching element that outputs a signal to the gate of the first power control element.

[0018] The present invention is constructed as described above, and therefore, can obtain the following driving circuit or semiconductor element and composite semiconductor element used for the driving circuit: even if a relatively high voltage power supply is used, the gate insulating film of the semiconductor element to be driven can be made thinner and stable operation can be performed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a cross-sectional view showing the structure of a first example of a semiconductor element according to an embodiment of the present invention.

[0020] Figure 2 It is a cross-sectional view showing the structure of a second example of the semiconductor element according to the embodiment of the present invention.

[0021] Figure 3This is a result obtained by calculating the relationship between the drain-source voltage and the auxiliary electrode-source voltage of the first example of the semiconductor element according to the embodiment of the present invention.

[0022] Figure 4 This is a result obtained by calculating the potential distribution during operation in the first example of the semiconductor element according to the embodiment of the present invention.

[0023] Figure 5 This is a result obtained by calculating the relationship between the drain-source voltage and the auxiliary electrode-source voltage of the second example of the semiconductor element according to the embodiment of the present invention.

[0024] Figure 6 These are the results of calculating the potential distribution during operation in the second example of the semiconductor element according to the embodiment of the present invention.

[0025] Figure 7 It is a cross-sectional view showing the structure of a modified example of the first example of the semiconductor element according to the embodiment of the present invention.

[0026] Figure 8 It is a diagram showing a configuration of a first example of a driving circuit according to an embodiment of the present invention.

[0027] Fig. 9 The diagram shows the correspondence between conventional general MOSFETs (n-channel type, p-channel type) and semiconductor elements (n-channel type, p-channel type) according to the embodiments of the present invention in terms of symbols.

[0028] Fig.10 It is a diagram showing the structure of a second example of the conventional driving circuit.

[0029] Fig.11 It is a diagram showing the configuration of a second example of the drive circuit according to the embodiment of the present invention.

[0030] Description of symbols

[0031] 1, 3, N1 to N4, N21, N22: n-channel devices (semiconductor devices); 2, P1 to P4: p-channel devices (semiconductor devices); 10, 11: n-layer; 12: p-layer (first semiconductor region); 13: n + Layer (second semiconductor region); 14: n layer (third semiconductor region); 15: n + Layer (4th semiconductor region); 16: p + Layer; 17: p +Layer (fifth semiconductor region); 21, 41: gate oxide film (gate insulating film); 22, 42, G: gate electrode; 23, 43, S: source electrode (first main electrode); 24, 44, D: drain electrode (second main electrode); 25, 45, B: body electrode; 26, 46, PE: auxiliary electrode; 27, 29, 47: buried oxide film layer; 28, 48: insulating layer; 31: n layer (first semiconductor region); 33: p + Layer (second semiconductor region); 34: p layer (third semiconductor region); 35: p + Layer (4th semiconductor region); 36: n + Layer; 37: n + Layer (5th semiconductor region); 100, 110, 910: power semiconductor element drive circuit (drive circuit); CL: coil; N0: n-channel MOSFET (2nd main switch element); N31, N32: n-channel MOSFET; N20, N30: ​​n-channel MOSFET (main switch element); P0: p-channel MOSFET (1st main switch element); S1, S2, S11, S12: power semiconductor element (power control element); S01, S02: input side switch element. DETAILED DESCRIPTION

[0032] First, the semiconductor element of the embodiment of the present invention is described below. The semiconductor element operates as a horizontal MOSFET, and can be realized in the same way as a normal MOSFET, and can be realized in both n-channel type and p-channel type. These semiconductor elements can be used to form a drive circuit (drive circuit) of a power semiconductor element. In the power semiconductor element drive circuit, the gate insulating film in the semiconductor element of the next stage driven by the semiconductor device can be made thinner and operate well.

[0033] Figure 1 This is a cross-sectional view schematically showing the structure of an n-channel element (semiconductor element) 1 as an example of the semiconductor element. Here, only the part directly related to the present invention is simplified, and only the structure of the upper side of the epitaxial layer, that is, the n-type layer (n layer 10) in the semiconductor substrate (silicon substrate) is shown.

[0034] The low-concentration n-type layer (n layer 11) of the n-channel MOSFET is formed on the surface of the n-layer 10. In addition, the n-layer 11 may be a low-concentration p-type layer instead of a low-concentration n-type layer. Furthermore, a low-concentration p-type layer (p layer 12: first semiconductor region) as the body layer of the n-channel MOSFET is formed on the surface of the n-layer 11. A high-concentration n-type layer (n layer 12: first semiconductor region) as a source region is formed on the surface of the p layer 12. +The n-type layer (n-layer 13: second semiconductor region) as the drain region and drift region is connected to the n-type layer (n-layer 14: third semiconductor region) on the surface of the n-layer 11. + Layer 13 is formed separately. + A gate electrode 22 is formed on the surface of the p-layer 12 between the n-layer 13 and the n-layer 14 via a relatively thin gate insulating film (silicon oxide film: insulating film) 21. + The source electrode (first main electrode) 23 is connected to the n layer 13, and the n layer 14 is connected to the source electrode (first main electrode) 23. + The layer 15 (the fourth semiconductor region) is provided with a drain electrode (the second main electrode) 24. + The layer 15 is formed as a high-concentration n-type layer locally for contact at a location sufficiently far from the gate electrode 22 in the horizontal direction. + The layer 16 also forms a body electrode 25. + The layer 16 is formed as a p-type layer having a local high concentration for contact.

[0035] In the above structure, when a voltage is applied between the drain electrode 24 and the source electrode 23 , the voltage between the gate electrode 22 and the source electrode 23 is controlled, thereby controlling the on / off of the current flowing between the drain electrode 24 and the source electrode 23 .

[0036] Here, in the n-channel element 1, the drain electrode 24 (n + The surface of the n-layer 14 between the n-layer 15 and the gate electrode 22 or the end of the n-layer 14 on the gate electrode 22 side is formed with a p + layer (fifth semiconductor region) 17, in which p + The layer 17 is connected to an auxiliary electrode 26. + Layer 15 and p + A buried oxide film layer 27 made of a LOCOS oxide film or the like is formed on the surface of the n-layer 14 between the layers 17 to electrically isolate them. In addition, an insulating layer 28 is formed on the surface of the semiconductor substrate except for the portion having the above-mentioned electrodes.

[0037] Figure 2 1 is a cross-sectional view schematically showing the structure of a p-channel element 2 as another example of the semiconductor element. In this structure, an n-layer 31 (first semiconductor region) is provided in an n-layer 10 which is a low-concentration n-type layer similar to the above-mentioned epitaxial layer. A p-type semiconductor region is provided on this region. + layer (second semiconductor region) 33 and n + Layer 36, with p + The layer 33 is separated from the p-layer (third semiconductor region) 34 as a drift region, in which a p-layer (third semiconductor region) is provided.+ Layer (fourth semiconductor region) 35. In p + A gate electrode 42 is formed on the surface between the p layer 33 and the p layer 34 via a relatively thin gate insulating film (silicon oxide film: insulating film) 41. + The source electrode (first main electrode) 43 is connected to the p layer 33, and the p layer 34 is connected to the source electrode (first main electrode) 43. + The layer 35 (fourth semiconductor region) is provided with a drain electrode (second main electrode) 44. + The layer 35 is formed as a p-type layer with a high concentration locally for contact at a location sufficiently far from the gate electrode 42 in the horizontal direction. + The layer 36 also forms a body electrode 45. + Layer 36 is formed as an n-type layer with a local high concentration for contact. + The layer (fifth semiconductor region) 37 is formed in the p layer 34 at a lower thickness than the p + Layer 35 is closer to p + The drain electrode 44 (p + The gate electrode 42 is formed between the p-layer 35 and the gate electrode 42 or the end of the p-layer 34 on the gate electrode 42 side. + The layer 37 is connected to an auxiliary electrode 46. In addition, the n-layer 10 may be a low-concentration p-type layer instead of a low-concentration n-type layer.

[0038] exist Figure 1 , 2 In the figure, an n-channel element 1 and a p-channel element 2 are shown separately, but they can be formed on a common semiconductor substrate having an n-layer 10 to provide a composite semiconductor element. Figure 1 The drain electrode 24 and Figure 2 The drain electrode 44 is connected to the gate insulating film 21 and can be used as a CMOS. In addition, the gate insulating film 21 and the gate insulating film 41 are formed at the same time.

[0039] right Figure 1 The structure and operation of the n-channel element 1 will be described in detail.

[0040] The impurity concentration of the n-layer 14 as the drift region is set to 5×10 16 ~5×10 17 cm -3 On the other hand, in order to deplete the n layer 14, the p + Layer 17 is also not depleted, p + The impurity concentration of layer 17 is much higher than that of n layer 14, and is set to 1×10 19 ~1×10 20cm -3 When the voltage between the drain electrode 24 and the source electrode 23 is gradually increased during the cut-off, the depletion layer gradually expands from the pn junction interface between the n layer 11 and the p layer 12. When the voltage between the drain electrode 24 and the source electrode 23 is further increased, the depletion layer reaches the pn junction interface. + When the voltage is further increased, the depletion layer in the n layer 14 further expands, but the p + Layer 17 is not completely depleted, so p + The potential of the layer 17 is saturated, and the increase in the potential of the auxiliary electrode 26 can be suppressed compared to the increase in the potential of the drain electrode 24 .

[0041] The saturation potential of the auxiliary electrode 26 depends on Figure 1 The depletion layer in the pn junction begins to extend to the p + The saturation potential increases as the distance between the layers 17 in the lateral direction increases. If the auxiliary electrode 26 is connected to the gate of the switching element driven by the gate of the n-channel element 1, the voltage applied to the gate of the switching element can be reduced even if the applied voltage of the n-channel element 1 is a relatively high voltage. As a result, the gate insulating film of the switching element can be made thinner.

[0042] In addition, Figure 2 The structure and operation of the p-channel element 2 are described in detail. The impurity concentration of the p-layer 34 as the drift region is set to 5×10 16 ~5×10 17 cm -3 On the other hand, in order to make n + Layer 37 is also not depleted, n + The impurity concentration of layer 37 is much higher than that of p layer 34, and is set to 1×10 19 ~1×10 20 cm -3 When the voltage between the drain electrode 44 and the source electrode 43 is gradually increased during the cut-off, the depletion layer gradually expands from the pn junction interface between the n layer 10 and the p layer 34. When the voltage between the drain electrode 44 and the source electrode 43 is further increased, the depletion layer reaches the n + When the voltage is further increased, the depletion layer in the p layer 34 further expands, but the n layer 37 + Layer 37 is not completely depleted, n + The potential of the layer 37 is saturated, and the increase in the potential of the auxiliary electrode 46 can be suppressed compared to the increase in the potential of the drain electrode 44 .

[0043] The saturation potential of the auxiliary electrode 46 depends on Figure 2 The depletion layer in the pn junction begins to extend to the n + The saturation potential increases as the distance in the lateral direction between the layers 37 increases. That is, if the auxiliary electrode 46 is connected to the gate of the switching element driven by the gate of the p-channel element 2, the voltage applied to the gate of the switching element can be reduced even if the applied voltage of the p-channel element 2 is a relatively high voltage. As a result, the gate insulating film of the switching element can be made thinner.

[0044] Figure 3 The result is as follows: Figure 1 In the n-channel element 1, the gate oxide film thickness is set to 20 nm, the n layer 11, the p layer 12, the n layer 14, and the p layer 16 are + The impurity concentration of layer 17 is set to (1×10 15 cm -3 , 1×10 17 cm -3 , 2×10 16 cm -3 , 1×10 19 cm -3 , n layers 14, p + The depths of layer 17 are set to 1.25 μm, 0.2 μm, and p + When the width of the p-layer 17 is set to 1.1 μm and the distance between the p-layer 12 and the end on the opposite side of the gate electrode 22 is set to 1.2 μm, the distance between the p-layer 12 and the gate electrode 22 is calculated by simulation. + The relationship between the drain-source voltage VDS and the auxiliary electrode-source voltage VxDS when the distance D between the layer 17 and the gate electrode 22 is set to 0.6μm and 0.8μm. As described above, even if VDS is increased, VxDS is saturated at a predetermined voltage, and this saturation voltage can be obtained by p + The position of layer 17 (gate electrode 22 and p + The distance D) between the layers 17 is adjusted.

[0045] also, Figure 4 When the gate electrode 22 is connected to the p + The equipotential lines (0.5 V interval) in the semiconductor substrate when the n-channel element 1 is off and VDS is 30 V are shown when the distance D between the layers 17 is 0.6 μm (a) and 0.8 μm (b).

[0046] As a result, it can be seen that in the above settings, + Layer 17 is not completely depleted, p + The region near the surface between layer 17 and gate electrode 22 is completely depleted. + At layer 17, due to the+ Layer 17 and n + The surface side between the layers 15 (close to p + The electric field strength locally becomes high on one side of the layer 17, so it can also be Figure 1 As shown, a buried oxide film layer 27 is provided. As described above, a LOCOS oxide film can be used as the buried oxide film layer 27, but a trench oxide film formed by burying a CVD oxide film in a trench (trench) formed by dry etching on the substrate surface, such as shallow trench isolation (STI), can also be used.

[0047] Figure 5 is the AND in p-channel element 2 Figure 3 The same characteristic of the relationship between the drain-source voltage VDS and the auxiliary electrode-source voltage VxDS, Figure 6 (a) and (b) are equipotential lines (0.5 V interval) in the semiconductor substrate when the p-channel element 2 is turned off when VDS is set to 20 V. Here, the n-layer 10, n-layer 31, p-layer 34, and n-layer 36 are shown in FIG. + The impurity concentration of layer 37 is set to 1×10 15 cm -3 , 1×10 17 cm -3 , 2×10 16 cm -3 , 1×10 19 cm -3 ), the gate oxide film thickness is set to 20nm, the depth of the p layer 34 is set to 2.2μm, and the n + The width of layer 37 is set to 1.1 μm. The gate electrode 42 is connected to the n + The distance D between the layers 37 was set to 0.6 μm and 0.8 μm in the same manner as described above.

[0048] according to Figure 5 It can be seen that even if VDS is increased, VxDS is saturated at a specified voltage and can pass p + The position of layer 17 (gate electrode 22 and p + The saturation voltage is adjusted by the distance between the layers 17. Figure 6 It can be seen that in n + Layer 37 is not completely depleted, n + The space between layer 37 and gate electrode 42 is completely depleted.

[0049] Figure 7 2 is a cross-sectional view showing the structure of an n-channel device 3 as a modified example of the above-mentioned n-channel device 1. Figure 4 The results show that p +The electric field intensity at the surface of the n-layer 14 between the n-layer 17 and directly below the gate electrode 22 becomes locally high. Figure 7 As shown in p + A buried oxide film layer 29 is provided on the surface of the n-layer 14 between the layer 17 and the gate electrode 22. The buried oxide film layer 29 can be a LOCOS oxide film or a trench oxide film. Figure 2 In the p-channel element 2, it is also possible to + A LOCOS oxide film or a trench oxide film is provided on the surface of the p-layer 34 between the layer 37 and directly below the gate electrode 42 .

[0050] Figure 8 It is shown that the use Figure 1 and Figure 2 FIG. 1 is a diagram showing a structure of a power semiconductor element drive circuit (drive circuit) 100 of an element shown in FIG. Here, power semiconductor elements S1 and S2 are provided as switch elements for turning on / off the coil CL. The point where the low voltage side of the high-side power semiconductor element S1 and the high voltage side of the low-side power semiconductor element S1 are connected is connected to one end of the coil CL as an example of a load.

[0051] Here, Fig. 9 Shows the typical MOSFET (n-channel, p-channel) and Figure 1 as well as Figure 2 Here, in addition to the gate (G), source (S), and drain (D), the body electrode (B) is also shown, and in the n-channel element 1 and the p-channel element 2, the auxiliary electrode (PE) mentioned above is further shown. Figure 8 In the examples, the symbols shown here are used.

[0052] exist Figure 8In FIG. 1 , the portion surrounded by the dotted line represents a driving circuit, and a p-channel MOSFET P0 and an n-channel MOSFET N0 are connected to the gate of the power semiconductor element S1 on the high side. The gate of the p-channel MOSFET P0 is connected to the auxiliary electrode (PE) of the p-channel element P2. In addition, the gate of the p-channel element 2, i.e., the p-channel element P2, is connected to the auxiliary electrode (PE) of the p-channel element 2, i.e., the p-channel element P1. In addition, the gate of the n-channel element 1, i.e., the n-channel element N2, is connected to the auxiliary electrode (PE) of the n-channel element 1, i.e., the n-channel element N1, and the gate of the n-channel element N1 is connected to the auxiliary electrode (PE) of the n-channel element N2. As a result, the gate connected to the auxiliary electrode (PE) is suppressed to the saturation voltage applied to the auxiliary electrode (PE), so that the potential of the gate connected to the auxiliary electrode (PE) can be made lower than the input voltage, and a thinner gate insulating film can be used for the gate. That is, the gate insulating films of the p-channel MOSFET P0, the p-channel type elements P1, P2, and the gate insulating films of the n-channel MOSFET N0, the n-channel type elements N1, N2 can be made similarly thin and of approximately the same thickness. Here, approximately the same thickness means that all of these gate insulating films are formed by a common oxidation process. In particular, the p-channel MOSFET P0 requires a relatively large current capacity to send a gate signal to the power semiconductor element (IGBT) S1 on the high side, and the effect of using a thinner gate insulating film is greater. The same relationship also holds true between the n-channel MOSFET N0 on the low side, the p-channel type element 2, i.e., the p-channel type elements P4, P3, and the n-channel type element 1, i.e., the n-channel type elements N4, N3.

[0053] A modified example of the power semiconductor element drive circuit (drive circuit) 100 is described. Even if the MOSFET (p-channel MOSFET P0, p-channel type elements P1, P2) constituting one of the CMOS is changed to a resistance load, the effect of the invention can be obtained. In this case, although the power consumption increases, it is not necessary to form a p-channel MOSFET in the same chip, so the manufacturing process can be simplified, making the switch element drive circuit cheap or small.

[0054] first, Fig.10 The structure of a conventional power semiconductor element drive circuit 910 using a common MOSFET is shown. Here, power semiconductor elements S11 and S12 are provided corresponding to the above-mentioned power semiconductor elements S1 and S2. Here, the structure for controlling the gate voltage of the power semiconductor element S11 is shown, and the structure for controlling the gate voltage of the power semiconductor element S12 is omitted.

[0055] The gate of the power semiconductor element S11 is connected to the drain of an n-channel MOSFET (main switch element) N30. The gate of the n-channel MOSFET N30 is connected to the drain of an n-channel MOSFET N32 and the gate of an n-channel MOSFET N31 at the previous stage. In addition, the gate of the n-channel MOSFET N32 is connected to the drain of the n-channel MOSFET N31. The operation of the power semiconductor element drive circuit (electric circuit) 910 is also controlled by the input side switch element S01, and the power supply voltage used is also 25V. A resistive load is provided between the power supply voltage and the n-channel MOSFETs N30, N31, and N32.

[0056] Fig.11 In this case, the configuration of a power semiconductor element drive circuit (drive circuit) 110 is shown in which n-channel MOSFETs N31 and N32 are replaced with the n-channel element 1, i.e., n-channel elements N21 and N22. Here, the n-channel MOSFET (main switch element) N20 of the final output stage is a common MOSFET similar to the n-channel MOSFET N30.

[0057] Here, the auxiliary electrode (PE) of the n-channel element N22 and the gate of the n-channel element N21 are connected to the gate of the n-channel MOSFET N20. Also, the auxiliary electrode (PE) of the n-channel element N21 is connected to the gate of the n-channel element N22.

[0058] In this structure, the gate voltage of the element (MOSFET) connected to the auxiliary electrode (PE) is also suppressed low, so the gate insulating film of the element connected to the auxiliary electrode (PE) can be made thinner.

[0059] In the above example, the following MOS gate structure is used: a silicon substrate is used as a semiconductor substrate, and a silicon oxide film is used as a gate insulating film. However, in a switch element using other semiconductor substrates or a switch element using a MIS gate structure of other insulating films, the thickness of the insulating film can be made thinner, and the chip can be made cheaper, so the above structure is effective. In addition, the power semiconductor elements S1, S2, S11, and S12 are not limited to IGBTs, but can also be well-known power semiconductor elements such as MOSFET and SJ-MOSFET.

[0060] In addition, in addition to the power semiconductor element driving circuit that drives the power semiconductor as described above, in an electrical circuit that similarly uses a plurality of MOSFETs with different operating voltages, the above-mentioned n-channel element and p-channel element can be similarly used, and by appropriately combining them, the MOSFET on the side that operates at a high voltage can cope with a low voltage. Thus, the chip constituting the electrical circuit can be made cheap.

Claims

1. A semiconductor element, characterized in that: On the surface of the semiconductor substrate there are: A first p-type semiconductor region; An n-type second semiconductor region formed on a surface within the first semiconductor region; an n-type third semiconductor region formed separately from the second semiconductor region; an n-type fourth semiconductor region formed in the third semiconductor region on a side away from the second semiconductor region so as to have a high local impurity concentration; a gate electrode formed on the semiconductor substrate between the second semiconductor region and the third semiconductor region via an insulating film; a first main electrode connected to the second semiconductor region; as well as a second main electrode connected to the fourth semiconductor region, The current flowing between the first main electrode and the second main electrode is controlled by the potential of the gate electrode. The semiconductor element has: a p-type fifth semiconductor region locally formed between the fourth semiconductor region and the gate electrode on the surface of the third semiconductor region; and An auxiliary electrode is connected to the fifth semiconductor region.

2. A semiconductor element, characterized in that: On the surface of the semiconductor substrate there are: A first n-type semiconductor region; A p-type second semiconductor region formed on a surface within the first semiconductor region; a p-type third semiconductor region formed separately from the second semiconductor region; a p-type fourth semiconductor region formed so as to have a locally high impurity concentration on a side of the third semiconductor region that is away from the second semiconductor region; a gate electrode formed on the semiconductor substrate between the second semiconductor region and the third semiconductor region via an insulating film; a first main electrode connected to the second semiconductor region; as well as a second main electrode connected to the fourth semiconductor region, The current flowing between the first main electrode and the second main electrode is controlled by the potential of the gate electrode. The semiconductor element has: an n-type fifth semiconductor region locally formed between the fourth semiconductor region and the gate electrode on the surface of the third semiconductor region; and An auxiliary electrode is connected to the fifth semiconductor region.

3. The semiconductor device according to claim 1 or 2, characterized in that: The impurity concentration of the fifth semiconductor region is higher than the impurity concentration of the third semiconductor region.

4. The semiconductor device according to claim 3, characterized in that A LOCOS oxide film or a trench oxide film is formed on the surface of the third semiconductor region between a portion connected to the second main electrode and the fifth semiconductor region.

5. A composite semiconductor device, characterized in that: The composite semiconductor element is formed by connecting the second main electrode in the semiconductor element according to claim 1 and the second main electrode in the semiconductor element according to claim 2 .

6. A driving circuit, characterized in that: The driving circuit has a structure in which the auxiliary electrode in the semiconductor element according to claim 1 or 2 is electrically connected to a gate in another semiconductor element.

7. The driving circuit according to claim 6, characterized in that: The drive circuit includes a switch element that provides a signal to a gate of a power control element that controls the supply of power to a load. In the semiconductor element according to claim 1 or 2, the auxiliary electrode is electrically connected to the gate electrode of the switching element.

8. The driving circuit according to claim 6, characterized in that: The drive circuit comprises, on the semiconductor substrate, the semiconductor element according to claim 1 or 2, namely a first semiconductor element and a second semiconductor element of a MOS structure that performs gate driving at a voltage lower than that of the first semiconductor element. The thickness of the insulating film of the first semiconductor element and the thickness of the insulating film of the MOS structure of the second semiconductor element are substantially the same.

9. A driving circuit, characterized in that: The drive circuit controls the power supply to a load connected to a point connecting the low voltage side of the high-side first power control element and the high voltage side of the low-side second power control element. The auxiliary electrode of the semiconductor element according to claim 1 or 2 is connected to a gate of a switching element that outputs a signal to a gate of the first power control element.

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