Structure for improving integration level of GaN n channel and GaN p channel devices and preparation method

Abstract

The invention discloses a structure for improving the integration level of GaN n-channel and p-channel devices and a preparation method, and relates to the technical field of semiconductor device preparation. A high-resistance buffer layer, a GaN channel layer, a barrier layer, a current transmission transition layer, a channel current expansion layer, a current blocking layer and a p-type ohmic contact layer are sequentially formed on a substrate; a current transmission transition layer, a channel current expansion layer, a current blocking layer and a p-type ohmic contact layer are removed through etching of an n-channel region etching mask, an n-channel device preparation region is exposed to manufacture a doped gate control layer, an ohmic contact electrode a and an ohmic contact electrode b are arranged on the left side and the right side of the doped gate control layer, an ohmic contact electrode c is arranged on the p-type ohmic contact layer, and an ohmic contact electrode c is arranged on the p-type ohmic contact layer. And etching the p-type ohmic contact layer, the current blocking layer and a part of the channel current expansion layer, then growing a dielectric layer, and preparing a gate metal layer a and a gate metal layer b in an n-channel device gate metal preparation region and a p-channel gate control region, so that the preparation precision requirement is low, and the current transmission capability of the p-channel device is high.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device technology, and in particular to a structure and a preparation method for improving the integration of GaN n-channel and p-channel devices. Background Art

[0002] GaN power switch devices have the characteristics of high switching speed and low on-resistance, and have important application value in efficient and miniaturized power supply systems. Although GaN power switch devices can achieve high switching speeds, the high parasitic inductance of discrete drive solutions seriously restricts the operating speed of the device. In order to solve this problem, the main solution currently used is the full monolithic integration of GaN drive and power switch. This solution effectively reduces the parasitic inductance between the drive and the power switch, thereby effectively improving the switching speed of GaN power switch devices.

[0003] Due to the high difficulty of p-type doping of GaN materials, existing GaN HEMT devices are all n-channel conductive devices. At present, the scheme for implementing GaN driver integration mainly adopts enhancement-mode GaN HEMT devices and resistor integration or enhancement-mode GaN HEMT devices and depletion-mode GaN HEMT devices to realize logic gate circuits such as inverters. Due to the lack of p-channel electrical devices, it is impossible to form a logic circuit similar to CMOS devices, which leads to the problem of high static power consumption in GaN driver integration schemes. In response to this problem, many research institutions in the world are conducting research on GaN n-channel and p-channel device integration technology, mainly using lateral conduction enhancement-mode n-channel GaN HEMT devices and lateral conduction enhancement-mode p-channel structures for integration. Due to the low hole mobility and low carrier concentration in GaN materials, the output current of GaN p-channel devices and GaN n-channel devices are far apart when lateral conduction devices are integrated, so large-sized GaN p-channel devices and n-channel devices need to be used for current matching, resulting in a large chip area and low integration. In order to improve the output current density of GaN p-channel devices and improve the integration level, the present invention adopts a structure integrating vertical transmission p-channel devices and n-channel devices to effectively realize a CMOS-like integrated structure. By adopting vertical transmission p-channel devices and a structure in which the two devices share a source and drain, the problem of a large area share in the integration of p-channel devices is further reduced, thereby effectively improving the device integration level. Summary of the invention

[0004] Technical issues solved:

[0005] The technical problem that needs to be solved in this application is that high parasitic inductance seriously restricts the working speed of the device, resulting in high static power consumption, large chip area, low integration and other problems in the GaN driver integration solution. A structure and preparation method for improving the integration of GaN n-channel and p-channel devices are provided.

[0006] Technical solution:

[0007] A method for preparing a structure for improving the integration of GaN n-channel and p-channel devices, the steps are as follows:

[0008] Step 1. Form a high-resistance buffer layer on the substrate, form a GaN channel layer on the high-resistance buffer layer, form a barrier layer on the GaN channel layer, form a current transmission transition layer on the barrier layer, form a channel current expansion layer on the current transmission transition layer, form a current blocking layer on the channel current expansion layer, and form a p-type ohmic contact layer on the current blocking layer; etch and remove the current transmission transition layer, the channel current expansion layer, the current blocking layer and the p-type ohmic contact layer above the barrier layer in the n-channel region through an n-channel region etching mask, and leak out the n-channel device preparation region;

[0009] Step 2. Fabricating a doped gate control layer in the n-channel device preparation area by a selective regrowth process;

[0010] Step 3. Prepare ohmic contact electrode a, ohmic contact electrode b and ohmic contact electrode c metal on the etched leaked barrier layer and the p-type ohmic contact layer by evaporation stripping process, wherein the ohmic contact electrode a and the ohmic contact electrode b are respectively arranged on the left and right sides of the doped gate control layer, and the ohmic contact electrode c is arranged on the p-type ohmic contact layer, and an ohmic contact is formed by an alloy;

[0011] Step 4. Etching the p-type ohmic contact layer and the current blocking layer and part of the channel current extension layer through the p-channel gate control region etching mask;

[0012] Step 5. Forming a gate control dielectric layer and a surface protection layer by growing a dielectric layer;

[0013] Step 6. Leaking the n-channel device gate metal preparation area above the doped gate control layer by dielectric etching;

[0014] Step 7. Prepare gate metal layer a and gate metal layer b in the n-channel device gate metal preparation region and the p-channel gate control region respectively by evaporation stripping to form the gates of the n-channel and p-channel devices;

[0015] Step 8. The metal electrodes of the ohmic contact electrode a, the ohmic contact electrode b and the ohmic contact electrode c are exposed through an etching process.

[0016] The present application also discloses a structure for improving the integration of GaNn-channel and p-channel devices obtained by the above-mentioned preparation method, wherein the structure for improving the integration of GaNn-channel and p-channel devices comprises a substrate, a high-resistance buffer layer formed on the substrate, a GaN channel layer formed on the high-resistance buffer layer, and a barrier layer formed on the GaN channel layer; an ohmic contact electrode a, a doped gate control layer, an ohmic contact electrode b, and a current transmission transition layer are sequentially arranged on the barrier layer; a channel current expansion layer, a current blocking layer, and a p-type ohmic contact layer are sequentially arranged on the current transmission transition layer, an ohmic contact electrode c is arranged on the p-type ohmic contact layer, and then a dielectric layer is arranged on the entire structure, a gate metal layer a is arranged on the doped gate control layer, and a gate metal layer b is arranged on the dielectric layer in the p-channel gate control region.

[0017] As a preferred technical solution of the present application: an n-channel carrier transport structure is formed by a barrier layer and a GaN channel layer, a source and a drain electrode of an n-channel device are formed by an ohmic contact electrode a and an ohmic contact electrode b, a gate control structure of an n-channel device is formed by a gate metal layer a and a doped gate control layer, a source and a drain electrode of a p-channel device are formed by an ohmic contact electrode b and an ohmic contact electrode c, a gate control of a p-channel device is realized by the gate metal layer b through a dielectric layer, and a p-channel carrier transport structure is formed by a current transmission transition layer, a channel current expansion layer, a current blocking layer, and a p-type ohmic contact layer arranged from bottom to top.

[0018] As a preferred technical solution of the present application: the substrate and the GaN channel layer are separated by a high-resistance buffer layer, and the substrate is a substrate for realizing epitaxy of GaN material, specifically one of doped or undoped silicon, silicon carbide, gallium nitride, aluminum nitrogen and gallium oxide.

[0019] As a preferred technical solution of the present application: the high-resistance buffer layer is carbon-doped AlGaN, carbon-doped GaN, a composite layer material of carbon-doped AlGaN and GaN, iron-doped AlGaN, iron-doped GaN, a composite layer material of iron-doped AlGaN and GaN, magnesium-doped AlGaN, magnesium-doped GaN, or a composite layer material of magnesium-doped AlGaN and GaN.

[0020] As a preferred technical solution of the present application: the GaN channel layer is an n-type lightly doped GaN material with a doping concentration of 1E16cm -3 -1E17cm -3 .

[0021] As a preferred technical solution of the present application: the current transmission transition layer is a GaN material with a gradient doping concentration, the doping concentration at the interface between the current transmission transition layer and the channel current extension layer is the same as the doping concentration of the channel current extension layer, and the doping concentration gradually decreases toward the interface between the current transmission transition layer and the barrier layer.

[0022] As a preferred technical solution of the present application: the channel current extension layer is p-type doped GaN material with a hole concentration of 1E15cm -3 -3E17cm -3 The current blocking layer is carbon-doped AlGaN material with a thickness of 100-200nm, and the p-type ohmic contact layer is p-type doped GaN material with a hole concentration of 3E17cm -3 -4E19cm -3 .

[0023] As a preferred technical solution of the present application: the doped gate control layer is a p-type GaN or AlGaN doped gate control layer; the hole concentration in the doped gate control layer is 1E17cm -3 -7E18cm -3 .

[0024] As a preferred technical solution of the present application: the ohmic contact electrode and the ohmic contact electrode are Ti single layer, Al single layer, Ti multilayer metal, Al multilayer metal, Ti nitride, Al nitride or Ti / Al multilayer metal.

[0025] Beneficial effects:

[0026] The structure and preparation method for improving the integration of GaN n-channel and p-channel devices described in this application adopt the above technical solution and have the following technical effects compared with the prior art:

[0027] 1. The p-channel device of the present invention adopts a vertical transmission structure, and the transmission path is determined by the epitaxial structure. Compared with the lateral structure, the process preparation accuracy requirement is low, and the p-channel device has a high current transmission capacity;

[0028] 2. The p-channel current transmission path is short, and a large current density can be obtained. At the same time, the source and drain electrodes of n-channel devices and p-channel devices are shared through the current transmission transition structure, which can effectively reduce the high current mismatch ratio and large size of integrated devices in n-channel and p-channel integration, and is conducive to the realization of higher density GaN n-channel and p-channel device monolithic integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of the epitaxial wafer material structure of the present application;

[0030] Figure 2 A schematic diagram of etching and removing part of the material above the barrier layer for this application;

[0031] Figure 3 This is a schematic diagram of the application after forming the gate control layer of the n-channel device;

[0032] Figure 4 This is a schematic diagram of the source-drain metal contacts of the device formed in this application;

[0033] Figure 5 This is a schematic diagram of etching part of the current blocking layer and the p-type ohmic contact layer in the present application;

[0034] Figure 6 A schematic diagram of the surface growth medium of this application;

[0035] Figure 7 A schematic diagram of the present application after forming the gate control metal;

[0036] Figure 8 Schematic diagram of GaN n-channel and p-channel integrated devices with dielectric hole etching completed for this application.

[0037] Explanation of the accompanying drawings: 1. substrate, 2. high-resistance buffer layer, 3. GaN channel layer, 4. barrier layer, 5. current transfer transition layer, 6. channel current extension layer, 7. current blocking layer, 8. p-type ohmic contact layer, 9. doped gate control layer, 10-a. ohmic contact electrode a, 10-b. ohmic contact electrode b, 10-c. ohmic contact electrode c, 11. dielectric layer, 12-a. gate metal layer a, 12-b. gate metal layer b. DETAILED DESCRIPTION

[0038] To make the description more vivid and intuitive, the specific technical solution of the present invention is further described below in conjunction with the accompanying drawings. It should be pointed out that the accompanying drawings are only an embodiment of the present invention and cannot be a limitation of the present invention.

[0039] Embodiment 1:

[0040] A method for preparing a structure for improving the integration of GaN n-channel and p-channel devices, the steps are as follows:

[0041] Step 1. Figure 1 As shown, a carbon-doped high-resistance buffer layer 2 of 200nmAlN / 1μmGaN is grown on a p-type doped silicon substrate 1, and a 200nm 1E16cm -3 A silicon-doped GaN channel layer 3 is formed, and a 10 nm Al 0.1 Ga 0.9 N barrier layer 4, a 100nm concentration of 1E16cm -3 To 1E18cm -3 A 300nm magnesium doped GaN current transmission transition layer 5 is formed on the current transmission transition layer 5. -3 A GaN channel current extension layer 6 is formed, and a 200nm carbon-doped Al 0.05 Ga 0.95 N current blocking layer 7, forming a 100nm magnesium doped 4E19cm-3 GaN p-type ohmic contact layer 8; using conventional photolithography technology, photolithography n-channel etching area, through the n-channel region photoresist etching mask, using chlorine-based ICP etching technology, etching and removing the current transmission transition layer 5, channel current expansion layer 6, current blocking layer 7 and p-type ohmic contact layer 8 above the n-channel region barrier layer 4, leaking out the n-channel device preparation area, and then removing the photoresist mask by organic cleaning, such as Figure 2 As shown;

[0042] Step 2. Grow SiO dielectric on the surface of the n-channel device preparation area through a selective regrowth process, form a regrowth mask for the n-channel device gate control area through photolithography and fluorine-based dry etching technology, and grow 100nm 7E18cm using MOCVD -3 The magnesium-doped p-type GaN-doped gate control layer 9 can be easily removed by BOE from the SiO and GaN materials above the SiO outside the gate control region of the n-channel device. Figure 3 As shown;

[0043] Step 3. Use the evaporation stripping process to evaporate and strip 200nm Ti / Al / Ni / Au metal on the etched leaked barrier layer 4 and the n-channel and p-channel ohmic contact regions on the p-type ohmic contact layer 8 to prepare ohmic contact electrode a 10-a, ohmic contact electrode b 10-b and ohmic contact electrode c 10-c metal, wherein the ohmic contact electrode a 10-a and the ohmic contact electrode b 10-b are respectively arranged on the left and right sides of the doped gate control layer 9, and the ohmic contact electrode c 10-c is arranged on the p-type ohmic contact layer 8, and through 800 degrees rapid annealing, ohmic contacts are formed in the n-channel region and the p-channel region. The result is as shown in FIG. Figure 4 As shown;

[0044] Step 4. Use conventional photolithography technology to make an etching mask for the p-channel gate control region, use chlorine-based dry etching technology to etch the p-type ohmic contact layer 8 and the current blocking layer 7 and part of the channel current expansion layer 6 in the p-channel gate control region, and remove the photoresist mask by organic cleaning, such as Figure 5 As shown;

[0045] Step 5. Use ALD growth method to grow 20nm Al 2 O 3 The dielectric layer 11 forms a gate control dielectric layer and a surface protection layer, such as Figure 6 As shown;

[0046] Step 6. Using conventional photolithography technology, an etching window is opened on the doped gate control layer 9 by dielectric etching, and the dielectric layer 11 in the area is etched using a developer to leak out the n-channel device gate metal preparation area;

[0047] Step 7. Prepare gate metal layer a 12-a and gate metal layer b 12-b by evaporation stripping in the n-channel device gate metal preparation region and the p-channel gate control region respectively, so as to form the gates of the n-channel and p-channel devices, as shown in FIG. Figure 7 As shown;

[0048] Step 8. Use a standard photolithography process to define the window position of the ohmic metal, etch the dielectric layer 11 with a developer, and leak out the metal electrodes of the ohmic contact electrode a 10-a, the ohmic contact electrode b 10-b and the ohmic contact electrode c 10-c, as shown in FIG. Figure 8 shown.

[0049] The above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit the same. There are many practical production methods that can be adopted. All equivalent changes and decorations made according to the claims of the present invention are within the scope of the present invention.

Claims

1. A method for preparing a structure for improving the integration of GaN n-channel and p-channel devices, characterized in that: Here are the steps: Step 1. forming a high-resistance buffer layer (2) on a substrate (1), forming a GaN channel layer (3) on the high-resistance buffer layer (2), forming a barrier layer (4) on the GaN channel layer (3), forming a current transmission transition layer (5) on the barrier layer (4), forming a channel current expansion layer (6) on the current transmission transition layer (5), forming a current blocking layer (7) on the channel current expansion layer (6), and forming a p-type ohmic contact layer (8) on the current blocking layer (7); etching and removing the current transmission transition layer (5), the channel current expansion layer (6), the current blocking layer (7) and the p-type ohmic contact layer (8) above the barrier layer (4) in the n-channel region through an n-channel region etching mask, and leaking out the n-channel device preparation region; Step 2. Fabricating a doped gate control layer (9) in the n-channel device preparation region by a selective regrowth process; Step 3. Using an evaporation stripping process, ohmic contact electrode a (10-a), ohmic contact electrode b (10-b) and ohmic contact electrode c (10-c) metals are prepared on the etched leaked barrier layer (4) and the p-type ohmic contact layer (8), wherein the ohmic contact electrode a (10-a) and the ohmic contact electrode b (10-b) are respectively arranged on the left and right sides of the doped gate control layer (9), and the ohmic contact electrode c (10-c) is arranged on the p-type ohmic contact layer (8), and ohmic contact is formed by alloy; Step 4. Etching the p-type ohmic contact layer (8), the current blocking layer (7) and part of the channel current extension layer (6) through the p-channel gate control region etching mask; Step 5. Forming a gate control dielectric layer and a surface protection layer by growing a dielectric layer (11); Step 6. Leaking the n-channel device gate metal preparation area above the doped gate control layer (9) by dielectric etching; Step 7. Prepare gate metal layer a (12-a) and gate metal layer b (12-b) in the n-channel device gate metal preparation region and the p-channel gate control region respectively by evaporation stripping to form the gates of the n-channel and p-channel devices; Step 8. The metal electrodes of the ohmic contact electrode a (10-a), the ohmic contact electrode b (10-b) and the ohmic contact electrode c (10-c) are exposed through an etching process.

2. A structure for improving the integration of GaN n-channel and p-channel devices obtained by the preparation method of claim 1, characterized in that: The structure for improving the integration degree of GaN n-channel and p-channel devices comprises a substrate (1), a high-resistance buffer layer (2) formed on the substrate (1), a GaN channel layer (3) formed on the high-resistance buffer layer (2), and a barrier layer (4) formed on the GaN channel layer (3); an ohmic contact electrode a (10-a), a doped gate control layer (9), an ohmic contact electrode b (10-b), and a current transmission transition layer (5) are sequentially provided on the barrier layer (4); a channel current expansion layer (6), a current blocking layer (7), and a p-type ohmic contact layer (8) are sequentially provided on the current transmission transition layer (5); an ohmic contact electrode c (10-c) is provided on the p-type ohmic contact layer (8); then a dielectric layer (11) is provided on the entire structure, a gate metal layer a (12-a) is provided on the doped gate control layer (9), and a gate metal layer b (12-b) is provided on the dielectric layer (11) in the p-channel gate control region.

3. The structure for improving the integration of GaN n-channel and p-channel devices according to claim 2, characterized in that: An n-channel carrier transport structure is formed by a barrier layer (4) and a GaN channel layer (3); a source and a drain electrode of an n-channel device are formed by an ohmic contact electrode a (10-a) and an ohmic contact electrode b (10-b); a gate control structure of an n-channel device is formed by a gate metal layer a (12-a) and a doped gate control layer (9); a source and a drain electrode of a p-channel device are formed by an ohmic contact electrode b (10-b) and an ohmic contact electrode c (10-c); a gate control of the p-channel device is achieved by the gate metal layer b (12-b) through a dielectric layer (11); and a p-channel carrier transport structure is formed by a current transport transition layer (5), a channel current expansion layer (6), a current blocking layer (7), and a p-type ohmic contact layer (8) arranged from bottom to top.

4. A structure for improving the integration of GaN n-channel and p-channel devices according to claim 2, characterized in that: The substrate (1) and the GaN channel layer (3) are separated by a high-resistance buffer layer (2); the substrate (1) is a substrate for realizing epitaxy of GaN materials, specifically one of doped or undoped silicon, silicon carbide, gallium nitride, aluminum nitrogen and gallium oxide.

5. The structure for improving the integration of GaN n-channel and p-channel devices according to claim 2, characterized in that: The high resistance buffer layer (2) is carbon-doped AlGaN, carbon-doped GaN, a composite layer material of carbon-doped AlGaN and GaN, iron-doped AlGaN, iron-doped GaN, a composite layer material of iron-doped AlGaN and GaN, magnesium-doped AlGaN, magnesium-doped GaN, or a composite layer material of magnesium-doped AlGaN and GaN.

6. The structure for improving the integration of GaN n-channel and p-channel devices according to claim 2, characterized in that: The GaN channel layer (3) is an n-type lightly doped GaN material with a doping concentration of 1E16 cm -3 -1E17cm -3 .

7. The structure for improving the integration of GaN n-channel and p-channel devices according to claim 2, characterized in that: The current transmission transition layer (5) is a GaN material with a gradually changing doping concentration; the doping concentration at the interface between the current transmission transition layer (5) and the channel current extension layer (6) is the same as the doping concentration of the channel current extension layer (6), and the doping concentration gradually decreases toward the interface between the current transmission transition layer (5) and the barrier layer (4).

8. The structure for improving the integration of GaN n-channel and p-channel devices according to claim 2, characterized in that: The channel current extension layer (6) is made of p-type doped GaN material with a hole concentration of 1E15 cm -3 -3E17m -3 The current blocking layer (7) is a carbon-doped AlGaN material with a thickness of 100-200 nm, and the p-type ohmic contact layer (8) is a p-type doped GaN material with a hole concentration of 3E17 cm -3 -4E19cm -3 .

9. The structure for improving the integration of GaN n-channel and p-channel devices according to claim 2, characterized in that: The doped gate control layer (9) is a p-type GaN or AlGaN doped gate control layer; the hole concentration in the doped gate control layer (9) is 1E17cm -3 -7E18cm -3 .

10. The structure for improving the integration of GaN n-channel and p-channel devices according to claim 2, characterized in that: The ohmic contact electrode (10-a) and the ohmic contact electrode (10-b) are Ti single layer, Al single layer, Ti multilayer metal, Al multilayer metal, Ti nitride, Al nitride or Ti / Al multilayer metal.

Images