Semiconductor device, preparation method of semiconductor device and electronic device

Abstract

The invention discloses a semiconductor device, a preparation method of the semiconductor device and an electronic device, and the semiconductor device comprises a semiconductor substrate which is provided with a first surface and a second surface which are opposite to each other; a plurality of photodiodes formed in the semiconductor substrate; a plurality of quenching resistor structures corresponding to the plurality of photodiodes; and trench isolation structures formed between adjacent photodiodes. The trench isolation structure comprises a deep trench isolation structure which extends into the semiconductor substrate from the first surface, and a first shallow trench isolation structure and a second shallow trench isolation structure which extend into the semiconductor substrate from the second surface. The two shallow trench isolation structures are distributed on the two sides of the deep trench isolation structure and intersect with the deep trench isolation structure in the semiconductor substrate, and a preset distance exists between the bottom of the deep trench isolation structure and the second surface. According to the invention, the electrical isolation between the polycrystalline silicon and the deep trench isolation structure is better, the high-voltage resistance is stronger, and electric leakage is avoided under high working voltage.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for preparing a semiconductor device, and an electronic device. Background Art

[0002] In order to meet the requirements of long detection distance, high ambient background brightness and high driving speed, the image sensor in the vehicle 3D range imaging system is required to have high time resolution and high gain performance, so silicon photomultiplier (SiPM) has become a common image sensor form for vehicle 3D range imaging systems. Among them, the back-illuminated SiPM sensor does not pass through the metal interconnect structure layer, so the amount of incident light that actually enters the photodiode is greater than that of the front-illuminated SiPM sensor.

[0003] The back-illuminated SiPM sensor in the related art will have a large leakage when it is at a higher operating voltage, such as a high voltage exceeding 40V, resulting in the back-illuminated SiPM sensor in the related art being unable to achieve a higher photon detection efficiency, and thus unable to meet the automotive three-dimensional distance imaging system's demand for higher gain performance of the image sensor. Summary of the invention

[0004] In order to solve the problems of the prior art, the embodiments of the present application provide a semiconductor device, a method for manufacturing a semiconductor device, and an electronic device. The technical solution is as follows:

[0005] In one aspect, a semiconductor device is provided, comprising:

[0006] A semiconductor substrate including a first surface and a second surface opposite to each other;

[0007] a plurality of photodiodes formed in the semiconductor substrate for converting photons incident from the first surface to the semiconductor substrate into electrical signals;

[0008] a plurality of quenching resistor structures, corresponding to the plurality of photodiodes, each quenching resistor structure comprising an electrical isolation layer and polysilicon, the electrical isolation layer being formed on the second surface side, the polysilicon being formed on the electrical isolation layer and being electrically connected to the corresponding photodiode through a metal interconnection structure layer;

[0009] A trench isolation structure is formed between adjacent photodiodes, comprising a deep trench isolation structure extending from the first surface into the semiconductor substrate and a first shallow trench isolation structure and a second shallow trench isolation structure extending from the second surface into the semiconductor substrate;

[0010] The first shallow trench isolation structure and the second shallow trench isolation structure are distributed on both sides of the deep trench isolation structure and respectively intersect with the deep trench isolation structure inside the semiconductor substrate, and there is a preset distance between the bottom of the deep trench isolation structure and the second surface.

[0011] In an exemplary embodiment, the first shallow trench isolation structure and the second shallow trench isolation structure each include a shallow trench, a first liner layer and a first light-shielding conductive layer, wherein the first liner layer is formed on the sidewall and bottom of the corresponding shallow trench, and the first light-shielding conductive layer fills the remaining space of the corresponding shallow trench.

[0012] In an exemplary embodiment, the device further includes a first dielectric layer, the first dielectric layer covers the second surface, the electrical isolation layer is located on a side of the first dielectric layer away from the second surface, and the quenching resistor is located on a side of the electrical isolation layer away from the first dielectric layer; the metal interconnection structure layer is formed on the first dielectric layer;

[0013] The first shallow trench isolation structure and the second shallow trench isolation structure respectively penetrate the first dielectric layer and extend from the second surface to the inside of the substrate to a preset depth; the preset depth is greater than or equal to the preset spacing.

[0014] In an exemplary embodiment, the metal interconnect structure layer includes an interlayer dielectric layer and a metal layer located in the interlayer dielectric layer, and the interlayer dielectric layer covers the first dielectric layer and the quenching resistor structure;

[0015] The interlayer dielectric layer has a first contact electrically connected to the quenching resistor in the quenching resistor structure, and a second contact electrically connected to the photodiode corresponding to the quenching resistor structure. A partial structure of the metal layer electrically connects the first contact and the second contact.

[0016] In an exemplary embodiment, the deep trench isolation structure includes a deep trench, a second liner layer and a second light-shielding conductive layer, wherein the second liner layer is formed on the sidewall and bottom of the deep trench, and the second light-shielding conductive layer fills the remaining space of the deep trench.

[0017] In an exemplary embodiment, the inverted pyramid structure further includes an inverted pyramid structure extending from a first area of ​​the first surface to the inside of the semiconductor substrate, wherein the first area is a region for forming a photodiode in the semiconductor substrate; the inverted pyramid structure includes a conical opening with a top facing the second surface and a dielectric material filled in the conical opening;

[0018] The first surface is covered with a second dielectric layer, and the deep trench isolation structure penetrates the second dielectric layer.

[0019] In an exemplary embodiment, it further includes a shallow trench structure formed on the first region of the first surface and extending through the second dielectric layer into the semiconductor substrate, wherein the inverted pyramid structure is located between the deep trench isolation structure and the shallow trench structure;

[0020] The shallow trench structure includes a shallow trench opening and a light-shielding conductive material filled in the shallow trench opening. The light-shielding conductive material is electrically connected to the second light-shielding conductive layer of the deep trench isolation structure through a conductive connection layer.

[0021] In an exemplary embodiment, a carrier wafer is further included, wherein the carrier wafer is bonded to the metal interconnect structure layer.

[0022] In another aspect, a method for preparing a semiconductor device is provided, comprising:

[0023] Providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other, wherein a plurality of photodiodes are formed in the semiconductor substrate;

[0024] On the second surface of the semiconductor substrate, two shallow trench isolation structures are formed between adjacent photodiodes, the shallow trench isolation structures are spaced apart and extend into the semiconductor substrate, and the spacing between adjacent side walls of the two shallow trench isolation structures is less than or equal to the width of the deep trench of the deep trench isolation structure used to isolate the adjacent photodiodes;

[0025] A quenching resistor structure corresponding to each of the photodiodes is formed on the second surface of the semiconductor substrate, wherein the quenching resistor structure comprises an electrical isolation layer and a quenching resistor, wherein the electrical isolation layer is formed on the second surface side, and the quenching resistor is formed on the electrical isolation layer;

[0026] forming a metal interconnect structure layer on the second surface side of the semiconductor substrate, so that the quenching resistor in the quenching resistor structure is electrically connected to the corresponding photodiode through the metal interconnect structure layer;

[0027] On the first surface of the semiconductor substrate, the deep trench isolation structure extending into the interior of the semiconductor substrate is formed between adjacent photodiodes, so that the two shallow trench isolation structures are distributed on both sides of the deep trench isolation structure and respectively intersect with the deep trench isolation structure inside the semiconductor substrate, and there is a preset distance between the bottom of the deep trench isolation structure and the second surface; wherein the deep trench isolation structure and the two shallow trench isolation structures form a trench isolation structure between the adjacent photodiodes.

[0028] In an exemplary embodiment, two shallow trench isolation structures are formed on the second surface of the semiconductor substrate between adjacent photodiodes and are spaced apart from each other and extend into the semiconductor substrate, including:

[0029] forming a first dielectric layer on the second surface of the semiconductor substrate;

[0030] Two shallow trenches are formed between adjacent photodiodes, penetrating the first dielectric layer and extending into the semiconductor substrate; a first preset distance is provided between adjacent side walls of the two shallow trenches, and the first preset distance is smaller than a width of the deep trench;

[0031] forming a first liner layer on the sidewall and bottom of the shallow trench;

[0032] A first light-shielding conductive layer is filled in the remaining space of the shallow trench, and the first light-shielding conductive layer is planarized and stopped at the first dielectric layer.

[0033] In an exemplary embodiment, the deep trench isolation structure extending into the semiconductor substrate is formed between adjacent photodiodes on the first surface of the semiconductor substrate, comprising:

[0034] A deep trench extending into the semiconductor substrate is formed on the first surface of the semiconductor substrate between adjacent photodiodes; a preset spacing is reserved between the bottom of the deep trench and the second surface, and two shallow trench isolation structures formed between the adjacent photodiodes are distributed on both sides of the deep trench and intersect with the deep trench;

[0035] forming a second liner layer on the sidewall and bottom of the deep trench;

[0036] A second light-shielding conductive layer is filled in the remaining space of the deep trench.

[0037] In an exemplary embodiment, before forming the deep trench isolation structure extending into the semiconductor substrate between adjacent photodiodes on the first surface of the semiconductor substrate, the method further includes:

[0038] Forming a tapered opening on a first region of the first surface, with the top of the tapered opening facing the second surface; the first region is a region for forming a photodiode in the semiconductor substrate;

[0039] A dielectric material is filled in the tapered opening, and the tapered opening and the filled dielectric material form an inverted pyramid structure.

[0040] In an exemplary embodiment, forming a second liner layer on the sidewall and the bottom of the deep trench includes:

[0041] Depositing a second dielectric layer on the first surface, the second dielectric layer comprising a first portion extending laterally on the first surface and a second portion extending to the sidewall and bottom of the deep trench; wherein the notch of the deep trench is closed by the first portion, and the second portion forms the second liner layer;

[0042] The filling of the remaining space of the deep trench with the second light-shielding conductive layer comprises: etching the second dielectric layer at the notch of the deep trench to expose the deep trench; and filling the remaining space of the deep trench with the second light-shielding conductive layer.

[0043] In an exemplary embodiment, the method further comprises:

[0044] A shallow trench opening is formed on the first area of ​​the first surface, penetrating the second dielectric layer and extending into the semiconductor substrate; the inverted pyramid structure is located between the deep trench isolation structure and the shallow trench opening;

[0045] Filling the shallow groove opening with a light-shielding conductive material; the shallow groove opening and the filled light-shielding conductive material form a shallow groove structure;

[0046] A conductive connection layer is deposited on the second dielectric layer to electrically connect the second light-shielding conductive layer and the light-shielding conductive material of the shallow groove structure.

[0047] In an exemplary embodiment, after forming a metal interconnect structure layer on the second surface side of the semiconductor substrate, the method further includes:

[0048] providing a carrier wafer;

[0049] The carrier wafer is bonded to the metal interconnect structure layer.

[0050] On the other hand, an electronic device is provided, comprising any one of the aforementioned semiconductor devices.

[0051] The semiconductor device of the embodiment of the present application includes a semiconductor substrate, a plurality of photodiodes formed in the semiconductor substrate, a plurality of quenching resistor structures and a trench isolation structure corresponding to the plurality of photodiodes, each quenching resistor structure includes an electrical isolation layer formed on the second surface side of the semiconductor substrate and polysilicon formed on the electrical isolation layer, the polysilicon is electrically connected to the corresponding photodiode through a metal interconnect structure layer; the trench isolation structure is formed between adjacent photodiodes, including a deep trench isolation structure extending from the first surface of the semiconductor substrate into the semiconductor substrate, with a preset spacing between the deep trench isolation structure and the second surface, and two spaced shallow trench isolation structures extending from the second surface of the semiconductor substrate into the semiconductor substrate, the two shallow trench isolation structures are distributed on both sides of the deep trench isolation structure and intersect with the deep trench isolation structure inside the semiconductor substrate. In this way, when an operating voltage is applied between the polysilicon of the quenching resistor structure and the deep trench isolation structure, the voltage can be blocked by the electrical isolation layer under the polysilicon and the semiconductor substrate of a preset spacing thickness retained between the deep trench isolation structure and the second surface of the semiconductor substrate, thereby making the electrical isolation between the polysilicon and the deep trench isolation structure better, ensuring that the thin film between the polysilicon and the deep trench isolation structure will not be broken down under high voltage, solving the leakage problem of the semiconductor device at high operating voltage (for example, an operating voltage exceeding 40V), so that the semiconductor device can meet the requirements of the automotive three-dimensional range imaging system for higher gain performance of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 This is a schematic diagram of the circuit principle of SiPM;

[0054] Figure 2 is a cross-sectional view of a conventional semiconductor device;

[0055] Figure 3 is a cross-sectional view of a semiconductor device provided in an embodiment of the present application;

[0056] Figure 4 is a cross-sectional view of another semiconductor device provided in an embodiment of the present application;

[0057] Figure 5 is a cross-sectional view of a semiconductor substrate provided in an embodiment of the present application;

[0058] Figure 6ais a cross-sectional view of a semiconductor device during the preparation process provided in an embodiment of the present application;

[0059] Figure 6b is a schematic diagram of a second photoresist for forming deep trenches provided in an embodiment of the present application;

[0060] Figure 6c is a schematic diagram of a first photoresist for forming two shallow trenches spaced apart from each other provided in an embodiment of the present application;

[0061] Figures 7 to 13 It is a cross-sectional view during the preparation process of the semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0063] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe specific objects or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0064] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0065] The basic structural unit of a silicon photomultiplier tube (SiPM) is composed of an avalanche photodiode in series with a quenching resistor working in Geiger mode. Multiple such basic structural units are connected in parallel to form a two-dimensional array and share a power supply terminal and an output terminal to form a SiPM. Figure 1 The figure shows a schematic diagram of the circuit principle of SiPM, where one array outputs a signal as a pixel, and multiple arrays can achieve three-dimensional imaging.

[0066] The back-illuminated SiPM sensor in the related art will have a large leakage when it is at a high working voltage, such as a high voltage exceeding 40V, which causes the back-illuminated SiPM sensor in the related art to be unable to achieve a higher photon detection efficiency, and thus cannot meet the requirements of the automotive three-dimensional range imaging system for image sensors with higher gain performance. The reason why the back-illuminated SiPM sensor has a large leakage at a high working voltage is analyzed in combination with the structure of a semiconductor device.

[0067] See also Figure 2, which is a cross-sectional view of a semiconductor device, wherein a plurality of photodiodes 220 (e.g., single photon avalanche photodiodes) are formed in a substrate 210 of the semiconductor device 200, and polysilicon 230 corresponding to a photodiode 220 is formed on a front side 211 of the substrate 210, and the polysilicon 230 is connected to a photodiode 220 through a metal interconnection structure layer 240 formed on the front side 211, so that the polysilicon 230 serves as a quenching resistor of the photodiode 220 connected thereto, and forms a basic structural unit of the semiconductor device 200 with the photodiode 220. In addition, a deep trench isolation groove 250 extending toward the inside of the substrate 210 and penetrating the substrate 210 is formed on a back side 212 of the substrate 210, and the deep trench isolation groove 250 is used to achieve isolation between adjacent photodiodes, wherein the deep trench isolation groove 250 may be filled with metal tungsten.

[0068] Understandably, in Figure 2 In the semiconductor device shown, in order to realize that the deep trench isolation trench 250 effectively isolates adjacent photodiodes, the deep trench isolation trench 250 needs to penetrate the substrate 210 .

[0069] In order to avoid leakage when applying working voltage between polysilicon 230 and deep trench isolation groove 250, Figure 2 As shown, an electrical isolation layer 260 is usually formed between the polysilicon 230 and the front side 211, and the polysilicon 230 is formed on the electrical isolation layer 260. For example, the material of the electrical isolation layer 260 can be silicon oxide and / or silicon nitride, so that the electrical isolation layer 260 can form electrical isolation between the polysilicon 230 and the deep trench isolation groove 250. Then, when an operating voltage is applied between the polysilicon 230 and the deep trench isolation groove 250, the electrical isolation formed by the electrical isolation layer 260 can block the voltage to avoid leakage.

[0070] However, it is found in actual applications that when a higher operating voltage, for example, a voltage of 40V is applied between the polysilicon 230 and the deep trench isolation groove 250, the electrical isolation formed by the electrical isolation layer 260 cannot block the high voltage of 40V, so that the electrical isolation layer 260 is punctured, thereby generating a large leakage.

[0071] In order to solve the problem that the above semiconductor device generates a large leakage current at a higher operating voltage (such as more than 40V), the present application provides a semiconductor device, see Figure 3 , which is a cross-sectional view of a semiconductor device provided in an embodiment of the present application.

[0072] like Figure 3As shown, the semiconductor device 300 of the embodiment of the present application includes a semiconductor substrate 310, and the semiconductor substrate 310 includes a first surface 311 and a second surface 312 opposite to each other. The first surface 311 corresponds to the back side of the semiconductor substrate 310, and the second surface 312 corresponds to the front side of the semiconductor substrate 310. A metal interconnection structure layer 320 is formed on the second surface 312 side.

[0073] Exemplarily, the constituent material of the semiconductor substrate 310 may be at least one of the following: silicon, a material containing silicon (such as a III-V compound semiconductor material of gallium arsenide (GaAs)), silicon on insulator (SOI), or other types of semiconductor materials capable of generating charges from photons of incident light.

[0074] The semiconductor device 300 further includes a plurality of photodiodes 330 formed in the semiconductor substrate 310 , and the plurality of photodiodes 330 are used to convert photons incident to the semiconductor substrate 310 into electrical signals.

[0075] In a specific implementation, the semiconductor device 300 may be a back-illuminated semiconductor device, that is, incident light is incident on the back side of the semiconductor substrate 310, that is, the first surface 311, and is incident on the semiconductor substrate 310. Then, the plurality of photodiodes 330 in the back-illuminated semiconductor device may be used to convert photons incident on the semiconductor substrate 310 from the first surface 311 into electrical signals.

[0076] The plurality of photodiodes 330 may be arranged in an array in the semiconductor substrate 310. The photodiode 330 is a PN junction photodiode, and illustratively, an N-type doped region may be formed in a P-type semiconductor substrate, and the N-type doped region and the P-type semiconductor substrate constitute a photodiode.

[0077] The semiconductor device 300 further includes a plurality of quenching resistor structures 340 formed on the second surface 312 of the semiconductor substrate 310, and the plurality of quenching resistor structures 340 correspond to the plurality of photodiodes 330. Each quenching resistor structure 340 includes an electrical isolation layer 341 and polysilicon 342, wherein the electrical isolation layer 341 is formed on a portion of the second surface 312 side, the polysilicon 342 is formed on the electrical isolation layer 341, and the polysilicon 342 in one quenching resistor structure 340 is electrically connected to the corresponding photodiode 330 through the metal interconnect structure layer 320, thereby serving as a quenching resistor of the photodiode 330.

[0078] Specifically, the electrical isolation layer 341 may be formed of a material having electrical isolation properties, for example, the constituent material of the electrical isolation layer 341 may be silicon oxide and / or silicon nitride. Exemplarily, the electrical isolation layer 341 may include one or more layers that can achieve electrical isolation, for example, the electrical isolation layer 341 may include a silicon nitride layer and a silicon oxide layer stacked in sequence.

[0079] Specifically, the polysilicon 342 on the electrical isolation layer 341 may be a doped polysilicon material or an undoped polysilicon material. The doping of the polysilicon may change the resistivity of the quenching resistor.

[0080] The semiconductor device 300 further includes a trench isolation structure 350 formed between adjacent photodiodes 330, and the trench isolation structure 350 can achieve isolation between adjacent photodiodes 330. The trench isolation structure 350 includes a deep trench isolation structure 351 extending from the aforementioned first surface 311 into the semiconductor substrate 310 and a first shallow trench isolation structure 3521 and a second shallow trench isolation structure 3522 extending from the aforementioned second surface 312 into the semiconductor substrate 310, wherein the first shallow trench isolation structure 3521 and the second shallow trench isolation structure 3522 are distributed on both sides of the deep trench isolation structure 351 and intersect with the deep trench isolation structure 351 inside the semiconductor substrate 310 respectively.

[0081] Specifically, the spacing between the first sidewall of the first shallow trench isolation structure 3521 and the second sidewall of the second shallow trench isolation structure 3522 is less than or equal to the width of the deep trench of the deep trench isolation structure 351, wherein the first sidewall is a sidewall of the first shallow trench isolation structure 3521 close to the second shallow trench isolation structure 3522, and the second sidewall is a sidewall of the second shallow trench isolation structure 3522 close to the first shallow trench isolation structure 3521. Exemplarily, the spacing between the first sidewall and the second sidewall may be equal to the width of the deep trench of the deep trench isolation structure 351.

[0082] It should be noted that the first shallow trench isolation structure 3521 and the second shallow trench isolation structure 3522 intersect with the deep trench isolation structure 351 inside the semiconductor substrate 310 in order to achieve effective isolation of adjacent photodiodes and avoid crosstalk between adjacent photodiodes.

[0083] It should be noted that there is a preset spacing H between the bottom of the deep trench isolation structure 351 and the second surface 312 of the semiconductor substrate 310. That is to say, the deep trench isolation structure 351 in the embodiment of the present application does not penetrate the semiconductor substrate 310, but a semiconductor substrate material with a preset spacing H thickness is reserved between the bottom of the deep trench isolation structure 351 and the aforementioned second surface 312. For example, when the material of the semiconductor substrate 310 is silicon Si, the semiconductor device 300 in the embodiment of the present application reserves silicon Si with a preset spacing H thickness between the bottom of the deep trench isolation structure 351 and the aforementioned second surface 312.

[0084] It can be understood that when an operating voltage is applied between the polysilicon 342 and the deep trench isolation structure 351 of the semiconductor device 300 in the embodiment of the present application, not only the electrical isolation layer 341 corresponding to the polysilicon 342 will play a role in electrical isolation, but also the semiconductor substrate with a preset spacing H thickness retained between the bottom of the deep trench isolation structure 351 and the aforementioned second surface 312 will also play a role in electrical isolation, thereby enabling better electrical isolation between the polysilicon 342 and the deep trench isolation structure 351, ensuring that the thin film between the polysilicon 342 and the deep trench isolation structure 351 will not be penetrated under a higher operating voltage, such as a high voltage exceeding 40V, and thus the semiconductor device of the embodiment of the present application can not only prevent crosstalk between adjacent photodiodes and achieve effective isolation, but also has a stronger ability to resist high voltages, and can avoid leakage problems under high operating voltages, thereby greatly improving the performance of the semiconductor device of the embodiment of the present application under high operating voltages, so that the semiconductor device can meet the requirements of the automotive three-dimensional range imaging system for image sensors with higher gain performance.

[0085] In a specific implementation, the preset spacing H between the bottom of the deep trench isolation structure 351 and the second surface 312 can be set based on the actual need to resist high voltage. Exemplarily, the preset spacing H can range from 0.1 μm to 2 μm. Taking the material of the semiconductor substrate as Si as an example, usually the intrinsic Si with a thickness of about 100 nm can withstand a voltage of 3V. Based on this characteristic and combined with the actual need to resist high voltage, the specific value of the preset spacing H can be set.

[0086] In some exemplary embodiments, the first shallow trench isolation structure 3521 and the second shallow trench isolation structure 3522 both include a shallow trench 352a, a first liner layer 352b and a first light-shielding conductive layer 352c, wherein the first liner layer 352b is formed on the sidewall and bottom of the shallow trench 352a, and the first light-shielding conductive layer 352c fills the remaining space of the shallow trench 352a.

[0087] Specifically, the constituent material of the first liner layer 352b can be an insulating material, such as silicon oxide, silicon oxynitride, etc. The formation of the first liner layer 352b on the sidewall and bottom of the shallow trench 352a can repair the damage to the edge surface of the shallow trench 352a when etching the semiconductor substrate 310 to form the shallow trench 352a, and can also have the effect of electrical isolation.

[0088] Specifically, the first light-shielding conductive layer 352c needs to isolate photons, so the light transmittance of the material used to constitute the first light-shielding conductive layer 352c should be lower than the light transmittance of the semiconductor substrate 310 and the first pad layer 352b. Exemplarily, the light transmittance of the first light-shielding conductive layer 352c is lower than the light transmittance of silicon and silicon dioxide, and the constituent material of the first light-shielding conductive layer 352c in the embodiment of the present application may be tungsten.

[0089] In an exemplary embodiment, continue to refer to Figure 3 The semiconductor device 300 may further include a first dielectric layer 360 formed on the second surface 312, the first dielectric layer 360 covers the second surface 312, wherein the electrical isolation layer 341 of each quenching resistor structure 340 is located on the side of the first dielectric layer 360 away from the second surface 312, and the corresponding polysilicon 342 is located on the side of the electrical isolation layer 341 away from the first dielectric layer 360, the metal interconnection structure layer 320 is formed on the first dielectric layer 360, and the first shallow trench isolation structure 3521 and the second shallow trench isolation structure 3522 respectively penetrate the first dielectric layer 360 and extend from the aforementioned second surface 312 to the inside of the semiconductor substrate 310 to a preset depth, and the preset depth is greater than or equal to the aforementioned preset spacing H. In a specific implementation, the preset depth of the shallow trench 352a extending in the semiconductor substrate is 0.1μm-3μm.

[0090] Exemplarily, the constituent material of the first dielectric layer 360 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. The top surfaces of the first shallow trench isolation structure 3521 and the second shallow trench isolation structure 3522 are flush with a surface of the first dielectric layer 360 away from the aforementioned second surface 312.

[0091] In some exemplary embodiments, the metal interconnect structure layer 320 may include an interlayer dielectric layer 321 and a metal layer 322 located in the interlayer dielectric layer 321, wherein the interlayer dielectric layer 321 covers the aforementioned first dielectric layer 360 and the quenching resistor structure 340. A first contact 3231 electrically connected to the polysilicon 342 in the quenching resistor structure 340 and a second contact 3232 electrically connected to the photodiode 330 corresponding to the quenching resistor structure 340 are formed in the interlayer dielectric layer 321, and a partial structure of the metal layer 322 electrically connects the first contact 3231 and the second contact 3232, thereby realizing electrical connection between the polysilicon 342 in the quenching resistor structure 340 and the corresponding photodiode 330.

[0092] In a specific implementation, the constituent material of the interlayer dielectric layer 321 may be silicon nitride, silicon carbide or a mixture thereof, such as silicon carbide nitride, silicon oxynitride, etc. The constituent material of the metal layer 322 may include tungsten, copper or aluminum copper, etc. The first contact 3231 may be formed by etching the interlayer dielectric layer 321 to form a quenching resistor contact hole extending to the polysilicon 342 in the quenching resistor structure 340, and then filling the quenching resistor contact hole with a conductive material to form the first contact 3231; similarly, the second contact 3232 may be formed by etching the interlayer dielectric layer 321 to form a photodiode contact hole extending to the photodiode 330, and then filling the photodiode contact hole with a conductive material to form the second contact 3232.

[0093] In actual applications, the quenching resistor contact hole and the photodiode contact hole are formed by etching in the same step. Therefore, the step height difference between the electrical isolation layer 341 in the quenching resistor structure 340 and the second surface 312 of the semiconductor substrate 310 must not be too large. If the step height difference between the electrical isolation layer 341 and the second surface 312 is too large, then during the contact hole etching process, the etching will reach the polysilicon 342 before the second surface 312 is etched. When etching reaches the second surface 312, a lot of polysilicon 342 will be etched away, making the contact hole etching process very difficult to implement and resulting in a lack of a window for the contact hole etching process, which makes mass production impossible.

[0094] In the semiconductor device of the embodiment of the present application, the trench isolation structure in the semiconductor device realizes the isolation of adjacent photodiodes, and at the same time, utilizes the semiconductor substrate with a preset spacing thickness retained between the bottom of the deep trench isolation structure and the front side surface (i.e., the second surface) of the semiconductor substrate to improve the high-voltage resistance between the polysilicon and the deep trench isolation structure, thereby not changing the step height difference between the electrical isolation layer 341 and the second surface 312 of the semiconductor substrate 310, thereby effectively avoiding the adverse effect of the excessive step height difference between the electrical isolation layer 341 and the second surface 312 of the semiconductor substrate 310 on the subsequent contact hole etching process.

[0095] Exemplarily, a silicon nitride layer (not shown) can also be formed between the interlayer dielectric layer 321 and the first dielectric layer 360, and the silicon nitride layer covers the first dielectric layer 360 and the quenching resistor structure 340. The interlayer dielectric layer 321 is formed on the silicon nitride layer. The silicon nitride layer can be used to further improve the high-voltage resistance of the semiconductor device.

[0096] In an exemplary embodiment, the semiconductor device 300 of the embodiment of the present application further includes a carrier wafer 370, which is bonded to the side of the metal interconnect structure layer 320 away from the second surface 312 to provide support. The carrier wafer 370 can be an organic glass wafer, an inorganic glass wafer, a resin wafer, a semiconductor material wafer, an oxide crystal wafer, a ceramic wafer, a metal wafer, an organic plastic wafer, an inorganic oxide wafer or a ceramic material wafer.

[0097] In a specific implementation, the bonding between the carrier wafer 370 and the metal interconnect structure layer 320 may be achieved by one or more bonding layers, adhesives, or bonding processes (such as fusion bonding).

[0098] In an exemplary embodiment, the deep trench isolation structure 351 includes a deep trench 351a, a second liner layer 351b and a second light-shielding conductive layer 351c, wherein the second liner layer 351b is formed on the sidewall and bottom of the deep trench 351a, and the second light-shielding conductive layer 351c fills the remaining space of the deep trench 351a.

[0099] The aspect ratio of the deep trench 351 a is 5:1 to 20:1.

[0100] Specifically, the constituent material of the second liner layer 351b may be an insulating material, such as silicon oxide, silicon oxynitride, etc. Forming the second liner layer 351b on the sidewall and bottom of the deep trench 351a can repair the damage to the edge surface of the deep trench 351a when etching the semiconductor substrate 310 to form the deep trench 351a, and can also achieve the effect of electrical isolation.

[0101] Specifically, the second light-shielding conductive layer 351c needs to isolate photons, so the light transmittance of the material used to constitute the second light-shielding conductive layer 351c should be lower than the light transmittance of the semiconductor substrate 310 and the second pad layer 351b. Exemplarily, the light transmittance of the second light-shielding conductive layer 351c is lower than the light transmittance of silicon and silicon dioxide, and the constituent material of the second light-shielding conductive layer 351c in the embodiment of the present application can be tungsten.

[0102] In an exemplary embodiment, in order to improve the photon detection efficiency, Figure 3 Based on the example of the semiconductor device shown, the embodiment of the present application also provides a cross-sectional view of another semiconductor device. Figure 4 As shown, the semiconductor device 400 also includes an inverted pyramid structure 410 extending from a first area of ​​a first surface 311 of the semiconductor substrate 310 to the interior of the semiconductor substrate 310, the first surface 311 of the semiconductor substrate 310 is covered with a second dielectric layer 420, and the deep trench 351a of the deep trench isolation structure 351 penetrates the second dielectric layer 420.

[0103] The first region is a region for forming a photodiode in the semiconductor substrate. The inverted pyramid structure 410 includes a tapered opening 411 with its top facing the second surface 312 of the semiconductor substrate 310 and a dielectric material 412 filled in the tapered opening 411 .

[0104] The depth of the tapered opening 411 is 0.1 μm-2 μm.

[0105] Exemplarily, the dielectric material 412 filled in the tapered opening 411 may be an oxide, such as silicon oxide, silicon oxynitride, or the like.

[0106] Exemplarily, the second dielectric layer 420 may be made of insulating material, such as silicon oxide, silicon oxynitride, etc. The second dielectric layer 420 in the embodiment of the present application may be formed by the second liner layer 351b extending upward from the deep trench 351a to above the first surface 311 and extending laterally along the first surface 311.

[0107] In a specific implementation, when the semiconductor substrate 310 has, for example <100> Crystal direction, <110> Crystalline <111> When the semiconductor substrate 310 is crystalline silicon of at least one crystal orientation, an etching process is used to etch the semiconductor substrate 310. Due to different densities of different crystal orientations, the etching rates of the etching process are different between different crystal orientations, thereby forming a side wall of the tapered opening 411 through the etching process.

[0108] In the above embodiment, an inverted pyramid structure is formed in the first region of the first surface of the semiconductor substrate. The tapered opening of the inverted pyramid structure can increase the number of photons incident from the first region, thereby improving the photon detection efficiency of the semiconductor device.

[0109] In an exemplary embodiment, see Figure 4 The semiconductor device 400 further includes a shallow trench structure 430, which is formed on the first region of the first surface 311 of the semiconductor substrate 310 and extends through the second dielectric layer 420 to the inside of the semiconductor substrate 310, and the inverted pyramid structure 410 is located between the deep trench isolation structure 351 and the shallow trench structure 430.

[0110] The shallow trench structure 430 includes a shallow trench opening 431 and a light-shielding conductive material 432 filled in the shallow trench opening 431, and the light-shielding conductive material 432 is electrically connected to the second light-shielding conductive layer 351c of the deep trench isolation structure 351 through a conductive connection layer 440, so that the required potential can be introduced into the deep trench isolation structure 351 through the shallow trench structure 430 and the conductive connection layer 440.

[0111] Exemplarily, the distance between the shallow trench opening 431 and the deep trench 351 a is 5-15 μm. The depth of the shallow trench opening 431 is 0.1 μm-3 μm.

[0112] It can be understood that in order to protect the conductive connection layer 440 , a protective layer 450 may be formed on the conductive connection layer 440 , and the material constituting the protective layer 450 may be an insulating material.

[0113] The present application also provides a method for manufacturing a semiconductor device for implementing the present application embodiment. Figures 5 to 13 The method for preparing the semiconductor device according to the embodiment of the present application is described in detail.

[0114] See also Figure 5 , providing a semiconductor substrate 510, the semiconductor substrate 510 includes a first surface 511 and a second surface 512 opposite to each other, and a plurality of photodiodes 520 ( Figure 5 Only two adjacent ones are shown in FIG.

[0115] The constituent material of the semiconductor substrate 510 can be at least one of the following: silicon, a material containing silicon (such as III-V compound semiconductor materials of gallium arsenide (GaAs)), silicon on insulator (Silicon On Insulator, SOI), or other types of semiconductor materials that can generate charges from photons of incident light.

[0116] A plurality of photodiodes 520 may be arranged in an array in the semiconductor substrate 510. The photodiode 520 may be specifically formed by: performing ion implantation on a region of the semiconductor substrate 510 where the photodiode 520 is to be formed, so as to form a doped region having a doping type opposite to that of the semiconductor substrate 510, and the doped region and the semiconductor substrate 510 constitute the photodiode 520. For example, an N-type doped region may be formed in a P-type semiconductor substrate, and the N-type doped region and the P-type semiconductor substrate constitute a photodiode.

[0117] Next, see Figure 6aOn the second surface 512 of the semiconductor substrate 510, two shallow trench isolation structures 531 are formed between adjacent photodiodes 520, and the two shallow trench isolation structures 531 are spaced apart and extend into the interior of the semiconductor substrate 510. The spacing between adjacent side walls of the two shallow trench isolation structures 531 is less than or equal to the width of the deep trench of the deep trench isolation structure 532 used to isolate the adjacent photodiodes.

[0118] In a specific implementation, a first photolithography plate is used in combination with an etching process to form the two spaced-apart shallow trench isolation structures 531, wherein the first photolithography plate defines the positions and sizes of shallow trench etching windows corresponding to the two spaced-apart shallow trench isolation structures, and requires that the spacing between the shallow trench etching windows corresponding to the two spaced-apart shallow trench isolation structures needs to be less than or equal to the width of the deep trench etching window corresponding to the subsequent deep trench isolation structure, and the deep trench etching window defines a predetermined deep trench to be formed between two adjacent photodiodes.

[0119] Figure 6b The figure shows the position schematic diagram of the deep trench etching window corresponding to the deep trench isolation structure defined by the second photomask. The second photomask 620 indicates that the deep trench etching window 603 is located between the regions 604 corresponding to two adjacent photodiodes, and the width of the deep trench etching window 603 is W.

[0120] like Figure 6c The figure shows a schematic diagram of the positions of the shallow trench etching windows corresponding to the two shallow trench isolation structures spaced apart by the first photomask, wherein the first photomask 610 indicates that the shallow trench etching window 601 corresponding to the first shallow trench isolation structure and the shallow trench etching window 602 corresponding to the second shallow trench isolation structure are spaced apart between the regions 604 corresponding to two adjacent photodiodes, and the spacing distance S between the two shallow trench etching windows 601 and 602 spaced apart is less than or equal to the width W of the deep trench etching window 603.

[0121] In an exemplary embodiment, a method for forming two shallow trench isolation structures 531 spaced apart and extending into the interior of the semiconductor substrate 510 between adjacent photodiodes 520 on the second surface 512 of the semiconductor substrate 510 may include: forming a first dielectric layer 540 on the second surface 512 of the semiconductor substrate 510; using the aforementioned first photolithography to form two spaced apart shallow trenches 531a between adjacent photodiodes, which penetrate the first dielectric layer 540 and extend into the semiconductor substrate 510; forming a first liner layer 531b on the sidewalls and bottom of the shallow trench 531a; filling the remaining space of the shallow trench 531a with a first light-shielding conductive layer 531c, flattening the first light-shielding conductive layer 531c, and stopping at the first dielectric layer 540.

[0122] For example, the first dielectric layer 540 may be formed by chemical vapor deposition, atomic layer deposition, thermal oxidation, or the like.

[0123] Exemplarily, the two shallow grooves 531a spaced apart from each other may be formed by: forming a photoresist layer on the first dielectric layer 540, and then using the aforementioned first photoresist to transfer the positions and sizes of the two shallow grooves spaced apart to the photoresist layer to obtain a patterned photoresist layer, wherein the patterned photoresist layer has an opening that exposes a portion of the first dielectric layer; then, using the patterned photoresist layer as a mask, sequentially etching the first dielectric layer 540 and a portion of the semiconductor substrate 510 to form two shallow grooves 531a spaced apart from each other, wherein the shallow grooves 531a are located between adjacent photodiodes; and then, removing the remaining photoresist layer.

[0124] The openings in the patterned photoresist layer allow one or more etchants to be applied during the etching process to remove portions of the first dielectric layer and / or the semiconductor substrate 510, while the patterned photoresist layer protects or shields the portions of the first dielectric layer and / or the semiconductor substrate 510 covered by the patterned photoresist layer. The etching may be performed by dry etching or wet etching, wherein the dry etching process may be reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may also be used.

[0125] The remaining photoresist layer can be removed by ashing or wet stripping.

[0126] The depth of the shallow trench 531a in the semiconductor substrate 510 can be set in combination with the preset thickness of the semiconductor substrate to be retained, and the depth of the shallow trench 531a in the semiconductor substrate 510 is required to be greater than or equal to the preset thickness. It should be noted that the preset thickness refers to the preset spacing H retained between the bottom of the subsequent deep trench isolation structure and the second surface 512.

[0127] The first liner layer 531 b may be formed by chemical vapor deposition, atomic layer deposition, thermal oxidation, or the like.

[0128] The first light-shielding conductive layer 531c can be obtained by depositing a light-shielding conductive material, such as metal tungsten, on the second surface 512. The planarization can be performed by chemical mechanical polishing.

[0129] Next, see Figure 7A quenching resistor structure 550 corresponding to each photodiode 520 is formed on the second surface 512 side of the semiconductor substrate 510, and the quenching resistor structure 550 includes an electrical isolation layer 551 and polysilicon 552. The electrical isolation layer 551 is formed on the second surface 512 side, and the polysilicon 552 is formed on the electrical isolation layer 551.

[0130] A quenching resistor structure corresponding to each photodiode can be formed in the area of ​​the second surface 512 predetermined for forming the quenching resistor structure 550. Specifically: an initial electrical isolation layer (not shown) covering the first dielectric layer 540 can be formed thereon, such as forming a silicon nitride layer and a silicon oxide layer stacked in sequence; then a patterned photoresist layer is formed on the initial electrical isolation layer, and the patterned photoresist layer defines an area for forming the quenching resistor structure 550; then, using the patterned photoresist layer as a mask, the initial electrical isolation layer is etched until the first dielectric layer 540 is exposed, and the remaining initial electrical isolation layer that has not been etched becomes an electrical isolation layer 551; then, the remaining photoresist layer is removed; then, polysilicon 552 is deposited on each electrical isolation layer 551.

[0131] Next, see Figure 8 , a metal interconnection structure layer 560 is formed on the second surface 512 of the semiconductor substrate 510 , so that the polysilicon 552 in the quenching resistor structure 550 is electrically connected to the corresponding photodiode 520 through the metal interconnection structure layer 560 .

[0132] In an exemplary embodiment, the method for forming the metal interconnect structure layer 560 on the second surface 512 of the semiconductor substrate 510 may include: forming an interlayer dielectric layer 561 on the first dielectric layer 540, the interlayer dielectric layer 561 covering the first dielectric layer 540 and the quenching resistor structure 550; then, forming contact holes in the interlayer dielectric layer 561 by a contact hole etching process, including a quenching resistor contact hole extending to the polysilicon and a photodiode contact hole extending to the photodiode; then, filling the contact holes with a conductive material, The contact hole and the conductive material filled in the contact hole form corresponding contacts, namely, a first contact 5631 electrically connected to the polysilicon 552 in the quenching resistor structure 550 and a second contact 5632 electrically connected to the photodiode 520 corresponding to the quenching resistor structure 550; thereafter, a metal layer 562 is formed on the interlayer dielectric layer 561. Specifically, metal can be deposited on the interlayer dielectric layer 561 and etched to obtain the metal layer 562, and a partial structure of the metal layer 562 is electrically connected to the first contact 5631 and the second contact 5632.

[0133] In an exemplary embodiment, after forming the metal interconnect structure layer 560, the carrier wafer 570 may be bonded on the metal interconnect structure layer 560. Exemplarily, the carrier wafer 570 may be bonded on the metal interconnect structure layer 560 using a fusion bonding process.

[0134] At this point, the relevant process treatment on the second surface 512 of the semiconductor substrate 510, i.e. the front side, is completed (which can be called the front-end processing process), and then the semiconductor substrate 510 is flipped over so that the back-end processing process can be performed on the first surface 511, i.e. the back side, of the semiconductor substrate 510.

[0135] Next, see Fig. 9 On the first surface 511 of the semiconductor substrate 510, a deep trench isolation structure 532 extending into the interior of the semiconductor substrate is formed between adjacent photodiodes 520, so that the two shallow trench isolation structures that have been formed are distributed on both sides of the deep trench isolation structure 532 and intersect with the deep trench isolation structure 532 inside the semiconductor substrate 510 respectively, and there is a preset spacing H between the bottom of the deep trench isolation structure 532 and the second surface 512.

[0136] In the embodiment of the present application, the deep trench isolation structure 532 and the shallow trench isolation structures 531 distributed on both sides thereof are referred to as trench isolation structures 530 .

[0137] In an exemplary embodiment, the method for forming the above-mentioned deep trench isolation structure 532 includes: forming a deep trench 532a extending into the interior of the semiconductor substrate 510 between adjacent photodiodes 520 on the first surface 511 of the semiconductor substrate 510; forming a second liner layer 532b on the sidewalls and bottom of the deep trench 532a; and filling a second light-shielding conductive layer 532c in the remaining space of the deep trench 532a.

[0138] Exemplarily, the method for forming the above-mentioned deep groove 532a can be: using the aforementioned second photoresist to form a patterned photoresist layer on the first surface 511, the patterned photoresist layer defines the position and size of the predetermined deep groove; etching the semiconductor substrate 510 using the patterned photoresist layer as a mask to form a deep groove 532a extending into the interior of the semiconductor; and removing the remaining photoresist layer.

[0139] The etching can be performed by dry etching or wet etching, wherein the dry etching process can be reactive ion etching, ion beam etching, plasma etching, laser ablation or any combination of these methods. A single etching method can also be used, or more than one etching method can also be used.

[0140] In the process of etching the semiconductor substrate 510 to form the deep groove 532a, the etching time can be controlled to ensure that the semiconductor substrate material of the preset spacing H thickness is retained between the bottom of the deep groove 532a and the second surface 512. Specifically, the required etching depth can be determined based on the difference between the thickness of the semiconductor substrate 510 to be etched and the preset spacing H, and then the preset etching time is calculated based on the required etching depth and the etching rate. Then, in the process of etching the semiconductor substrate to form the deep groove 532a, the etching time is recorded, and the etching is stopped when the etching time reaches the above-mentioned preset etching time. When the etching is stopped, the bottom of the deep groove 532a obtained has a preset spacing with the second surface 512, and the semiconductor substrate of the preset spacing H thickness can be retained without being etched.

[0141] It can be understood that since the shallow trench 531a and the deep trench 532a in the trench isolation structure 530 are respectively etched from two opposite surfaces of the semiconductor substrate 510 to the interior of the semiconductor substrate, and the etching depth of the shallow trench 531a inside the semiconductor substrate 510 is greater than or equal to the above-mentioned preset spacing H, and the spacing between the adjacent side walls of the two shallow trenches 531a is less than or equal to the width of the deep trench 532a, the deep trench 532a obtained by controlling the etching time based on the above-mentioned etching can ensure that the deep trench 532a intersects with the shallow trench 531a in the semiconductor substrate 510.

[0142] In the case where the semiconductor device of the embodiment of the present application is configured to sense light incident from the first surface 511 of the semiconductor substrate 510, as shown in FIG. Fig.10 As shown, the photodiode 520 in the semiconductor substrate 510 can be used to convert photons incident to the semiconductor substrate 510 along the direction 100 into electrical signals.

[0143] Exemplarily, in order to allow light to be incident on the photodiode 520 in the semiconductor substrate 510 through the first surface 511 of the semiconductor substrate 510, the semiconductor substrate 510 may be thinned before forming the deep trench 532a. In a specific implementation, the first surface 511 of the semiconductor substrate 510 may be etched to reduce the thickness of the semiconductor substrate, and the first surface 511 of the semiconductor substrate 510 may be mechanically ground to reduce the thickness of the semiconductor substrate 510.

[0144] The second liner layer 532 b may be formed by chemical vapor deposition, atomic layer deposition, thermal oxidation, or the like.

[0145] The second light-shielding conductive layer 532c can be obtained by depositing a light-shielding conductive material, such as metal tungsten, on the first surface 511. In some embodiments, after forming the second light-shielding conductive layer 532c, a planarization process can be performed to remove excess light-shielding conductive material.

[0146] In an exemplary embodiment, when the semiconductor substrate 510 has, for example, <100> Crystal direction, <110> Crystalline <111> When the crystalline silicon has at least one of the crystal orientations, refer to Fig.10 Before forming the deep trench isolation structure 532, the preparation method may further include: forming a conical opening 580 on the first area 511a of the first surface 511, the top of the conical opening 580 faces the second surface 512, and the first area 511a is a region for forming a photodiode 520 in the semiconductor substrate 510; then, filling the conical opening 580 with a dielectric material, and the conical opening 580 and the filled dielectric material form an inverted pyramid structure.

[0147] Specifically, the dielectric material filled in the tapered opening 580 includes silicon oxide and / or silicon oxynitride.

[0148] Exemplarily, the formation of the conical opening 580 can be achieved by forming a patterned photoresist layer on the first surface 511, wherein the patterned photoresist layer defines the position and size of the predetermined conical opening 580, and then etching the semiconductor substrate 510 using the patterned photoresist layer as a mask to form the conical opening 580 with the top facing the second surface 512 of the semiconductor substrate; thereafter, removing the remaining photoresist layer.

[0149] Due to the different densities of different crystal orientations of the semiconductor substrate, the etching rates of different crystal orientations are different when etching the semiconductor substrate, so that a tapered opening 581 can be formed by the etching process.

[0150] In an exemplary embodiment, after the inverted pyramid structure is formed on the first surface 511, a deep groove 532a may be formed on the first surface 511. Then, as shown in FIG. Fig.11 As shown, the method for forming a second substrate layer 532b on the sidewall and bottom of the deep trench 532a may include: depositing a second dielectric layer 590 on the first surface 511, the second dielectric layer 590 including a first portion 591 extending laterally on the first surface 511 and a second portion 592 extending to the sidewall and bottom of the deep trench 532a; wherein the notch of the deep trench 532a is closed by the first portion 591, and the second portion 592 forms the second liner layer 532b.

[0151] Then, if Fig.12As shown, the method of filling the remaining space of the deep trench 532a with the second light-shielding conductive layer 532c may include: etching the second dielectric layer at the notch of the deep trench to expose the deep trench 532a, and filling the remaining space of the exposed deep trench 532a with the second light-shielding conductive layer 532c.

[0152] In the above embodiment, after the inverted pyramid structure is formed, in order to avoid the subsequent filling of the second light-shielding conductive layer 532c into the inverted pyramid structure, after the deep groove 532a is formed, the second dielectric layer 590 is first deposited on the first surface 511, and the second dielectric layer 590 extends to the side wall and the bottom of the deep groove 532a to form a substrate layer of the deep groove 532a. At the same time, the second dielectric layer 590 layer will also seal the deep groove 532a, and then the second light-shielding conductive layer 532c is filled after the deep groove 532a is opened. This can prevent the material of the second light-shielding conductive layer from being filled into the inverted pyramid structure and affecting the photon detection efficiency while forming the deep trench isolation structure.

[0153] In an exemplary embodiment, after forming the deep trench isolation structure 532, as shown in FIG. Fig.13 As shown, the preparation method may also include: forming a shallow groove opening 1310 on the first area 511a of the first surface 511, which penetrates the aforementioned second dielectric layer 590 and extends into the semiconductor substrate, wherein the aforementioned inverted pyramid structure is located between the deep trench isolation structure 532 and the shallow groove opening 1310; then, filling the shallow groove opening 1310 with a light-shielding conductive material, and the shallow groove opening 1310 and the filled light-shielding conductive material form a shallow groove structure; then, depositing a conductive connection layer 1320 on the second dielectric layer 590 to electrically connect the second light-shielding conductive layer 532a with the light-shielding conductive material of the shallow groove structure.

[0154] Exemplarily, a method for forming a shallow groove opening 1310 on the first area 511a of the first surface 511 that penetrates the aforementioned second dielectric layer 590 and extends into the semiconductor substrate 510 may be: forming a patterned photoresist layer on the second dielectric layer 590, wherein the patterned photoresist layer defines a predetermined position and size for forming the shallow groove opening 1310; and sequentially etching the second dielectric layer 590 and a portion of the semiconductor substrate 510 using the patterned photoresist layer as a mask to form a shallow groove opening 1310 that penetrates the second dielectric layer 590 and extends into the semiconductor substrate 510.

[0155] In some other embodiments, after the second light shielding conductive layer 532c and the shallow groove structure are electrically connected, a protective layer 1330 covering the conductive connection layer 1320 may be formed on the second dielectric layer 590. For example, the material of the protective layer 1330 may be silicon oxide and / or silicon oxynitride.

[0156] Correspondingly, an embodiment of the present application further provides an electronic device, which includes any one of the semiconductor devices described above in the embodiments of the present application.

[0157] Since the semiconductor device has better working performance, the electronic device adopts the semiconductor device, which correspondingly improves the performance of the electronic device. The electronic device can be any electronic product or equipment such as a mobile phone, a tablet computer, a laptop, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a PSP, etc., or an intermediate product having the semiconductor device, such as a device motherboard having the semiconductor device.

[0158] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor substrate including a first surface and a second surface opposite to each other; a plurality of photodiodes formed in the semiconductor substrate; a plurality of quenching resistor structures, corresponding to the plurality of photodiodes, each quenching resistor structure comprising an electrical isolation layer and polysilicon, the electrical isolation layer being formed on the second surface side, the polysilicon being formed on the electrical isolation layer and being electrically connected to the corresponding photodiode through a metal interconnection structure layer; A trench isolation structure is formed between adjacent photodiodes, comprising a deep trench isolation structure extending from the first surface into the semiconductor substrate and a first shallow trench isolation structure and a second shallow trench isolation structure extending from the second surface into the semiconductor substrate; The first shallow trench isolation structure and the second shallow trench isolation structure are distributed on both sides of the deep trench isolation structure and respectively intersect with the deep trench isolation structure inside the semiconductor substrate, and there is a preset distance between the bottom of the deep trench isolation structure and the second surface.

2. The semiconductor device according to claim 1, wherein: The first shallow trench isolation structure and the second shallow trench isolation structure both include a shallow trench, a first liner layer and a first light-shielding conductive layer, the first liner layer is formed on the sidewall and bottom of the corresponding shallow trench, and the first light-shielding conductive layer fills the remaining space of the corresponding shallow trench.

3. The semiconductor device according to claim 1, wherein: It also includes a first dielectric layer, the first dielectric layer covers the second surface, the electrical isolation layer is located on a side of the first dielectric layer away from the second surface, and the polysilicon is located on a side of the electrical isolation layer away from the first dielectric layer; The metal interconnect structure layer is formed on the first dielectric layer; The first shallow trench isolation structure and the second shallow trench isolation structure respectively penetrate the first dielectric layer and extend from the second surface to the inside of the semiconductor substrate to a preset depth; the preset depth is greater than or equal to the preset spacing.

4. The semiconductor device according to claim 3, characterized in that The metal interconnect structure layer comprises an interlayer dielectric layer and a metal layer located on the interlayer dielectric layer, and the interlayer dielectric layer covers the first dielectric layer and the quenching resistor structure; The interlayer dielectric layer has a first contact electrically connected to the polysilicon in the quenching resistor structure and a second contact electrically connected to the photodiode corresponding to the quenching resistor structure, and a partial structure of the metal layer electrically connects the first contact and the second contact.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The deep trench isolation structure includes a deep trench, a second liner layer and a second light-shielding conductive layer, wherein the second liner layer is formed on the sidewall and the bottom of the deep trench, and the second light-shielding conductive layer fills the remaining space of the deep trench.

6. The semiconductor device according to claim 5, characterized in that It also includes an inverted pyramid structure extending from a first area of ​​the first surface to the inside of the semiconductor substrate, wherein the first area is a region for forming a photodiode in the semiconductor substrate; the inverted pyramid structure includes a conical opening with a top facing the second surface and a dielectric material filled in the conical opening; The first surface is covered with a second dielectric layer, and the deep trench isolation structure penetrates the second dielectric layer.

7. The semiconductor device according to claim 6, characterized in that It also includes a shallow trench structure, which is formed on the first area of ​​the first surface and extends through the second dielectric layer into the semiconductor substrate, and the inverted pyramid structure is located between the deep trench isolation structure and the shallow trench structure; The shallow trench structure includes a shallow trench opening and a light-shielding conductive material filled in the shallow trench opening. The light-shielding conductive material is electrically connected to the second light-shielding conductive layer of the deep trench isolation structure through a conductive connection layer.

8. The semiconductor device according to claim 1, wherein: Also included is a carrier wafer, the carrier wafer being bonded to the metal interconnect structure layer.

9. A method for preparing a semiconductor device, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other, wherein a plurality of photodiodes are formed in the semiconductor substrate; On the second surface of the semiconductor substrate, two shallow trench isolation structures are formed between adjacent photodiodes, the shallow trench isolation structures are spaced apart and extend into the semiconductor substrate, and the spacing between adjacent side walls of the two shallow trench isolation structures is less than or equal to the width of the deep trench of the deep trench isolation structure used to isolate the adjacent photodiodes; forming a quenching resistor structure corresponding to each of the photodiodes on the second surface of the semiconductor substrate, wherein the quenching resistor structure comprises an electrical isolation layer and polysilicon, wherein the electrical isolation layer is formed on the second surface side, and the polysilicon is formed on the electrical isolation layer; forming a metal interconnect structure layer on the second surface side of the semiconductor substrate so that the polysilicon in the quenching resistor structure is electrically connected to the corresponding photodiode through the metal interconnect structure layer; On the first surface of the semiconductor substrate, the deep trench isolation structure extending into the interior of the semiconductor substrate is formed between adjacent photodiodes, so that the two shallow trench isolation structures are distributed on both sides of the deep trench isolation structure and respectively intersect with the deep trench isolation structure inside the semiconductor substrate, and there is a preset distance between the bottom of the deep trench isolation structure and the second surface; wherein the deep trench isolation structure and the two shallow trench isolation structures form a trench isolation structure between the adjacent photodiodes.

10. The preparation method according to claim 9, characterized in that: The second surface of the semiconductor substrate is provided with two shallow trench isolation structures spaced apart from each other and extending into the semiconductor substrate between adjacent photodiodes, including: forming a first dielectric layer on the second surface of the semiconductor substrate; Between adjacent photodiodes, two shallow trenches are formed which penetrate the first dielectric layer and extend into the semiconductor substrate; the spacing between adjacent side walls of the two shallow trenches is less than or equal to the width of the deep trench; forming a first liner layer on the sidewall and bottom of the shallow trench; A first light-shielding conductive layer is filled in the remaining space of the shallow trench, and the first light-shielding conductive layer is planarized and stopped at the first dielectric layer.

11. The preparation method according to claim 9, characterized in that: The deep trench isolation structure extending into the semiconductor substrate is formed between adjacent photodiodes on the first surface of the semiconductor substrate, comprising: A deep trench extending into the semiconductor substrate is formed on the first surface of the semiconductor substrate between adjacent photodiodes; a preset spacing is reserved between the bottom of the deep trench and the second surface, and two shallow trench isolation structures formed between the adjacent photodiodes are distributed on both sides of the deep trench and intersect with the deep trench; forming a second liner layer on the sidewall and bottom of the deep trench; A second light-shielding conductive layer is filled in the remaining space of the deep trench.

12. The preparation method according to claim 11, characterized in that: Before forming the deep trench isolation structure extending into the semiconductor substrate between adjacent photodiodes on the first surface of the semiconductor substrate, the method further includes: Forming a tapered opening on a first region of the first surface, with the top of the tapered opening facing the second surface; the first region is a region for forming a photodiode in the semiconductor substrate; A dielectric material is filled in the tapered opening, and the tapered opening and the filled dielectric material form an inverted pyramid structure.

13. The preparation method according to claim 12, characterized in that: The forming of a second liner layer on the sidewall and bottom of the deep trench comprises: Depositing a second dielectric layer on the first surface, the second dielectric layer comprising a first portion extending laterally on the first surface and a second portion extending to the sidewall and bottom of the deep trench; wherein the notch of the deep trench is closed by the first portion, and the second portion forms the second liner layer; Filling the remaining space of the deep trench with the second light-shielding conductive layer comprises: etching the second dielectric layer at the notch of the deep trench to expose the deep trench; and filling the remaining space of the deep trench with the second light-shielding conductive layer.

14. The preparation method according to claim 13, characterized in that: The method further comprises: A shallow trench opening is formed on the first area of ​​the first surface, penetrating the second dielectric layer and extending into the semiconductor substrate; the inverted pyramid structure is located between the deep trench isolation structure and the shallow trench opening; Filling the shallow groove opening with a light-shielding conductive material; the shallow groove opening and the filled light-shielding conductive material form a shallow groove structure; A conductive connection layer is deposited on the second dielectric layer to electrically connect the second light-shielding conductive layer and the light-shielding conductive material of the shallow groove structure.

15. The preparation method according to claim 9, characterized in that: After forming a metal interconnect structure layer on the second surface side of the semiconductor substrate, the method further includes: providing a carrier wafer; The carrier wafer is bonded to the metal interconnect structure layer.

16. An electronic device, characterized in that: The electronic apparatus includes the semiconductor device according to any one of claims 1 to 8.

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