Updating method of software test library, electronic equipment and medium

Abstract

The invention relates to the technical field of chips, in particular to a software test library updating method, electronic equipment and a medium, and the method comprises the following steps: S1, obtaining a current software test library which comprises N software test library files; s2, acquiring a to-be-updated software test library file; s3, running a preset test case in a preset test case set based on the current software test library and the to-be-updated software test library file: calling a corresponding Aq when the Fn needing to be called has the corresponding Aq, otherwise, calling the corresponding Fn; and S4, if all the preset test cases in the preset test case set pass the test, updating {A1, A2,..., Aq,..., AQ} to {F1, F2,..., Fn,..., FN}, and if all the preset test cases in the preset test case set pass the test, updating {A1, A2,..., Aq,..., AQ} to {F1, F2,..., Fn,..., FN}. According to the invention, the updating reliability of the software test library is improved, so that the chip test efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a method for updating a software test library, electronic equipment and a medium. Background Art

[0002] In the process of chip verification, it is necessary to generate software test cases based on the software test library, and to interact with the chip design to be tested based on the software test cases to verify the chip design to be tested. There are different library files in the software test library, and different users have different needs to generate different test cases. The library files in the software test library are updated frequently, and the update of the library files will cause the interface to change frequently, and some updates will cause some test cases to fail to run. The software test library has poor update reliability, which reduces the chip test efficiency. It can be seen from this that how to improve the reliability of the software test library update and then improve the chip test efficiency has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] The present invention aims to provide a method for updating a software test library, thereby improving the reliability of updating the software test library and further improving chip testing efficiency.

[0004] According to a first aspect of the present invention, there is provided a method for updating a software test library, comprising:

[0005] Step S1: Obtain the current software test library, which includes N software test library files {F1, F2, ..., F n ,...,F N}, where F n is the nth software test library file, where the value of n ranges from 1 to N;

[0006] Step S2: Obtain the software test library file to be updated {A1, A2, ..., A q ,...,A Q}, A q is the qth software test library file to be updated, the value range of q is 1 to Q, N ≥ Q;

[0007] Step S3: Run the preset test cases in the preset test case set based on the current software test library and the software test library file to be updated: n There is a corresponding A q When calling the corresponding A q Otherwise, call the corresponding F n , the preset test cases are test cases in which the update of the software test library will have an impact on the hardware;

[0008] Step S4: If all the preset test cases in the preset test case set pass the test, {A1, A2, ..., A q ,...,A Q}Update to {F1,F2,...,F n ,...,F N}middle.

[0009] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0010] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0011] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the software test library update method, electronic device and medium provided by the present invention can achieve considerable technical advancement and practicality, and have wide industrial utilization value, and at least have the following beneficial effects:

[0012] The present invention provides a standardized software test library file update process. Before the software test library is updated, test cases that will affect the hardware are first run based on the current software test library and the software test library files to be updated in the updated software test library. If all tests pass, the software test library files to be updated are updated to the current software test library, thereby improving the reliability of the software test library update and further improving the chip testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 A flow chart of a method for updating a software test library provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0016] The embodiment of the present invention provides a method for updating a software test library, such as Figure 1 As shown, including:

[0017] Step S1: Obtain the current software test library, which includes N software test library files {F1, F2, ..., F n ,...,F N}, where F n is the nth software test library file, the value range of n is 1 to N, and N is the total number of software test library files in the current software test library.

[0018] The software test library may be an existing MQL test library or a GQL test library, etc. The software test library files include drawing library files, transport database files, general calculation library files, matrix operation library files, model analysis library files, etc.

[0019] Step S2: Obtain the software test library file to be updated {A1, A2, ..., A q ,...,A Q}, A q is the qth software test library file to be updated, the value range of q is 1 to Q, Q is the total number of software test library files to be updated, N≥Q.

[0020] Step S3: Run the preset test cases in the preset test case set based on the current software test library and the software test library file to be updated: n There is a corresponding A q When calling the corresponding A q Otherwise, call the corresponding F n The preset test cases are test cases in which the update of the software test library will have an impact on the hardware.

[0021] Step S4: If all the preset test cases in the preset test case set pass the test, {A1, A2, ..., A q ,...,A Q}Update to {F1,F2,...,F n ,...,F N}middle.

[0022] It should be noted that the software test library file to be updated is written based on the software language and is usually aligned with the software code, that is, the update usually does not affect the software verification interface. If the preset test case verification passes, it means that the current software test library file to be updated will not affect the hardware verification interface or the software verification interface. If all the preset test cases in the preset test case set pass the test, it means that the update of the software test library file to be updated will not affect the verification. Therefore, {A1,A2,...,A q ,...,A Q}Update to {F1,F2,...,F n ,...,F N Through steps S1 to S4, the software test library file update process can be standardized, the reliability of the software test library update is improved, and the chip test efficiency is further improved.

[0023] As an embodiment, in step S4, if there is a preset test case that fails in the preset test case set, step S5 is executed;

[0024] Step S5, determine whether the software code and the hardware code are aligned with the software test library file to be updated, if not aligned with the hardware code, execute step S6, if not aligned with the software code, execute step S7.

[0025] It should be noted that the alignment of software code with the software test library file to be updated means that the software test library file to be updated is generated without affecting the software verification interface. The alignment of hardware code with the software test library file to be updated means that the software test library file to be updated is generated without affecting the hardware verification interface.

[0026] Step S6: Update the code service layer based on the preset test cases that have not passed, wherein the code service layer is used to call the software test library to generate software test cases, and return to execute step S1.

[0027] It should be noted that the failure of the preset test cases due to misalignment with the hardware code is usually caused by the update of the hardware interface. In this case, the code service layer can be updated so that both the software interface and the hardware interface match the preset test cases, so that the preset test cases can be run and passed.

[0028] Step S7: Update {A1, A2, ..., A based on the preset test cases that failed q ,...,A Q}, return to execute step S1.

[0029] It should be noted that if {A1,A2,...,A q,...,A Q} is usually an unreasonable update, so it is necessary to re-acquire {A1,A2,...,A q ,...,A Q}.

[0030] As an embodiment, the code service layer is implemented based on software code, and the software code can be implemented in C language, C++ language, etc. The code service layer includes a global function module, a command package creation and distribution module, a queue wake-up module, a multi-process scheduling module, and an operation result inspection module. Each module of the code service layer is bound to at least one F n It should be noted that each module in the code service layer may be bound to a F n , it is also possible to bind multiple F n The same F n It may be bound to multiple different modules in the code service layer. After binding, users no longer need to directly connect to a large number of test library files when generating software test cases. They only need to call related functional modules based on simple parameter configuration. Each module in the code service layer is provided with an application program interface for configuring each module. Step S3 includes:

[0031] Step S31: Generate an option parameter file based on each preset test case.

[0032] Step S32: extracting parameter options corresponding to each module of the code service layer from the option parameter file, and respectively calling corresponding application programming interfaces to configure the parameter options into the corresponding modules of the code service layer.

[0033] Step S33: Each module of the code service layer is used to call the bound F n Generate corresponding functional instructions, convert the functional instructions corresponding to each module into functional instructions that should be implemented in hardware language and send them to the chip design under test. The chip design under test executes the received functional instructions implemented in hardware language to generate execution results, and compares the execution results with the target results. If they are consistent, the verification passes, otherwise, the verification fails.

[0034] It should be noted that, during the chip verification process, software test cases can usually be directly run in the system-level verification and / or software-level verification stages, and run on real hardware accelerators or physical chips. If problems are found again in the system-level verification stage and the software verification stage, a large amount of update costs will be consumed, reducing the efficiency of chip development. If some system-level verification and / or software-level verification can be performed in advance based on the chip RTL code, some problems existing in the RTL code can be solved before the hardware accelerator or physical chip is generated, which can improve the chip development efficiency and reduce the chip development cost. Therefore, the embodiment of the present invention runs the generated software test cases on the chip design to be tested, so as to realize some system-level verification and / or software-level verification in advance. The chip design to be tested is implemented based on hardware code, and the hardware code can specifically be a code implemented by Verilog language, SystemVeriliog language, etc.

[0035] Specifically, a conversion interface can be used to convert the functional instructions corresponding to each module into functional instructions implemented in the hardware language. As an embodiment, the conversion interface can be implemented through an existing direct programming interface (Direct Programming Interface, referred to as DPI). DPI is a standard interface that allows SystemVerilog code to directly call C or C++ functions, and vice versa. DPI allows data and control information to be transferred between the two languages. Therefore, based on DPI, the conversion between the software language and the SystemVerilog language can be realized, which will not be repeated here.

[0036] As an embodiment, step S33 includes:

[0037] Step S331: Generate a preset function on or off instruction based on the global function module.

[0038] The preset functions include virtualization function, virtual address translation function and multi-card interconnection function. The preset function on or off instructions are set through the global function module, which is effective for the same test case without the need to set them separately at each location involving the preset function.

[0039] Step S332, create a distribution module based on the command package. The distribution module is used to create command packages, and randomly map the command packages to a single or multiple queues according to user needs, or map each command package to the corresponding queue one by one according to a preset mapping relationship, and distribute the command package to the corresponding queue after the queue corresponding to the command package is awakened.

[0040] As an embodiment, the command package creation and distribution module includes M command package templates {R1, R2, ..., R m ,...,R M}, R m is the mth command package template, where the value of m ranges from 1 to M, and M is the total number of command package templates. In step S332, a distribution module is created based on the command package. A distribution module is used to create a command package, including:

[0041] Step S3321: The command package creation and distribution module calls the corresponding command package template based on the corresponding parameter options, and updates the corresponding parameters in the command package template based on the corresponding parameter options to generate the corresponding command package.

[0042] It should be noted that one test case can create one or more command packages. If multiple command packages are created, the multiple command packages can be the same command packages or different command packages.

[0043] Step S333: The queue-based wake-up module wakes up the queue through a doorbell operation according to the queue execution order.

[0044] The queue wake-up module is used to wake up the queue through the doorbell operation according to the queue execution order. It should be noted that the queue wake-up module can wake up the queue by type. The queue wake-up module includes a physical function queue wake-up unit, a virtualization queue wake-up unit and a queue wake-up unit in multi-GPU mode. The physical function queue wake-up unit, the virtualization queue wake-up unit and the queue wake-up unit in multi-GPU mode are bound to different F n The physical function queue wake-up unit is used to call the bound F n The wake-up unit physical function queue; the virtualized queue wake-up unit is used to call the bound F n Wake up the virtualization queue; the queue wake-up unit in the multi-GPU mode is used to call the bound F n Wake up the queue in multi-GPU mode.

[0045] Step S334, set at least one process based on the multi-process scheduling module. If there are multiple processes, set the multiple processes to be executed in order or in parallel according to user needs, and build a mapping relationship between each process and the queue. When the queue is awakened, the corresponding command packet corresponding to the chip under test design is executed in the queue through the corresponding process, and the chip under test design generates an execution result.

[0046] Step S335: Obtain the execution result based on the operation result check module, and compare the execution result with the target result. If they are consistent, the verification passes; otherwise, the verification fails.

[0047] As an embodiment, the operation result checking module is used to obtain the execution result, and compare the execution result with the target result. If they are consistent, the verification is passed; otherwise, the verification fails. After the chip under test is designed to generate the execution result, the execution result is stored in the target address, and the target address is sent to the operation result checking module; the operation result checking module is used to obtain the execution result based on the target address, and compare the execution result with the target result. If they are consistent, the verification is passed; otherwise, the verification fails. It should be noted that the embodiment of the present invention, by setting up the operation result checking module, only needs to pass the target address to obtain the execution result, and compare the execution result with the target result, without the need to design a complex monitoring module, thereby reducing the chip verification cost and improving the chip verification efficiency.

[0048] As an embodiment, the code service layer may further include a parallel operation module. During the execution of step S3, the parallel operation module is used to issue parallel operation instructions for multiple virtual devices and set multiple virtualized devices to work in parallel.

[0049] In some application scenarios, multiple engines are required to work together. As an embodiment, the code service layer also includes engine collaborative work instructions. During the execution of step S3, it is used to issue collaborative work instructions between multiple engines in sequence according to the engine working order and execution quality type, thereby supporting multiple engines to work together. Specifically, engine 0 may write data first, engine 2 and engine 3 may read data, and so on.

[0050] The abnormality of the chip circuit is also part of the abnormal test. As an embodiment, the code service layer also includes an exception handling module, which is used to issue an abnormal test instruction during the execution of step S3. When the target test abnormality is obtained in the chip design to be tested, it means that it meets the abnormal test expectations, and the next step can be continued. The abnormal clearing instruction can be issued to continue running. If the target test abnormality does not occur, it means that the abnormal test has not passed, and a prompt message can be generated.

[0051] It should be noted that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0052] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0053] The embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0054] An embodiment of the present invention provides a standardized software test library file update process. Before the software test library is updated, test cases that will affect the hardware are first run based on the current software test library and the software test library files to be updated in the updated software test library. If all tests pass, the software test library files to be updated are updated to the current software test library, thereby improving the reliability of the software test library update and further improving the chip testing efficiency.

[0055] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A method for updating a software test library, characterized in that: include: Step S1: Obtain the current software test library, which includes N software test library files {F1, F2, ..., F n ,...,F N }, where F n is the nth software test library file, where the value of n ranges from 1 to N; Step S2: Obtain the software test library file to be updated {A1, A2, ..., A q ,...,A Q }, A q is the qth software test library file to be updated, the value range of q is 1 to Q, N ≥ Q; Step S3: Run the preset test cases in the preset test case set based on the current software test library and the software test library file to be updated: n There is a corresponding A q When calling the corresponding A q Otherwise, call the corresponding F n , the preset test cases are test cases in which the update of the software test library will have an impact on the hardware; Step S4: If all the preset test cases in the preset test case set pass the test, {A1, A2, ..., A q ,...,A Q }Update to {F1,F2,...,F n ,...,F N }middle.

2. The method according to claim 1, characterized in that In step S4, if there is a preset test case that fails in the preset test case set, step S5 is executed; Step S5, determining whether the software code and the hardware code are aligned with the software test library file to be updated, if so, executing step S6, otherwise, executing step S7; Step S6: updating the code service layer based on the preset test cases that have not passed, wherein the code service layer is used to call the software test library to generate software test cases, and returning to execute step S1; Step S7: Update {A1, A2, ..., A based on the preset test cases that failed q ,...,A Q }, return to execute step S1.

3. The method according to claim 1, characterized in that The code service layer includes a global function module, a command package creation and distribution module, a queue wake-up module, a multi-process scheduling module, and an operation result inspection module. Each module of the code service layer is bound to at least one F n Each module in the code service layer is provided with an application program interface for configuring each module, and the step S3 includes: Step S31, generating an option parameter file based on each preset test case; Step S32, extracting parameter options corresponding to each module of the code service layer from the option parameter file, and calling corresponding application program interfaces to configure the parameter options to the corresponding modules of the code service layer; Step S33: Each module of the code service layer is used to call the bound F n Generate corresponding functional instructions, convert the functional instructions corresponding to each module into functional instructions that should be implemented in hardware language and send them to the chip design under test. The chip design under test executes the received functional instructions implemented in hardware language to generate execution results, and compares the execution results with the target results. If they are consistent, the verification passes, otherwise, the verification fails.

4. The method according to claim 3, characterized in that The step S33 comprises: Step S331: Generate a preset function on or off instruction based on the global function module; Step S332: Create a distribution module based on the command packet. Create a distribution module for creating a command packet, and randomly map the command packet to a single or multiple queues, or map each command packet to a corresponding queue one by one according to a preset mapping relationship, and distribute the command packet to the corresponding queue after the queue corresponding to the command packet is awakened; Step S333: Based on the queue wake-up module, the queue is woken up through the doorbell operation according to the queue execution order; Step S334: at least one process is set based on the multi-process scheduling module. If there are multiple processes, the multiple processes are set to be executed in order or in parallel, and a mapping relationship between each process and a queue is constructed. When the queue is awakened, the command packet corresponding to the chip under test is executed through the corresponding process in the queue, and the chip under test generates an execution result; Step S335: Obtain the execution result based on the operation result check module, and compare the execution result with the target result. If they are consistent, the verification passes; otherwise, the verification fails.

5. The method according to claim 4, characterized in that The command package creation and distribution module includes M command package templates {R1, R2, ..., R m ,...,R M }, R m is the mth command package template, where the value of m ranges from 1 to M. In step S332, creating a distribution module based on the command package and building a distribution module for creating a command package include: Step S3321: The command package creation and distribution module calls the corresponding command package template based on the corresponding parameter options, and updates the corresponding parameters in the command package template based on the corresponding parameter options to generate the corresponding command package.

6. The method according to claim 1, characterized in that The software testing library files include drawing library files, transport database files, general calculation library files, matrix operation library files and model analysis library files.

7. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method according to any one of the preceding claims 1-6.

Images