Memory expansion card, electronic equipment and memory expansion method

Abstract

The invention provides a memory expansion card which can be applied to the technical field of computers, and particularly can be applied to the technical field of computer memory expansion. The memory expansion card comprises a connector interface, a golden finger interface, m multiplexers and m memory expansion controllers, wherein m is an integer greater than 1; wherein the input end of the multiplexer is respectively connected with the connector interface and the golden finger interface, the output end of the multiplexer is connected with the memory expansion controller, and the multiplexer is used for gating a data signal from the connector interface or a data signal from the golden finger interface to the memory expansion controller; the expansion end of the memory expansion controller is connected with the n memory expansion interfaces, the memory expansion controller is used for transmitting the data signals to the n memory expansion interfaces, and n is a positive integer. The invention further provides electronic equipment and a memory expansion method.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, in particular to the field of computer memory expansion technology, and more particularly to a memory expansion card, an electronic device, and a memory expansion method. Background Art

[0002] With the continuous development of technologies such as big data, cloud computing, and artificial intelligence, the computing needs of various emerging businesses, such as the metaverse and large models, are growing exponentially. To meet the computing needs, computing nodes have an increasing demand for memory capacity. Therefore, how to configure more memory resources for computing nodes is an urgent problem to be solved. Summary of the invention

[0003] In view of the above problems, the present disclosure provides a memory expansion card, an electronic device and a memory expansion method.

[0004] One aspect of the present disclosure provides a memory expansion card, comprising: a connector interface, a gold finger interface, m multiplexers and m memory expansion controllers, where m is an integer greater than 1; wherein the input end of the multiplexer is respectively connected to the connector interface and the gold finger interface, the output end of the multiplexer is connected to the memory expansion controller, and the multiplexer is used to select a data signal from the connector interface or a data signal from the gold finger interface to the memory expansion controller; and the expansion end of the memory expansion controller is respectively connected to n memory expansion interfaces, and the memory expansion controller is used to transmit the data signal to the n memory expansion interfaces, where n is a positive integer.

[0005] Another aspect of the present disclosure provides an electronic device including at least one memory expansion card as described above.

[0006] Another aspect of the present disclosure provides a memory expansion method, comprising: in response to an external host accessing a connector interface or a gold finger interface, selecting a data signal from the above connector interface or a data signal from the above gold finger interface to a memory expansion controller through a multiplexer; and transmitting the above data signal to an extended memory through the above memory expander, wherein the above extended memory is configured to be communicatively connected with the above memory expander through the memory expansion interface of the above memory expander.

[0007] According to an embodiment of the present disclosure, a memory expansion card may be provided with two physical interfaces, a connector interface and a gold finger interface, to meet the connection requirements of the memory expansion card in different scenarios. The multiplexer may provide a data signal from the connector interface or a data signal from the gold finger interface to the memory expansion controller, and the memory expansion controller may transmit the received data signal to the memory expansion interface through the configured memory channel, thereby realizing signal interaction between the two physical interfaces and multiple memory expansion interfaces, thereby increasing the number of memory bars that can be connected to a single physical interface and improving the expansion performance of the memory capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above contents and other purposes, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0009] Figure 1 A schematic diagram of a memory expansion card according to an embodiment of the present disclosure is schematically shown.

[0010] Figure 2 A schematic diagram of a memory expansion card according to another embodiment of the present disclosure is schematically shown.

[0011] Figure 3 A schematic diagram of a memory expansion card according to another embodiment of the present disclosure is schematically shown.

[0012] Figure 4A A schematic diagram of a memory expansion card according to another embodiment of the present disclosure is schematically shown.

[0013] Figure 4B A schematic diagram of a memory expansion card according to another embodiment of the present disclosure is schematically shown.

[0014] Figure 4C A schematic diagram of a memory expansion card according to another embodiment of the present disclosure is schematically shown.

[0015] Figure 4D A schematic diagram of a memory expansion card according to another embodiment of the present disclosure is schematically shown.

[0016] Figure 5 A schematic diagram of a memory expansion card according to another embodiment of the present disclosure is schematically shown.

[0017] Figure 6 The schematic diagram of the layout and wiring of the memory expansion card according to the embodiment of the present disclosure is schematically shown.

[0018] Figure 7 The schematic diagram shows the structure of the memory expansion interface according to the embodiment of the present disclosure.

[0019] Figure 8A schematic diagram of an electronic device according to an embodiment of the present disclosure is schematically shown.

[0020] Fig. 9 The flowchart of the memory expansion method according to the embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0022] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0023] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0024] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0025] The embodiment of the present disclosure provides a memory expansion card to meet the urgent demand for memory resources in data-intensive applications such as high-performance computing and artificial intelligence. The memory expansion card includes: a connector interface, a gold finger interface, m multiplexers and m memory expansion controllers, where m is an integer greater than 1; wherein the input end of the multiplexer is respectively connected to the connector interface and the gold finger interface, the output end of the multiplexer is connected to the memory expansion controller, and the multiplexer is used to select the data signal from the connector interface or the data signal from the gold finger interface to the memory expansion controller; and the expansion end of the memory expansion controller is respectively connected to n memory expansion interfaces, and the memory expansion controller is used to transmit the data signal to the n memory expansion interfaces, where n is a positive integer.

[0026] Figure 1 A schematic diagram of a memory expansion card according to an embodiment of the present disclosure is schematically shown.

[0027] like Figure 1 As shown, the memory expansion card 100 may include a connector interface 10, a gold finger interface 20, m multiplexers 30, and m memory expansion controllers 40. m may be an integer greater than 1.

[0028] The connector interface 10 and the gold finger interface 20 may be different physical interfaces. For example, the connector interface 10 may be a CDFP connector interface based on PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard), and the gold finger interface 20 may be a Gold Finger interface based on PCIe. Different physical interfaces may adapt to different connection modes between the memory expansion card 100 and the server. For example, the gold finger interface 20 may be a x16PCIe Gen5 gold finger, through which the memory expansion card 100 may be connected to the motherboard of the server or the PCIe Riser card of the server. For another example, the connector interface 10 may be a x16 PCIe Gen5 CDFP connector, which may have a smaller size and may be directly connected to the cable of the server; or, through the interface, the memory expansion card 100 may be connected to the front and rear windows of the server, and then the memory expansion card 100 may be connected to the corresponding host through a cable, so as to facilitate the assembly and maintenance of the memory expansion card 100. x16 indicates that the interface can send and receive 16 signals, and Gen5 indicates that the interface is adapted to the fifth generation PCIe standard.

[0029] The multiplexer 30 can be a combinational logic circuit with multiple inputs and a single output. An n-input multiplexer can be equivalent to an n-way digital switch, which can select one output from n inputs to a common output terminal according to different control signals.

[0030] In the embodiment of the present disclosure, the input end of the multiplexer 30 can be connected to the connector interface 10 and the gold finger interface 20 respectively, and the output end of the multiplexer 30 can be connected to the memory expansion controller 40, that is, the multiplexer 30 can be a 2-input multiplexer. Based on the different control signals received by the multiplexer 30, the multiplexer 30 can select the data signal from the connector interface 10 to the memory expansion controller 40, or select the data signal from the gold finger interface 20 to the memory expansion controller 40. The source of the control signal received by the multiplexer 30 is not limited here, for example, the control signal can be provided by a processor configured on the memory expansion card 100; or, the control signal can also be provided by an external device connected to the memory expansion card 100; or, the control signal can include the respective in-place detection signals of the connector interface 10 and the gold finger interface 20, and the in-place detection signal can be used to indicate the connection status of the corresponding interface; it is not limited here.

[0031] The memory expansion controller 40 may be a memory expansion chip that complies with the CXL (Compute Express Link, memory consistency bus) protocol. The CXL protocol is an open industrial standard for high-bandwidth, low-latency device interconnection. CXL can connect devices such as the CPU (Central Processing Unit, CPU) and Accelerator, Memory Buffer, and Smart NIC (Smart Network Interface Card, smart network card) for use in scenarios such as AI machine learning and high-performance computing.

[0032] In an embodiment of the present disclosure, the expansion end of the memory expansion controller 40 may have n memory channels, which may be used to respectively connect n memory expansion interfaces 50 . The memory expansion controller 40 may be used to transmit data signals to the n memory expansion interfaces 50 , where n is a positive integer.

[0033] The type of the memory expansion interface 50 is not limited. For example, the memory expansion interface 50 can be a DDR5 (Double Data Rate Synchronous Dynamic Random Access Memory 5, the fifth generation of double data rate synchronous dynamic random access memory) DIMM (Dual Inline Memory Modules, dual inline memory module) interface, then the interface can be used to access a DDR5 RDIMM memory stick, and the memory channel connected to the interface can be divided into two sub-channels. For another example, the memory expansion interface 50 can be a DDR4 DIMM interface, then the interface can be used to access a DDR4 RDIMM memory stick, and the memory channel connected to the interface does not need to be divided into sub-channels.

[0034] The memory expansion controller 40 can be used to implement memory expansion, memory sharing and memory pooling. For example, the memory expansion controller can be used to provide extended memory to a processor of an external device, the external device can be a device connected to the connector interface 10 or the gold finger interface 20, and the extended memory can be provided by a memory stick connected to the memory expansion interface 50.

[0035] The memory expansion controller 40 and the memory expansion interface 50 may exchange various signals, which may include but are not limited to data signals, data selection signals, clock signals, initialization signals, and the like.

[0036] According to an embodiment of the present disclosure, a memory expansion card may be provided with two physical interfaces, a connector interface and a gold finger interface, to meet the connection requirements of the memory expansion card in different scenarios. The multiplexer may provide a data signal from the connector interface or a data signal from the gold finger interface to the memory expansion controller, and the memory expansion controller may transmit the received data signal to the memory expansion interface through the configured memory channel, thereby realizing signal interaction between the two physical interfaces and multiple memory expansion interfaces, thereby increasing the number of memory bars that can be connected to a single physical interface and improving the expansion performance of the memory capacity.

[0037] In the embodiment of the present disclosure, the data signal accessed through the connector interface 10 or the gold finger interface 20 can be provided to the memory bars accessed by the m×n memory expansion interfaces 40. Optionally, in order to ensure that the memory bars accessed through the memory expansion interfaces can work at full capacity, the number of channels required by each memory expansion interface 40 can be greater than or equal to 4. Accordingly, the number of channels of the data signal accessed by the connector interface 10 or the gold finger interface 20 can be at least m×n×4 channels.

[0038] For example, the number of channels required by each memory expansion interface 40 is k, where k is an integer greater than 1. The connector interface 10 or the gold finger interface 20 can be used to access m×n×k data signals respectively.

[0039] For each of the m multiplexers 30, the multiplexer can be used to receive n×k data signals from the connector interface 10 through the first memory consistency bus, or n×k data signals from the gold finger interface 20 through the second memory consistency bus, and transmit the n×k data signals to the memory expansion controller 40 through the third memory consistency bus.

[0040] The first memory consistency bus, the second memory consistency bus and the third memory consistency bus can all be transmission lines based on the CXL protocol. The number of channels of the first memory consistency bus, the second memory consistency bus and the third memory consistency bus can be n×k, so that n×k data signals can be transmitted.

[0041] The expansion end of the memory expansion controller 40 may include n memory channels, and the memory expansion controller 40 is further used to transmit k-channel data signals to the n memory expansion interfaces 50 through the n memory channels, respectively. That is, for each of the n memory expansion interfaces 50 connected to the memory expansion controller 40, the number of channels of the memory expansion interface 50 may be k channels, and the memory expansion interface 50 may be used to transmit k-channel data signals.

[0042] The following takes the case where the number of multiplexers and memory expansion controllers included in the memory expansion card is 2, and the number of memory expansion interfaces connected to the expansion end of each memory expansion controller is 2 as an example to further illustrate the memory expansion card of the embodiment of the present disclosure.

[0043] Figure 2 A schematic diagram of a memory expansion card according to another embodiment of the present disclosure is schematically shown.

[0044] like Figure 2 As shown, in the memory expansion card 200, the m multiplexers 30 may include a first multiplexer 31 and a second multiplexer 32, and the m memory expansion controllers 40 may include a first memory expansion controller 41 and a second memory expansion controller 42. The n memory expansion interfaces 50 connected to the first memory expansion controller 41 may include a first memory expansion interface 51 and a second memory expansion interface 52. The n memory expansion interfaces 50 connected to the second memory expansion controller 42 may include a third memory expansion interface 53 and a fourth memory expansion interface 54.

[0045] The connector interface 10 and the gold finger interface 20 can be x16 PCIe interfaces, that is, the connector interface 10 and the gold finger interface 20 can be used to transmit 16 PCIe signals simultaneously. The connector interface 10 or the gold finger interface 20 can divide the 16 PCIe signals connected into two 8 PCIe signals. The two 8 PCIe signals can be provided to two multiplexers by two memory consistency buses respectively. Among them, the connector interface 10 can be connected to the first multiplexer 31 through a first memory consistency bus, and connected to the second multiplexer 32 through a second memory consistency bus. The gold finger interface 20 can be connected to the first multiplexer 31 through another first memory consistency bus, and connected to the second multiplexer 32 through another second memory consistency bus. Similarly, the first multiplexer 31 can be connected to the first memory expansion controller 41 through a third memory consistency bus, and the second multiplexer 32 can be connected to the second memory expansion controller 42 through another third memory consistency bus. The first memory consistency bus, the second memory consistency bus and the third memory consistency bus can all be x8 CXL.

[0046] Each memory expansion controller can support x8 PCIE Lane and can implement CXL communication through the MXC (Memory Expander Controller) protocol. The two memory channels of the first memory expansion controller 41 and the second memory expansion controller 42 can be used to transmit four PCIe signals respectively. Among them, the first memory expansion controller 41 can be connected to the first memory expansion interface 51 through one x4 CXL, and connected to the second memory expansion interface 52 through another x4 CXL. The second memory expansion controller 42 can be connected to the third memory expansion interface 53 through one x4 CXL, and connected to the fourth memory expansion interface 54 through another x4 CXL.

[0047] In an example, each memory expansion interface can be connected to a DDR4 RDIMM memory stick, and the maximum capacity of a single DDR4 RDIMM memory stick that can be supported is 64 GB, so that a memory expansion card can expand a maximum of 256 GB of DDR4 RDIMM.

[0048] Optionally, when the memory expansion card is connected to the corresponding physical interface through a connector interface or a gold finger interface, the connector interface or the gold finger interface can output a presence detection signal, and the presence detection signal can be used to control the selection of the input end of the multiplexer.

[0049] For example, the connector interface may include a first in-place detection terminal, and the gold finger interface may include a second in-place detection terminal. The control terminal of the multiplexer may be connected to the first in-place detection terminal and the second in-place detection terminal, respectively, and the multiplexer is used to select the data signal from the connector interface or the data signal from the gold finger interface to the memory expansion controller in response to the in-place detection signal from the first in-place detection terminal or the in-place detection signal from the second in-place detection terminal.

[0050] Figure 3 A schematic diagram of a memory expansion card according to another embodiment of the present disclosure is schematically shown.

[0051] like Figure 3 As shown, in the memory expansion card 300, the connector interface 10 may include a first in-place detection terminal AD1, and the gold finger interface 20 may include a second in-place detection terminal AD2. The control terminal C1 of the first multiplexer 31 may be connected to the first in-place detection terminal AD1 and the second in-place detection terminal AD2, respectively, and the control terminal C2 of the second multiplexer 32 may be connected to the first in-place detection terminal AD1 and the second in-place detection terminal AD2, respectively. The first input terminal of the first multiplexer 31 may be connected to the connector interface 10, and the second input terminal of the first multiplexer 31 may be connected to the gold finger interface 20. The first input terminal of the second multiplexer 32 may be connected to the connector interface 10, and the second input terminal of the second multiplexer 32 may be connected to the gold finger interface 20.

[0052] When the connector interface 10 is connected to an external device, the connector interface 10 can send a presence detection signal to the control terminal C1 of the first multiplexer 31 and the control terminal C2 of the second multiplexer 32 through the first presence detection terminal AD1. After receiving the presence detection signal, the first multiplexer 31 can control the first input terminal of the first multiplexer 31 to be connected to the output terminal of the first multiplexer 31, thereby realizing the selection of the first input terminal of the first multiplexer 31; the second multiplexer 32 can control the first input terminal of the second multiplexer 32 to be connected to the output terminal of the second multiplexer 32, thereby realizing the selection of the first input terminal of the second multiplexer 32.

[0053] Similarly, when the gold finger interface 20 is connected to an external device, the gold finger interface 20 can send a presence detection signal to the control terminal C1 of the first multiplexer 31 and the control terminal C2 of the second multiplexer 32 through the second presence detection terminal AD2. After receiving the presence detection signal, the first multiplexer 31 can control the second input terminal of the first multiplexer 31 to be connected to the output terminal of the first multiplexer 31, thereby realizing the gating of the second input terminal of the first multiplexer 31; the second multiplexer 32 can control the second input terminal of the second multiplexer 32 to be connected to the output terminal of the second multiplexer 32, thereby realizing the gating of the second input terminal of the second multiplexer 32.

[0054] Optionally, the potentials of the presence detection signals sent by the connector interface and the gold finger interface may be different, and the multiplexer may determine the selection condition of the input end of the multiplexer based on the potential level of the signal received by the control end.

[0055] Alternatively, the potentials of the in-place detection signals sent by the connector interface and the gold finger interface may be the same, and the control end of the multiplexer may include a first contact and a second contact, the first contact may be connected to the first in-place detection end, and the second contact may be connected to the second in-place detection end. The multiplexer may determine the gating condition of the input end of the multiplexer based on the level states of the signals received by the first contact and the second contact.

[0056] According to an embodiment of the present disclosure, by connecting the in-place detection signal to the control end of the multiplexer, the multiplexer can automatically identify the access status of the two physical interfaces to achieve automatic switching of the source of the PCIe signal, thereby eliminating the need to add additional control logic to the multiplexer, thereby reducing the computing resource loss of the memory expansion card.

[0057] Optionally, the memory expansion card further includes a clock unit, and the clock unit can be used to provide clock signals for m memory expansion controllers respectively.

[0058] Figure 4A A schematic diagram of a memory expansion card according to another embodiment of the present disclosure is schematically shown.

[0059] like Figure 4A As shown, the memory expansion card 400A may further include a clock unit 60, and the clock unit 60 may be provided with a first clock signal output terminal and a second clock signal output terminal, the first clock signal output terminal may be connected to the first memory expansion controller 41, and the second clock signal output terminal may be connected to the second memory expansion controller 42. The clock unit 60 may output a clock signal through the first clock signal output terminal and the second clock signal output terminal, respectively.

[0060] The implementation of the clock unit is not limited herein. For example, in one embodiment, the clock unit may be a clock signal generator. The clock signal generator may be connected to the m memory expansion controllers respectively. The clock signal generator may generate a clock signal by means of the vibration of an internal crystal, an internally set oscillator, etc., and provide the clock signal to the m memory expansion controllers respectively.

[0061] Figure 4B A schematic diagram of a memory expansion card according to another embodiment of the present disclosure is schematically shown.

[0062] like Figure 4B As shown, the memory expansion card 400B may further include a clock signal generator 61, and the clock signal generator 61 may be provided with a first clock signal output terminal and a second clock signal output terminal, the first clock signal output terminal may be connected to the first memory expansion controller 41, and the second clock signal output terminal may be connected to the second memory expansion controller 42. The clock signal generator 61 may output a clock signal through the first clock signal output terminal and the second clock signal output terminal respectively.

[0063] Optionally, the clock signal generator 61 can provide a synchronous clock signal to the first memory expansion controller 41 and the second memory expansion controller 42, that is, the clock signal output through the first clock signal output terminal and the clock signal output through the second clock signal output terminal can be the same clock signal. In this case, the extended memories respectively connected to the first memory expansion interface 51, the second memory expansion interface 52, the third memory expansion interface 53 and the fourth memory expansion interface 54 can work under the same clock signal.

[0064] Alternatively, the clock signal generator 61 may provide an asynchronous clock signal to the first memory expansion controller 41 and the second memory expansion controller 42, that is, the clock signal output through the first clock signal output terminal and the clock signal output through the second clock signal output terminal may be different clock signals. At this time, the extended memory connected to the first memory expansion interface 51 and the second memory expansion interface 52 respectively may work under the first clock signal, and the extended memory connected to the third memory expansion interface 53 and the fourth memory expansion interface 54 respectively may work under the second clock signal. There may be a difference between the first clock signal and the second clock signal in signal frequency and / or signal phase.

[0065] According to an embodiment of the present disclosure, by using a signal generator to provide a clock signal for a memory expansion card, the clock architecture of the memory expansion card can be switched between an SRNS (Separate Reference Clock with No Spread) architecture and an SRIS (Separate Reference Clock Independent Spread) architecture, thereby improving the application flexibility of the memory expansion card.

[0066] For another example, in one embodiment, the clock unit may include a clock signal selector and a clock signal buffer.

[0067] The clock signal selector can be a multiplexer, which can realize the gating of the clock signal. The input end of the clock signal selector is respectively connected to the connector interface and the gold finger interface, and the output end of the clock signal selector is connected to the clock signal buffer. The clock signal selector is used to gating the clock signal from the connector interface or the clock signal from the gold finger interface to the clock signal buffer.

[0068] The clock signal buffers can be connected to the m memory expansion controllers respectively, and the clock signal buffers can be used to store clock signals and provide clock signals to the m memory expansion controllers respectively.

[0069] Figure 4C A schematic diagram of a memory expansion card according to another embodiment of the present disclosure is schematically shown.

[0070] like Figure 4C As shown, the memory expansion card 400C may further include a clock signal selector 62 and a clock signal buffer 63 .

[0071] The clock signal selector 62 may have a first input terminal and a second input terminal, wherein the first input terminal may be connected to the clock signal output terminal of the connector interface 10, and the second input terminal may be connected to the clock signal output terminal of the gold finger interface 20. The clock signal output terminal of the connector interface 10 may output the clock signal of the external device connected to the connector interface 10, and similarly, the clock signal output terminal of the gold finger interface 20 may output the clock signal of the external device connected to the gold finger interface 20.

[0072] The output end of the clock signal selector 62 can be connected to the clock signal buffer 63. The clock signal selector 62 can transmit the clock signal from the connector interface 10 or the clock signal from the gold finger interface 20 to the clock signal buffer 63.

[0073] The clock signal buffer 63 can cache the received clock signal and can be connected to the first memory expansion controller 41 and the second memory expansion controller 42 respectively, so as to provide the cached clock signal to the first memory expansion controller 41 and the second memory expansion controller 42 respectively.

[0074] The clock signal selector 62 can select the first input terminal and the second input terminal based on the received control signal. The source of the control signal received by the clock signal selector 62 is not limited here. For example, the control signal can be provided by a processor configured on the memory expansion card 400C; or, the control signal can also be provided by an external device connected to the memory expansion card 400C; or, the control signal can include the respective in-place detection signals of the connector interface 10 and the gold finger interface 20, and the in-place detection signal can be used to indicate the connection status of the corresponding interface; it is not limited here.

[0075] For example, in one embodiment, the connector interface includes a first in-place detection terminal, and the gold finger interface includes a second in-place detection terminal; wherein the control terminal of the clock signal selector is respectively connected to the first in-place detection terminal and the second in-place detection terminal, and the clock signal selector is used to respond to the in-place detection signal from the first in-place detection terminal or the in-place detection signal from the second in-place detection terminal, and select the clock signal from the connector interface or the clock signal from the gold finger interface to the clock signal buffer.

[0076] Figure 4D A schematic diagram of a memory expansion card according to another embodiment of the present disclosure is schematically shown.

[0077] like Figure 4D As shown, in the memory expansion card 400D, the connector interface 10 may include a first in-place detection terminal AD1, and the gold finger interface 20 may include a second in-place detection terminal AD2. The control terminal C3 of the clock signal selector 62 may be connected to the first in-place detection terminal AD1 and the second in-place detection terminal AD2, respectively. The first input terminal of the clock signal selector 62 may be connected to the connector interface 10, and the second input terminal of the clock signal selector 62 may be connected to the gold finger interface 20.

[0078] When the connector interface 10 is connected to an external device, the connector interface 10 can send a presence detection signal to the control terminal C3 of the clock signal selector 62 through the first presence detection terminal AD1. After receiving the presence detection signal, the clock signal selector 62 can control the first input terminal of the clock signal selector 62 to be connected to the output terminal of the clock signal selector 62, thereby realizing the gating of the first input terminal of the clock signal selector 62. When the gold finger interface 20 is connected to an external device, the gold finger interface 20 can send a presence detection signal to the control terminal C3 of the clock signal selector 62 through the second presence detection terminal AD2. After receiving the presence detection signal, the clock signal selector 62 can control the second input terminal of the clock signal selector 62 to be connected to the output terminal of the clock signal selector 62, thereby realizing the gating of the second input terminal of the clock signal selector 62.

[0079] According to an embodiment of the present disclosure, by providing a clock signal from a connector interface or a gold finger interface to a memory expansion controller, clock synchronization between an external device and an extended memory can be achieved, thereby reducing the risk of extended memory working errors and improving the reliability of the memory expansion card.

[0080] Optionally, the memory expansion card may be further configured with m flash memory units, which may be respectively connected to the m memory expansion controllers for communication, and the flash memory units are used to store firmware programs, which are used to execute data signal communication between the memory expansion controller and the connector interface or the gold finger interface.

[0081] Figure 5 A schematic diagram of a memory expansion card according to another embodiment of the present disclosure is schematically shown.

[0082] like Figure 5 , the memory expansion card 500 may include a first flash memory unit 71 and a second flash memory unit 72 .

[0083] The first flash memory unit 71 may be connected to the first memory expansion controller 41. The first flash memory unit 71 may store a first firmware program, which may be read and executed by the first memory expansion controller 41. When an external device is connected to the connector interface 10 or the gold finger interface 20, the first memory expansion controller 41 may execute the first firmware program so that the first firmware program executes data signal communication between the first memory expansion controller 41 and the connector interface 10 or the gold finger interface 20.

[0084] Similarly, the second flash memory unit 72 can be connected to the second memory expansion controller 42. The second flash memory unit 72 can store a second firmware program, which can be read and run by the second memory expansion controller 42. When an external device is connected to the connector interface 10 or the gold finger interface 20, the second memory expansion controller 42 can run the second firmware program so that the second firmware program executes data signal communication between the second memory expansion controller 42 and the connector interface 10 or the gold finger interface 20.

[0085] The interface type of the memory expansion interface is not limited here. For example, the memory expansion interface can be a DDR5 DIMM interface adapted to a DDR5 RDIMM memory stick. Since a power chip is usually configured on a DDR5 RDIMM memory stick, in this case, no additional power chip and power circuit need to be provided on the memory expansion card.

[0086] Alternatively, in some embodiments, the memory expansion interface may also be a DDR4 DIMM interface adapted to a DDR4 RDIMM memory stick. Since a DDR4 RDIMM memory stick is usually not equipped with a power chip, a power chip needs to be mounted on the memory expansion card so that the power chip can provide multiple working power supplies for the DDR4 RDIMM memory stick.

[0087] Due to the limitation of the board size specification, the memory expansion card cannot be arbitrarily enlarged in size or modified in appearance. After the connector interface, multiplexer and a large number of PCIe are added to the memory expansion card, there is not enough space on the memory expansion card to place the power chip and power circuit required for the DDR4 RDIMM memory bar. Therefore, a power interface can be set on the memory expansion card, and the power chip and power circuit required for the DDR4 RDIMM memory bar can be placed on an additional power board. The power board can be vertically plugged into the memory expansion card through the power interface so that the power board can supply power to the DDR4 RDIMM memory bar.

[0088] Optionally, the memory expansion card may further include m power supply interfaces, the m power supply interfaces correspond to the m memory expansion controllers respectively, and the power supply interfaces corresponding to the memory expansion controllers are respectively electrically connected to the n memory expansion interfaces connected to the memory expansion controllers. The power supply interface is used to access the power board, and the memory expansion interface is used to access the extended memory; wherein the power board connected to the power supply interface corresponding to the memory expansion controller is used to supply power to the extended memory connected to the n memory expansion interfaces connected to the memory expansion controller.

[0089] According to the embodiments of the present disclosure, by setting a power interface on the memory expansion card, the power chip and power circuit required for the DDR4 RDIMM memory stick can be designed on a separate power board, thereby occupying less horizontal space of the memory expansion card, and the separate power board is also convenient for replacement and maintenance at any time without the need to replace and maintain the entire memory expansion card, thereby reducing maintenance costs. Figure 6 The schematic diagram of the layout and wiring of the memory expansion card according to the embodiment of the present disclosure is schematically shown.

[0090] like Figure 6 As shown, a gold finger interface may be provided below the memory expansion card 600, and a connector interface may be provided on the left side of the memory expansion card 600. The dotted line on the memory expansion card 600 may indicate the location of the x8 PCIe Lane wiring. A first memory expansion interface and a second memory expansion interface may be provided above the memory expansion card 600, and a first multiplexer, a first memory expansion controller and a first power supply interface may be provided adjacent to the second memory expansion interface, so that the first memory expansion controller communicates data with the first memory expansion interface and the second memory expansion interface respectively, and the first power supply interface supplies power to the first memory expansion interface and the second memory expansion interface respectively. A third memory expansion interface and a fourth memory expansion interface may be provided at the central position of the memory expansion card 600. A second multiplexer, a second memory expansion controller and a second power supply interface may be provided below the fourth memory expansion interface. A layout position of a clock signal selector, a clock signal buffer and a clock signal generator may be provided below the fourth memory expansion interface. Optionally, when assembling the memory expansion card 600, you can choose to assemble a clock signal selector and a clock signal buffer at the corresponding layout position without assembling a clock signal generator; or, you can also choose to assemble a clock signal generator at the corresponding layout position without assembling a clock signal selector and a clock signal buffer, which is not limited here.

[0091] In an embodiment of the present disclosure, the memory expansion interface includes a base and a memory slot; wherein the memory slot is configured to be tilted on the base, and the angle between the memory slot and the memory expansion card 600 is within a preset angle range.

[0092] Figure 7 The schematic diagram shows the structure of the memory expansion interface according to the embodiment of the present disclosure.

[0093] like Figure 7 As shown, the memory expansion interface 50 may include a base 501 and a memory slot 502. The base 501 may be fixedly arranged on the memory expansion card. The memory slot 502 may be tiltedly arranged on the base 501.

[0094] According to an embodiment of the present disclosure, when the extended memory is connected to the memory slot, the extended memory can be tilted relative to the memory expansion card. Compared with vertically connecting the extended memory to the memory expansion interface, this tilted setting method can reduce the height of the memory expansion card in the vertical direction, thereby improving the layout density of the memory expansion card in the entire machine and increasing the memory expansion capacity of a single machine.

[0095] Figure 8 A schematic diagram of an electronic device according to an embodiment of the present disclosure is schematically shown.

[0096] like Figure 8 As shown, the electronic device 800 may include at least one memory expansion card 810, and the memory expansion card 810 may be any one of the memory expansion card 100, memory expansion card 200, memory expansion card 300, memory expansion card 400A, memory expansion card 400B, memory expansion card 400C, memory expansion card 400D, memory expansion card 500 and memory expansion card 600 as described above, without limitation herein.

[0097] The electronic device 800 may further include a mainboard 820, which may be disposed inside the host of the electronic device 800. The mainboard 820 may include a processor 821 and at least one memory interface 822. The at least one memory interface may be connected to at least one memory expansion card 810, respectively, so that the at least one memory expansion card 810 provides an extended memory for the processor 821.

[0098] Optionally, the electronic device 800 can be used to access multiple extended memories through a memory expansion card 810; wherein the extended memory is configured to be obliquely accessed to a memory expansion interface of the memory expansion card 810.

[0099] Fig. 9 The flowchart of the memory expansion method according to the embodiment of the present disclosure is schematically shown.

[0100] like Fig. 9 As shown, the memory expansion method 900 may include operations S910 to S920.

[0101] In operation S910, in response to an external host accessing the connector interface or the gold finger interface, a data signal from the connector interface or a data signal from the gold finger interface is selected to a memory expansion controller through a multiplexer.

[0102] In operation S910, a data signal is transmitted to an extended memory through a memory expander, wherein the extended memory is configured to be communicatively connected with the memory expander through a memory expansion interface of the memory expander.

[0103] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0104] It will be appreciated by those skilled in the art that the features described in the various embodiments of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure may be combined and / or combined in a variety of ways. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0105] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A memory expansion card, comprising: A connector interface, a gold finger interface, m multiplexers and m memory expansion controllers, where m is an integer greater than 1; The input end of the multiplexer is connected to the connector interface and the gold finger interface respectively, the output end of the multiplexer is connected to the memory expansion controller, and the multiplexer is used to select the data signal from the connector interface or the data signal from the gold finger interface to the memory expansion controller; and The expansion ends of the memory expansion controller are respectively connected to n memory expansion interfaces, and the memory expansion controller is used to transmit the data signal to the n memory expansion interfaces, where n is a positive integer.

2. The memory expansion card according to claim 1, wherein: The memory expansion card also includes: m power supply interfaces, the m power supply interfaces respectively correspond to the m memory expansion controllers, and the power supply interfaces corresponding to the memory expansion controllers are respectively electrically connected to n memory expansion interfaces connected to the memory expansion controllers.

3. The memory expansion card according to claim 2, wherein: The power interface is used to access the power board, and the memory expansion interface is used to access the extended memory; The power board connected to the power interface corresponding to the memory expansion controller is used to supply power to the extended memory connected to each of the n memory expansion interfaces connected to the memory expansion controller.

4. The memory expansion card according to claim 1, wherein: The connector interface includes a first in-place detection terminal, and the gold finger interface includes a second in-place detection terminal; The control end of the multiplexer is respectively connected to the first in-place detection end and the second in-place detection end, and the multiplexer is used to select the data signal from the connector interface or the data signal from the gold finger interface to the memory expansion controller in response to the in-place detection signal from the first in-place detection end or the in-place detection signal from the second in-place detection end.

5. The memory expansion card according to claim 1, further comprising: The clock unit is used to provide clock signals to the m memory expansion controllers respectively.

6. The memory expansion card according to claim 5, wherein: The clock unit includes a clock signal selector and a clock signal buffer; The input end of the clock signal selector is connected to the connector interface and the gold finger interface respectively, the output end of the clock signal selector is connected to the clock signal buffer, and the clock signal selector is used to select the clock signal from the connector interface or the clock signal from the gold finger interface to the clock signal buffer; The clock signal buffers are connected to the m memory expansion controllers respectively, and are used to store the clock signals and provide the clock signals to the m memory expansion controllers respectively.

7. The memory expansion card according to claim 6, wherein: The connector interface includes a first in-place detection terminal, and the gold finger interface includes a second in-place detection terminal; Among them, the control end of the clock signal selector is respectively connected to the first in-place detection end and the second in-place detection end, and the clock signal selector is used to respond to the in-place detection signal from the first in-place detection end or the in-place detection signal from the second in-place detection end, and select the clock signal from the connector interface or the clock signal from the gold finger interface to the clock signal buffer.

8. The memory expansion card according to claim 5, wherein: The clock unit includes a clock signal generator; The clock signal generators are connected to the m memory expansion controllers respectively, and are used to generate clock signals and provide the clock signals to the m memory expansion controllers respectively.

9. The memory expansion card according to claim 1, further comprising: m flash memory units, the m flash memory units are respectively connected to the m memory expansion controllers for communication, the flash memory units are used to store firmware programs, and the firmware programs are used to execute data signal communication between the memory expansion controller and the connector interface or the gold finger interface.

10. The memory expansion card according to claim 1, wherein: The connector interface or the gold finger interface is used to access m×n×k data signals respectively, where k is an integer greater than 1; The multiplexer is used to receive n×k data signals from the connector interface through a first memory consistency bus, or n×k data signals from the gold finger interface through a second memory consistency bus, and transmit the n×k data signals to the memory expansion controller through a third memory consistency bus.

11. The memory expansion card according to claim 10, wherein: The expansion end of the memory expansion controller includes n memory channels, and the memory expansion controller is further used to transmit k data signals to the n memory expansion interfaces through the n memory channels respectively.

12. The memory expansion card according to any one of claims 1 to 11, wherein: The memory expansion interface includes a base and a memory slot; The memory slot is configured to be tilted on the base, and an angle between the memory slot and the memory expansion card is within a preset angle range.

13. An electronic device comprising at least one memory expansion card according to any one of claims 1 to 12.

14. The electronic device according to claim 13, wherein: The electronic device is used to access multiple extended memories through the memory expansion card; Wherein, the extended memory is configured to be obliquely connected to the memory expansion interface of the memory expansion card.

15. A memory expansion method, comprising: In response to an external host accessing the connector interface or the gold finger interface, a data signal from the connector interface or a data signal from the gold finger interface is selected to the memory expansion controller through a multiplexer; as well as The data signal is transmitted to an extended memory via the memory expander, wherein the extended memory is configured to be communicatively connected with the memory expander via a memory expansion interface of the memory expander.

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