Memory device performance regulation and control method and device and electronic equipment

Abstract

The invention provides a memory device performance regulation and control method and device and electronic equipment, and belongs to the technical field of memories. The method comprises the following steps: performing ion implantation simulation on all initial ion implantation conditions by using SRIM software to obtain an ion doping distribution parameter set corresponding to each initial ion implantation condition; screening out an optimal ion doping distribution parameter set meeting a set condition from the ion doping distribution parameter sets of all the initial ion implantation conditions; and based on TCAD software, carrying out overall preparation process flow simulation on the memory selecting the initial ion implantation condition corresponding to the optimal ion doping distribution parameter set. According to the method, SRIM software and TCAD software are combined, the initial ion implantation condition corresponding to the optimal ion doping distribution parameter set is selected from a plurality of initial ion implantation conditions to serve as the optimal implantation condition according to the CNLDD implantation technology for the drain electrode of the device in the technological process, the ion implantation mode is accurately regulated and controlled, and high performance of the storage device is achieved.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory device performance control method, a memory device performance control device, an electronic device, a machine-readable storage medium and a computer program product. Background Art

[0002] Ion implantation technology in the memory preparation process is a semiconductor doping process developed in the 1960s. The development of ion implantation technology is driving progress in the field of integrated circuits. At present, ion implantation is the main doping process used in the production and manufacturing of very large-scale integrated circuits. Compared with other semiconductor doping processes such as diffusion processes, ion implantation can ensure that the doping purity is not affected by the impurity source and can accurately control the number of doping atoms or ions injected into the substrate. By controlling the energy and dose of the injected ions and using multiple injections of the same or different impurities, the impurity distribution can be controlled.

[0003] Since ion implantation technology involves many parameters, the impact of ion implantation technology under various parameter setting modes on the electrical performance of memory devices needs to be systematically analyzed. How to accurately control the ion implantation mode to achieve high performance of memory devices has become an urgent problem to be solved. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a method, apparatus and electronic device for controlling the performance of a memory device, so as to solve the problem of how to accurately control the ion implantation mode to achieve high performance of the memory device, which has become an urgent problem to be solved.

[0005] In order to achieve the above object, an embodiment of the present invention provides a method for controlling performance of a memory device, comprising:

[0006] Acquiring a plurality of initial ion implantation conditions of an ion implantation process for a drain of a memory;

[0007] Using SRIM software to perform ion implantation simulation on all the initial ion implantation conditions to obtain an ion doping distribution parameter set corresponding to each initial ion implantation condition; the ion doping distribution parameter set includes an average ion penetration depth and an ion peak concentration;

[0008] Selecting an optimal ion doping distribution parameter set that meets the set conditions from the ion doping distribution parameter sets of all the initial ion implantation conditions;

[0009] Based on TCAD software, the overall preparation process flow of the memory using the initial ion implantation conditions corresponding to the optimal ion doping distribution parameter set is simulated.

[0010] Optionally, the step of selecting an optimal ion doping distribution parameter set that meets set conditions from the ion doping distribution parameter sets of all the initial ion implantation conditions includes:

[0011] Selecting an ion doping distribution parameter set that meets the set conditions from all the ion doping distribution parameter sets of the initial ion implantation conditions as the optimal ion doping distribution parameter set; or,

[0012] A plurality of ion doping distribution parameter sets satisfying set conditions are screened out from the ion doping distribution parameter sets of all the initial ion implantation conditions; an ion doping distribution parameter set consisting of an average value of the average ion penetration depth and an average value of the ion peak concentration in the plurality of ion doping distribution parameter sets is used as the optimal ion doping distribution parameter set.

[0013] Optionally, the setting conditions include an average ion penetration depth of 90 nm to 115 nm, an ion peak concentration greater than or equal to 1×10 15 cm-3.

[0014] Optionally, the overall manufacturing process flow simulation of the memory using the initial ion implantation conditions corresponding to the optimal ion doping distribution parameter set based on the TCAD software includes:

[0015] Based on the Sprocess module in the TCAD software, the overall preparation process flow of the memory using the optimal ion doping distribution parameter set is simulated to obtain a first simulation result;

[0016] Performing device electrical performance simulation and / or reliability performance simulation on the first simulation result based on the Sdevice module in the TCAD software to obtain a second simulation result;

[0017] Simulation parameters are obtained based on the second simulation result; the simulation parameters include the programming and erasing threshold voltage window of the device and / or the number of cycles of reliability.

[0018] Optionally, the initial ion implantation conditions include at least two of implantation energy, masking layer type, implantation dose, masking layer thickness, implantation times and implantation angle.

[0019] On the other hand, an embodiment of the present invention further provides a memory device performance control device, comprising:

[0020] An acquisition module, used for acquiring a plurality of initial ion implantation conditions of an ion implantation process of a memory drain;

[0021] A first simulation module is used to perform ion implantation simulation on all the initial ion implantation conditions using SRIM software to obtain an ion doping distribution parameter set corresponding to each initial ion implantation condition; the ion doping distribution parameter set includes an average ion penetration depth and an ion peak concentration;

[0022] A screening module, used to screen out an optimal ion doping distribution parameter set that meets set conditions from all ion doping distribution parameter sets of the initial ion implantation conditions;

[0023] The second simulation module is used to simulate the overall preparation process flow of the memory using the initial ion implantation conditions corresponding to the optimal ion doping distribution parameter set based on TCAD software.

[0024] Optionally, the step of selecting an optimal ion doping distribution parameter set that meets set conditions from the ion doping distribution parameter sets of all the initial ion implantation conditions includes:

[0025] Selecting an ion doping distribution parameter set that meets the set conditions from all the ion doping distribution parameter sets of the initial ion implantation conditions as the optimal ion doping distribution parameter set; or,

[0026] A plurality of ion doping distribution parameter sets satisfying set conditions are screened out from the ion doping distribution parameter sets of all the initial ion implantation conditions; an ion doping distribution parameter set consisting of an average value of the average ion penetration depth and an average value of the ion peak concentration in the plurality of ion doping distribution parameter sets is used as the optimal ion doping distribution parameter set.

[0027] Optionally, the setting conditions include an average ion penetration depth of 90 nm to 115 nm, an ion peak concentration greater than or equal to 1×10 15 cm-3.

[0028] Optionally, the overall manufacturing process flow simulation of the memory using the initial ion implantation conditions corresponding to the optimal ion doping distribution parameter set based on the TCAD software includes:

[0029] Based on the Sprocess module in the TCAD software, the overall preparation process flow of the memory using the optimal ion doping distribution parameter set is simulated to obtain a first simulation result;

[0030] Performing device electrical performance simulation and / or reliability performance simulation on the first simulation result based on the Sdevice module in the TCAD software to obtain a second simulation result;

[0031] Simulation parameters are obtained based on the second simulation result; the simulation parameters include the programming and erasing threshold voltage window of the device and / or the number of cycles of reliability.

[0032] Optionally, the initial ion implantation conditions include at least two of implantation energy, masking layer type, implantation dose, masking layer thickness, implantation times and implantation angle.

[0033] On the other hand, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned memory device performance control method when executing the program.

[0034] On the other hand, the present invention further provides a machine-readable storage medium having a computer program stored thereon, and the computer program implements the above-mentioned memory device performance control method when executed by a processor.

[0035] On the other hand, the present invention also provides a computer program product, including a computer program, and when the computer program is executed by a processor, the above-mentioned memory device performance control method is implemented.

[0036] Through the above technical scheme, the embodiment of the present invention combines the SRIM software and TCAD software for ion implantation simulation, mainly for the CNLDD implantation process of the device drain in the process flow, and selects the initial ion implantation condition corresponding to the optimal ion doping distribution parameter set from multiple initial ion implantation conditions as the optimal implantation condition, so as to realize precise control of the ion implantation mode and achieve high performance of the storage device.

[0037] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0039] Figure 1 This is one of the flow charts of the memory device performance control method provided by the present invention;

[0040] Figure 2 This is the second flow chart of the method for controlling the performance of a memory device provided by the present invention;

[0041] Figure 3 It is a schematic diagram of the doping distribution of the substrate after vertical angle implantation provided by the present invention;

[0042] Figure 4 It is a schematic diagram of substrate doping distribution at an implantation angle in an optimal implantation condition corresponding to an optimal ion doping distribution parameter set provided by the present invention;

[0043] Figure 5 It is a schematic diagram of electrical performance simulated by TCAD software provided by the present invention;

[0044] Figure 6 It is a structural schematic diagram of the memory device performance control device provided by the present invention;

[0045] Figure 7 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0046] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0047] Method Embodiment

[0048] Please refer to Figure 1 , an embodiment of the present invention provides a method for controlling performance of a memory device, comprising:

[0049] Step 100: Acquire a plurality of initial ion implantation conditions of an ion implantation process for a memory drain.

[0050] The electronic device obtains multiple initial ion implantation conditions of the ion implantation process of the memory drain. Among them, the initial ion implantation conditions include at least two of the implantation energy, the type of masking layer, the implantation dose, the thickness of the masking layer, the number of implantations, and the implantation angle. In one embodiment, the initial ion implantation conditions include the implantation energy, the type of masking layer, the implantation dose, the thickness of the masking layer, the number of implantations, and the implantation angle in the CNLDD implantation process of the device drain in the process flow of the memory device. Among them, the types of masking layers include Si3N4, SiO2, etc. The target material includes silicon or gallium arsenide. The ion types include boron (B), phosphorus (P), or arsenic (As), etc. The implantation energy is between tens of keV and hundreds of keV, which determines the penetration depth of the ions in the target material, and the implantation dose determines the doping concentration in the target material. After confirming these parameters, the parameters can be set in the SRIM software.

[0051] Step 200: Use SRIM software to perform ion implantation simulation on all the initial ion implantation conditions to obtain an ion doping distribution parameter set corresponding to each initial ion implantation condition.

[0052] The electronic device uses SRIM software to perform ion implantation simulation on all the initial ion implantation conditions to obtain an ion doping distribution parameter set corresponding to each initial ion implantation condition. The ion doping distribution parameter set includes an average ion penetration depth and an ion peak concentration.

[0053] Specifically, 15 to 25 steps of ion implantation are generally used in modern semiconductor processes. The most important process parameters are implantation energy, type of masking layer, implantation dose, number of implantations, and implantation angle. In the ion implantation process of the embodiment of the present invention, when a beam of boron ions is selected to bombard a silicon-based substrate, a portion of the scattered boron ions is reflected on the target surface and cannot enter the silicon-based substrate. The boron ions that enter the silicon-based substrate are called implanted boron ions. This part of the scattered boron ions will continuously collide with the nuclei and extranuclear electrons of the target atoms, and lose energy until they finally stop at a certain position on the silicon substrate. Some collision processes are random, so the study of the distribution of these doped ions near the drain region of the substrate requires consideration of the deflection angle, energy loss, travel distance between two adjacent collisions, and total movement distance of a large number of ions. These large numbers of ions can be used to quickly estimate the doping distribution of the implanted ions in the target using Gaussian distribution. The important parameters after parameterizing this process are: average ion penetration depth and ion peak concentration.

[0054] The electronic device sets parameters in the SRIM software based on multiple initial ion implantation conditions. Continue to start the simulation run, and the SRIM software will generate data such as the depth distribution of ions in the material, energy loss, and doping distribution. After the simulation is completed, the SRIM software will generate some key results: the average ion penetration depth and ion peak concentration are important parameters for describing ion distribution. With these values, the depth and concentration distribution of the doping layer can be estimated.

[0055] The embodiment of the present invention uses SRIM software to calculate and simulate in detail every detail of the collision process between the implanted ions and the target material atoms under different initial ion implantation conditions (different implantation energies, types of masking layers, implantation doses, implantation times, and implantation angle conditions), and can provide a simulation image of the final stop range of the implanted ions. Through this method, the average penetration depth of ions and the peak ion concentration under different modes are summarized to avoid the deformity of the gradient doping concentration distribution curve of the silicon surface layer and select a suitable ion implantation mode. The above discussion is about a single injection method, and multiple injections are required to achieve gradient doping. The TRIM software is used to study the influence of multiple energy injection modes on the doping distribution.

[0056] Step 300: Filter out an optimal ion doping distribution parameter set that meets set conditions from all ion doping distribution parameter sets of the initial ion implantation conditions.

[0057] The setting conditions include an average ion penetration depth of 90 nm to 115 nm and an ion peak concentration greater than or equal to 1×10 15cm-3. The optimal ion doping distribution parameter set may include one or more. In the case where the optimal ion doping distribution parameter set may include one or more, the optimal ion doping distribution parameter set may be determined according to the following manner.

[0058] The step of selecting an optimal ion doping distribution parameter set that meets set conditions from the ion doping distribution parameter sets of all the initial ion implantation conditions comprises: selecting an ion doping distribution parameter set that meets the set conditions from the ion doping distribution parameter sets of all the initial ion implantation conditions as the optimal ion doping distribution parameter set; or selecting multiple ion doping distribution parameter sets that meet the set conditions from the ion doping distribution parameter sets of all the initial ion implantation conditions; and selecting an ion doping distribution parameter set composed of an average value of average ion penetration depths and an average value of ion peak concentrations in multiple ion doping distribution parameter sets as the optimal ion doping distribution parameter set.

[0059] That is, when the ion doping distribution parameter set that meets the set conditions includes one, it is determined to be the optimal ion doping distribution parameter set. The initial ion implantation condition corresponding to the optimal ion doping distribution parameter set is that the CNLDD lightly doped drain region selects the following doping mode: the first time, the implantation dose: 3e14, the implantation energy: As implantation at 2keV; the second time, the implantation dose: 2e13, the implantation energy: 35keV, the BF2 implantation at an implantation angle of 25°; the third time, the implantation dose: 2.5e13, the implantation energy: 20keV, the B implantation at an implantation angle of 45°. The above modes can achieve the working state threshold voltage window of the memory device: >6V; the number of cycles of device reliability: >100k.

[0060] When there are multiple ion doping distribution parameter sets that meet the set conditions, an embodiment of the present invention may use an ion doping distribution parameter set composed of the average values ​​of the average ion penetration depths and the average values ​​of the ion peak concentrations in the multiple ion doping distribution parameter sets as the optimal ion doping distribution parameter set.

[0061] The embodiment of the present invention can find the most suitable optimal implantation conditions by repeatedly adjusting the ion implantation parameters in the initial ion implantation conditions and analyzing the simulation results (ion doping distribution parameter set) to achieve the goal of optimizing doping and controlling device performance.

[0062] Step 400: Based on TCAD software, an overall manufacturing process flow simulation is performed on a memory device using initial ion implantation conditions corresponding to the optimal ion doping distribution parameter set.

[0063] In one embodiment, please refer to Figure 2, the overall preparation process flow simulation of the memory using the initial ion implantation conditions corresponding to the optimal ion doping distribution parameter set based on the TCAD software includes: the overall preparation process flow simulation of the memory using the optimal ion doping distribution parameter set is performed based on the Sprocess module in the TCAD software to obtain a first simulation result; the device electrical performance simulation and / or reliability performance simulation is performed on the first simulation result based on the Sdevice module in the TCAD software to obtain a second simulation result. Simulation parameters are obtained based on the second simulation result; the simulation parameters include the programming and erasing threshold voltage window of the device and / or the number of cycles of reliability.

[0064] The embodiment of the present invention uses sprocess to simulate the overall preparation process of the device according to the optimal injection conditions corresponding to the above optimal ion doping distribution parameter set in combination with TCAD simulation software. The overall preparation process of the device involves the preparation simulation of the substrate, the bottom silicon oxide dielectric layer, the polysilicon selection gate, the first ONO dielectric layer, the floating gate, the second ONO dielectric layer source, the control gate, the top oxide layer, the erase gate, the drain region and the drain CNLDD, the sidewall spacer and the metal connection. Based on the sprocess results, sdevice is used to simulate the electrical performance and reliability of the device, focusing on the reading, programming and erasing of the device, and the transient simulation scans the IV curve of the device under different working conditions and the IV curve after 100k cycles. Based on the above simulation results, simulation parameters such as the programming and erasing threshold voltage window of the device and the number of cycles of reliability can be obtained.

[0065] The following is a comparison of memory performance before and after ion implantation using the best implantation conditions corresponding to the best ion doping distribution parameter set, as described in exemplary embodiments.

[0066] Figure 3 and Figure 4 Schematic diagram of TCAD simulation doping distribution of the present invention, where Figure 3 is the substrate doping distribution after vertical angle implantation, Figure 4 The substrate doping distribution using the implantation angle in the optimal implantation condition. Figure 3 and Figure 4 The different colors represent the total number of electrically active doping ions in the semiconductor material. From red to blue, the total number of electrically active doping ions in the semiconductor material gradually decreases. Figure 3 , Figure 4The horizontal and vertical axes in the figure represent the spatial distribution of the device, in micrometers. The embodiment of the present invention mainly focuses on the CNLDD injection in the drain region, which belongs to the Halo (Pocket) injection. The tilt angle of the injection is relatively large. The injection at a large angle can make the dopants distributed under the gate oxide electrode. The change of the injection tilt angle will cause the change of the threshold voltage and leakage current of the device, which can reduce the strong electric field in the drain region, reduce the lateral expansion width of the drain region and the substrate depletion region, and prevent the source-drain crosstalk phenomenon of the short channel device.

[0067] Figure 5 The diagram of electrical performance simulated by TCAD software in an embodiment of the present invention, wherein the horizontal axis represents the voltage at the control gate (cg) terminal, in V; the vertical axis represents the current at the bit line (bl) terminal, in A. The red and green curves respectively represent the IV electrical property curves of the device under the condition of vertical angle injection in the CNLDD process under the erase and programming working state, and the blue and cyan curves respectively represent the IV electrical property curves of the device under the condition of tilt angle injection in the CNLDD process under the optimal injection condition under the erase and programming working state.

[0068] from Figure 5 It can be seen that the LDD structure (Lightly Doped Drain) of the embodiment of the present invention forms a low-doped shallow junction extension area between the drain source and the gate boundary, and cooperates with the heavily doped drain source to slow down the doping distribution of the drain region, thereby reducing the electric field strength near the drain region. The junction area of ​​the drain-source pn junction facing the channel of these shallow drain-source extension regions is reduced, and the drain source with a heavier doping and a deeper junction depth is connected slightly away from the channel to form a gradual junction so that the depletion layer has a smaller extension range relative to the channel. LDD improves subthreshold leakage. The purpose of the second and third tilted injections is to further reduce the subthreshold current. They belong to pocket injections to increase the impurity ion concentration of the channel region and the drain region substrate, and reduce the lateral expansion width of the depletion region between the drain and the substrate (to prevent drain-source punch-through). The injection depth is greater than the LDD depth. It can be intuitively seen from the device electrical simulation results that this ion injection tilt angle causes the threshold voltage to drift and the leakage current to drop significantly (drop by 2 orders of magnitude).

[0069] In summary, the embodiments of the present invention have the technical advantage of efficiently and accurately controlling the CNLDD process (including other ion implantation processes).

[0070] The present invention combines SRIM software (including injection energy, masking layer type, injection dose, injection number and injection angle condition parts) and TCAD software (including Sprocess software part and Sdevice software part) for ion implantation simulation, mainly targeting the CNLDD implantation process for the device drain in the process flow, and selecting the best implantation condition from different initial ion implantation conditions to achieve the optimal memory operating electrical properties and reliability.

[0071] In other words, the embodiment of the present invention combines the SRIM software and TCAD software for ion implantation simulation, mainly targeting the CNLDD implantation process for the device drain in the process flow, and selects the initial ion implantation condition corresponding to the optimal ion doping distribution parameter set from multiple initial ion implantation conditions as the optimal implantation condition, so as to achieve precise control of the ion implantation mode and realize high performance of the storage device.

[0072] Device Embodiment

[0073] Please refer to Figure 6 On the other hand, an embodiment of the present invention further provides a memory device performance control device, including:

[0074] An acquisition module 601 is used to acquire a plurality of initial ion implantation conditions of an ion implantation process of a memory drain;

[0075] A first simulation module 602 is used to perform ion implantation simulation on all the initial ion implantation conditions using SRIM software to obtain an ion doping distribution parameter set corresponding to each initial ion implantation condition; the ion doping distribution parameter set includes an average ion penetration depth and an ion peak concentration;

[0076] A screening module 603 is used to screen out an optimal ion doping distribution parameter set that meets set conditions from all ion doping distribution parameter sets of the initial ion implantation conditions;

[0077] The second simulation module 604 is used to simulate the overall manufacturing process flow of the memory using the initial ion implantation conditions corresponding to the optimal ion doping distribution parameter set based on TCAD software.

[0078] Optionally, the step of selecting an optimal ion doping distribution parameter set that meets set conditions from the ion doping distribution parameter sets of all the initial ion implantation conditions includes:

[0079] Selecting an ion doping distribution parameter set that meets the set conditions from all the ion doping distribution parameter sets of the initial ion implantation conditions as the optimal ion doping distribution parameter set; or,

[0080] A plurality of ion doping distribution parameter sets satisfying set conditions are screened out from the ion doping distribution parameter sets of all the initial ion implantation conditions; an ion doping distribution parameter set consisting of an average value of the average ion penetration depth and an average value of the ion peak concentration in the plurality of ion doping distribution parameter sets is used as the optimal ion doping distribution parameter set.

[0081] Optionally, the set conditions include an average ion penetration depth of 90 nm to 115 nm and an ion peak concentration greater than or equal to 1×1015 cm-3.

[0082] Optionally, the overall manufacturing process flow simulation of the memory using the initial ion implantation conditions corresponding to the optimal ion doping distribution parameter set based on the TCAD software includes:

[0083] Based on the Sprocess module in the TCAD software, the overall preparation process flow of the memory using the optimal ion doping distribution parameter set is simulated to obtain a first simulation result;

[0084] Performing device electrical performance simulation and / or reliability performance simulation on the first simulation result based on the Sdevice module in the TCAD software to obtain a second simulation result;

[0085] Simulation parameters are obtained based on the second simulation result; the simulation parameters include the programming and erasing threshold voltage window of the device and / or the number of cycles of reliability.

[0086] Optionally, the initial ion implantation conditions include at least two of implantation energy, masking layer type, implantation dose, masking layer thickness, implantation times and implantation angle.

[0087] The memory device performance control device includes a processor and a memory. The above-mentioned acquisition module 601, the first simulation module 602, the screening module 603 and the second simulation module 604 are all stored in the memory as program units, and the processor executes the above-mentioned program units stored in the memory to realize corresponding functions.

[0088] The processor includes a kernel, which calls the corresponding program unit from the memory. There can be one or more kernels.

[0089] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

[0090] Figure 7 An example of a physical structure diagram of an electronic device is shown in FIG. Figure 7As shown, the electronic device may include: a processor 710, a communication interface 720, a memory 730 and a communication bus 740, wherein the processor 710, the communication interface 720 and the memory 730 communicate with each other through the communication bus 740. The processor 710 may call the logic instructions in the memory 730 to execute the memory device performance control method, the method comprising: obtaining multiple initial ion implantation conditions of the ion implantation process of the memory drain; using SRIM software to perform ion implantation simulation on all the initial ion implantation conditions to obtain an ion doping distribution parameter set corresponding to each initial ion implantation condition; the ion doping distribution parameter set includes an average ion penetration depth and an ion peak concentration; selecting an optimal ion doping distribution parameter set that meets the set conditions from the ion doping distribution parameter set of all the initial ion implantation conditions; and performing overall preparation process flow simulation on the memory using the initial ion implantation condition corresponding to the optimal ion doping distribution parameter set based on TCAD software.

[0091] In addition, the logic instructions in the above-mentioned memory 730 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0092] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a machine-readable storage medium. When the computer program is executed by a processor, the computer can execute a memory device performance control method, which includes: obtaining multiple initial ion implantation conditions of the ion implantation process of the memory drain; using SRIM software to perform ion implantation simulation on all the initial ion implantation conditions to obtain an ion doping distribution parameter set corresponding to each initial ion implantation condition; the ion doping distribution parameter set includes an average ion penetration depth and an ion peak concentration; screening out an optimal ion doping distribution parameter set that meets the set conditions from the ion doping distribution parameter set of all the initial ion implantation conditions; and based on TCAD software, simulating the overall preparation process flow of the memory using the initial ion implantation conditions corresponding to the optimal ion doping distribution parameter set.

[0093] On the other hand, the present invention also provides a machine-readable storage medium having a computer program stored thereon, which, when executed by a processor, is implemented to execute a method for controlling the performance of a memory device, the method comprising: obtaining multiple initial ion implantation conditions of the ion implantation process of the memory drain; using SRIM software to perform ion implantation simulation on all the initial ion implantation conditions to obtain an ion doping distribution parameter set corresponding to each initial ion implantation condition; the ion doping distribution parameter set includes an average ion penetration depth and an ion peak concentration; screening out an optimal ion doping distribution parameter set that meets the set conditions from the ion doping distribution parameter set of all the initial ion implantation conditions; and simulating the overall preparation process flow of the memory using the initial ion implantation conditions corresponding to the optimal ion doping distribution parameter set based on TCAD software.

[0094] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0095] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for controlling the performance of a memory device, characterized in that: include: Acquiring a plurality of initial ion implantation conditions of an ion implantation process for a drain of a memory; Using SRIM software to perform ion implantation simulation on all the initial ion implantation conditions to obtain an ion doping distribution parameter set corresponding to each initial ion implantation condition; the ion doping distribution parameter set includes an average ion penetration depth and an ion peak concentration; Selecting an optimal ion doping distribution parameter set that meets the set conditions from the ion doping distribution parameter sets of all the initial ion implantation conditions; Based on TCAD software, the overall preparation process flow of the memory using the initial ion implantation conditions corresponding to the optimal ion doping distribution parameter set is simulated.

2. The memory device performance control method according to claim 1, characterized in that: The step of selecting an optimal ion doping distribution parameter set that meets set conditions from the ion doping distribution parameter sets of all the initial ion implantation conditions comprises: Selecting an ion doping distribution parameter set that meets the set conditions from all the ion doping distribution parameter sets of the initial ion implantation conditions as the optimal ion doping distribution parameter set; or, A plurality of ion doping distribution parameter sets satisfying set conditions are screened out from the ion doping distribution parameter sets of all the initial ion implantation conditions; an ion doping distribution parameter set consisting of an average value of the average ion penetration depth and an average value of the ion peak concentration in the plurality of ion doping distribution parameter sets is used as the optimal ion doping distribution parameter set.

3. The memory device performance control method according to claim 1, characterized in that: The setting conditions include an average ion penetration depth of 90 nm to 115 nm, an ion peak concentration greater than or equal to 1×10 15 cm-3.

4. The memory device performance control method according to claim 1, characterized in that: The overall manufacturing process flow simulation of the memory using the initial ion implantation conditions corresponding to the optimal ion doping distribution parameter set based on the TCAD software includes: Based on the Sprocess module in the TCAD software, the overall preparation process flow of the memory using the optimal ion doping distribution parameter set is simulated to obtain a first simulation result; Performing device electrical performance simulation and / or reliability performance simulation on the first simulation result based on the Sdevice module in the TCAD software to obtain a second simulation result; Simulation parameters are obtained based on the second simulation result; the simulation parameters include the programming and erasing threshold voltage window of the device and / or the number of cycles of reliability.

5. The memory device performance control method according to claim 1, characterized in that: The initial ion implantation conditions include at least two of implantation energy, masking layer type, implantation dose, masking layer thickness, implantation times and implantation angle.

6. A memory device performance control device, characterized in that: include: An acquisition module, used for acquiring a plurality of initial ion implantation conditions of an ion implantation process of a memory drain; A first simulation module is used to perform ion implantation simulation on all the initial ion implantation conditions using SRIM software to obtain an ion doping distribution parameter set corresponding to each initial ion implantation condition; the ion doping distribution parameter set includes an average ion penetration depth and an ion peak concentration; A screening module, used to screen out an optimal ion doping distribution parameter set that meets set conditions from all ion doping distribution parameter sets of the initial ion implantation conditions; The second simulation module is used to simulate the overall preparation process flow of the memory using the initial ion implantation conditions corresponding to the optimal ion doping distribution parameter set based on TCAD software.

7. The memory device performance control device according to claim 6, characterized in that: The step of selecting an optimal ion doping distribution parameter set that meets set conditions from the ion doping distribution parameter sets of all the initial ion implantation conditions comprises: Selecting an ion doping distribution parameter set that meets the set conditions from all the ion doping distribution parameter sets of the initial ion implantation conditions as the optimal ion doping distribution parameter set; or, A plurality of ion doping distribution parameter sets satisfying set conditions are screened out from the ion doping distribution parameter sets of all the initial ion implantation conditions; an ion doping distribution parameter set consisting of an average value of the average ion penetration depth and an average value of the ion peak concentration in the plurality of ion doping distribution parameter sets is used as the optimal ion doping distribution parameter set.

8. The memory device performance control device according to claim 6, characterized in that: The setting conditions include an average ion penetration depth of 90 nm to 115 nm, an ion peak concentration greater than or equal to 1×10 15 cm-3.

9. The memory device performance control device according to claim 6, characterized in that: The overall manufacturing process flow simulation of the memory using the initial ion implantation conditions corresponding to the optimal ion doping distribution parameter set based on the TCAD software includes: Based on the Sprocess module in the TCAD software, the overall preparation process flow of the memory using the optimal ion doping distribution parameter set is simulated to obtain a first simulation result; Performing device electrical performance simulation and / or reliability performance simulation on the first simulation result based on the Sdevice module in the TCAD software to obtain a second simulation result; Simulation parameters are obtained based on the second simulation result; the simulation parameters include the programming and erasing threshold voltage window of the device and / or the number of cycles of reliability.

10. The memory device performance control device according to claim 6, characterized in that: The initial ion implantation conditions include at least two of implantation energy, masking layer type, implantation dose, masking layer thickness, implantation times and implantation angle.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the memory device performance control method according to any one of claims 1 to 5 is implemented.

12. A machine-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the memory device performance control method according to any one of claims 1 to 5 is implemented.

13. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the memory device performance control method according to any one of claims 1 to 5 is implemented.

Images