Solution method and device for interface configuration and acquisition, equipment and storage medium

Abstract

The invention relates to an interface configuration and acquisition solution method and device, equipment and a storage medium, and relates to the technical field of software and hardware co-simulation. The method is based on a hyperSemu system and Testbench containing a simulation code template and a packaging function clip. The method comprises the following steps: creating an hsCompile project; when the design code is received, instantiating and connecting the GPIO TVM in the design code; the GPIO TVM and the design code are compiled in an hsCompile project, and a bit stream file is generated; when the test excitation is received, a simulation code template and a packaging function clip in the Testbench are called, and a target simulation code is generated according to the simulation code template, the packaging function clip and the GPIO TVM; creating an hsRun project, and obtaining an executable file by utilizing the hsRun project according to the target simulation code; and downloading the bit stream file to the FPGA, and executing the executable file on the FPGA to obtain simulation data corresponding to the test excitation. The method has the technical effects that data can be transmitted between software and hardware more quickly, and the hardware simulation speed is increased.

Description

Technical Field

[0001] The present application relates to the technical field of software-hardware co-simulation, and in particular to a method, device, equipment and storage medium for solving the problem of interface configuration and acquisition. Background Art

[0002] Hardware-software co-simulation technology refers to a simulation technology that simultaneously simulates the entire system in which hardware and software are integrated. Signal configuration in hardware accelerated simulation refers to the process of defining, allocating and managing signals in the simulation environment according to simulation requirements and the characteristics of the hardware platform during hardware accelerated simulation. Signal acquisition in hardware accelerated simulation refers to the process of capturing, extracting or reading signal data from a simulation model or hardware platform in a hardware accelerated simulation environment.

[0003] Users initiate configuration of related signal ports by adjusting the DIP switches on the FPGA board to select firmware to configure different clocks and download different bits of hardware operations; signals are usually obtained using the hardware debugging IP core ILA (Integrated Logic Analyzer) logic analyzer provided by Xilinx to capture the digital signals inside the FPGA.

[0004] Signal configuration requires inserting an SD card containing multiple kits into the SD slot of the developer kit. Before use, adjust the dip switches according to requirements and needs. The hardware simulation and debugging efficiency is low when the configuration kit is fixed in advance and the configuration is manually adjusted as needed. Inserting IP core data during signal acquisition occupies RAM resources and affects the layout and routing results. This method is conducive to debugging while also greatly reducing the simulation speed. Summary of the invention

[0005] In order to transfer data between software and hardware faster and improve the speed of hardware simulation, the present application provides a solution, device, equipment and storage medium for interface configuration and acquisition.

[0006] In a first aspect, the present application provides a solution, device, equipment and storage medium for interface configuration and acquisition, adopting the following technical solution: the method is based on a hyperSemu system and a Testbench including a simulation code template and a package function folder, and the method includes:

[0007] Retrieve the installation data of hsCompile in the hyperSemu system, and create an hsCompile project according to the installation data of hsCompile;

[0008] When receiving the design code, instantiate and connect the GPIO TVM in the design code;

[0009] Compile the GPIO TVM and the design code in the hsCompile project to generate a bitstream file;

[0010] When a test stimulus is received, the simulation code template and the package function folder in the Testbench are retrieved, and the target simulation code is generated according to the simulation code template, the package function folder and the GPIO TVM;

[0011] Retrieve the installation data of hsRun in the hyperSemu system, create an hsRun project according to the installation data of hsRun, and obtain an executable file using the hsRun project according to the target simulation code;

[0012] The bit stream file is downloaded to the FPGA, and the executable file is executed on the FPGA to obtain simulation data corresponding to the test stimulus.

[0013] Through the above technical solution, GPIO TVM is instantiated and connected, the system can better debug signal data, debugging efficiency is improved, and simulation efficiency is also improved. Signal data is obtained by combining the encapsulation function and TVM, which avoids IP core data occupying RAM resources and improves simulation efficiency.

[0014] In a specific implementation scheme, instantiating and connecting the GPIO TVM in the design code includes:

[0015] When receiving the setting of data bit width, set TVM parameters according to the data bit width;

[0016] According to the TVM parameters, a GPIOTVM is instantiated and connected at a location where the design code needs to configure data or collect data, and the GPIOTVM includes a GPIO_MASTER TVM for implementing interface configuration and a GPIO_SLAVE TVM for implementing interface acquisition.

[0017] Through the above technical solution, setting the TVM parameters to instantiate the connection GPIOTVM can obtain data with a fixed data width during interface configuration and acquisition, reduce the transmission inconvenience caused by excessively large data, and improve the efficiency of interface configuration and acquisition.

[0018] The hsCompile project is configured with a Stream transactor required for connecting to the TVM. Compiling the GPIO TVM and the design code in the hsCompile project to generate a bitstream file includes:

[0019] Connect the GPIO TVM and the hsCompile project through the Stream transactor;

[0020] Add the design code to the hsCompile project through the GPIO TVM;

[0021] Compile the GPIO TVM and the design code in the hsCompile project to generate a folder, which includes a bitstream file and a system configuration file.

[0022] Through the above technical solution, the GPIO TVM is connected to the hsCompile project through the built-in Stream transactor of the hsCompile project; the design code is connected to the hsCompile project through the GPIO TVM, and the GPIOTVM and design code required for compilation are first added to the hsCompile project. The code is transmitted through TVM to improve the transmission efficiency and the speed of the overall simulation process.

[0023] In a specific implementation scheme, generating target simulation code according to the simulation code template, the package function folder and the GPIO TVM includes:

[0024] Selecting a target encapsulation function corresponding to the test stimulus in the encapsulation function folder;

[0025] Selecting a target GPIOTVM corresponding to the test stimulus in the GPIO TVM;

[0026] The simulation code template is modified according to the target encapsulation function and the target GPIO TVM to obtain the target simulation code.

[0027] Through the above technical solution, the encapsulation function and GPIO TVM corresponding to the test stimulus are selected, and the two pieces of information are modified in the simulation code template to obtain the target simulation code, so that the testbench simulation can be carried out as expected.

[0028] In a specific implementation scheme, obtaining an executable file using the hsRun project according to the target simulation code includes:

[0029] Generating a user template using the system configuration file in the hsRun project, wherein the user template includes an underlying template file;

[0030] Compile the underlying template file and the target simulation code to generate an executable file.

[0031] Through the above technical solution, generating an executable file in the hyperSemu system also requires an underlying template file so that the executable file can be run in the hyperSemu system.

[0032] In a specific implementation scheme, when executing the executable file on the FPGA to obtain simulation data corresponding to the test stimulus, the method further includes:

[0033] Determining whether an instruction to analyze the simulation data is received;

[0034] If an instruction to analyze the simulation data is received, the Testbench is opened to analyze the simulation data of the test stimulus.

[0035] Through the above technical solution, the host computer testbench is closed when there is no need to monitor the simulation, which speeds up the simulation and improves the debugging efficiency. The host computer testbench is opened when monitoring is required.

[0036] In a specific implementation scheme, analyzing the simulation data of the test stimulus includes:

[0037] The simulation data of the test stimulus is transmitted to the Testbench through the GPIO TVM and analyzed.

[0038] Through the above technical solution, more direct data change monitoring can be provided to the TB side through the interface GPIO TVM, so that scripts can be used for collection and comparison, fault analysis and other automated inspections, which improves analysis efficiency and makes analysis results more accurate.

[0039] In a second aspect, the present application provides a device for solving interface configuration and acquisition, which adopts the following technical solution: the device includes:

[0040] The hsCompile project creation module is used to retrieve the installation data of hsCompile in the hyperSemu system and create an hsCompile project according to the installation data of hsCompile;

[0041] Instantiate and connect the GPIO TVM module, for instantiating and connecting the GPIO TVM in the design code when receiving the design code;

[0042] A bitstream file generation module, used to compile the GPIO TVM and the design code in the hsCompile project to generate a bitstream file;

[0043] A simulation code generation module, used for calling the simulation code template and the package function folder in the Testbench when receiving the test stimulus, and generating the target simulation code according to the simulation code template, the package function folder and the GPIO TVM;

[0044] An executable file generation module, used for retrieving the installation data of hsRun in the hyperSemu system, creating an hsRun project according to the installation data of hsRun, and obtaining an executable file by using the hsRun project according to the target simulation code;

[0045] The simulation data generation module is used to download the bit stream file to the FPGA, and execute the executable file on the FPGA to obtain simulation data corresponding to the test stimulus.

[0046] In a third aspect, the present application provides a computer device, which adopts the following technical solution: it includes a memory and a processor, and the memory stores a computer program that can be loaded by the processor and executes the solution for the interface configuration and acquisition as described above.

[0047] In a fourth aspect, the present application provides a computer-readable storage medium, which adopts the following technical solution: a computer program that can be loaded by a processor and execute the above-mentioned interface configuration and acquisition solution is stored.

[0048] In summary, this application has the following beneficial technical effects:

[0049] This application can better debug signal data by instantiating and connecting GPIO TVM, improve debugging efficiency, and also improve simulation efficiency; by combining encapsulation functions and TVM to obtain signal data, it avoids IP core data occupying RAM resources and improves simulation efficiency. Through flexible and changeable GPIO signal configuration and acquisition, it is integrated into transaction-level transmission, reduces the number of software and hardware interactions, and improves hardware simulation and debugging efficiency. Users can switch the signal acquisition module in the host computer test case, saving a lot of practical operations and time. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 It is a flow chart of the solution for interface configuration and acquisition in the embodiment of the present application.

[0051] Figure 2 It is a structural block diagram of a solution device for interface configuration and acquisition in an embodiment of the present application.

[0052] Figure numerals: 201, hsCompile project creation module; 202, instantiated connection GPIOTVM module; 203, bitstream file generation module; 204, simulation code generation module; 205, executable file generation module; 206, simulation data generation module. DETAILED DESCRIPTION

[0053] The following is combined with Figure 1-2 This application is described in further detail.

[0054] The embodiment of the present application discloses a solution for interface configuration and acquisition, which is used to transmit data between software and hardware more quickly and improve the speed of hardware simulation.

[0055] Hardware-software co-simulation technology refers to a simulation technology that simultaneously simulates the entire system in which hardware and software are integrated. Signal configuration in hardware accelerated simulation refers to the process of defining, allocating and managing signals in the simulation environment according to simulation requirements and the characteristics of the hardware platform during hardware accelerated simulation. Signal acquisition in hardware accelerated simulation refers to the process of capturing, extracting or reading signal data from a simulation model or hardware platform in a hardware accelerated simulation environment.

[0056] Users initiate configuration of related signal ports by adjusting the DIP switches on the FPGA board to select firmware to configure different clocks and download different bits of hardware operations; signals are usually obtained using the hardware debugging IP core ILA (Integrated Logic Analyzer) logic analyzer provided by Xilinx to capture the digital signals inside the FPGA.

[0057] Signal configuration requires inserting an SD card containing multiple kits into the SD slot of the developer kit. Before use, adjust the dip switches according to requirements and needs. The hardware simulation and debugging efficiency is low when the configuration kit is fixed in advance and the configuration is manually adjusted as needed. Inserting IP core data during signal acquisition occupies RAM resources and affects the layout and routing results. This method is conducive to debugging while also greatly reducing the simulation speed.

[0058] Therefore, the present application proposes a solution for interface configuration and acquisition to configure and acquire data between software and hardware more quickly, thereby improving the speed of hardware simulation.

[0059] Before describing the present application, some terms or concepts involved in the present application are explained.

[0060] hyperSemu: The hyperSemu system is a fusion hardware simulation accelerator launched by Wuxi Yaco Hongyu Electronics Co., Ltd. It can achieve exponential simulation acceleration, complete iterations within minutes, and significantly shorten the development cycle.

[0061] hsCompile: hsCompile is the compilation system of hyperSemu.

[0062] hsRun: hsRun is the running system of hyperSemu.

[0063] DUT: DUT (Design under Test) is the design to be tested.

[0064] Testbench: In hardware engineering, a testbench is a special device or platform used to test electronic devices or systems. It usually includes a series of signal generators, measuring instruments, and other tools to send specific input signals to the device under test and record its response.

[0065] GPIO: GPIO is the abbreviation of General Purpose Input / Output, which means general input / output. It is one of the very important basic hardware resources in embedded systems and is an interface for digital signal interaction with external devices.

[0066] TVM: TVM is the abbreviation of transaction verification model, which is a collection of transactions that occur on a specific interface.

[0067] GPIO TVM: Combines the interface and transaction verification modules. GPIO TVM includes GPIO_MASTER TVM for implementing interface configuration and GPIO_SLAVE TVM for implementing interface acquisition.

[0068] Encapsulation function: Encapsulation function refers to organizing a specific code block into a single functional unit. The main purpose of the encapsulation function is to improve the readability, maintainability and reusability of the code.

[0069] like Figure 1 As shown, the method specifically comprises the following steps:

[0070] S10, retrieve the installation data of hsCompile in the hyperSemu system, and create an hsCompile project according to the installation data of hsCompile.

[0071] Specifically, the complete hyperSemu system includes hsCompile and hsRun on the software side and the FPGA board on the hardware side. The method of this application is based on the hyperSemu system, and the installation data of hsCompile is retrieved from the hyperSemu system to create an hsCompile project.

[0072] S20: When the design code is received, the GPIO TVM is instantiated and connected in the design code.

[0073] Specifically, DUT is the design to be tested, which contains design code. In order to test the design code function, the design code needs to be received from the DUT side first. In order to implement interface configuration and obtain data, this application instantiates and connects GPIO TVM where the design code needs to be configured or collected. GPIO TVM includes GPIO_MASTERTVM for implementing interface configuration and GPIO_SLAVE TVM for implementing interface acquisition.

[0074] S30, compile GPIO TVM and design code in the hsCompile project to generate a bitstream file.

[0075] Specifically, the hyperSemu system includes an FPGA chip for simulation verification. The GPIOTVM and design code are compiled in the hsCompile project. The hsCompile software process is followed and the software automatically analyzes, including detecting compilation errors, setting clock groups, and setting probe signals as needed. After completing constraints, synthesis, FPGA layout and routing, a bitstream file is generated.

[0076] S40, when the test stimulus is received, the simulation code template and the package function folder in the Testbench are retrieved, and the target simulation code is generated according to the simulation code template, the package function folder and the GPIO TVM.

[0077] Specifically, the host computer Testbench contains a package function folder, which contains multiple functions for users to call on demand. The host computer Testbench will generate a simulation code template for use when performing software-side simulation. When receiving a test stimulus, the test stimulus mainly includes configuration (set) and acquisition (get) data. According to the test stimulus, simulation preparation is performed on the host computer testbench, mainly selecting the package function corresponding to the test stimulus and the GPIO TVM interface to modify the simulation code template to obtain the target simulation code, and transplanting or adapting the existing software simulation test environment or the newly built test platform to the EDA hardware simulation acceleration platform to complete the Testbench preparation.

[0078] S50, retrieve the installation data of hsRun in the hyperSemu system, create an hsRun project according to the installation data of hsRun, and obtain an executable file using the hsRun project according to the target simulation code.

[0079] Specifically, the complete hyperSemu system includes hsCompile and hsRun on the software side and the FPGA board on the hardware side. The present application method is based on the hyperSemu system, retrieves the installation data of hsRun from the hyperSemu system, and then creates an hsRun project, generates an executable file in the hsRun project according to the target simulation code, and enables it to run on the FPGA board.

[0080] S60, downloading the bitstream file to the FPGA, and executing the executable file on the FPGA to obtain simulation data corresponding to the test stimulus.

[0081] Specifically, the bitstream file is downloaded to the FPGA to simulate the performance of the design code, and the executable file is run on the FPGA to obtain simulation data corresponding to the test stimulus.

[0082] Through the interface GPIO TVM can provide more direct data change monitoring to the TB side, so that scripts can be used for collection comparison, fault analysis and other automated inspections, which improves analysis efficiency and makes analysis results more accurate.

[0083] In a specific implementation scheme, the step of instantiating and connecting GPIOTVM in the design code can be specifically performed as follows:

[0084] First, when the data width setting is received, the TVM parameters are set according to the data width. Specifically, the user will set the desired data width according to actual needs, which is reflected in the system as setting the TVM parameters according to the data width when the data width setting is received. Then, according to the TVM parameters, the GPIO TVM is instantiated and connected at the place where the design code needs to configure data or collect data. The GPIO TVM includes the GPIO_MASTER TVM for implementing interface configuration and the GPIO_SLAVE TVM for implementing interface acquisition; specifically, the GPIOTVM is instantiated and connected at the place where the design code needs to configure data or collect data, and the parameters are passed during the instantiation process according to the TVM parameters set in advance. In this way, the data of the expected data width can be obtained. The GPIO TVM includes the GPIO_MASTER TVM for implementing interface configuration and the GPIO_SLAVE TVM for implementing interface acquisition.

[0085] By setting TVM parameters to instantiate the GPIOTVM connection, data with a fixed data width can be obtained during interface configuration and acquisition, reducing the transmission inconvenience caused by excessively large data and improving the efficiency of interface configuration and acquisition.

[0086] In a specific implementation scheme, the hsCompile project is configured with the Streamtransactor required to connect to TVM. The step of compiling GPIO TVM and design code in the hsCompile project and generating a bitstream file can be specifically performed as follows:

[0087] First, connect GPIO TVM and hsCompile project through Stream transactor. Specifically, Streamtransactor is the interface corresponding to GPIO TVM on hsCompile project, and GPIO TVM can be connected to hsCompile project through Streamtransactor. Then, add the design code to hsCompile project through GPIO TVM. Specifically, GPIO TVM connects hsCompile and design code, and design code and GPIOTVM can be added to hsCompile project. Next, compile GPIOTVM and design code in hsCompile project to generate folder, which includes bitstream file and system configuration file. Specifically, compile GPIO TVM and design code in hsCompile project, follow the hsCompile software process, and the software automatically analyzes, including detecting compilation errors, setting clock grouping, and setting probe signals as needed, and then automatically completes constraints, synthesis, FPGA layout and routing, and generates a folder with suffix db, which contains compiled bitstream file and system configuration file.

[0088] The hsCompile project is configured with the Stream transactor required to connect to TVM. You only need to connect TVM at the code to realize the design code transmission. Transmitting code through TVM improves the transmission efficiency and speeds up the overall simulation process.

[0089] In a specific implementation scheme, the step of generating target simulation code according to the simulation code template, the package function folder and the GPIO TVM can be specifically performed as follows:

[0090] First, select the target package function corresponding to the test stimulus in the package function folder. Specifically, for example, if the test stimulus is to assign a value (set) to the DUT, the Testbench side contains the package function folder GPIO_MASTER_SLAVE.sv. Get the assignment package function from the package folder, and connect the GPIO MASTER SLAVE Transactor at the same time. The assignment package function with the assignment data is transmitted to the hardware side through the GPIOMASTERSLAVE Transactor.

[0091] Next, select the target GPIO TVM corresponding to the test stimulus in the GPIO TVM. Specifically, if the test stimulus is to assign a value (set) to the DUT, select the GPIO_MASTER TVM used to implement the interface configuration, and transmit the assignment data to the DUT side through the GPIO_MASTER TVM.

[0092] Then, the simulation code template is modified according to the target encapsulation function and the target GPIO TVM to obtain the target simulation code. Specifically, the simulation preparation in the testbench is to simulate the actual operation of the test stimulus, that is, the assignment (set) and acquisition (get) operating environment. The simulation code template is modified according to the selected encapsulation function and GPIO TVM to obtain the target simulation code, which is convenient for simulation on the board.

[0093] Select the package function and GPIO TVM corresponding to the test stimulus, modify these two pieces of information in the simulation code template to obtain the target simulation code, so that the testbench simulation can be performed as expected on the FPGA.

[0094] In a specific implementation scheme, the step of obtaining an executable file using the hsRun project according to the target simulation code can be specifically performed as follows:

[0095] First, in the hsRun project, a user template is generated using the system configuration file. The user template includes the underlying template file. Specifically, the gen_tb_templatesvtbsvtb instruction is input in the hsRun project to generate a user template including the underlying template file according to the system configuration file.

[0096] Then, compile the underlying template file and the target simulation code to generate an executable file. Specifically, run the makefile script in the hsRun project, execute make compile, compile the underlying template file and the target simulation code, and generate an executable file.

[0097] Generating an executable file in the hyperSemu system also requires an underlying template file so that the executable file can run in the hyperSemu system.

[0098] In a specific feasible implementation scheme, when executing the executable file on the FPGA to obtain simulation data corresponding to the test stimulus, the following steps may also be performed:

[0099] First, determine whether an instruction to analyze simulation data is received, specifically, determine whether the test stimulus includes a stimulus for obtaining (get) data; if an instruction to analyze simulation data is received, open Testbench and analyze the simulation data of the test stimulus. Specifically, if the test stimulus includes a stimulus for obtaining (get) data, Testbench turns on a switch, which is used to control the interface to obtain GPIO_SLAVE TVM, so that Testbench receives and analyzes the simulation data of the test stimulus. If the test stimulus does not include a stimulus for obtaining (get) data, only an assignment (set) is performed, and Testbench turns off the switch, turns off the GPIO_SLAVE TVM used to implement interface acquisition, speeds up the simulation, and improves debugging efficiency.

[0100] In a specific implementation scheme, the step of analyzing the simulation data of the test stimulus can be specifically performed as follows:

[0101] The simulation data of the test stimulus is transferred to the Testbench through the GPIO TVM and analyzed. Specifically, the simulation data is transferred to the Testbench through the GPIO_SLAVE TVM for user analysis.

[0102] Through the interface GPIO TVM can provide more direct data change monitoring to the TB side, so that scripts can be used for collection comparison, fault analysis and other automated inspections, which improves analysis efficiency and makes analysis results more accurate.

[0103] Based on the above method, the embodiment of the present application also discloses a solution device for interface configuration and acquisition, such as Figure 2 , the device includes the following modules:

[0104] The hsCompile project creation module 201 is used to retrieve the installation data of hsCompile in the hyperSemu system and create the hsCompile project according to the installation data of hsCompile;

[0105] The instantiation and connection GPIO TVM module 202 is used to instantiate and connect the GPIO TVM in the design code when the design code is received;

[0106] The bitstream file generation module 203 is used to compile GPIOTVM and design code in the hsCompile project to generate a bitstream file;

[0107] The simulation code generation module 204 is used to call the simulation code template and the package function folder in the Testbench when receiving the test stimulus, and generate the target simulation code according to the simulation code template, the package function folder and the GPIO TVM;

[0108] The executable file generation module 205 is used to retrieve the installation data of hsRun in the hyperSemu system, create an hsRun project according to the installation data of hsRun, and obtain an executable file using the hsRun project according to the target simulation code;

[0109] The simulation data generation module 206 is used to download the bit stream file to the FPGA and execute the executable file on the FPGA to obtain simulation data corresponding to the test stimulus.

[0110] In one embodiment, the GPIO TVM module 202 is instantiated and connected, specifically for setting TVM parameters according to the data bit width when receiving the setting of the data bit width; instantiating and connecting the GPIOTVM at the place where the design code needs to configure data or collect data according to the TVM parameters, and the GPIOTVM includes the GPIO_MASTER TVM for implementing interface configuration and the GPIO_SLAVE TVM for implementing interface acquisition.

[0111] In one embodiment, the bitstream file generation module 203 is specifically used to connect the GPIO TVM and the hsCompile project through the Streamtransactor; add the design code to the hsCompile project through the GPIOTVM; compile the GPIO TVM and the design code in the hsCompile project to generate a folder, and the folder includes a bitstream file and a system configuration file.

[0112] In one embodiment, the simulation code generation module 204 is specifically used to select a target encapsulation function corresponding to the test stimulus in the encapsulation function folder; select a target GPIO TVM corresponding to the test stimulus in the GPIO TVM; and modify the simulation code template according to the target encapsulation function and the target GPIOTVM to obtain the target simulation code.

[0113] In one embodiment, the executable file generation module 205 is specifically used to generate a user template using a system configuration file in the hsRun project, the user template including an underlying template file; and compile the underlying template file and the target simulation code to generate an executable file.

[0114] The embodiment of the present application also discloses a computer device.

[0115] Specifically, the computer device includes a memory and a processor, and the memory stores a computer program that can be loaded by the processor and execute the above-mentioned interface configuration and acquisition solution.

[0116] The embodiment of the present application also discloses a computer-readable storage medium.

[0117] Specifically, the computer-readable storage medium stores a computer program that can be loaded by a processor and executes a solution such as the above-mentioned interface configuration and acquisition. The computer-readable storage medium includes, for example: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

Claims

1. A solution for interface configuration and acquisition, characterized in that: The method is based on the hyperSemu system and a Testbench including a simulation code template and a package function folder, and the method comprises: Retrieve the installation data of hsCompile in the hyperSemu system, and create an hsCompile project according to the installation data of hsCompile; When receiving the design code, instantiate and connect the GPIO TVM in the design code; Compile the GPIO TVM and the design code in the hsCompile project to generate a bitstream file; When a test stimulus is received, the simulation code template and the package function folder in the Testbench are retrieved, and the target simulation code is generated according to the simulation code template, the package function folder and the GPIO TVM; Retrieve the installation data of hsRun in the hyperSemu system, create an hsRun project according to the installation data of hsRun, and obtain an executable file using the hsRun project according to the target simulation code; The bit stream file is downloaded to the FPGA, and the executable file is executed on the FPGA to obtain simulation data corresponding to the test stimulus.

2. The method according to claim 1, characterized in that: Instantiating and connecting the GPIO TVM in the design code includes: When receiving the setting of data bit width, set TVM parameters according to the data bit width; According to the TVM parameters, a GPIOTVM is instantiated and connected at a location where the design code needs to configure data or collect data, and the GPIOTVM includes a GPIO_MASTER TVM for implementing interface configuration and a GPIO_SLAVETVM for implementing interface acquisition.

3. The method according to claim 1, characterized in that: The hsCompile project is configured with a Stream transactor required for connecting to the TVM. Compiling the GPIO TVM and the design code in the hsCompile project to generate a bitstream file includes: Connect the GPIO TVM and the hsCompile project through the Stream transactor; Add the design code to the hsCompile project through the GPIO TVM; Compile the GPIO TVM and the design code in the hsCompile project to generate a folder, which includes a bitstream file and a system configuration file.

4. The method according to claim 1, characterized in that: Generating the target simulation code according to the simulation code template, the encapsulation function folder and the GPIO TVM comprises: Selecting a target encapsulation function corresponding to the test stimulus in the encapsulation function folder; Selecting a target GPIO TVM corresponding to the test stimulus in the GPIO TVM; The simulation code template is modified according to the target encapsulation function and the target GPIO TVM to obtain the target simulation code.

5. The method according to claim 3, characterized in that: The step of obtaining an executable file by using the hsRun project according to the target simulation code includes: Generating a user template using the system configuration file in the hsRun project, wherein the user template includes an underlying template file; Compile the underlying template file and the target simulation code to generate an executable file.

6. The method according to claim 1, characterized in that: When executing the executable file on the FPGA to obtain simulation data corresponding to the test stimulus, it also includes: Determining whether an instruction to analyze the simulation data is received; If an instruction to analyze the simulation data is received, the Testbench is opened to analyze the simulation data of the test stimulus.

7. The method according to claim 6, characterized in that: The analyzing the simulation data of the test stimulus comprises: The simulation data of the test stimulus is transmitted to the Testbench through the GPIO TVM and analyzed.

8. A device for solving interface configuration and acquisition, characterized in that: The device comprises: The hsCompile project creation module (201) retrieves the installation data of hsCompile in the hyperSemu system and creates the hsCompile project according to the installation data of hsCompile; Instantiating and connecting the GPIO TVM module (202), when receiving the design code, instantiating and connecting the GPIO TVM in the design code; A bitstream file generating module (203) compiles the GPIO TVM and the design code in the hsCompile project to generate a bitstream file; The simulation code generation module (204) retrieves the simulation code template and the package function folder in the Testbench when receiving the test stimulus, and generates the target simulation code according to the simulation code template, the package function folder and the GPIO TVM; An executable file generation module (205) retrieves the installation data of hsRun in the hyperSemu system, creates an hsRun project according to the installation data of hsRun, and obtains an executable file using the hsRun project according to the target simulation code; A simulation data generation module (206) downloads the bit stream file to the FPGA, and executes the executable file on the FPGA to obtain simulation data corresponding to the test stimulus.

9. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program which can be loaded by the processor and executes the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: A computer program is stored which can be loaded by a processor and execute the method according to any one of claims 1 to 7.

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