Semiconductor structure, manufacturing method and testing method

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a semiconductor structure, a manufacturing method and a testing method, and the manufacturing method comprises the steps: providing a substrate which comprises a plurality of chip regions and scribing channel regions located between the adjacent chip regions; a mask layer is formed, the mask layer is located on the surface of the substrate, and the mask layer comprises a target mask area located in the chip area and an offset mask area located in the scribing channel area; wherein the mask layer has a corresponding target position parameter, the target mask region has no offset vector relative to the target position parameter, the offset mask region comprises a plurality of sub offset mask regions, and each sub offset mask region has a preset offset vector relative to the target position parameter; and a pattern transfer step is carried out to transfer the pattern of the mask layer to the substrate so as to form a target pattern in the chip area of the substrate and form an offset pattern in the scribing channel area, and the offset pattern comprises a plurality of sub offset patterns so as to improve the accuracy of the overlay error.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the semiconductor field, and in particular to a semiconductor structure, a manufacturing method, and a testing method. Background Art

[0002] Photolithography is a process that transfers mask patterns to wafers through a series of steps such as alignment and exposure. In the manufacturing process of semiconductor structures, multiple layers of photolithography are required to complete the entire manufacturing process.

[0003] With the development of semiconductor manufacturing technology and the development of integrated circuit design and manufacturing, the photolithography process has developed accordingly, and the characteristic size of semiconductor devices has continued to shrink. In order to achieve good product performance and high yield, how to control the position alignment of the current layer pattern and the previous layer pattern (the pattern on the substrate) to meet the requirements of overlay accuracy is a crucial step in the multi-layer photolithography process, where the overlay error refers to the position alignment error of the photolithography patterns of the substrate layer and layer. In order to improve the overlay error, a system for measuring the position alignment error between the current layer photolithography pattern and the previous layer photolithography pattern is proposed, which is called a photolithography overlay measurement system. Both the current layer photolithography pattern and the previous layer photolithography pattern have overlay marks, and the overlay error is obtained by measuring the position difference between the overlay marks.

[0004] However, the accuracy of the measured overlay error needs to be improved. Summary of the invention

[0005] The embodiments of the present disclosure provide a semiconductor structure, a manufacturing method, and a testing method, which are at least beneficial to improving the accuracy of overlay error measurement.

[0006] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate comprising a plurality of chip areas and a scribing street area located between adjacent chip areas; forming a mask layer, the mask layer being located on a surface of the substrate, the mask layer comprising a target mask area located in the chip area and an offset mask area located in the scribing street area; wherein the mask layer has corresponding target position parameters, the target mask area has no offset vector relative to the target position parameters, the offset mask area comprises a plurality of sub-offset mask areas, each sub-offset mask area has a preset offset vector relative to the target position parameters; performing a graphic transfer step to transfer the graphic of the mask layer to the substrate, so as to form a target pattern in the chip area of ​​the substrate and an offset pattern in the scribing street area, the offset pattern comprising a plurality of sub-offset patterns.

[0007] In some embodiments, in a direction parallel to the substrate surface, a size of each sub-shift mask region is greater than or equal to 5 μm.

[0008] In some embodiments, a distance between adjacent sub-shift mask regions is less than or equal to 200 nm.

[0009] In some embodiments, a preset offset vector of at least one sub-offset mask region relative to the target position parameter is zero.

[0010] In some embodiments, in any direction parallel to the substrate surface, the preset offset vectors of at least two sub-offset mask regions relative to the target position parameter are opposite vectors to each other.

[0011] In some embodiments, a shape of a pattern in the sub-offset mask region is the same as a shape of a pattern in the target mask region, and a size of a pattern in the sub-offset mask region is the same as a size of a pattern in the target mask region.

[0012] In some embodiments, a mask layer is formed on a surface of a substrate, including: forming a first mask layer on the surface of the substrate, the first mask layer including a first graphic area and a second graphic area, the first graphic area being located in a chip area, and the second graphic area being located in a dicing area, wherein a relative position parameter of the first mask layer is a target position parameter, the first graphic area has no offset vector relative to the target position parameter, and the second graphic area includes a plurality of sub-graphic areas, each of which has a first offset vector relative to the target position parameter.

[0013] In some embodiments, after forming the first mask layer, it also includes: forming a second mask layer on the substrate, the second mask layer includes a third graphic area and a fourth graphic area, the third graphic area is located in the chip area, and the fourth graphic area is located in the dicing area, wherein the relative position parameter of the second mask layer is the target position parameter, the third graphic area has no offset vector relative to the target position parameter, and the fourth graphic area includes multiple sub-graphic areas, each sub-graphic area has a second offset vector relative to the target position parameter; wherein the preset offset vector is the sum of the first offset vector and the second offset vector.

[0014] In some embodiments, the substrate includes a reference coordinate system, the reference coordinate system includes an X-axis and a Y-axis that are perpendicular to each other, the preset offset vector includes a first sub-preset offset vector and a second sub-preset offset vector, the first sub-preset offset vector is an offset vector of each sub-offset mask area along the X-axis direction, and the second sub-preset offset vector is an offset vector of each sub-offset mask area along the Y-axis direction.

[0015] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a semiconductor structure, including: a substrate; a target pattern, disposed on the substrate, the target pattern corresponding to a target position parameter; an offset pattern, disposed on the substrate, the offset pattern including a plurality of sub-offset patterns, each sub-offset pattern corresponding to a preset offset vector relative to the target position parameter.

[0016] In some embodiments, the substrate includes a plurality of chip regions and a scribe line region located between adjacent chip regions, the target pattern is located in the chip region, and the offset pattern is located in the scribe line region.

[0017] In some embodiments, in a direction parallel to the substrate surface, a size of each sub-offset pattern is greater than or equal to 5 μm.

[0018] In some embodiments, a distance between adjacent sub-offset patterns is less than or equal to 200 nm.

[0019] In some embodiments, a shape of the sub-offset pattern is the same as a shape of the target pattern, and a size of the sub-offset pattern is the same as a size of the target pattern.

[0020] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for testing a semiconductor structure, including: providing a semiconductor structure as in the above-mentioned embodiments; obtaining an actual offset vector, which is an offset vector of an actually measured sub-offset pattern relative to a target position parameter; establishing an overlay error model, which is represented by a correspondence between a preset offset vector and an actual offset vector; obtaining an actually measured offset vector of a target pattern relative to a target position parameter; and obtaining an actual overlay error of the target pattern based on the actually measured offset vector and the overlay error model.

[0021] In some embodiments, obtaining an actual offset vector includes: obtaining actual offset vectors of multiple test points in each sub-offset pattern; establishing an overlay error model includes: establishing an initial overlay error model, the initial overlay error model being represented by a correspondence between actual offset vectors of some test points and corresponding preset offset vectors; and calibrating the initial overlay error model according to the actual offset vectors of another part of the test points and the corresponding preset offset vectors to obtain the overlay error model.

[0022] In some embodiments, obtaining actual offset vectors of multiple test points in each sub-offset pattern includes: performing tests at different wavelengths and polarizabilities to obtain actual offset vectors corresponding to the test points at different wavelengths and polarizabilities; establishing an initial overlay error model includes: establishing multiple initial overlay error models, each initial overlay error model corresponds to a set of wavelengths and polarizabilities, and if the initial overlay error model meets a preset condition, calibrating the initial overlay error model, otherwise excluding the initial overlay error model.

[0023] In some embodiments, the initial overlay error model is a linear relationship, and the preset conditions include: the slope of the linear relationship is 0.85-1.25, the intercept is -0.1-0.1, and the fit is 0.70-1.

[0024] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0025] In the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, in the process of forming a mask layer, the same process step is adopted to simultaneously form a target mask area in the chip area and an offset mask area in the scribing area. The target mask area can be used to form a semiconductor structure corresponding to the chip area, and the offset mask area can be used to form a test pattern located in the scribing area. The same process step is adopted to form the target mask area and the offset mask area, so the overlay error generated by the offset mask area is more consistent with the actual overlay error of the target mask area. The target position parameter can be understood as the position parameter when the relative position of the mask layer and the substrate is in an aligned state. In this way, the target mask area has no offset vector relative to the target position parameter. When the substrate is etched with the mask layer, it is more conducive to the accurate transfer of the pattern in the target mask area to the substrate, so as to improve the manufacturing accuracy of the semiconductor structure. The offset mask area includes a plurality of sub-offset mask areas, and each sub-offset mask area has a preset offset vector relative to the target position parameter, that is, when designing the sub-offset mask area, a known preset offset vector is provided for each sub-offset mask area. Under ideal conditions, when the substrate is etched using the sub-offset mask area as a mask, the sub-offset pattern formed on the substrate should have the same preset offset vector. However, during the actual pattern transfer process, the actual offset vector generated after the sub-offset pattern 220 is actually formed may deviate from the preset offset vector. An overlay error model can be established based on the corresponding relationship between the known preset offset vector and the actual offset vector. For the target pattern 110, the measured offset vector of the target pattern 110 should conform to the overlay error model. In this way, combined with the test result of the target pattern 110, the actual overlay error of the target pattern 110 can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figures 1 to 5 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure;

[0028] Figure 6 A flowchart corresponding to a method for testing a semiconductor structure provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] The detection of overlay error is generally divided into post-development detection (ADI, After Development Inspection) and post-etching detection (AEI, After Etching Inspection).

[0030] Post-development inspection refers to the measurement of CD (critical dimension) after development. It is generally used to detect the performance indicators of the exposure machine and the developer. After the exposure and development are completed, the ADI machine is used to qualitatively check the generated graphics to see if they are normal. Since it cannot be measured by transmitted light, ADI is generally measured by electron beam or scanning electron microscope. Post-etching inspection refers to the CD measurement after etching. Before and after the photoresist is removed in the etching process, the product is fully inspected or sampled.

[0031] Overlay error can generally be measured through image recognition-based measurement technology (IBO, Image Based Overlay), scanning electron microscope (SEM, scanning electron microscope) and new diffraction measurement technology (IDM, In Device Metrology, also known as In Die Measurement).

[0032] The disclosed embodiments provide a method for manufacturing a semiconductor structure, which is at least beneficial for improving the accuracy of overlay error measurement.

[0033] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0034] Figures 1 to 5 The schematic diagram of the structure corresponding to each step of the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, wherein: Figure 3 for Figure 2 Schematic diagram of the local enlarged structure of the offset mask area. Figure 5 for Figure 4 A locally enlarged structural schematic diagram of the offset pattern in the middle is shown. The manufacturing method of the semiconductor structure provided by this embodiment will be described in detail below in conjunction with the accompanying drawings.

[0035] The method for manufacturing a semiconductor structure comprises:

[0036] refer to Figure 1 , a substrate is provided, wherein the substrate 100 includes a plurality of chip regions 101 and a dicing street region 102 located between adjacent chip regions 101 .

[0037] The substrate 100 may be a semiconductor substrate, wherein the semiconductor substrate includes a silicon substrate, a silicon germanium substrate, a gallium arsenide substrate, a silicon carbide substrate, a gallium nitride substrate, or the like.

[0038] In some embodiments, the substrate 100 may also be a silicon-on-insulator structure, a silicon-germanium-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

[0039] In some embodiments, the base may include a substrate and a target layer, and the target layer may be used to form a transistor structure, a word line, a bit line, a capacitor structure, or an insulating structure.

[0040] The material of the substrate may include semiconductor materials such as silicon, gallium arsenide, silicon carbide or gallium nitride. The material of the target layer may be selected according to the semiconductor structure to be formed. For example, the target layer may include silicon oxide, silicon nitride, silicon oxynitride or silicon carbonitride, etc., which are used to form an insulating structure in the semiconductor structure to avoid leakage problems between adjacent transistor structures, adjacent word lines or adjacent bit lines; or, the target layer may also include at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium or tungsten, which are used to form word lines; or, the material of the target layer may also include at least one of metal silicide, titanium nitride or tungsten, which are used to form bit lines.

[0041] The chip area 101 is the area occupied by the semiconductor device, and the scribe area 102 is the area used to cut the wafer into semiconductor devices one by one after the semiconductor device processing is completed. Usually, a test pattern for monitoring the production process is set in the scribe area 102 to facilitate monitoring the process of the semiconductor structure.

[0042] Combined with reference Figure 2 and Figure 3 , forming a mask layer 200, the mask layer 200 is located on the surface of the substrate 100, the mask layer 200 includes a target mask area 201 located in the chip area 101 and an offset mask area 202 located in the dicing street area 102; wherein, the mask layer 200 has corresponding target position parameters, the target mask area 201 has no offset vector relative to the target position parameters, and the offset mask area 202 includes a plurality of sub-offset mask areas 212, each of which has a preset offset vector relative to the target position parameters.

[0043] Combined with reference Figure 4 and Figure 5, a pattern transfer step is performed to transfer the pattern of the mask layer 200 to the substrate 100, so as to form a target pattern 110 in the chip area 101 of the substrate 100, and to form an offset pattern 120 in the scribe line area 102, wherein the offset pattern 120 includes a plurality of sub-offset patterns 220. The pattern of the target pattern 110 corresponds to the pattern of the target mask area 201, the pattern of the offset pattern 120 corresponds to the pattern of the offset mask area 202, and the pattern of the sub-offset pattern 220 corresponds to the pattern of the sub-offset mask area 212.

[0044] In the process of forming the mask layer 200, the target mask area 201 is formed in the chip area 101 and the offset mask area 202 is formed in the scribing street area 102 by the same process step. The target mask area 201 can be used to form the semiconductor structure corresponding to the chip area 101, and the offset mask area 202 can be used to form the test pattern located in the scribing street area 102. The target mask area 201 and the offset mask area 202 are formed by the same process step, and the overlay error generated by the offset mask area 202 is more consistent with the actual overlay error of the target mask area 201. The target mask area 201 needs to have an ideal alignment state relative to the substrate 100, that is, the target position parameter can be understood as the position parameter that the corresponding mask layer 200 should have when the relative position of the target mask area 201 and the substrate 100 is in the alignment state. In this way, when the substrate 100 is etched by the mask layer 200, the pattern in the target mask area 201 can be accurately transferred to the substrate 100, so as to improve the manufacturing accuracy of the semiconductor structure. The offset mask area 202 includes a plurality of sub-offset mask areas 212, and each sub-offset mask area 212 has a preset offset vector relative to the target position parameter, that is, when designing the sub-offset mask area 212, a known preset offset vector is provided for each sub-offset mask area 212. Under ideal conditions, when the substrate 100 is etched using the sub-offset mask area 212 as a mask, the sub-offset pattern 220 formed on the substrate 100 should have the same preset offset vector. However, in the actual pattern transfer process, the actual offset vector generated after the sub-offset pattern 220 is actually formed may deviate from the preset offset vector. An overlay error model can be established based on the corresponding relationship between the known preset offset vector and the actual offset vector. For the target pattern 110, the measured offset vector of the target pattern 110 should conform to the overlay error model. In this way, combined with the test result of the target pattern 110, the actual overlay error of the target pattern 110 can be obtained.

[0045] Among them, the preset offset can be determined according to the process of the semiconductor structure formed corresponding to the target mask area 201 and the allowable overlay error range. For example, for a 20nm process, the overlay error must be controlled below 8nm. Then, in the direction parallel to the surface of the substrate 100, the corresponding preset offset vector can be in the range of -8nm to 8nm. For example, the offset value of the preset offset vector can be -8nm, -6nm, -4nm, -2nm, 0nm, 2nm, 4nm, 6nm or 8nm, etc.

[0046] In some embodiments, reference Figure 2 , the boundary of the target mask area 201 can extend to the scribe line area 102. In this way, when the substrate 100 is subsequently etched based on the mask layer 200, the height difference between the boundary of the target mask area 201 and the blank area outside the target mask area 201 due to the difference in pattern density can be avoided, thereby avoiding the problem of defects in the pattern etched on the substrate 100.

[0047] It is understandable that if Figure 2 As shown, the number and arrangement of the chip regions 101 of the substrate 100 are only examples and do not constitute a limitation on the number and arrangement of the chip regions 101. The number and arrangement of the chip regions 101 can be designed according to actual needs. Similarly, the number and position of the offset mask regions 202 in the scribe line region 102 can be designed according to actual needs.

[0048] In some embodiments, the material of the mask layer 200 may be photoresist or a hard mask material, wherein the hard mask material may include a hard mask material with relatively high hardness, such as silicon nitride, carbon material, or polysilicon.

[0049] In some embodiments, reference Figure 2 , a reference coordinate system may be established on the substrate 100, the reference coordinate system including an X-axis and a Y-axis perpendicular to each other, the preset offset vector may include a first sub-preset offset vector and a second sub-preset offset vector, the first sub-preset offset vector is an offset vector of each sub-offset mask area 212 along the X-axis direction, and the second sub-preset offset vector is an offset vector of each sub-offset mask area 212 along the Y-axis direction. In this way, in the reference coordinate system, the offset vector along any direction may be represented by the coordinates formed by the X-axis and the Y-axis.

[0050] exist Figure 2 In the example, the origin where the X-axis and the Y-axis intersect is inside the base 100. In some embodiments, the origin of the reference coordinate system may be outside the base, that is, relative to the reference coordinate system, any point on the base may be represented by the coordinates corresponding to the reference coordinate system.

[0051] In some embodiments, the X-axis and the Y-axis may not be perpendicular or parallel, for example, the angle between the X-axis and the Y-axis may be 30°, 45°, or 60°. It is understood that when the X-axis and the Y-axis intersect, in the reference coordinate system, the offset vector along any direction can still be represented by the coordinates formed by the X-axis and the Y-axis.

[0052] In some embodiments, in a direction parallel to the surface of substrate 100 , a size of each sub-offset mask region 212 is greater than or equal to 5 μm, for example 5 μm, 4.5 μm, 4 μm, 3.5 μm, 3 μm, 2.5 μm, 2 μm, 1.5 μm, 1 μm or 500 nm. For each sub-offset mask area 212, the size of the sub-offset mask area 212 needs to be greater than 5 μm, so as to facilitate the measurement of the sub-offset mask area 212; the size of the sub-offset mask area 212 can be adjusted according to the semiconductor structure to be formed, but the larger the size of the sub-offset mask area 212, the easier it is for the error between the offset vector of the corresponding sub-offset mask area 212 actually formed and the preset offset vector to occur, resulting in the inability of the preset offset vector to be accurately implemented on the sub-offset mask area 212 actually formed, and then after etching the substrate 100 based on the sub-offset mask area 212, the error between the actual offset vector of the sub-offset pattern formed on the substrate 100 and the preset offset vector is larger, resulting in an inaccurate overlay error model corresponding to the actual offset vector and the preset offset vector, and then the accuracy of the actual overlay error of the obtained target pattern 110 is reduced. Therefore, the size of the sub-offset mask area 212 needs to be selected within an appropriate range in combination with the actual structure to be formed, so that the designed preset offset vector can be accurately implemented on the sub-offset mask area 212 actually formed.

[0053] In some embodiments, the distance between adjacent sub-offset mask areas 212 is less than or equal to 200nm, for example, 200nm, 180nm, 160nm, 140nm, 120nm, 100nm, 80nm, 60nm, 40nm, 20nm or 0nm. It can be understood that the larger the distance between adjacent sub-offset mask areas 212, the larger the area occupied by the corresponding offset mask area 202. The offset mask area 202 located in the scribe line area 102 is used to test and monitor the structure of the chip area 101. The scribe line area 102 is not used to form products. The larger the area of ​​the scribe line area 102, the smaller the area of ​​the corresponding chip area 101, and the effective area decreases, and the corresponding chip manufacturing cost increases. Therefore, the distance between adjacent sub-offset mask areas 212 needs to be less than or equal to 200nm to reduce the chip manufacturing cost.

[0054] It can be understood that the more sub-offset mask areas 212 are set, the more different preset offset vectors can be set for different sub-offset mask areas 212 within the acceptable range of overlay error, so as to fully cover multiple different values ​​within the allowed range of overlay error. In the case where multiple sub-offset mask areas 212 have different preset offset vectors, there are multiple data of offset vectors actually generated corresponding to the multiple sub-offset patterns 220 transferred to the substrate 100. The overlay error model obtained based on more complete data has higher accuracy, and thus the actual overlay error of the target pattern 110 obtained based on the overlay error model is more accurate. In addition, when designing the offset mask area and the sub-offset mask areas in the offset mask area, the number of sub-offset mask areas also needs to be set in combination with the size of the sub-offset mask area and the distance between adjacent sub-offset mask areas.

[0055] In some embodiments, the preset offset vector of at least one sub-offset mask area 212 relative to the target position parameter is 0. In this way, when the sub-offset mask area 212 is aligned with the substrate 100, the offset vector actually generated by the sub-offset pattern 220 formed after etching the substrate 100 based on the sub-offset mask area 212 can be obtained, and a more accurate overlay error model can be obtained based on the preset offset vector and the actually generated offset vector, which is conducive to improving the accuracy of obtaining the actual overlay error of the target pattern 110.

[0056] In some embodiments, in any direction parallel to the surface of the substrate 100, at least two sub-offset mask areas 212 have preset offset vectors relative to the target position parameter that are opposite to each other. It is understandable that when the preset offset vectors of the two sub-offset mask areas 212 are opposite to each other, under ideal conditions, the offset vectors actually generated by the two sub-offset patterns 220 formed after etching the substrate 100 based on the two sub-offset mask areas 212 should also be opposite to each other. A more accurate overlay error model can be obtained based on the preset offset vectors and the actually generated offset vectors, thereby facilitating the improvement of the accuracy of obtaining the actual overlay error of the target pattern 110.

[0057] In some embodiments, the shape of the pattern of the sub-offset mask area 212 is the same as the shape of the pattern of the target mask area 201, and the size of the pattern of the sub-offset mask area 212 is the same as the size of the pattern of the target mask area 201. In other words, the sub-offset mask area 212 replicates the pattern of the target mask area 201, so that the formation process of the sub-offset mask area 212 can be more consistent with the process of actually forming the target mask area 201, and the corresponding scene when etching the substrate 100 based on the sub-offset mask area 212 is also closer to the scene when etching the substrate 100 based on the target mask area 201, so as to eliminate the error caused by the different shapes or sizes of the target mask area 201 and the sub-offset mask area 212, and improve the accuracy of the overlay error model.

[0058] In some embodiments, a mask layer is formed on a surface of a substrate, including: forming a first mask layer on the surface of the substrate, the first mask layer including a first graphic area and a second graphic area, the first graphic area being located in a chip area, and the second graphic area being located in a dicing area, wherein a relative position parameter of the first mask layer is a target position parameter, the first graphic area has no offset vector relative to the target position parameter, and the second graphic area includes a plurality of sub-graphic areas, each of which has a first offset vector relative to the target position parameter.

[0059] In some embodiments, the first mask layer can be directly used as the mask layer to perform subsequent pattern transfer steps, and the first pattern area is the target mask area, the second pattern area is the offset mask area, the sub-pattern area is the sub-offset mask area, and the first offset vector is the preset offset vector. In other words, the mask layer can be composed of a single mask layer.

[0060] In some embodiments, the mask layer may also be composed of multiple mask layers. For example, after forming the first mask layer, the process further includes: forming a second mask layer on the substrate, the second mask layer including a third graphic area and a fourth graphic area, the third graphic area being located in the chip area, and the fourth graphic area being located in the dicing road area, wherein the relative position parameter of the second mask layer is the target position parameter, the third graphic area has no offset vector relative to the target position parameter, and the fourth graphic area includes a plurality of sub-graphic areas, each sub-graphic area having a second offset vector relative to the target position parameter.

[0061] Among them, the pattern jointly formed by the first graphic area and the third graphic area corresponds to the target pattern, the pattern jointly formed by the second graphic area and the fourth graphic area corresponds to the offset pattern, the pattern jointly formed by the sub-graphic area and the sub-graphic area corresponds to the sub-offset pattern, and the preset offset vector is the sum of the first offset vector and the second offset vector.

[0062] In some embodiments, the second mask layer may be located on the surface of the substrate, that is, the first mask layer and the second mask layer are arranged in the same layer, and the first mask layer and the second mask layer are used together as mask layers for subsequent pattern transfer steps. In some embodiments, the second mask layer may be located on the first mask layer, and the pattern of the second mask layer is first transferred to the first mask layer, and then the remaining first mask layer is used as a mask layer for subsequent pattern transfer steps.

[0063] That is to say, the pattern on the substrate can be obtained through multiple patterning, wherein, during the multiple patterning process, the sub-pattern area and sub-pattern area corresponding to the sub-offset mask area in each mask layer can have their own corresponding offset vectors, and finally the part corresponding to the sub-offset mask area formed after multiple patterning is the sum of the offset vectors corresponding to each mask layer.

[0064] In some embodiments, the first offset vector and the second offset vector may be the same or different.

[0065] In some embodiments, at least one first offset vector is 0 relative to a preset offset vector of the target position parameter, and / or at least one second offset vector is 0 relative to a preset offset vector of the target position parameter.

[0066] In some embodiments, in any direction parallel to the substrate surface, at least two first offset vectors are opposite vectors to each other, and / or at least two second offset vectors are opposite vectors to each other.

[0067] In some embodiments, if the substrate includes a reference coordinate system, the first offset vector and the second offset vector may each include an offset vector along the X-axis direction and an offset vector along the Y-axis direction.

[0068] In the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure, during the process of forming the mask layer 200, the target mask area 201 is formed in the chip area 101 and the offset mask area 202 is formed in the scribing street area 102 by the same process step. The target mask area 201 can be used to form a semiconductor structure corresponding to the chip area 101, and the offset mask area 202 can be used to form a test pattern located in the scribing street area 102. The target mask area 201 and the offset mask area 202 are formed by the same process step, so that the overlay error generated by the offset mask area 202 is more consistent with the actual overlay error of the target mask area 201. The target position parameter can be understood as the position parameter that the corresponding mask layer 200 should have when the relative position of the target mask area 201 and the substrate 100 is in an aligned state. In this way, when the substrate 100 is etched with the mask layer 200, the pattern in the target mask area 201 can be accurately transferred to the substrate 100, so as to improve the manufacturing accuracy of the semiconductor structure. The offset mask area 202 includes a plurality of sub-offset mask areas 212, and each sub-offset mask area 212 has a preset offset vector relative to the target position parameter, that is, when designing the sub-offset mask area 212, a known preset offset vector is provided for each sub-offset mask area 212. Under ideal conditions, when the substrate 100 is etched using the sub-offset mask area 212 as a mask, the sub-offset pattern 220 formed on the substrate 100 should have the same preset offset vector. However, in the actual pattern transfer process, the actual offset vector generated after the sub-offset pattern 220 is actually formed may deviate from the preset offset vector. An overlay error model can be established based on the corresponding relationship between the known preset offset vector and the actual offset vector. For the target pattern 110, the measured offset vector of the target pattern 110 should conform to the overlay error model. In this way, combined with the test result of the target pattern 110, the actual overlay error of the target pattern 110 can be obtained.

[0069] Another embodiment of the present disclosure provides a semiconductor structure that can be formed by the manufacturing method of the semiconductor structure to improve the accuracy of the overlay error. It should be noted that the parts that are the same or corresponding to the above embodiment can refer to the corresponding description of the above embodiment, and will not be described in detail below.

[0070] The semiconductor structure provided by this embodiment will be described in detail below with reference to the accompanying drawings.

[0071] Return to reference Figure 4 and Figure 5 , the semiconductor structure includes:

[0072] A substrate 100; a target pattern 110 disposed on the substrate 100, the target pattern 110 corresponding to a target position parameter; an offset pattern 120 disposed on the substrate 100, the offset pattern 120 including a plurality of sub-offset patterns 220, each sub-offset pattern 220 corresponding to a preset offset vector relative to the target position parameter.

[0073] Among them, the target position parameter corresponding to the target pattern 110 is not the actual position parameter of the target pattern 110. The target position parameter can be understood as the position parameter that the corresponding mask layer should have when the target pattern 110 is aligned with the substrate 100. The target pattern 110 should be aligned with the substrate 100, but the target pattern 110 actually formed may be offset relative to the substrate 100. In addition, the preset offset vector corresponding to the sub-offset pattern 220 is also not the actual offset vector of the sub-offset pattern 220. The preset offset vector can be understood as the offset vector of the corresponding sub-offset mask area relative to the target position parameter when the sub-offset pattern 220 is formed. However, the actual offset vector of the sub-offset pattern 220 actually formed may deviate from the preset offset vector. Through the correspondence between the actual offset vector obtained by the actual test of the sub-offset pattern 220 and the corresponding preset offset vector, an overlay error model can be obtained, and then the actual overlay error of the target pattern can be obtained according to the overlay error model and the measured offset vector of the target pattern 110, so that the accuracy of the actual overlay error of the target pattern 110 can be improved.

[0074] In some embodiments, the substrate 100 includes a plurality of chip regions 101 and a scribe line region 102 located between adjacent chip regions 101, the target pattern 110 is located in the chip region 101, and the offset pattern 120 is located in the scribe line region 102. The target pattern 110 can be used to form a semiconductor structure, and the offset pattern 120 can be used to monitor and test the process of the semiconductor structure.

[0075] In some embodiments, in a direction parallel to the surface of substrate 100, the size of each sub-offset pattern 120 is greater than or equal to 5 μm, for example, 5 μm, 4.5 μm, 4 μm, 3.5 μm, 3 μm, 2.5 μm, 2 μm, 1.5 μm, 1 μm or 500 nm. It is understood that sub-offset pattern 120 needs to have a sufficiently large size to meet test requirements, and the size of sub-offset pattern 120 needs to be designed in combination with the formed semiconductor structure.

[0076] In some embodiments, the distance between adjacent sub-offset patterns 120 is less than or equal to 200 nm, for example, 200 nm, 180 nm, 160 nm, 140 nm, 120 nm, 100 nm, 80 nm, 60 nm, 40 nm, 20 nm or 0 nm. It can be understood that the sub-offset pattern 120 is used to monitor the process of the semiconductor structure, not to form a product. The larger the size of the sub-offset pattern 120, the larger the area occupied, the smaller the area of ​​the target pattern 110, the lower the effective area, and the higher the manufacturing cost of the chip. Therefore, the distance between adjacent sub-offset patterns 120 should be less than or equal to 200 nm.

[0077] In some embodiments, the shape of the sub-offset pattern 120 is the same as the shape of the target pattern 110, and the size of the sub-offset pattern 120 is the same as the size of the target pattern 110. In other words, the pattern of the sub-offset pattern 120 replicates the pattern of the target pattern 110, so that the formation conditions of the sub-offset pattern 120 and the target pattern 110 are the same, thereby avoiding errors caused by different patterns between the sub-offset pattern 120 and the target pattern 110.

[0078] Another embodiment of the present disclosure provides a method for testing a semiconductor structure, which can be used to test the semiconductor structure to improve the accuracy of the overlay error. It should be noted that the parts that are the same or corresponding to the above embodiment can refer to the corresponding description of the above embodiment, and will not be described in detail below.

[0079] The semiconductor structure testing method provided by this embodiment will be described in detail below with reference to the accompanying drawings.

[0080] Figure 6 A flowchart corresponding to a method for testing a semiconductor structure provided in one embodiment of the present disclosure.

[0081] refer to Figure 6 , test methods for semiconductor structures, including:

[0082] Step S11: Reference Figure 4 and Figure 5, providing a semiconductor structure, the semiconductor structure comprising a substrate 100; a target pattern 110, disposed on the substrate 100, the target pattern 110 corresponding to a target position parameter; an offset pattern 120, disposed on the substrate 100, the offset pattern 120 comprising a plurality of sub-offset patterns 220, each sub-offset pattern 220 corresponding to a preset offset vector relative to the target position parameter;

[0083] Step S12: obtaining an actual offset vector, where the actual offset vector is an offset vector of the sub-offset pattern actually measured relative to the target position parameter.

[0084] Step S13: establishing an overlay error model, where the error model is represented by a corresponding relationship between a preset offset vector and an actual offset vector.

[0085] In some embodiments, obtaining an actual offset vector includes: obtaining actual offset vectors of multiple test points in each sub-offset pattern; establishing an overlay error model includes: establishing an initial overlay error model, the initial overlay error model being represented by a correspondence between actual offset vectors of some test points and corresponding preset offset vectors; and calibrating the initial overlay error model according to the actual offset vectors of another part of the test points and the corresponding preset offset vectors to obtain the overlay error model.

[0086] That is to say, multiple test points are selected in each sub-offset pattern. In the same sub-offset pattern, multiple test points have the same corresponding preset offset vector, but the actual offset vector obtained by actually measuring the test point may not be equal to the preset offset vector. In this way, multiple test points correspond to multiple groups of data of actual offset vectors and preset offset vectors. A part of the multiple groups of data is used as basic data for algorithm simulation to obtain the corresponding initial overlay error model of the actual offset vector and the preset offset vector through training, and then the initial overlay error model is verified or calibrated with another part of the data, so as to improve the accuracy of the initial overlay error model and obtain a more accurate overlay error model.

[0087] In some embodiments, 80% of the data of multiple groups of actual offset vectors and preset offset vectors may be selected as basic data for obtaining an initial overlay error model, and the remaining 20% ​​of the data may be used as verification and calibration data.

[0088] In some embodiments, obtaining actual offset vectors of multiple test points in each sub-offset pattern includes: performing tests at different wavelengths and polarizabilities to obtain actual offset vectors corresponding to the test points at different wavelengths and polarizabilities; establishing an initial overlay error model includes: establishing multiple initial overlay error models, each initial overlay error model corresponds to a set of wavelengths and polarizabilities, and if the initial overlay error model meets a preset condition, calibrating the initial overlay error model, otherwise excluding the initial overlay error model.

[0089] In some embodiments, the light diffraction method can be used to test the test points in each sub-offset pattern to obtain the actual offset vector. For different material layers and different structures, the wavelengths and polarization rates required for testing by the light diffraction method may be different. In order to obtain more accurate test results under the best test conditions, tests can be performed at different wavelengths and polarization rates to obtain multiple groups of initial overlay error models, and then the multiple groups of initial overlay error models are screened.

[0090] In some embodiments, there may be multiple overlay error models finally screened out. It can be understood that multiple overlay error models can be simulated respectively for the offset patterns 120 at different positions on the substrate 100, and then the overlay error model that can adapt to the entire wafer is selected from the multiple overlay error models to obtain a more accurate overlay error model that can correspond to the entire wafer.

[0091] In some embodiments, the offset patterns corresponding to different overlay error models may be evenly dispersed on the wafer, so that multiple overlay error models may be more comprehensively integrated to obtain an overlay error model applicable to the entire wafer.

[0092] In some embodiments, the initial overlay error model can be a linear relationship. For example, a preset offset vector is used as the horizontal axis, and the actual offset vector is used as the vertical axis. The data of multiple test points are used to establish discrete points, and the discrete points are then fitted to obtain a linear relationship. Theoretically, the actual offset vector should be equal to the preset offset vector. Therefore, the slope of the corresponding linear relationship should be 1, the intercept should be 0, and the degree of fit should be equal to 1. However, due to the existence of errors, the fitted linear relationship may have appropriate errors. For example, the preset conditions may include: the slope of the linear relationship is 0.85 to 1.25, for example, 0.85, 0.88, 0.90, 0.93, 0.96, 0.99, 1.10 or 1.25; the intercept is -0.1 to 0.1, for example, -0.1, -0.05, 0, 0.05 or 1; the degree of fit is 0.70 to 1, for example, 0.70, 0.73, 0.76, 0.81, 0.84, 0.87, 0.92, 0.95, 0.98 or 1.

[0093] Step S14: obtaining a measured offset vector of the target pattern relative to the target position parameter;

[0094] Step S15: Obtaining the actual overlay error of the target pattern according to the measured offset vector and the overlay error model.

[0095] The testing method of the semiconductor structure provided by the embodiment of the present disclosure tests the sub-offset pattern 220 to obtain the actual offset vector of the sub-offset pattern 220. Since the sub-offset pattern 220 corresponds to a preset offset vector, an overlay error model representing the corresponding relationship between the preset offset vector and the actual offset vector is established to obtain a more accurate overlay error algorithm. When the target pattern 110 is measured again, the actually measured offset vector of the target pattern 110 can be brought into the overlay error model for calculation, so that a more accurate overlay error of the target pattern 110 can be obtained.

[0096] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a plurality of chip regions and a scribe line region located between adjacent chip regions; Forming a mask layer, the mask layer being located on the surface of the substrate, the mask layer comprising a target mask region located in the chip region and an offset mask region located in the scribe line region; wherein the mask layer has a corresponding target position parameter, the target mask region has no offset vector relative to the target position parameter, the offset mask region comprises a plurality of sub-offset mask regions, each of the sub-offset mask regions having a preset offset vector relative to the target position parameter; A pattern transfer step is performed to transfer the pattern of the mask layer to the substrate to form a target pattern in the chip region of the substrate and an offset pattern in the scribe line region, wherein the offset pattern includes a plurality of sub-offset patterns.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: In a direction parallel to the substrate surface, a size of each of the sub-shift mask regions is greater than or equal to 5 μm.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The distance between adjacent sub-offset mask regions is less than or equal to 200 nm.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The preset offset vector of at least one of the sub-offset mask regions relative to the target position parameter is 0.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein: In any direction parallel to the substrate surface, the preset offset vectors of at least two of the sub-offset mask regions relative to the target position parameter are opposite vectors to each other.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The graphic shape of the sub-offset mask area is the same as the graphic shape of the target mask area, and the graphic size of the sub-offset mask area is the same as the graphic size of the target mask area.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Forming the mask layer located on the surface of the substrate comprises: A first mask layer is formed on the surface of the substrate, the first mask layer includes a first graphic area and a second graphic area, the first graphic area is located in the chip area, and the second graphic area is located in the dicing area, wherein the relative position parameter of the first mask layer is the target position parameter, the first graphic area has no offset vector relative to the target position parameter, and the second graphic area includes a plurality of sub-graphic areas, each of the sub-graphic areas has a first offset vector relative to the target position parameter.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: After forming the first mask layer, the method further includes: A second mask layer is formed on the substrate, wherein the second mask layer comprises a third graphic area and a fourth graphic area, wherein the third graphic area is located in the chip area, and the fourth graphic area is located in the scribe line area, wherein the relative position parameter of the second mask layer is the target position parameter, the third graphic area has no offset vector relative to the target position parameter, and the fourth graphic area comprises a plurality of sub-graphic areas, and each of the sub-graphic areas has a second offset vector relative to the target position parameter; The preset offset vector is the sum of the first offset vector and the second offset vector.

9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The substrate includes a reference coordinate system, the reference coordinate system includes an X-axis and a Y-axis that are perpendicular to each other, the preset offset vector includes a first sub-preset offset vector and a second sub-preset offset vector, the first sub-preset offset vector is an offset vector of each sub-offset mask area along the X-axis direction, and the second sub-preset offset vector is an offset vector of each sub-offset mask area along the Y-axis direction.

10. A semiconductor structure, characterized in that: include: substrate; A target pattern is disposed on the substrate, and the target pattern corresponds to a target position parameter; The offset pattern is disposed on the substrate, and the offset pattern includes a plurality of sub-offset patterns, each of which corresponds to a preset offset vector relative to the target position parameter.

11. The semiconductor structure according to claim 10, characterized in that: The substrate includes a plurality of chip regions and a scribing street region located between adjacent chip regions. The target pattern is located in the chip region, and the offset pattern is located in the scribing street region.

12. The semiconductor structure according to claim 10, characterized in that In a direction parallel to the surface of the substrate, a size of each of the sub-offset patterns is greater than or equal to 5 μm.

13. The semiconductor structure according to claim 10, characterized in that: The distance between adjacent sub-offset patterns is less than or equal to 200 nm.

14. The semiconductor structure according to claim 10, characterized in that The graphic shape of the sub-offset pattern is the same as the graphic shape of the target pattern, and the graphic size of the sub-offset pattern is the same as the graphic size of the target pattern.

15. A method for testing a semiconductor structure, characterized in that: include: Providing a semiconductor structure as claimed in any one of claims 10 to 14; Acquire an actual offset vector, where the actual offset vector is an actually measured offset vector of the sub-offset pattern relative to the target position parameter; Establishing an overlay error model, wherein the error model is represented by a corresponding relationship between the preset offset vector and the actual offset vector; Obtaining a measured offset vector of the target pattern relative to the target position parameter; An actual overlay error of the target pattern is obtained according to the measured offset vector and the overlay error model.

16. The method for testing a semiconductor structure according to claim 15, characterized in that: Get the actual offset vector, including: Acquire the actual offset vectors of a plurality of test points in each of the sub-offset patterns; Establishing the overlay error model includes: Establishing an initial overlay error model, wherein the initial overlay error model is represented by a corresponding relationship between the actual offset vectors of some of the test points and the corresponding preset offset vectors; The initial overlay error model is calibrated according to the actual offset vectors of another part of the test points and the corresponding preset offset vectors to obtain the overlay error model.

17. The method for testing a semiconductor structure according to claim 16, characterized in that: Acquiring the actual offset vectors of a plurality of test points in each of the sub-offset patterns comprises: Performing tests at different wavelengths and polarizabilities to obtain the actual offset vector corresponding to the test point at different wavelengths and polarizabilities; Establishing an initial overlay error model includes: establishing multiple initial overlay error models, each of which corresponds to a set of wavelengths and polarizabilities. If the initial overlay error model meets a preset condition, the initial overlay error model is calibrated, otherwise the initial overlay error model is excluded.

18. The method for testing a semiconductor structure according to claim 17, characterized in that: The initial overlay error model is a linear relationship, and the preset conditions include: the slope of the linear relationship is 0.85 to 1.25, the intercept is -0.1 to 0.1, and the fitting degree is 0.70 to 1.

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