Semiconductor chip and semiconductor package having same

Abstract

A semiconductor chip includes a substrate, a device layer and an interconnect layer on the substrate in this order, and a bond pad on the interconnect layer. A bottom surface of the bond pad may be located at a constant level, and a side surface of the bond pad may have a roughened shape.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and in particular, to a semiconductor chip and a method of manufacturing a semiconductor package including the semiconductor chip. Background Art

[0002] Semiconductor devices are considered important elements in the electronics industry due to their small size, multifunctionality and / or low cost characteristics. Semiconductor devices are classified into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices including both memory elements and logic elements.

[0003] Due to the recent growing demand for electronic devices with fast speed and / or low power consumption, semiconductor memory devices require fast operating speed and / or low operating voltage. In order to meet this requirement, it is desirable to improve the integration density of semiconductor memory devices. Therefore, many studies are being conducted to realize highly integrated semiconductor memory devices. Summary of the invention

[0004] Some example embodiments of the inventive concepts provide a semiconductor chip having improved reliability and a semiconductor package including the semiconductor chip.

[0005] According to some example embodiments of the present inventive concept, a semiconductor chip may include a substrate, a device layer and an interconnect layer sequentially on the substrate, and a bonding pad on the interconnect layer. The bottom surface of the bonding pad may be located at a constant level, and the side surface of the bonding pad may have a roughened shape.

[0006] According to some example embodiments of the present inventive concept, a semiconductor chip may include a substrate, a device layer and an interconnect layer sequentially on the substrate, a bonding pad on the interconnect layer, and a first insulating layer, a barrier layer, and a second insulating layer sequentially on the interconnect layer. The barrier layer may be located at a lower level than the bonding pad, and the barrier layer may include Al 2 O 3 .

[0007] According to some example embodiments of the present inventive concept, a semiconductor package may include a semiconductor chip. The semiconductor chip may include a substrate, a device layer and an interconnect layer sequentially on the substrate, and a bonding pad on the interconnect layer. The bottom surface of the bonding pad may be located at a constant level, and the side surface of the bonding pad may have a roughened shape. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 are cross-sectional views illustrating semiconductor chips according to some example embodiments of the inventive concepts.

[0009] Figure 2 is corresponding to Figure 1 An enlarged view of portion “P1”.

[0010] Figure 3 are cross-sectional views illustrating semiconductor chips according to some example embodiments of the inventive concepts.

[0011] Figure 4 is corresponding to Figure 3 An enlarged view of portion “P1”.

[0012] Figure 5 are cross-sectional views illustrating semiconductor chips according to some example embodiments of the inventive concepts.

[0013] Figure 6 are cross-sectional views illustrating semiconductor chips according to some example embodiments of the inventive concepts.

[0014] Figure 7 are cross-sectional views illustrating semiconductor chips according to some example embodiments of the inventive concepts.

[0015] Figure 8 and Fig. 9 It is shown Figure 7 An enlarged view of portion “P1”.

[0016] Fig.10 are cross-sectional views illustrating semiconductor chips according to some example embodiments of the inventive concepts.

[0017] Fig.11 are cross-sectional views illustrating semiconductor chips according to some example embodiments of the inventive concepts.

[0018] Fig.12 are cross-sectional views illustrating semiconductor chips according to some example embodiments of the inventive concepts.

[0019] Fig.13 are cross-sectional views illustrating semiconductor chips according to some example embodiments of the inventive concepts.

[0020] Figures 14 to 17 are cross-sectional views illustrating a method of manufacturing a semiconductor chip according to some example embodiments of the inventive concept.

[0021] Fig.18 are cross-sectional views illustrating a method of manufacturing a semiconductor chip according to some example embodiments of the inventive concept.

[0022] Fig.19 are cross-sectional views illustrating a method of manufacturing a semiconductor chip according to some example embodiments of the inventive concept.

[0023] Fig. 20are cross-sectional views illustrating a method of manufacturing a semiconductor chip according to some example embodiments of the inventive concept.

[0024] Figure 21 to Figure 23 are cross-sectional views illustrating a method of manufacturing a semiconductor chip according to some example embodiments of the inventive concept.

[0025] Fig.24 are cross-sectional views illustrating a method of manufacturing a semiconductor chip according to some example embodiments of the inventive concept.

[0026] Fig.25 are cross-sectional views illustrating a method of manufacturing a semiconductor chip according to some example embodiments of the inventive concept.

[0027] Fig.26 are cross-sectional views illustrating semiconductor packages including semiconductor chips according to some example embodiments of the inventive concepts.

[0028] Fig. 27 are cross-sectional views illustrating semiconductor packages including semiconductor chips according to some example embodiments of the inventive concepts.

[0029] Fig.28 are cross-sectional views illustrating a plurality of semiconductor chips according to some example embodiments of the inventive concepts.

[0030] Fig.29 are cross-sectional views illustrating a plurality of semiconductor chips according to some example embodiments of the inventive concepts.

[0031] Fig.30 are cross-sectional views illustrating a plurality of semiconductor chips according to some example embodiments of the inventive concepts.

[0032] Fig.31 are cross-sectional views illustrating semiconductor packages including semiconductor chips according to some example embodiments of the inventive concepts.

[0033] Fig.32 are cross-sectional views illustrating semiconductor packages including semiconductor chips according to some example embodiments of the inventive concepts. DETAILED DESCRIPTION

[0034] Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.

[0035] Figure 1 are cross-sectional views illustrating semiconductor chips according to some example embodiments of the inventive concepts. Figure 2 is corresponding to Figure 1 An enlarged view of portion “P1”.

[0036] Reference Figure 1 , the semiconductor chip 1000 may include a substrate 100. In some example embodiments, the substrate 100 may be a single crystal silicon substrate, a silicon-germanium substrate, or a semiconductor substrate including a semiconductor material (eg, a silicon on insulator (SOI) substrate).

[0037] The device layer DL may be provided on the substrate 100. The device layer DL may include one or more field effect transistors (FETs). As an example, the field effect transistor may be a metal oxide semiconductor FET (MOSFET), but the inventive concept is not limited to this example. In some example embodiments, the device layer DL may include a DRAM cell.

[0038] The interconnect layer BEOL may be provided on the device layer DL. The interconnect layer BEOL may include a plurality of conductive lines CL, a plurality of via patterns VI, and an upper insulating layer UIL covering them. The conductive lines CL may be electrically connected to each other through the via pattern VI. The conductive lines CL and the via pattern VI may be electrically connected to the device layer DL. In some example embodiments, each of the conductive lines CL and the via pattern VI may be formed of at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Au, Ta, Ru, and Ir) or a metal nitride material (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, and Ir), or include at least one of the metal material or the metal nitride material. In this specification, each of the expressions "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B, and C", and "at least one of A, B, or C" may be used to represent one of the elements listed in the expression or any possible combination of the elements listed.

[0039] The upper insulating layer UIL may include a composite layer. In some example embodiments, the upper insulating layer UIL may be made of SiO 2 , TEOS, HDP, SiN, SiCN, SiCOH or SiON, or includes SiO 2 , TEOS, HDP, SiN, SiCN, SiCOH or SiON.

[0040] The conductive pad CP may be provided on the interconnect layer BEOL. The conductive pad CP may be electrically connected to the device layer DL through the conductive line CL and the via pattern VI. In some example embodiments, the conductive pad CP may be formed of or include at least one of metal materials (e.g., Ti, Mo, W, Cu, Al, Au, Ta, Ru, and Ir).

[0041] The first insulating layer IS1 may be provided on the interconnect layer BEOL. The first insulating layer IS1 may cover the conductive pad CP. The first insulating layer IS1 may be a single layer or a composite layer. In some example embodiments, the first insulating layer IS1 may be made of SiO 2 , TEOS, HDP or SiN, or includes SiO 2 , TEOS, HDP or SiN. As an example, a portion of the first insulating layer IS1 may be formed of the same material as the upper insulating layer UIL, or include the same material as the upper insulating layer UIL. In this case, it may be difficult to distinguish the portion of the first insulating layer IS1 from the upper insulating layer UIL.

[0042] The first recess RS1 may be defined in the first insulating layer IS1. The first recess RS1 may be provided on the conductive pad CP. The first recess RS1 may be provided to penetrate the first insulating layer IS1. At least a portion of an inner surface of the first recess RS1 may be defined by the conductive pad CP.

[0043] A barrier layer BAL may be provided on the first insulating layer IS1. The barrier layer BAL may be interposed between the first insulating layer IS1 and a second insulating layer IS2 to be described below. The barrier layer BAL may cover a top surface of the first insulating layer IS1. The barrier layer BAL may cover an inner side surface of the first recess RS1. In some example embodiments, the barrier layer BAL may conformally cover the top surface of the first insulating layer IS1 and the inner side surface of the first recess RS1. The barrier layer BAL may extend to continuously cover the top surface of the first insulating layer IS1 and the inner side surface of the first recess RS1. The barrier layer BAL may be in contact with the conductive pad CP. The barrier layer BAL may be located at a level lower than the bonding pad BP to be described below. In some example embodiments, the barrier layer BAL may be made of Al 2 O 3 Forming or including Al 2 O 3 .

[0044] According to some example embodiments of the present inventive concept, 2 O 3 Forming or including Al 2 O 3 The barrier layer BAL may cover the top surface of the first insulating layer IS1 and the inner surface of the first recess RS1. The barrier layer BAL may be configured to prevent or reduce the hydroxide (OH) from entering the layer below it (e.g., the first insulating layer IS1). This makes it possible to prevent or reduce failures caused by hydroxide (OH) in the semiconductor chip, thereby improving the reliability of the semiconductor chip.

[0045] The second insulating layer IS2 may be provided on the barrier layer BAL. The second insulating layer IS2 may cover the top surface of the first insulating layer IS1 and the inner side surface of the first recess RS1. In some example embodiments, the second insulating layer IS2 may cover the barrier layer BAL on the top surface of the first insulating layer IS1 and the inner side surface of the first recess RS1. An upper portion of the second insulating layer IS2 may be provided to surround a redistribution pattern RDL to be described below. In some example embodiments, the second insulating layer IS2 may be made of SiO 2 or TEOS, or includes SiO 2 or at least one of TEOS.

[0046] The second recess RS2 may be defined in the second insulating layer IS2. The second recess RS2 may be provided on the top surface of the barrier layer BAL.

[0047] The redistribution pattern RDL may be provided on the second insulating layer IS2. The redistribution pattern RDL may contact and be electrically connected to the conductive pad CP. The redistribution pattern RDL may be electrically connected to the device layer DL through the conductive pad CP, the conductive line CL and the via pattern VI. The redistribution pattern RDL may include a portion placed in the first recess RS1 to penetrate the first insulating layer IS1, the barrier layer BAL and the second insulating layer IS2. The redistribution pattern RDL may further include another portion provided to fill the second recess RS2. The top surface of the redistribution pattern RDL may be located at the same or substantially the same level as the top surface of the second insulating layer IS2. In some example embodiments, the redistribution pattern RDL may be formed of at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Au, Ta, Ru and Ir), or include at least one of the metal materials.

[0048] A barrier pattern (not shown) may be further interposed between the redistribution pattern RDL and the second insulating layer IS2 and between the redistribution pattern RDL and the conductive pad CP. The barrier pattern may prevent or reduce diffusion of materials in the redistribution pattern RDL into adjacent elements (e.g., the second insulating layer IS2 and the conductive pad CP). In some example embodiments, the barrier pattern may be formed of or include at least one of metal nitride materials (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, and Ir).

[0049] A bonding pad BP may be provided on the redistribution pattern RDL. The bonding pad BP may be electrically connected to the conductive pad CP through the redistribution pattern RDL. The bonding pad BP may overlap vertically with the redistribution pattern RDL. In the area vertically overlapping with the bonding pad BP, the top surface of the redistribution pattern RDL may be located at a constant or substantially constant level. The bottom surface of the bonding pad BP may also be located at a constant or substantially constant level. In this specification, the expression "the surface is located at a constant or substantially constant or uniform level" will be used to indicate that the surface extends to have a flat or substantially flat shape.

[0050] A bonding pad BP may be provided at the uppermost level of the semiconductor chip 1000. The semiconductor chip 1000 may be electrically connected to an external device (e.g., another semiconductor chip or a package substrate) through the bonding pad BP. In some example embodiments, the bonding pad BP may be formed of or include at least one of metal materials (e.g., Ti, Mo, W, Cu, Al, Au, Ta, Ru, and Ir).

[0051] The seed pattern SD may be interposed between the bonding pad BP and the redistribution pattern RDL. In some example embodiments, the seed pattern SD may be formed of or include at least one of metal materials (e.g., Ti, Mo, W, Cu, Al, Au, Ta, Ru, and Ir). The seed pattern SD may be formed of or include at least one of TiCu or TaCu.

[0052] The mold pattern MP may be provided on the side surface BS of the bonding pad BP. The mold pattern MP may cover the redistribution pattern RDL and the second insulating layer IS2. In some example embodiments, the mold pattern MP may include a portion penetrating the first insulating layer IS1. The top surface of the mold pattern MP and the top surface of the bonding pad BP may be located at the same or substantially the same level and may be coplanar or substantially coplanar with each other. In some example embodiments, the mold pattern MP may be formed of or include silicone.

[0053] Reference Figure 2, the side surface BS of the bonding pad BP may be roughened. In this specification, the expression "the surface of the element is roughened or has a roughened shape" will be used to indicate that the surface has an uneven shape. Therefore, the roughened surface may not be smooth and may be uneven. In some example embodiments, in order to roughen the surface of the element, an additional process may be performed on the surface of the element. Alternatively, the element may be formed to cover the roughened surface formed by the additional process, in which case the surface of the element may also have a roughened shape. The additional process may include an etching process performed on the surface of the element. In detail, during the etching process, large grains in the element may be etched at a slow rate compared to small grains. As a result, large grains may be less removed or hardly removed by the etching process, while small grains between large grains are completely removed. Surface roughening of an element or layer may be achieved by this method, but the inventive concept is not limited to this method.

[0054] The mold pattern MP may be provided to surround and cover the side surface BS of the bonding pad BP. In some example embodiments, the inner side surface MS of the mold pattern MP may contact the side surface BS of the bonding pad BP. Therefore, the inner side surface MS of the mold pattern MP may also be roughened, for example, to match the roughened side surface BS of the bonding pad BP.

[0055] According to some example embodiments of the inventive concept, since the side surface BS of the bonding pad BP is roughened, the contact area between the bonding pad BP and the mold pattern MP can be increased. This can make it possible to increase the adhesion strength between the bonding pad BP and the mold pattern MP and prevent or reduce the delamination problem therebetween and the cracking problem therein. Therefore, the reliability of the semiconductor chip can be improved.

[0056] In the following, reference will be made to Figures 3 to 13 Semiconductor chips according to some example embodiments of the inventive concept are described. In the following description, for the sake of concise description, previously described elements may be identified by the same reference numerals without repeating overlapping descriptions thereof.

[0057] Figure 3 are cross-sectional views illustrating semiconductor chips according to some example embodiments of the inventive concepts. Figure 4 is corresponding to Figure 3 An enlarged view of portion “P1”.

[0058] Reference Figure 3 and Figure 4, a connection terminal CT may be provided on the top surface of the bonding pad BP. The connection terminal CT may be a solder bump or a solder cap. The bonding pad BP may be electrically connected to an external device (e.g., an interposer or a package substrate) through the connection terminal CT. In some example embodiments, the connection terminal CT may be formed of at least one of metal materials (e.g., Ti, Mo, W, Cu, Al, Au, Ta, Ru, and Ir), or include at least one of the metal materials. The connection terminal CT may include a single metal layer or multiple metal layers. In some example embodiments, one of the metal layers in contact with the bonding pad BP may be formed of or include an intermetallic compound (IMC).

[0059] The top surface Ba of the bonding pad BP may be roughened, which may increase the contact area between the bonding pad BP and the connection terminal CT. As a result, the bonding strength between the bonding pad BP and the connection terminal CT may be enhanced, and thus, the delamination problem therebetween and the cracking problem therein may be prevented or reduced. Therefore, the reliability of the semiconductor chip may be improved.

[0060] Figure 5 and Figure 6 are cross-sectional views illustrating semiconductor chips according to some example embodiments of the inventive concepts.

[0061] Reference Figure 5 and Figure 6 , the top surface of the bonding pad BP may have an upwardly convex shape. This means that, regardless of whether there is a roughened portion, the center of the top surface of the bonding pad BP is located at a higher level than its edge. The connection terminal CT may be provided on the top surface Ba of the bonding pad BP.

[0062] References can be omitted Figures 1 to 4 In a subsequent packaging process, a mold layer (not shown) may be formed to cover the bonding pads BP and the connection terminals CT.

[0063] Reference Figure 5 ,and Figure 3 and Figure 4 Compared to the example embodiment of FIG. 1 , the top surface Ba of the bonding pad BP may not be roughened. In this case, the connection terminal CT may have a bottom surface Cb that contacts the top surface Ba of the bonding pad BP and has a non-roughened shape.

[0064] Alternatively, the top surface Ba of the bonding pad BP may be roughened, as shown in FIG. Figure 6 Since the bottom surface Cb of the connection terminal CT is in contact with the top surface Ba of the bonding pad BP, it may have a roughened shape.

[0065] Figure 7 are cross-sectional views illustrating semiconductor chips according to some example embodiments of the inventive concepts. Figure 8 and Fig. 9 It is shown Figure 7 An enlarged view of portion “P1”.

[0066] Reference Figures 7 to 9 , a screen pad PF may be provided on the top surface Ba of the bonding pad BP. Due to the screen pad PF, the top surface of the bonding pad BP may not be exposed to the outside. Therefore, the bonding pad BP may be prevented from being oxidized or reduced. In some example embodiments, the screen pad PF may include at least one of the transition metals. As an example, the screen pad PF may be formed of SnAg or include SnAg.

[0067] A portion of the mold pattern MP may cover the side surface of the shielding pad PF. An inner side surface MS' of the portion of the mold pattern MP may not have a roughened shape. The top surface of the mold pattern MP and the top surface of the shielding pad PF may be located at the same or substantially the same level and may be coplanar or substantially coplanar with each other.

[0068] Reference Figure 8 , the top surface Ba of the bonding pad BP may not have a roughened shape. The shielding pad PF may have a bottom surface Pb that contacts the top surface Ba of the bonding pad BP and does not have a roughened shape. The top surface Ba of the bonding pad BP may bulge toward the inside of the shielding pad PF. The bottom surface Pb of the shielding pad PF may be concave toward the inside of the shielding pad PF. However, other profiles may be used, such as a flat, or opposite concave / convex relationship.

[0069] Reference Fig. 9 , the top surface Ba of the bonding pad BP can be roughened, in which case the contact area between the bonding pad BP and the shielding pad PF can be increased. Therefore, the bonding strength between the bonding pad BP and the shielding pad PF can be enhanced, and thus, the delamination problem therebetween and the cracking problem therein can be prevented or reduced. As a result, the reliability of the semiconductor chip can be improved.

[0070] Fig.10 are cross-sectional views illustrating semiconductor chips according to some example embodiments of the inventive concepts.

[0071] Reference Fig.10 , the semiconductor chip 1000 may include a substrate 100. A device layer DL may be provided on the substrate 100. The substrate 100 and the device layer DL may be provided to have Figure 1 The features are the same or substantially the same or similar features.

[0072] An interconnect layer BEOL may be provided on the device layer DL. The interconnect layer BEOL may include a conductive line CL, a via pattern VI, and an upper insulating layer UIL covering them. The conductive line CL and the via pattern VI may be electrically connected to the device layer DL and may be electrically connected to a through plug TSV to be described below.

[0073] The conductive pad CP may be provided on the interconnection layer BEOL. The conductive pad CP may be electrically connected to the device layer DL and the through plug TSV through the conductive line CL and the via pattern VI.

[0074] The first insulating layer IS1, the barrier layer BAL, and the second insulating layer IS2 may be sequentially provided on the side surface CS of the conductive pad CP. The barrier layer BAL may be configured to prevent or reduce the hydroxide (OH) from entering the layer therebelow (e.g., the upper insulating layer UIL). The barrier layer BAL may be spaced apart from the conductive pad CP by the first insulating layer IS1. The first insulating layer IS1, the barrier layer BAL, and the second insulating layer IS2 may be located at a lower level than the first bonding pad BP1 to be described below. In some example embodiments, each of the first insulating layer IS1 and the second insulating layer IS2 may be made of SiO 2 Forming or including SiO 2 .

[0075] The third insulating layer IS3 may be provided on the second insulating layer IS2. The uppermost surface of the third insulating layer IS3 may be located at the same or substantially the same level as the top surface of the conductive pad CP. The third insulating layer IS3 may be a single layer or a composite layer. In some example embodiments, the third insulating layer IS3 may be formed of or include at least one of TEOS or HDP.

[0076] The first bonding pad BP1 may be provided on the conductive pad CP. The first bonding pad BP1 may vertically overlap the conductive pad CP. In the region vertically overlapping the first bonding pad BP1, the top surface of the conductive pad CP may be located at a constant or substantially constant level. The bottom surface of the first bonding pad BP may be located at a constant or substantially constant level. The first bonding pad BP1 may be electrically connected to the conductive pad CP without reference to Figure 1 The side surface BS of the first bonding pad BP1 may be provided to have a Figure 2 The side surface BS of the bonding pad BP is described to have the same or substantially the same or similar features.

[0077] The seed pattern SD may be interposed between the first bonding pad BP1 and the conductive pad CP. The seed pattern SD may be provided to have Figure 1 The features are the same or substantially the same or similar features.

[0078] The mold pattern MP may be provided on the side surface BS of the first bonding pad BP1. The mold pattern MP may be in contact with both the conductive pad CP and the barrier layer BAL. The inner side surface MS of the mold pattern MP may have a Figure 2 The features are the same or substantially the same or similar features.

[0079] The lower insulating layer 101 may be provided on the bottom surface 100b of the substrate 100. The lower insulating layer 101 may include a single layer or a composite layer. In some example embodiments, the lower insulating layer 101 may be made of SiO 2 , SiN or SiCN, or includes SiO 2 , SiN or SiCN.

[0080] The through plug TSV may be provided to penetrate the substrate 100 and the device layer DL. The through plug TSV may be in contact with one of the conductive lines CL of the interconnect layer BEOL. Thus, the first bonding pad BP1 may be electrically connected to the through plug TSV through the conductive pad CP, the conductive line CL, and the via pattern VI. The through plug TSV may be formed of at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Au, Ta, Ru, and Ir) or a metal nitride material (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, and Ir), or include at least one of the metal material or the metal nitride material.

[0081] The second bonding pad BP2 may be provided in the lower insulating layer 101. The second bonding pad BP2 may be in contact with the through plug TSV. The second bonding pad BP2 may be electrically connected to the first bonding pad BP1 through the through plug TSV. In some example embodiments, the second bonding pad BP2 may be formed of at least one of a metal material (e.g., Ti, Mo, W, Cu, Al, Au, Ta, Ru, and Ir), or include at least one of the metal materials.

[0082] Figures 11 to 13 are cross-sectional views illustrating semiconductor chips according to some example embodiments of the inventive concepts.

[0083] Reference Figures 11 to 13 , the connection terminal CT may be provided on the top surface Ba of the first bonding pad BP1. The connection terminal CT may be a solder bump or a solder cap. The connection terminal CT may include a single metal layer or a plurality of metal layers. In some example embodiments, one of the metal layers in contact with the first bonding pad BP1 may be formed of or include an intermetallic compound (IMC).

[0084] Reference Fig.11, the top surface Ba of the first bonding pad BP1 may have a roughened shape. In this case, the bottom surface Cb of the connection terminal CT in contact with the top surface Ba of the first bonding pad BP1 may have a roughened shape. The top surface of the mold pattern MP may be located at a level higher (e.g., much higher or significantly higher) than the top surface Ba of the first bonding pad BP1 or at the same level as the top surface Ba of the first bonding pad BP1.

[0085] Reference Fig.12 and Fig.13 , the top surface Ba of the first bonding pad BP1 may have an upwardly convex shape. Fig.10 In a subsequent packaging process, a mold layer (not shown) may be formed to cover the first bonding pads BP1 and the connection terminals CT.

[0086] Reference Fig.12 , the top surface Ba of the first bonding pad BP1 may not have the roughened shape. In this case, the bottom surface Cb of the connection terminal CT contacting the top surface Ba of the first bonding pad BP may not have the roughened shape.

[0087] Reference Fig.13 , the top surface Ba of the first bonding pad BP1 may have a roughened shape. In this case, the bottom surface Cb of the connection terminal CT contacting the top surface Ba of the first bonding pad BP may have a roughened shape.

[0088] In the following, reference will be made to Figures 14 to 25 Methods of manufacturing semiconductor chips according to some example embodiments of the inventive concept are described in more detail. In the following description, for concise description, previously described elements may be identified by the same reference numerals without repeating overlapping descriptions thereof.

[0089] Figures 14 to 17 are cross-sectional views illustrating a method of manufacturing a semiconductor chip according to some example embodiments of the inventive concept.

[0090] Will refer to Figures 14 to 17 The described manufacturing method can be used to manufacture Figure 1 and Figure 2 The semiconductor chip 1000 and Figure 3 and Figure 4 A semiconductor chip 1000 is provided.

[0091] Reference Fig.14 , a substrate 100 may be provided. A device layer DL may be formed on the substrate 100. The formation of the device layer DL may include forming a field effect transistor.

[0092] An interconnect layer BEOL may be formed on the device layer DL. The formation of the interconnect layer BEOL may include forming a conductive line CL on the device layer DL, forming a via pattern VI to connect the conductive lines CL to each other, and forming an upper insulating layer UIL to cover them. Considering the steps of forming the conductive line CL and the via pattern VI, the upper insulating layer UIL may be formed by one or more layer forming steps, but the inventive concept is not limited to the order or manner of the layer forming steps. Next, a conductive pad CP may be formed on the interconnect layer BEOL.

[0093] A first insulating layer IS1 may be formed on the interconnect layer BEOL. The first insulating layer IS1 may be formed to cover the top surface of the upper insulating layer UIL. The first insulating layer IS1 may be formed to cover the top surface and side surfaces of the conductive pad CP. The first insulating layer IS1 may be formed by one or more layer forming steps.

[0094] Reference Fig.15 , a patterning process may be performed to remove a portion of the first insulating layer IS1. Thus, a first recess RS1 may be formed in the first insulating layer IS1, and an inner surface of the first recess RS1 may be exposed to the outside. During the patterning process, an upper portion of the conductive pad CP may be partially recessed to a specific (or optionally, desired) depth, and a portion of a top surface of the conductive pad CP may be exposed to the outside.

[0095] A barrier layer BAL may be formed to conformally cover the exposed top surface of the first insulating layer IS1, the exposed inner side surface of the first recess RS1, and the exposed top surface of the conductive pad CP (including the recessed portion thereof). A second insulating layer IS2 may be formed to conformally cover the barrier layer BAL. The second insulating layer IS2 may further form a recess corresponding to the first recess RS1. A temporary layer TL may be formed to conformally cover the second insulating layer IS2. In some example embodiments, the temporary layer TL may be formed of at least one of SiN or SiCN, or include at least one of SiN or SiCN.

[0096] A redistribution mask pattern RMP may be formed on the temporary layer TL. The redistribution mask pattern RMP may be formed such that it does not vertically overlap the conductive pad CP.

[0097] Reference Fig.16, a removal process of the second insulating layer IS2 and the temporary layer TL may be performed using the redistribution mask pattern RMP as an etching mask. Therefore, a portion of the top surface of the conductive pad CP may be exposed to the outside again. In some example embodiments, the removal process may leave a portion of the barrier layer BAL extending along the recessed portion of the top surface of the conductive pad CP that is not exposed to the outside. During the removal process, a second recess RS2 may be formed in the second insulating layer IS2. During the removal process, a remaining portion of the temporary layer TL may remain on the top surface of the remaining portion of the second insulating layer IS2.

[0098] Thereafter, a barrier pattern (not shown) may be formed to conformally cover the exposed top surface of the conductive pad CP, the second insulating layer IS2, and the temporary layer TL. A redistribution pattern RDL may be formed to cover the barrier pattern. The redistribution pattern RDL may be formed in the first recess RS1 and the second recess RS2, and may cover the top surface of the second insulating layer IS2. The redistribution pattern RDL may be formed along the inner surface of the first recess RS1 and may fill the second recess RS2. Next, the redistribution pattern RDL on the top surface of the second insulating layer IS2 may be removed. The redistribution pattern RDL in the first recess RS1 and the second recess RS2 may not be removed by a removal process and may remain after the removal process. In some example embodiments, a removal process may be performed to remove the temporary layer TL from the top surface of the second insulating layer IS2, and thus, the top surface of the second insulating layer IS2 may be exposed to the outside. Thereafter, a seed pattern SD may be formed to conformally cover the exposed top surface of the second insulating layer IS2 and the redistribution pattern RDL.

[0099] The bonding mask pattern BMP may be formed to cover the substrate 100. In some example embodiments, a portion of the bonding mask pattern BMP may be formed to fill a remaining portion of the first recess RS1.

[0100] The bonding pad BP may be formed on the seed pattern SD. In some example embodiments, the formation of the bonding pad BP may include forming an opening OP in the bonding mask pattern BMP and forming the bonding pad BP on the seed pattern SD to fill the opening OP. In some example embodiments, the formation of the bonding pad BP may include performing an electroplating process.

[0101] Reference Fig.17 , a portion of the seed pattern SD and the bonding mask pattern BMP may be removed. In the removal process, a remaining portion of the seed pattern SD may remain between the bonding pad BP and the redistribution pattern RDL. As a result of the removal process, a side surface BS of the bonding pad BP may be exposed to the outside.

[0102] Next, the exposed side surface BS and top surface Ba of the bonding pad BP may be roughened. For example, the roughening process may include performing an etching process. In some example embodiments, the etching process may include a CZ treatment process. In detail, an etching process may be performed to remove small grains of material and suppress etching of large grains. In this case, small grains between large grains may be removed, and as a result, the surface may have a roughened (e.g., uneven or not smooth) shape. However, in some example embodiments, the opening OP may have a roughened side surface, and therefore, the bonding pad BP may be formed with a roughened surface.

[0103] In some example embodiments, after the roughening process of the bonding pad BP, a Figure 6 The connection terminal CT may be formed so that its bottom surface Cb contacts the top surface Ba of the bonding pad BP, and thus, the bottom surface Cb may have a roughened shape. In some example embodiments, the formation of the connection terminal CT may include performing a screen printing process. In addition, during the formation of the connection terminal CT, a reflow process may be performed on the connection terminal CT. In this case, the connection terminal CT may be formed to have Figure 6 The outline shown.

[0104] Return to reference Figure 1 , a mold pattern MP may be formed to cover the side surface BS of the bonding pad BP. A portion of the mold pattern MP may be formed to fill the remaining portion of the first recess RS1. During the formation of the mold pattern MP, a removal process may be performed on an upper portion of the mold pattern MP. In some example embodiments, the removal process on the upper portion of the mold pattern MP may include performing a chemical mechanical polishing process. Thus, a top surface of the mold pattern MP and a top surface of the bonding pad BP may be located at the same or substantially the same level and may be coplanar or substantially coplanar with each other. The removal process may be performed so that the top surface of the bonding pad BP is located at the same or substantially the same level, in which case the semiconductor chip 1000 may be formed to have a reference Figure 1 and Figure 2 The structure of the description.

[0105] According to some example embodiments of the inventive concept, the mold pattern MP may be formed after the bonding pad BP is formed. Therefore, a removal (e.g., etching) process of the mold pattern MP may be omitted, and damage to the mold pattern MP and the redistribution pattern RDL by the removal process may be prevented or reduced. As a result, the reliability of the semiconductor chip may be improved.

[0106] and Figure 1 Compared to the example implementation of Figure 3 and Figure 4The semiconductor chip 1000 may be formed in Figure 1 An additional process is further performed after forming the mold pattern MP.

[0107] Reference Figure 3 , in forming a reference Figure 1 After the mold pattern MP is described, a roughening process may be performed on the top surface Ba of the bonding pad BP. Therefore, the top surface Ba of the bonding pad BP may have a roughened shape. Fig.17 The roughening process is performed in a similar manner as described above. Thereafter, the connection terminal CT may be formed to cover the top surface Ba of the bonding pad BP. The bottom surface Cb of the connection terminal CT may be formed to contact the top surface Ba of the bonding pad BP, and thus, the bottom surface Cb may have a roughened shape.

[0108] In some example embodiments, the formation of the connection terminal CT may include performing a screen printing process. In addition, during the formation of the connection terminal CT, a reflow process may be performed on the connection terminal CT. Thus, the connection terminal CT may be formed to have Figure 3 As shown in the figure, in this case, the semiconductor chip 1000 can be manufactured with reference to Figure 3 and Figure 4 The structure of the description.

[0109] Fig.18 are cross-sectional views illustrating a method of manufacturing a semiconductor chip according to some example embodiments of the inventive concept.

[0110] Will refer to Fig.18 Describe the manufacturing method can be used to manufacture Figure 5 A semiconductor chip 1000 is provided.

[0111] Reference Fig.18 , in reference Fig.16 After the process of forming the opening OP in the bonding mask pattern BMP described above, the bonding pad BP and the connection terminal CT may be sequentially formed in the opening OP of the bonding mask pattern BMP. The connection terminal CT may be formed to cover the top surface of the bonding pad BP. In some example embodiments, the formation of the connection terminal CT may include performing an electroplating process.

[0112] Reference Figure 5 , a portion of the seed pattern SD and the bonding mask pattern BMP may be removed. The removal process may be performed to expose the side surface BS of the bonding pad BP to the outside, where the top surface of the bonding pad BP may not be exposed to the outside due to the connection terminal CT.

[0113] Next, a reflow process may be performed on the connection terminals CT. Thus, the connection terminals CT may be formed to have Figure 5The outline shown.

[0114] The exposed side surface BS of the bonding pad BP may be roughened. Fig.17 The roughening process is performed in a similar manner as described above. In this case, the semiconductor chip 1000 may be manufactured to have a roughening process as described above. Figure 5 The structure of the description.

[0115] Fig.19 are cross-sectional views illustrating a method of manufacturing a semiconductor chip according to some example embodiments of the inventive concept.

[0116] Will refer to Fig.19 The described manufacturing method can be used to manufacture Figure 7 and Figure 8 A semiconductor chip 1000 is provided.

[0117] Reference Fig.19 , in reference Fig.16 After the process of forming the opening OP in the described bonding mask pattern BMP, the bonding pad BP and the shielding pad PF may be sequentially formed in the opening OP of the bonding mask pattern BMP. The shielding pad PF may be formed to cover the top surface of the bonding pad BP. Therefore, the bonding pad BP may be prevented or reduced from being oxidized. In some example embodiments, the formation of the shielding pad PF may include performing an electroplating process.

[0118] Reference Figure 7 , a portion of the seed pattern SD and the bonding mask pattern BMP may be removed. The removal process may be performed to expose the side surface BS of the bonding pad BP to the outside, where the top surface of the bonding pad BP may not be exposed to the outside due to the shielding pad PF.

[0119] The exposed side surface BS of the bonding pad BP may be roughened. Fig.17 A similar method is described to perform the roughening process.

[0120] Thereafter, the mold pattern MP may be formed to cover the side surface of the bonding pad BP and the side surface of the shielding pad PF. During the formation of the mold pattern MP, a removal process may be performed on the upper portion of the mold pattern MP. Therefore, the top surface of the mold pattern MP may be formed at the same or substantially the same level as the top surface of the shielding pad PF. In this case, the semiconductor chip 1000 may be manufactured to have a reference Figure 7 and Figure 8 The structure of the description.

[0121] Fig. 20 are cross-sectional views illustrating a method of manufacturing a semiconductor chip according to some example embodiments of the inventive concept.

[0122] Will refer to Fig. 20 The described manufacturing method can be used to manufacture Figure 7 and Fig. 9 A semiconductor chip 1000 is provided.

[0123] Reference Fig. 20 , in reference Fig.17 After the roughening process of the bonding pad BP described above, a shielding pad PF may be formed to cover the top surface of the bonding pad BP. In some example embodiments, the formation of the shielding pad PF may include performing a screen printing process. The shielding pad PF may be formed so that its bottom surface Pb contacts the top surface Ba of the bonding pad BP, and thus, the bottom surface Pb of the shielding pad PF may have a roughened shape.

[0124] Next, the aforementioned manufacturing method can be used to form a reference Figure 7 and Fig. 9 A semiconductor chip 1000 is described.

[0125] Figure 21 to Figure 23 are cross-sectional views illustrating a method of manufacturing a semiconductor chip according to some example embodiments of the inventive concept.

[0126] Will refer to Figure 21 to Figure 23 The described manufacturing method can be used to manufacture Fig.10 The semiconductor chip 1000 and Fig.11 A semiconductor chip 1000 is provided.

[0127] Reference Fig.21 , a substrate 100 may be provided. A device layer DL may be provided on the substrate 100. The device layer DL may be formed by Fig.14 The method described is similar to the method described above.

[0128] Through-plugs TSV may be formed in the device layer DL and the substrate 100. The through-plugs TSV may be formed to penetrate the device layer DL and extend into the substrate 100.

[0129] An interconnect layer BEOL may be formed on the device layer DL. The interconnect layer BEOL may be formed by Fig.14 One of the conductive lines CL may be formed to cover the top surface of the through-plug TSV. Thereafter, a conductive pad CP may be formed on the interconnect layer BEOL.

[0130] The first insulating layer IS1, the barrier layer BAL, and the second insulating layer IS2 may be formed to sequentially cover the top surface of the upper insulating layer UIL. The first insulating layer IS1, the barrier layer BAL, and the second insulating layer IS2 may be formed to cover the side surface and the top surface of the conductive pad CP. The third insulating layer IS3 and the fourth insulating layer IS4 may be formed to sequentially cover the second insulating layer IS2. In some example embodiments, the fourth insulating layer IS4 may be formed of or include at least one of SiN or SiCN.

[0131] Reference Fig. 22 , a seed pattern SD may be formed to cover the entire top surface of the substrate 100. The seed pattern SD may be formed on the top surface of the conductive pad CP. A bonding mask pattern BMP may be formed on the seed pattern SD.

[0132] The first bonding pad BP1 may be formed on the conductive pad CP. In some example embodiments, the first bonding pad BP1 may be formed by contacting the reference Fig.16 The bonding pad BP is formed in a similar manner as described above.

[0133] Reference Fig.23 , the bonding mask pattern BMP and the seed pattern SD may be removed. A portion of the seed pattern SD may remain between the first bonding pad BP1 and the conductive pad CP. As a result of the removal process, the side surface BS of the first bonding pad BP1 may be exposed to the outside.

[0134] Next, the exposed side surface BS and the top surface Ba of the first bonding pad BP1 may be roughened. Fig.17 The roughening process for the first bonding pad BP1 is performed in a similar manner to the roughening process for the bonding pad BP described above.

[0135] Reference Fig.10 , the mold pattern MP may be formed to cover the side surface BS of the first bonding pad BP1. During the process of forming the mold pattern MP, a removal process may be performed on the upper portion of the mold pattern MP. Therefore, the top surface of the mold pattern MP and the top surface of the first bonding pad BP1 may be located at the same level or substantially the same level, and may be flat or substantially coplanar with each other. During the removal process, the top surface of the first bonding pad BP1 may be formed to be located at a constant or substantially constant level.

[0136] Thereafter, a removal process may be performed on the lower portion of the substrate 100. Thus, the bottom surface 100b of the substrate 100 may be located at the same or substantially the same level as the bottom surface of the through plug TSV.

[0137] A lower insulating layer 101 may be formed on the bottom surface 100b of the substrate 100. Next, a second bonding pad BP2 may be formed in the lower insulating layer 101. The second bonding pad BP2 may be formed to contact the through-plug TSV. In this case, the semiconductor chip 1000 may be manufactured to have a reference Fig.10 The structure of the description.

[0138] and Fig.10 Compared to the example implementation of Fig.11 The semiconductor chip 1000 is formed Fig.10 An additional process described below may be further performed after the mold pattern MP is formed and before the removal process of the lower portion of the substrate 100 .

[0139] Reference Fig.11 , in forming a reference Fig.10 After the mold pattern MP described above is formed, a roughening process may be performed on the top surface Ba of the first bonding pad BP1. Therefore, the top surface Ba of the first bonding pad BP1 may have a roughened shape. Thereafter, a connection terminal CT may be formed to cover the top surface Ba of the first bonding pad BP1. Therefore, the bottom surface Cb of the connection terminal CT may be disposed in contact with the top surface Ba of the first bonding pad BP1, and therefore, the bottom surface Cb may also be roughened.

[0140] In some example embodiments, the formation of the connection terminal CT may include performing a screen printing process. In addition, during the formation of the connection terminal CT, a reflow process may be performed on the connection terminal CT. Thus, the connection terminal CT may be formed to have Fig.11 The outline shown.

[0141] Next, the aforementioned manufacturing method can be used to form a reference Fig.11 A semiconductor chip 1000 is described.

[0142] Fig.24 are cross-sectional views illustrating a method of manufacturing a semiconductor chip according to some example embodiments of the inventive concept.

[0143] Will refer to Fig.24 The described manufacturing method can be used to manufacture Fig.12 A semiconductor chip 1000 is provided.

[0144] Reference Fig.24 , in forming a reference Fig. 22 After forming the bonding mask pattern BMP as described above, the first bonding pad BP1 and the connection terminal CT may be sequentially formed in the opening OP of the bonding mask pattern BMP. The connection terminal CT may be formed to cover the top surface of the first bonding pad BP1. In some example embodiments, the formation of the connection terminal CT may include performing an electroplating process.

[0145] Reference Fig.12 , a portion of the seed pattern SD and the bonding mask pattern BMP may be removed. The removal process may be performed to expose the side surface BS of the first bonding pad BP1 to the outside, where the top surface of the first bonding pad BP1 may not be exposed to the outside due to the connection terminal CT.

[0146] Thereafter, a reflow process may be performed on the connection terminals CT. Thus, the connection terminals CT may be formed to have Fig.12 The outline shown.

[0147] The exposed side surface BS of the first bonding pad BP1 may be roughened. Fig.17 The roughening process is performed in a similar manner to the method described above. Fig.10 Compared to the example embodiments of FIG. 1 , a process of forming the mold pattern MP may be omitted.

[0148] Next, the aforementioned manufacturing method can be used to form a reference Fig.12 A semiconductor chip 1000 is described.

[0149] Fig.25 are cross-sectional views illustrating a method of manufacturing a semiconductor chip according to some example embodiments of the inventive concept.

[0150] Will refer to Fig.25 The described manufacturing method can be used to manufacture Fig.13 A semiconductor chip 1000 is provided.

[0151] Reference Fig.25 , in reference Fig.23 After the described roughening process of the first bonding pad BP1, the connection terminal CT may be formed to cover the top surface Ba of the first bonding pad BP1. Since the bottom surface Cb of the connection terminal CT is formed to contact the top surface Ba of the first bonding pad BP1, it may have a roughened shape.

[0152] In some example embodiments, the formation of the connection terminal CT may include performing a screen printing process. In addition, during the formation of the connection terminal CT, a reflow process may be performed on the connection terminal CT. Thus, the connection terminal CT may be formed to have Fig.25 The outline shown.

[0153] Reference Fig.13 ,and Fig.10 Compared to the example embodiments of FIG. 1 , a process of forming the mold pattern MP may be omitted.

[0154] Thereafter, the aforementioned manufacturing method can be used to form a reference Fig.13 A semiconductor chip 1000 is described.

[0155] Fig.26 are cross-sectional views illustrating semiconductor packages according to some example embodiments of the inventive concepts.

[0156] Reference Fig.26 , the semiconductor package 1 may include a semiconductor chip 1000 , a package substrate 500 , external connection terminals 530 , and a mold layer MD.

[0157] The semiconductor chip 1000 may be mounted on a package substrate 500. In some example embodiments, the semiconductor chip 1000 may be similar to the Figure 1 , Figure 2 and Figures 7 to 9 One of the semiconductor chips 1000 described herein or a reference Figure 1 , Figure 2 and Figures 7 to 9 One of the semiconductor chips 1000 is depicted.

[0158] The package substrate 500 may be a printed circuit board (PCB). The package substrate 500 may have a top surface and a bottom surface opposite to each other, and may include an inner connection pad 510, an outer connection pad 520, and an inner line ICL electrically connecting them to each other. The inner connection pad 510 may be disposed on the top surface of the package substrate 500. The outer connection pad 520 may be disposed on the bottom surface of the package substrate 500. An adhesive layer 515 may be interposed between the package substrate 500 and the semiconductor chip 1000.

[0159] The semiconductor chip 1000 may be electrically connected to the package substrate 500 through an additional element. In some example embodiments, the bonding pads BP of the semiconductor chip 1000 may be electrically connected to the inner connection pads 510 of the package substrate 500 through wires W.

[0160] The mold layer MD may cover the semiconductor chip 1000 on the package substrate 500. In some example embodiments, the mold layer MD may be formed of or include epoxy molding compound (EMC).

[0161] External connection terminals 530 may be provided under the package substrate 500. Each external connection terminal 530 may contact a corresponding one of the external connection pads 520. Thus, the semiconductor package 1 may be electrically connected to an external device (eg, other semiconductor packages, a main board, etc.) through the external connection terminals 530.

[0162] Fig. 27 are cross-sectional views illustrating semiconductor packages according to some example embodiments of the inventive concepts.

[0163] Reference Fig. 27, the semiconductor package 1 may include a semiconductor chip 1000, a package substrate 500, an external connection terminal 530, and a mold layer MD. In some example embodiments, the semiconductor chip 1000 may be a reference Figures 3 to 6 One of the semiconductor chips 1000 is depicted.

[0164] and Fig.26 Compared with the semiconductor chip 1000 of FIG. 1 , the semiconductor chip 1000 may be inverted. Each connection terminal CT of the semiconductor chip 1000 may contact a corresponding one of the internal connection pads 510. Therefore, the semiconductor chip 1000 may be electrically connected to the package substrate 500 through the connection terminal CT. Fig.26 The adhesive layer 515 is described. A mold layer MD may be provided to surround and cover side surfaces of the connection terminals CT of the semiconductor chip 1000.

[0165] The semiconductor chip 1000 is a reference Figure 3 and Figure 4 In the case of the described semiconductor chip 1000 , the mold layer MD may not be in contact with the side surface of the bonding pad BP.

[0166] Although not shown in the drawings, if the semiconductor chip 1000 has a reference Figure 5 or Figure 6 The described structure, the mold pattern MP may not be provided, and the mold layer MD may be provided to surround and cover the side surface of the bonding pad BP.

[0167] Fig.28 are cross-sectional views illustrating a plurality of semiconductor chips according to some example embodiments of the inventive concepts.

[0168] Reference Fig.28 , the semiconductor chips 1000 may be vertically arranged on top of each other. Each semiconductor chip 1000 may be a reference Fig.10 A semiconductor chip 1000 is described. Fig.28 An example in which two semiconductor chips 1000 are provided is shown, but the inventive concept is not limited to this example; for example, three or more semiconductor chips 1000 may be stacked.

[0169] The semiconductor chip 1000 may include a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. Each of the first semiconductor chip and the second semiconductor chip may include a through-plug TSV. The first bonding pad BP1 of the first semiconductor chip may be electrically connected to the second bonding pad BP2 of the first semiconductor chip through the through-plug TSV. The first bonding pad BP1 of the second semiconductor chip may be electrically connected to the second bonding pad BP2 of the second semiconductor chip through the through-plug TSV. Fig.29, the first bonding pad BP1 is illustrated as being physically connected to the through-plug TSV, but the inventive concept is not limited to this example; for example, they may be electrically connected to each other through an additional contact (not shown) provided therebetween.

[0170] Each of the second bonding pads BP2 of the first semiconductor chip may make contact with a corresponding one of the first bonding pads BP1 of the second semiconductor chip. Thus, the through-plugs TSV of the first semiconductor chip may be electrically connected to the through-plugs TSV of the second semiconductor chip without an additional connection terminal.

[0171] Fig.29 are cross-sectional views illustrating a plurality of semiconductor chips according to some example embodiments of the inventive concepts.

[0172] Reference Fig.29 , the semiconductor chips 1000 may be vertically arranged on top of each other. Each semiconductor chip 1000 may be a reference Fig.11 A semiconductor chip 1000 is described.

[0173] The connection terminals CT may be interposed between the second bonding pads BP2 of the first semiconductor chip and the first bonding pads BP1 of the second semiconductor chip. Therefore, the second bonding pads BP2 of the first semiconductor chip may be electrically connected to the first bonding pads BP1 of the second semiconductor chip through the connection terminals CT, respectively.

[0174] The mold layer MD may be interposed between the first and second semiconductor chips to cover and surround side surfaces of the connection terminals CT. In some example embodiments, the mold layer MD may be formed of or include epoxy molding compound (EMC).

[0175] Fig.30 are cross-sectional views illustrating a plurality of semiconductor chips according to some example embodiments of the inventive concepts.

[0176] Reference Fig.30 , a plurality of semiconductor chips 1000 may be vertically arranged on top of each other. Each semiconductor chip 1000 may be a reference Fig.12 and Fig.13 One of the semiconductor chips 1000 is depicted.

[0177] The connection terminal CT may be interposed between the second bonding pad BP2 of the first semiconductor chip and the first bonding pad BP1 of the second semiconductor chip.

[0178] The mold layer MD may be interposed between the first semiconductor chip and the second semiconductor chip. The mold layer MD may be provided to surround and cover the side surfaces of the first bonding pads BP1 and the side surfaces of the connection terminals CT. That is, one of the bonding pads (eg, one of the first bonding pads BP1) may extend into the mold layer MD.

[0179] Fig.31 are cross-sectional views illustrating semiconductor packages including semiconductor chips according to some example embodiments of the inventive concepts.

[0180] Reference Fig.31 , the semiconductor package 2000 may include a substrate chip 1100 and a plurality of semiconductor chips 1000 and 1000 ′ on the substrate chip 1100 . Fig.31 As shown, the semiconductor chip 1000 may be a reference Fig.28 The semiconductor chip 1000 described above is a semiconductor chip 1000, but the inventive concept is not limited to this example. Alternatively, although not shown in the drawings, the semiconductor chip 1000 may be a semiconductor chip 1000 of the embodiment of the present invention. Fig.29 and Fig.30 One of the semiconductor chips 1000 is depicted.

[0181] The substrate chip 1100 may be electrically connected to the semiconductor chips 1000 and 1000' and may include a host core or a buffer die. The host core may include a processor configured to perform various operations. The buffer die may be configured to receive commands, data, and signals sent from the outside and send them to the semiconductor chips 1000 and 1000'. In other words, the semiconductor chips 1000 and 1000' connected to the substrate chip 1100 may be used to perform various tasks depending on the signals sent from the substrate chip 1100.

[0182] The semiconductor chips 1000 and 1000' may be electrically connected to the substrate chip 1100 through penetration plugs TSV. In some example embodiments, the substrate chip 1100 may include substrate bonding pads BPH placed at an uppermost level thereof, and the penetration plugs TSV may be electrically connected to the substrate chip 1100 through the substrate bonding pads BPH. In some example embodiments, the penetration plugs TSV may not be provided in the uppermost semiconductor chip 1000', but the inventive concept is not limited to this example.

[0183] Fig.32 are cross-sectional views illustrating semiconductor packages including semiconductor chips according to some example embodiments of the inventive concepts.

[0184] Reference Fig.32, the semiconductor package 2 may include package substrates 400 and 500, a storage structure 3000, and a host structure 800. The storage structure 3000 and the host structure 800 may be provided on the package substrates 400 and 500 and may be horizontally spaced apart from each other. The storage structure 3000 and the host structure 800 may be electrically connected to each other through the package substrates 400 and 500.

[0185] In some example embodiments, the package substrates 400 and 500 may include a first package substrate 400 and a second package substrate 500. The first package substrate 400 may be placed on the second package substrate 500, and the storage structure 3000 and the host structure 800 may be placed on the first package substrate 400. The first package substrate 400 may be an interposer, and the second package substrate 500 may be a printed circuit board (PCB). A first internal connection terminal 430 may be provided to electrically connect the first package substrate 400 to the second package substrate 500. A second internal connection terminal 540 may be provided to electrically connect the semiconductor package 2 to an external device (e.g., a mainboard).

[0186] The storage structure 3000 may include a substrate chip 300, a plurality of semiconductor chips 1000 and 1000' on the substrate chip 300, a first mold layer MD1 surrounding the semiconductor chips 1000 and 1000', and storage connection terminals 340 between the substrate chip 300 and the package substrates 400 and 500. The semiconductor chips 1000 and 1000' may correspond to Fig.31 The substrate chip 300 may correspond to the semiconductor chips 1000 and 1000'. Fig.31 A substrate chip 1100 is provided.

[0187] The substrate chip 300 may include a substrate layer 310, an upper interconnection layer 330 provided on one surface (e.g., the top surface) of the substrate layer 310, and a lower substrate pad 320 disposed near an opposite surface (e.g., the bottom surface) of the substrate layer 310 and exposed to the outside of the substrate layer 310. The upper interconnection layer 330 may include an upper substrate pad 332 and a base protection layer 334 surrounding the upper substrate pad 332.

[0188] The substrate chip 300 may be configured to allow for redistribution of the semiconductor chips 1000 and 1000'. The upper substrate pads 332 and the lower substrate pads 320 may be electrically connected to the circuit interconnects in the substrate layer 310, and may be combined with the circuit interconnects to form a redistribution circuit. The storage connection terminals 340 may be placed between the lower substrate pads 320 and the package substrates 400 and 500. The storage connection terminals 340 may include solder balls or solder bumps.

[0189] The first mold layer MD1 may include an insulating material. As an example, the first mold layer MD1 may include an epoxy molding compound (EMC). As an example, the first mold layer MD1 may correspond to Fig.30 The mold layer MD or Fig.31 The mold layer MD.

[0190] The host structure 800 may be a data processing device. The host connection terminal 840 may be interposed between the host structure 800 and the packaging substrates 400 and 500. The host connection terminal 840 may electrically connect the host structure 800 to the packaging substrates 400 and 500. The second mold layer MD2 may be provided on the packaging substrates 400 and 500 to encapsulate the storage structure 3000 and the host structure 800.

[0191] According to some example embodiments of the present inventive concept, the side surface of the bonding pad may be formed to have a roughened shape, which may make it possible to increase the contact area between the bonding pad and the mold pattern. As a result, the bonding strength between the bonding pad and the mold pattern may be enhanced, and thus, the delamination problem therebetween and the cracking problem therein may be prevented or reduced. Therefore, the reliability of the semiconductor chip may be improved.

[0192] According to some example embodiments of the present inventive concept, the top surface of the bonding pad may be formed to have a roughened shape, which may make it possible to increase the contact area between the shielding pad and the bonding pad or the contact area between the connection terminal and the bonding pad. As a result, the bonding strength between the shielding pad and the bonding pad or the bonding strength between the connection terminal and the bonding pad may be enhanced, and thus, the delamination problem therebetween and the cracking problem therein may be prevented or reduced. Therefore, the reliability of the semiconductor chip may be improved.

[0193] According to some example embodiments of the present inventive concept, a mold pattern may be formed after forming a bonding pad. Therefore, a removal (e.g., etching) process of the mold pattern may be omitted, and damage to the mold pattern and the redistribution pattern by the removal process may be prevented or reduced. As a result, the reliability of the semiconductor chip may be improved.

[0194] According to some example embodiments of the present inventive concept, 2 O 3 Forming or including Al 2 O 3 A barrier layer may be provided on the first insulating layer to prevent or reduce the hydroxide (OH) from entering the layer below the barrier layer (eg, the first insulating layer). As a result, failures caused by hydroxide in the semiconductor chip may be prevented or reduced, and the reliability of the semiconductor chip may be improved.

[0195] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value. In addition, when the words "approximately" and "substantially" are used in conjunction with a geometric shape, it is intended that the geometric shape is not required to be precise, but rather that tolerance of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the stated numerical value or shape.

[0196] While example embodiments of the present inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

[0197] CROSS-REFERENCE TO RELATED APPLICATIONS

[0198] This patent application claims the priority of Korean Patent Application No. 10-2023-0116381 filed in the Korean Intellectual Property Office on September 1, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor chip, comprising: substrate; a device layer and an interconnect layer sequentially on the substrate; as well as a bonding pad on the interconnect layer, The bottom surface of the bonding pad is located at a constant level, and A side surface of the bonding pad has a roughened shape.

2. The semiconductor chip according to claim 1 , further comprising a mold pattern on the side surface of the bonding pad, in, An inner side surface of the mold pattern has a roughened shape.

3. The semiconductor chip according to claim 1, wherein: A top surface of the bonding pad has a roughened shape.

4. The semiconductor chip according to claim 1 , further comprising a connection terminal on a top surface of the bonding pad, in, A bottom surface of the connection terminal has a roughened shape. 5 . The semiconductor chip of claim 1 , further comprising a shielding pad on a top surface of the bonding pad.

6. The semiconductor chip according to claim 5, wherein: A bottom surface of the shielding pad has a roughened shape.

7. The semiconductor chip according to claim 1, further comprising: a conductive pad on the interconnect layer; as well as A redistribution pattern beneath the bonding pad, Wherein, the bonding pad is electrically connected to the conductive pad through the redistribution pattern.

8. The semiconductor chip according to claim 1, further comprising a first insulating layer, a barrier layer, and a second insulating layer sequentially on the interconnect layer, in, The barrier layer includes Al2O3.

9. The semiconductor chip according to claim 1, wherein The bonding pad is a first bonding pad, The semiconductor chip further comprises, a second bonding pad on a bottom surface of the substrate; and a through-plug penetrating the substrate, and The first bonding pad is electrically connected to the second bonding pad via the penetration plug.

10. The semiconductor chip according to claim 1, wherein the device layer is a DRAM.

11. A semiconductor chip, comprising: substrate; a device layer and an interconnect layer sequentially on the substrate; a bonding pad on the interconnect layer; as well as a first insulating layer, a barrier layer and a second insulating layer sequentially on the interconnect layer, The barrier layer is located at a lower level than the bonding pad, and The barrier layer includes Al2O3.

12. The semiconductor chip according to claim 11, wherein: The first insulating layer and the second insulating layer include SiO 2 .

13. The semiconductor chip according to claim 11, further comprising a conductive pad under the bonding pad, in, The first insulating layer, the barrier layer, and the second insulating layer are sequentially on the side surface of the conductive pad.

14. The semiconductor chip according to claim 11, further comprising a redistribution pattern on the interconnect layer, The redistribution pattern penetrates the barrier layer.

15. The semiconductor chip according to claim 11, further comprising a first recess defined in the first insulating layer, in, The barrier layer covers the inner surface of the first recess.

16. The semiconductor chip according to claim 11, wherein: A side surface of the bonding pad has a roughened shape.

17. A semiconductor package comprising a semiconductor chip, The semiconductor chip comprises: substrate; a device layer and an interconnect layer sequentially on the substrate; as well as a bonding pad on the interconnect layer, The bottom surface of the bonding pad is at a constant level, and A side surface of the bonding pad has a roughened shape.

18. The semiconductor package according to claim 17, further comprising a package substrate below the semiconductor chip, in, The bonding pads are electrically connected to the package substrate through wires or connection terminals.

19. The semiconductor package according to claim 17, wherein the semiconductor chip comprises: a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, and Through-plugs electrically connecting the first semiconductor chip to the second semiconductor chip.

20. The semiconductor package according to claim 19, wherein The bonding pad is a first bonding pad, Each of the first semiconductor chip and the second semiconductor chip includes a second bonding pad on a bottom surface of the substrate, and The first bonding pad of the first semiconductor chip is electrically connected to the second bonding pad of the second semiconductor chip.

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