Semiconductor device and manufacturing method thereof

Abstract

The embodiment of the invention relates to a semiconductor device and a manufacturing method thereof. In a plan view, an electrode pad of a semiconductor chip includes: a first region including a center of an exposed portion of the electrode pad; the second area is located around the first area; and a third region around the first region and between the first region and the second region. Herein, a first recess that separates a plurality of semiconductor elements formed in a semiconductor substrate from each other is formed in the semiconductor substrate. The semiconductor substrate includes a fourth region that overlaps the third region but does not overlap each of the first and second regions, and a fifth region that overlaps the first region but does not overlap the third region. And a first recess is formed at the fifth region rather than the fourth region in the semiconductor substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-142929 filed on September 4, 2023, including specification, drawings and abstract, is incorporated herein by reference in its entirety. Background Art

[0003] The present invention relates to a semiconductor device.

[0004] In this article, the disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2023-11445

[0006] Patent document 1 discloses a semiconductor device in which a groove is formed on the upper surface of a semiconductor substrate at a position overlapping with an electrode pad formed on the upper surface of this semiconductor substrate, and the groove is separated from a device isolation arrangement prohibited area overlapping with the end portion of the spherical portion of a copper wire bonded to the electrode pad. Summary of the invention

[0007] As shown in Patent Document 1, an element isolation groove for separating a plurality of elements from each other is formed in a semiconductor substrate. If the element isolation groove formed on the semiconductor substrate is located at a position overlapping with an electrode pad formed on the upper surface of the semiconductor substrate, the periphery of the element isolation groove may be damaged due to stress generated when the spherical portion of the wire is bonded to the electrode pad.

[0008] On the other hand, as part of efforts to improve the performance of semiconductor devices, from the perspective of reducing the planar size of semiconductor devices, it is preferred to form elements at positions of a semiconductor substrate constituting the semiconductor device that overlap with electrode pads constituting the semiconductor device.

[0009] A semiconductor device according to one embodiment includes an electrode pad. In this article, in a plan view, the electrode pad includes: a first region including the center of an exposed portion of the electrode pad; a second region located around the first region; and a third region located around the first region and between the first region and the second region. In addition, a first groove that separates a plurality of semiconductor elements formed in a semiconductor substrate from each other is formed in the semiconductor substrate. In addition, the semiconductor substrate includes: a fourth region that overlaps with the third region but does not overlap with each of the first region and the second region, and a fifth region that overlaps with the first region but does not overlap with the third region. In addition, the first groove is formed at the fifth region in the semiconductor substrate instead of the fourth region.

[0010] According to one embodiment, the performance of a semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a top surface view of a semiconductor device according to an embodiment.

[0012] Figure 2 It is along Figure 1 Cross-sectional view of line AA.

[0013] Figure 3 is shown in perspective Figure 1 FIG. 2 is a perspective plan view of the internal structure of the semiconductor package in a state of sealing the body.

[0014] Figure 4 It is shown Figure 3 FIG. 1 is an enlarged plan view of one electrode pad among a plurality of electrode pads of a semiconductor chip shown.

[0015] Figure 5 is shown in the joint Figure 4 An enlarged plan view of the electrode pad prior to the wire being shown.

[0016] Figure 6 It is along Figure 5 An enlarged cross-sectional view of line BB.

[0017] Figure 7 It is shown Figure 6 The semiconductor substrate shown in Figure 5 An enlarged plan view of a portion where the enlarged plan views are overlapped is shown.

[0018] Figure 8 is an enlarged plan view schematically showing the positional relationship between the vibration direction of ultrasonic waves applied during the wire bonding step and the DTI.

[0019] Fig. 9 is shown with Figure 7 An enlarged plan view of a first modified example of a semiconductor substrate is shown.

[0020] Fig.10 is shown with Figure 7 An enlarged plan view of a second modified example of the semiconductor substrate shown.

[0021] Fig.11 is shown with Figure 6 An enlarged cross-sectional view of a modified example related to an element isolation trench is shown.

[0022] Fig.12 is shown with the formation in Figure 6 An enlarged cross-sectional view of a modified example of a trench in a semiconductor substrate is shown.

[0023] Fig.13is an explanatory diagram showing an assembly flow of a semiconductor package according to one embodiment.

[0024] Fig.14 It is shown in Fig.13 An enlarged plan view showing a state in which a semiconductor chip is mounted on a die pad of a lead frame during a semiconductor chip mounting step is shown.

[0025] Fig.15 is an enlarged cross-sectional view showing details of a wire bonding step.

[0026] Fig.16 It is shown Fig.15 Magnified cross-sectional view of detail of subsequent wire bonding step.

[0027] Fig.17 is shown with Figure 4 An enlarged plan view of a related modified example.

[0028] Fig.18 It is shown Fig.17 The semiconductor substrate of the semiconductor chip shown in FIG. Fig.17 An enlarged plan view of a portion where the enlarged plan views are overlapped is shown. DETAILED DESCRIPTION

[0029] (Description of tables, basic terms and usage in this application)

[0030] In this application, for convenience, the description of the embodiment is divided into multiple sections as needed. Unless otherwise clearly stated, no matter how the order of description is, these are not independent and separate from each other, and the parts of a single example can be details of each other, or a part or all of a modified example. In principle, the description of similar parts is omitted. In addition, each component in the embodiment is not required, and unless otherwise clearly stated, it is theoretically limited to this numerical value, and it is obviously not the case from the context.

[0031] Similarly, in the description of the embodiments, etc., regarding materials, compositions, etc., "X consisting of A" etc. does not exclude elements other than A unless it is clearly indicated otherwise and it is obvious from the context that this is not the case. For example, regarding components, it means "X includes A as a main component" etc. For example, the term "silicon member" etc. is not limited to pure silicon, and needless to say, it also includes members including SiGe (silicon germanium) alloys, multinary alloys including silicon as their main component, other additives, etc. In addition, unless otherwise specifically stated, terms such as gold plating, copper layer, nickel plating, etc. are not limited to pure forms, but include members including gold, Cu, nickel, etc. as their main components.

[0032] Furthermore, a recitation of a particular value or amount may be greater or less than that particular value unless expressly stated otherwise, is theoretically limited to that value, and is clearly not so from the context.

[0033] In the drawings of the embodiments, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description will not be repeated in principle.

[0034] Furthermore, in the drawings, when the cross section becomes complicated or when it is clearly distinguished from the gap, hatching or the like may be omitted even in the cross section.

[0035] In this case, even if the hole is closed on a plane, the outer shape of the background may be omitted when it is obvious from the description, etc. In addition, hatching or a dot pattern may be added to indicate that the area is not a void even if it is not a cross section or to indicate the boundary of the area.

[0036] In the present application, a semiconductor device refers to a device including a plurality of elements (semiconductor elements) formed on a semiconductor substrate and a wiring layer electrically connecting the plurality of elements. In the following description, a semiconductor chip and a semiconductor package are distinguished, wherein the semiconductor chip is mounted on a chip mounting area and is sealed. Each of the semiconductor chip and the semiconductor package is considered to be a semiconductor device.

[0037] <Semiconductor Package>

[0038] First, use Figures 1 to 3 An overview of the configuration of the semiconductor package PKG1 in the present embodiment is explained. Figure 1 is a top view of a semiconductor package according to this embodiment. Figure 2 It is along Figure 1 In addition, Figure 3 is shown in perspective Figure 1 FIG. 2 is a perspective plan view of the internal structure of the semiconductor package in a state of sealing the body.

[0039] exist Figures 1 to 3 In the description of X direction and Y direction (refer to Figure 1 and Figure 3 ) or Z direction (reference Figure 2 ). The Y direction is the side intersecting with the X direction, and in the following description, the X direction and the Y direction are orthogonal to each other. The Z direction is orthogonal to both the X direction and the Y direction. In other words, the Z direction is the normal direction of the XY plane including the X direction and the Y direction. In the following description, "thickness" mainly means the length in the Z direction. In addition, in the following description, "plan view" mainly means observing the XY plane.

[0040] The technology described in the following embodiments is widely applicable to semiconductor packages in which a wire or a columnar bump (a bump having a spherical portion formed at the tip of the wire, the spherical portion is bonded to the electrode pad, and then the wire portion is cut) is connected to an electrode pad exposed on the surface of a semiconductor chip. In this embodiment, as an example of a semiconductor package in which a wire is connected to an electrode pad of a semiconductor chip, a lead frame type semiconductor package is discussed. In the case of a lead frame type semiconductor package, a semiconductor chip mounted on a die pad of a lead frame and a plurality of leads arranged around the die pad are electrically connected via a wire.

[0041] like Figures 1 to 3 As shown, the semiconductor package PKG1 includes a semiconductor chip CP (refer to Figure 2 and Figure 3 ), a plurality of leads (terminals, external terminals) LD arranged around the semiconductor chip CP, and a plurality of wires BW (reference Figure 2 and Figure 3 ). In addition, the semiconductor chip CP and the plurality of wires BW are sealed in a sealing body (resin body) MR. In addition, each inner lead portion ILD (reference Figure 2 and Figure 3 ) is sealed in the sealing body MR, and each outer lead portion OLD of the plurality of leads LD is exposed from the sealing body MR.

[0042] like Figure 1 As shown, the sealing body MR included in the semiconductor package PKG1 has a rectangular planar shape. The sealing body MR includes an upper surface MRt, a lower surface (rear surface, mounting surface) MRb (reference Figure 2 ) and multiple ( Figure 1 There are four side surface MRs in the figure.

[0043] In addition, in the semiconductor package PKG1, a plurality of leads LD are arranged along each of the four side surfaces MRs of the sealing body MR having a rectangular plane shape. A plurality of leads LD are made of metal, and in the present embodiment, a plurality of leads LD are metal components such as mainly composed of copper (Cu). As in the present embodiment, a semiconductor package in which a plurality of leads LD are arranged along each of the four sides of the sealing body MR is referred to as a QFP (square flat package). Although not shown, a semiconductor package in which a plurality of leads LD are arranged along two sides on the opposite sides of the four sides of the sealing body MR and a plurality of leads LD are not arranged on the other two sides is referred to as a SOP (small outline package). This embodiment describes an embodiment of the semiconductor package PKG1 applied as a QFP, but as a modified example, it can also be applied to a semiconductor package as an SOP.

[0044] In the following embodiment, the semiconductor package PKG1 in which the semiconductor chip CP is mounted on a lead frame is described as a representative. However, the technology described below can be applied to a semiconductor package in which the semiconductor chip CP is mounted on a wiring substrate not shown in the figure.

[0045] like Figure 2 As shown, the outer lead portion OLD of the plurality of leads LD protrudes toward the outside of the sealing body MR on the side surface MRs of the sealing body MR. In the case of QFP or SOP, the outer lead portion OLD protrudes from the side surface MRs of the sealing body MR and has a shape bent toward the mounting surface side. In addition, although not shown, as a modified example of the semiconductor package PKG1, there is a semiconductor package in which each of the plurality of leads LD is exposed on the lower surface MRb of the sealing body MR. The semiconductor package in which the leads LD are exposed on the lower surface MRb of the sealing body MR includes a QFN (quad flat leadless package) and a SON (small outline leadless package).

[0046] like Figure 2 and Figure 3 As shown in FIG. 1 , the semiconductor chip CP is sealed with a sealing body MR. Figure 3 As shown, the semiconductor chip CP is formed into a rectangular shape in a plan view, which has an upper surface (main surface) CPt and a lower surface CPb (reference Figure 2). On the upper surface CPt of the semiconductor chip CP, a plurality of electrode pads (bonding pads) PD are provided along each of the four sides constituting the outer edge of the upper surface CPt. In addition, the semiconductor chip CP (specifically, the semiconductor substrate) is made of, for example, silicon (Si). Although not shown, a plurality of semiconductor elements (circuit elements) are formed on the main surface of the semiconductor chip CP (specifically, a semiconductor element formation region provided on the upper surface of the semiconductor substrate of the semiconductor chip CP). The plurality of electrode pads PD are electrically connected to the plurality of semiconductor elements through wiring (not shown) formed in a wiring layer located on the inner side of the semiconductor chip CP (specifically, between the upper surface CPt and the semiconductor element formation region not shown), respectively. In other words, the plurality of electrode pads PD are electrically connected to the circuit formed in the semiconductor chip CP.

[0047] In addition, on the upper surface CPt of the semiconductor chip CP, an insulating film covering the substrate and wiring of the semiconductor chip CP is formed, and the surface of each of the plurality of electrode pads PD is exposed in an opening formed in this insulating film. Additionally, these electrode pads PD are made of metal, and in this embodiment, for example, they are made of aluminum (Al).

[0048] The semiconductor chip CP is mounted on the die pad DP as a chip mounting portion. Figure 3 As shown, in the plan view, the die pad (chip mounting section) DP as the chip mounting section for mounting the semiconductor chip CP is arranged between the four sides S1, S2, S3 and S4 of the sealing body MR, and the semiconductor chip CP is mounted on the upper surface (front surface, main surface, chip mounting surface) DPt of the die pad DP. The upper surface DPt of the die pad DP is composed of a rectangle whose plane area is larger than the surface area of ​​the semiconductor chip CP. However, the die pad DP is a supporting member for supporting the semiconductor chip CP, and in addition to Figure 3 In addition to the examples shown, its shape and size can be applied to various modified examples. For example, the planar shape of the die pad DP can be circular. In addition, for example, the planar area of ​​the die pad DP can be smaller than the upper surface CPt of the semiconductor chip CP. In the case of the semiconductor package PKG1, the die pad DP is sealed in the sealing body MR. Although not shown, as a modified example of the semiconductor package PKG1, there is a case where the lower surface of the die pad DP is exposed from the sealing body MR on the lower surface MRb of the sealing body MR.

[0049] In addition, if Figure 2As shown, the semiconductor chip CP is mounted on the die pad DP via the die bonding material (adhesive material) DB so that its lower surface CPb faces the upper surface DPt of the die pad DP. In other words, it is mounted by the so-called face-up mounting method, in which the opposite surface (lower surface CPb) of the upper surface (main surface) CPton formed with a plurality of electrode pads PD faces the chip mounting surface (upper surface DPt). The die bonding material DB is an adhesive material used when mounting (die bonding) the semiconductor chip CP, for example, a conductive resin adhesive material containing a plurality of (numerous) conductive particles (for example, silver particles) in an epoxy-based thermosetting resin, or a solder material.

[0050] A plurality of leads LD are arranged around the semiconductor chip CP (in other words, around the die pad DP). A plurality of electrode pads (electrodes, pads) PD exposed on the upper surface CPt of the semiconductor chip CP are electrically connected to the inner lead portion ILD of the plurality of leads LD located inside the sealing body MR via a plurality of wires (conductive members) BW. One end portion of the wire BW (to be described later) is electrically connected to the inner lead portion ILD of the plurality of leads LD located inside the sealing body MR. Fig.14 The ball portion BWb shown is bonded to the electrode pad PD, and the other end portion is bonded to a portion (wire bonding area) of the inner lead portion ILD.

[0051] In the present embodiment, the wire BW is made of, for example, copper (Cu). However, the material of the wire BW is not limited to copper and can be applied to various modified examples such as gold (Au). When the wire BW is made of copper, it is preferable from the perspective of reducing material cost or reducing the impedance component of the transmission path formed by the wire.

[0052] In addition, if Figure 3 As shown, a plurality of suspension leads HL are arranged around the die pad DP. The suspension leads HL are members for supporting the die pad DP on a supporting portion (frame portion) of a lead frame during a manufacturing process of the semiconductor package PKG1.

[0053] <Semiconductor Chip>

[0054] Next, we will discuss Figure 2 and Figure 3 The semiconductor chip shown. Figure 4 It is shown Figure 3 FIG. 1 is an enlarged plan view of one of the plurality of electrode pads of the semiconductor chip shown. Figure 5 is shown in the joint Figure 4 An enlarged plan view of the electrode pad before the wire is shown. Figure 4 and Figure 5 In FIG. 1 , in order to show the planar shape of the portion of the electrode pad PD covered by the insulating layer PV, the outline of the electrode pad PD is illustrated with a dotted line. Figure 4 and Figure 5 , the boundaries of regions R1, R2, and R3 are indicated by double-dashed lines. Figure 6 It is along Figure 5 Magnified cross-sectional view of line BB in FIG. Figure 7 It is shown Figure 6 The semiconductor substrate shown in Figure 5 An enlarged plan view of a portion of the enlarged planes shown overlapping. Figure 7 In FIG. 1 , the boundaries of regions R4, R5, and R6 are indicated by double-dashed lines. Figure 7 1 is a plan view of the semiconductor substrate, but in order to show the planar positional relationship between the electrode pad PD and the regions R4, R5, and R6 of the semiconductor substrate SS, the outline of the electrode pad PD is illustrated by a dotted line.

[0055] exist Figure 6 , for simplicity, an example is illustrated in which a single insulating layer IL1 is placed between the electrode pad PD and the semiconductor substrate SS. However, there may be a case in which a plurality of wiring layers and a plurality of insulating layers IL1 are alternately stacked between the electrode pad PD and the semiconductor substrate SS.

[0056] like Figure 3 As shown, the semiconductor chip CP has an upper surface (main surface) CPt. The upper surface CPt of the semiconductor chip CP forms a square in a plan view, including a side CPs1 extending in the X direction, a side CPs2 extending in the Y direction intersecting (perpendicular) with the X direction, a side CPs3 located on the opposite side of the side CPs1, and a side CPs4 located on the opposite side of the side CPs2.

[0057] like Figure 4 and Figure 6 As shown, on the upper surface CPt, an insulating layer (protective film, protective insulating film) PV is formed. The insulating layer PV is made of, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON) or a laminated film thereof.

[0058] like Figure 6 As shown, the electrode pad PD is formed between the insulating layer PV and the semiconductor substrate SS (specifically, between the insulating layer PV and the insulating layer IL1). A portion of the electrode pad PD is exposed from the insulating layer PV at an opening portion PVk formed in the insulating layer PV. Figure 3 ) is formed in the insulating layer PV, and in each of these opening portions PVk, the electrode pad PD is exposed. In other words, the electrode pad PD has an exposed portion PDE exposed in the opening portion PVk of the insulating layer PV, and a peripheral portion PDP located around the exposed portion PDE and covered by the insulating layer PV.

[0059] like Figure 4 As shown, the ball portion BWb of the wire BW is bonded to a part of the exposed portion PDE of the electrode pad PD. In the present embodiment, the ball portion BWb of the wire BW is bonded to the exposed portion PDE in the regions R1 and R3.

[0060] The planar shape of the exposed portion PDE of the electrode pad PD forms a rectangle. This can be expressed as follows: each of the plurality of opening portions PVk formed in the insulating layer PV has a plurality of sides. The opening shape of the opening portion PVk includes a side Pks1 extending in the X direction, a side Pks2 intersecting the X direction (in Figure 4 In the example shown, there are a side Pks2 extending in the Y direction (vertical), a side Pks3 located on the opposite side of the side Pks1, and a side Pks4 located on the opposite side of the side Pks2. The side Pks1 of the opening portion PVk is arranged along the side CPs1 of the semiconductor chip CP, and the side Pks2 of the opening portion PVk is arranged along the side CPs2 of the semiconductor chip CP. In addition, the side Pks3 of the opening portion PVk is arranged along the side CPs3 of the semiconductor chip CP, and the side Pks4 of the opening portion PVk is arranged along the side CPs4 of the semiconductor chip CP.

[0061] In a plan view, the exposed portion PDE of the electrode pad PD includes a region R1 including the center of the opening portion PVk, a region R2 located around the region R1 , and a region R3 located around the region R1 and between the region R1 and the region R2 .

[0062] In a plan view, the region R3 is provided in a ring shape along each side of the exposed portion PDE of the electrode pad PD, so that the planar shape of the region R3 is formed as a hollow square. Figure 4 and Figure 5 In the example shown, the outer edge of the region R1 (the boundary between the region R1 and the region R3) and the outer edge of the region R3 (the boundary between the region R3 and the region R2) are each square. In addition, the region R2 is located at the outermost periphery of the exposed portion PDE, and its outer edge (the boundary between the region R2 and the surrounding portion PDP) is square.

[0063] like Figure 4 As shown, in a plan view, the outer edge of the spherical portion BWb of the wire BW overlaps with the region R3. Figure 4 In the illustrated example, a portion of the outer edge of the spherical portion BWb of the wire BW overlaps with the region R3 , and another portion of the outer edge of the spherical portion BWb of the wire BW overlaps with the region R1 .

[0064] In addition, if Figure 6As shown, the semiconductor chip CP has a semiconductor substrate SS with an upper surface SSt and an insulating layer IL1 formed on the upper surface SSt of the semiconductor substrate SS. An electrode pad PD is formed on the insulating layer IL1. An insulating layer PV is formed on the insulating layer IL1 so as to cover a peripheral portion PDP of the electrode pad PD.

[0065] exist Figure 6 In the embodiment, for simplification, an example is shown in which a single insulating layer IL1 is placed between the electrode pad PD and the semiconductor substrate SS. However, the number of layers of the insulating layer IL1 placed between the electrode pad PD and the semiconductor substrate SS is not limited to one layer, and there may be two or more layers. For example, a plurality of wiring layers not shown may be formed between the electrode pad PD and the semiconductor substrate SS, and a plurality of insulating layers IL1 may be placed as an interlayer insulating film for each wiring layer. The insulating layer IL1 is made of, for example, silicon dioxide (SiO2).

[0066] The semiconductor substrate SS is a base material of the semiconductor chip CP and is mainly composed of, for example, silicon (Si). The semiconductor device Q1 has a semiconductor region with p-type or n-type conductivity. The semiconductor region is formed by doping impurities from the upper surface SSt of the semiconductor substrate SS. The bottom surface of the semiconductor device Q1 to be described later is defined as a surface at a position farthest from the upper surface SSt in the thickness direction of the semiconductor substrate SS included in the doped semiconductor region.

[0067] A plurality of grooves TR are formed on the semiconductor substrate SS. The plurality of grooves TR include a groove TR1. The groove TR1 is a device isolation groove (DTI: deep trench isolation) for separating a plurality of semiconductor devices Q1 formed on the semiconductor substrate SS. Each of the plurality of semiconductor devices Q1 formed on the upper surface SSt of the semiconductor substrate SS includes, for example, a transistor or a diode.

[0068] like Figure 6 As shown, based on the upper surface SSt of the semiconductor substrate SS as a reference surface, the groove TR1 extends deeper than the semiconductor device Q1. In other words, if the upper surface SSt of the semiconductor substrate SS is regarded as a reference surface, the distance from the upper surface SSt to the bottom surface of the groove TR1 is longer than the distance from the upper surface SSt to the bottom surface of the semiconductor element Q1. For example, in Figure 6 In the example shown, the depth of the groove TR1 (the distance from the upper surface SSt to the bottom surface of the groove TR1) is about 1 μm to 20 μm. On the other hand, the depth of the semiconductor element Q1 from the upper surface SSt is about 50 nm to 100 nm.

[0069] In addition, if Figure 7As shown, the groove TR1 continuously surrounds the semiconductor element Q1. By providing the groove TR1 as an element isolation groove around the semiconductor element Q1, it is possible to prevent a plurality of semiconductor elements Q1 from interfering with each other. The width of the groove TR, i.e., Figure 6 The size of the opening shown on the upper surface SSt of the semiconductor substrate SS is, for example, about 0.5 μm to 1.0 μm. In the following description, an element isolation trench arranged to continuously surround the semiconductor element Q1 and extending deeper than the semiconductor element Q1 from the upper surface SSt of the semiconductor substrate SS used as a reference surface may be referred to as DTI.

[0070] <Questions about the location of the element isolation trench>

[0071] Herein, according to the research of the present inventors, it has been found that when the DTI is located at a position overlapping with the electrode pad PD, cracks may occur in the insulating layer IL1, resulting in separation from the semiconductor substrate SS. Figure 4 As shown, the aforementioned crack occurs during the wire bonding step in which the wire BW is bonded to the electrode pad PD. Specifically, it is considered that the stress generated by the ultrasonic wave applied to the spherical portion BWb of the wire BW is concentrated around the DTI, causing the crack.

[0072] The simplest way to prevent the aforementioned cracks from occurring is to not place the DTI at a position overlapping the electrode pad PD. In this case, the occurrence of cracks can be prevented by keeping the electrode pad PD away from the DTI through which the ultrasonic wave propagates.

[0073] However, if the DTI is not placed at a position overlapping with the electrode pad PD, it is impossible to place the semiconductor element Q1 (reference Figure 7 ) is placed at a position overlapping with the electrode pad PD. In this case, the area overlapping with the electrode pad PD cannot be used as an active area. Therefore, from the perspective of reducing the planar size of the semiconductor chip CP, it is preferred to place both the DTI and the semiconductor element Q1 at a position overlapping with the electrode pad PD.

[0074] Therefore, the present inventors have additionally studied the conditions under which the aforementioned cracks occur, and found that even if the DTI is formed at a position overlapping the electrode pad PD, there is a situation where cracks are less likely to occur depending on the positional relationship between the spherical portion BWb of the wire BW and the DTI. Below, the conditions under which cracks occur and the method of placing the DTI in consideration of these conditions will be explained in detail.

[0075] like Figure 4As shown, the spherical portion BWb of the wire BW forms a circle in a plan view. According to the research of the present inventors, it has been found that when the DTI is formed at a position overlapping with the outer edge of the spherical portion BWb forming a circle, cracks may occur near the DTI. In addition, it has been found that the DTI located at a position not overlapping with the outer edge of the spherical portion BWb forming a circle is less likely to cause cracks.

[0076] Furthermore, according to studies by the present inventors, it has been found that the occurrence of cracks is related to the direction of ultrasonic vibration applied to the wire BW during wire bonding and the extending direction of DTI is related to the frequency of crack occurrence.

[0077] Figure 8 is an enlarged plan view schematically showing the positional relationship between the vibration direction of ultrasonic waves applied during the wire bonding step and the DTI. Figure 8 In FIG. 1 , the outer edge of the electrode pad PD and the outer edge of the spherical portion BWb of the wire BW are indicated by dotted lines. Figure 8 , the boundaries of regions R4, R5, and R6 are indicated by dot-dash lines.

[0078] For example, Figure 8 As shown, the case where the vibration direction of the ultrasonic wave USW is parallel to the X direction will be explained. Figure 8 The grooves TRA, TRB and TRC shown are Figure 6 and Figure 7 The grooves TR1 shown have grooves of the same depth.

[0079] The groove TRA is formed in a direction intersecting the vibration direction of the ultrasonic wave USW (in Figure 8 The groove TRA extends in the Y direction in FIG. 1 , and a portion of the groove TRA overlaps with the outer edge of the spherical portion BWb. The groove TRA may cause the occurrence of cracks.

[0080] The groove TRB extends in the vibration direction of the ultrasonic wave USW, and the end of the groove TRB does not overlap with the outer edge of the spherical part BWb. In this case, although a part of the groove TRB overlaps with the outer edge of the spherical part BWb, the groove TRB is unlikely to cause the occurrence of cracks.

[0081] The groove TRC extends in the vibration direction of the ultrasonic wave USW, and the end of the groove TRC overlaps with the outer edge of the spherical portion BWb. The groove TRA may cause the occurrence of cracks.

[0082] also, Figure 8The depth and width (length of one side) of the hole HA shown are the same as the depth and width (width of the opening) of the groove TR. The planar shape of the hole HA forms a square having sides having a length substantially the same as the width (length in a direction intersecting the extension direction) of the groove TR. The hole HA overlaps the outer edge of the spherical portion BWb. However, the hole HA is unlikely to cause the occurrence of cracks.

[0083] From the above findings, the mechanism of crack occurrence is presumed as follows: when the DTI is located at a position overlapping the outer edge of the spherical portion BWb of the wire BW, stress generated by the propagation of the ultrasonic wave USW tends to concentrate around the DTI.

[0084] However, in the case of a small opening area, such as hole HA, the stress value propagated around hole HA is small, so it is considered unlikely to cause cracks. Figure 8 In the example, the case where the opening shape of the hole HA is a square is illustrated, but the same is applicable if, for example, the opening diameter of the hole HA is a circle.

[0085] In addition, in the case of a groove TRB, in which the groove extends along the vibration direction of the ultrasonic wave USW and the end of the groove TRB does not overlap with the outer edge of the spherical part BWb, it is considered that stress is unlikely to be concentrated at the position overlapping with the spherical part BWb, thereby making it impossible for cracks to occur.

[0086] The vibration direction of the ultrasonic wave USW can be set arbitrarily, but in many cases, the ultrasonic wave USW vibrates in the X direction or the Y direction. Figure 7 As shown, the upper surface SSt of the semiconductor substrate SS includes a region R3 (reference Figure 5 ) but does not overlap with region R1 (reference Figure 5 ) and region R2 (reference Figure 5 ), and a region R5 which overlaps with the region R1 but does not overlap with the region R3. The groove TR1 is formed at the region R5 in the semiconductor substrate SS instead of the region R4.

[0087] In other words, in the case of the present embodiment, the region R4 (refer to Figure 4 ) is not provided with the groove TR1 and is unlikely to overlap with the outer edge of the spherical portion BWb of the wire BW (reference Figure 4 ) is placed with groove TR1.

[0088] Furthermore, in the case of the present embodiment, the region R4 (refer to Figure 4) is set as a prohibited area for placing the element isolation groove. According to the present embodiment, since the groove TR1 is not placed in the region R4 that may overlap with the outer edge of the spherical portion BWb of the wire BW (refer to Figure 4 ), so the occurrence of cracks due to stress concentration can be suppressed regardless of the ultrasonic USW in the wire bonding step (reference Figure 8 )'s vibration direction.

[0089] Furthermore, according to the present embodiment, on the upper surface SSt of the semiconductor substrate SS, the groove TR1 is placed in the region R5 surrounded by the region R4 and overlapping with the electrode pad PD. Therefore, the semiconductor element Q1 can be formed in the region R1. Therefore, by making the region overlapping with the electrode pad PD an active region where the semiconductor element Q1 can be formed, the plane size of the semiconductor chip CP can be reduced (refer to Figure 3 ).

[0090] <First Modification Example>

[0091] Next, we will describe Figure 7 Modification examples of the illustrated embodiments. Fig. 9 is shown with Figure 7 FIG. 1 is an enlarged plan view of a first modified example of a semiconductor substrate. Fig. 9 In FIG. 1 , the outer edges of the electrode pad PD and the spherical portion BWb of the wire BW are indicated by dotted lines. Fig. 9 , the boundaries of regions R4, R5, and R6 are indicated by dot-dash lines. Fig. 9 The upper surface SSt of the semiconductor substrate SS1 shown has regions R4, R5 and R6. Figure 7 The upper surface SSt of the semiconductor substrate SS is shown. Fig. 9 As shown, the planar shape of region R4 is a hollow square. In other words, in the plan view, the outer edge of region R4 (the boundary between regions R4 and R6) is a square, and region R4 is arranged to continuously surround region R5. This is also similar to Figure 7 The upper surface SSt of the semiconductor substrate SS is shown. In addition, in the plan view, the boundary of the region R4 and the boundary of the region R5 have four sides S54 and four corners C54, wherein any two of the four sides S54 intersect. This is also similar to Figure 7 The upper surface SSt of the semiconductor substrate SS is shown.

[0092] Fig. 9 The upper surface SSt of the semiconductor substrate SS1 is shown Figure 7The upper surface SSt of the semiconductor substrate SS shown is different in the following points. That is, on the upper surface SSt of the semiconductor substrate SS1, a hole H1 having an opening area smaller than that of the groove TR1 is arranged between each of the four corners C54 and the groove TR1. Fig. 9 In the example shown, four holes H1 are formed at the region R5 in the semiconductor substrate SS.

[0093] If used Figure 8 As explained, even if the hole HA having a small opening area is formed at a position overlapping with the outer edge of the spherical portion BWb of the wire BW, crack formation is unlikely to occur. Similarly, regardless of the depth of the hole H1, the Fig. 9 Each of the plurality of holes H1 shown is unlikely to cause crack formation. The diameter of the hole H1 is the same as the size of one side of the hole HA, for example, about 0.5 μm to 1.0 μm. Note that the planar shape of the hole H1 is not limited to a circle, but may be a square, a straight line, or an L-shape. However, when the hole is a square, a straight line, or an L-shape, the width of the hole is the same as the width of the hole HA. Fig. 9 The diameters of the holes H1 shown are of the same size. In this document, the width of a hole refers to the length in a direction intersecting the direction in which the hole extends in a plan view.

[0094] Considering the processing accuracy in the step of bonding the wire BW to the electrode pad PD, the actual bonding position of the wire BW may have an error from the designed bonding position in either or both of the directions X and Y. Therefore, around the four corners C54 of the boundary between the regions R4 and R5, there is a possibility of overlapping with the spherical portion BWb depending on the degree of misalignment of the wire BW.

[0095] In the case of this modified example, near each of the four corners C54 of the region R5 having a square planar shape, there is a hole H1 that is unlikely to cause crack formation. Each corner of the plurality of holes H1 is spaced from the groove TR1 as the DTI. Therefore, it is possible to avoid placing the groove TR1 around the four corners C54. In other words, each of the four holes H1 serves as a dummy groove to prevent the groove TR1 from being placed at a position overlapping the outer edge of the spherical portion BWb.

[0096] In addition to the differences mentioned above, Fig. 9 The semiconductor substrate SS1 shown is similar to the one used in Figure 7 Therefore, repeated description is omitted.

[0097] <Second Modification Example>

[0098] Next, we will describe Figure 7 Another modified example of the illustrated embodiment. Fig.10is shown with Figure 7 An enlarged plan view of a second modified example of a semiconductor substrate shown in FIG. Fig.10 In FIG. 1 , the outer edges of the electrode pad PD and the spherical portion BWb of the wire BW are indicated by dotted lines. Fig.10 , the boundaries of regions R4, R5 and R6 are shown by dotted lines. Fig.10 The upper surface SSt of the semiconductor substrate SS2 shown has regions R4, R5 and R6. Figure 7 The upper surface SSt of the semiconductor substrate SS is shown. Fig.10 As shown, the planar shape of region R4 is a hollow square. In other words, in the plan view, the outer edge of region R4 (the boundary between regions R4 and R6) is a square, and region R4 is arranged to continuously surround region R5. This is also similar to Figure 7 The upper surface SSt of the semiconductor substrate SS is shown. In addition, in the plan view, the boundary of the region R4 and the boundary of the region R5 have four sides S54 and four corners C54 where any two of the four sides S54 intersect. This is also similar to Figure 7 The upper surface SSt of the semiconductor substrate SS is shown.

[0099] Fig.10 The upper surface SSt of the semiconductor substrate SS2 shown in FIG. Figure 7 The upper surface SSt of the semiconductor substrate SS shown is different in the following points: That is, in a plan view, each of the four corners C54 has an arc shape.

[0100] As mentioned above, considering the processing accuracy in the step of bonding the wire BW to the electrode pad PD, the actual bonding position of the wire BW may deviate from the designed bonding position in at least one of the directions X and Y or in both directions. Therefore, depending on the degree of misalignment of the wire BW, the vicinity of the four corners C54 in the boundary between the regions R4 and R5 may overlap with the spherical portion BWb.

[0101] In the case of this modified example, each of the four corners C54 is arc-shaped in a plan view, Fig. 9 Compared with the example shown, the margin between the outer edge of the spherical portion BWb and the four corners C54 can be widened. This allows avoiding placing the groove TR1 at a position overlapping with the outer edge of the spherical portion BWb.

[0102] In addition to the differences mentioned above, Fig.10 The semiconductor substrate SS2 shown is similar to the one used in Figure 7 Therefore, repeated description is omitted.

[0103] <Third Modification Example>

[0104] Next, a modified example of the DTI structure will be described. Fig.11 is shown with Figure 6 This is an enlarged cross-sectional view of a modified example of the element isolation trench shown. Fig.11 In the example shown, the structure of the groove TR1 as DTI is the same as Figure 7 The example shown differs in the following points. Fig.11 Inside the groove TR1 shown, there is an insulating material layer ITR covering the inner wall of the groove TR1 and an air layer AGL surrounded by the insulating material layer ITR. Compared with the groove TR1 without the air layer AGL, Fig.11 The groove TR1 including the air layer AGL shown has the following advantages: namely, the withstand voltage characteristics (withstand voltage characteristics) of the semiconductor integrated circuit are improved. Figure 7 The withstand voltage value of the groove TR1 shown is 75V (volts), so when using Fig.11 The withstand voltage value of the groove TR1 shown is 100 V (volts).

[0105] On the other hand, according to the research conducted by the inventors of the present invention, it has been found that when the groove TR1 including the air layer AGL is formed at a position overlapping with the spherical portion BWb of the wire BW, the frequency of crack occurrence increases significantly (refer to Figure 8 ).

[0106] However, as mentioned above, if Fig.11 The groove TR1 shown is not located in the region R4, so the frequency of crack occurrence can be suppressed.

[0107] Therefore, according to this modification example, it is possible to improve the withstand voltage characteristics of the semiconductor integrated circuit while suppressing the occurrence of cracks.

[0108] <Fourth Modification Example>

[0109] Next, modified examples of the groove formed in the semiconductor substrate will be described. Fig.12 It is shown that the Figure 6 An enlarged cross-sectional view of a modified example of a groove in a semiconductor substrate is shown.

[0110] The semiconductor element Q1 may be formed by a combination of a plurality of semiconductor regions. Fig.12 In the illustrated case, the semiconductor element Q1 has semiconductor regions QR1 and QR2. There are various modified examples of the configuration of the semiconductor regions QR1 and QR2, for example, one of the semiconductor regions QR1 and QR2 is an n-type semiconductor region, and the other is a p-type semiconductor region. A groove TR2 is formed between the semiconductor regions QR1 and QR2. Fig.12In the case of the illustrated modification example, the plurality of grooves TR formed on the upper surface SSt of the semiconductor substrate SS includes the grooves TR1 and the like, and the grooves TR2 .

[0111] The groove TR2 is one of the grooves TR formed on the upper surface SSt of the semiconductor substrate SS. The groove TR2 is a groove called STI (shallow trench isolation). The groove TR2 is located across two different semiconductor regions and serves as an insulating region to prevent leakage current between adjacent semiconductor regions.

[0112] Taking the upper surface SSt of the semiconductor substrate SS as a reference surface, the groove TR2 is shallower than the groove TR1. Fig.12 In the example shown, the depth of the groove TR2 (the distance from the upper surface SSt to the bottom surface of the groove TR2) is about 30 nm. In such a shallow groove TR2, the aforementioned crack is unlikely to be caused. Therefore, even if the groove TR2 is located Figure 7 In the region R4 shown, and Figure 4 The outer edge of the spherical portion BWb of the wire BW is shown Fig.12 The grooves TR2 shown overlap and the frequency of crack occurrence does not increase.

[0113] <Method of Manufacturing Semiconductor Package>

[0114] Next, we will describe Figure 1 The manufacturing method of the semiconductor package PKG1 shown in FIG. Fig.13 The assembly process shown is to manufacture the semiconductor package PKG1 of this embodiment. Fig.13 is an explanatory diagram showing the assembly flow of the semiconductor package of this embodiment. Fig.13 In the example shown, the method for manufacturing a semiconductor package of the present embodiment includes a semiconductor chip preparation step, a substrate preparation step, a semiconductor chip mounting process, a wire bonding step, a sealing step, and a singulation step. In the following description, when explaining each component constituting the semiconductor package, reference will be made to Figures 1 to 12 .

[0115] <Substrate preparation step>

[0116] exist Fig.13 In the substrate preparation steps shown, the Fig.14 The lead frame (substrate) LF is shown. Fig.14 It is shown in Fig.13 An enlarged plan view of a state in which a semiconductor chip is mounted on a die pad of a lead frame in the semiconductor chip mounting step shown. As a modified example of the present embodiment, in the case of a method for manufacturing a semiconductor package in which a semiconductor chip CP is mounted on an unshown wiring substrate, a wiring substrate is prepared in this step instead of a lead frame.

[0117] like Fig.14 As shown, the lead frame LF prepared in this step includes a plurality of device forming sections LFd connected to a frame section (frame portion) LFf. Each of the plurality of device forming sections LFd is connected to a frame section (frame portion) LFf. Figure 1 One semiconductor package PKG1 shown corresponds to the lead frame LF, which is a so-called multi-unit substrate in which a plurality of device forming sections LFd are arranged.

[0118] The lead frame LF is made of a metal material mainly composed of copper (Cu). Each of the plurality of device forming sections LFd is connected to the frame section LFf. The frame section LFf serves as a supporting portion that supports each component formed in the device forming section LFd until Fig.13 The lead separation steps are shown.

[0119] Furthermore, in the device forming section LFd, as shown in FIG. Figure 3 As shown, a die pad DP and a plurality of leads LD are formed. The die pad DP is connected to the frame section LFf through a suspension lead and supported by the frame section LFf. Each of the plurality of leads LD is connected to the frame section LFf through a tie bar TB and supported by the frame section LFf.

[0120] <Semiconductor chip preparation step>

[0121] exist Fig.13 In the semiconductor chip preparation steps shown, the preparation Fig.14 The semiconductor chip CP shown. Fig.14 As shown, the semiconductor chip CP prepared in this step is bonded to the bonding wire BW (reference Figure 3 ) semiconductor chips before. Figures 2 to 12 The detailed structure of the semiconductor chip CP is explained, and thus redundant explanation is omitted.

[0122] <Semiconductor chip mounting steps>

[0123] Next, in Fig.13 In the semiconductor chip mounting step shown, Fig.14 As shown, the semiconductor chip CP is mounted on the die pad DP.

[0124] In this step, if Figure 2 As shown, the semiconductor chip CP is mounted on the upper surface DPt of the die pad DP via the die bonding material DB. In this step, after the die bonding material DB is applied on the upper surface DPt of the die pad DP, the semiconductor chip CP is placed on the die bonding material DB. Then, by curing the die bonding material DB, the semiconductor chip CP and the die pad DP are fixed.

[0125] In this step, if Figure 2 As shown, the semiconductor chip CP is mounted on the die pad DP in a state where the lower surface CPb of the semiconductor chip CP faces the upper surface DPt of the die pad DP. This allows the wire BW (reference wire) to be easily bonded to the die pad DP in the subsequent wire bonding step. Figure 2 ) is bonded to each of a plurality of electrode pads PD located on the upper surface CPt of the semiconductor chip.

[0126] <Wire Bonding Step>

[0127] Next, in Fig.13 In the wire bonding step shown in FIG. 1 , a wire is bonded to the electrode pad PD of the semiconductor chip CP, as shown in FIG. Figure 3 In the present embodiment, during the wire bonding step, the electrode pads PD of the semiconductor chip CP and the leads LD are electrically connected via the wires BW. Fig.15 and Fig.16 is an enlarged cross-sectional view showing details of a wire bonding step.

[0128] Reference below Fig.15 and Fig.16 A method of bonding the wire BW to the electrode pad PD using a ball bonding method is described. Figure 4 As shown in FIG. 1 , when the spherical portion BWb of the wire BW is bonded to the electrode pad PD using a ball bonding method, the bonding strength can be improved by applying high-frequency vibrations (such as ultrasonic vibrations) to the spherical portion BWb. "Ultrasonic waves" refer to elastic waves with frequencies higher than the human audible range. In this application, high frequencies of 20 kHz or higher are referred to as "ultrasonic waves."

[0129] In the ball bonding step, in addition to applying ultrasonic waves, a scrubbing action for removing an oxide film on the bonding surface between the electrode pad PD and the ball portion BWb may be performed. Figure 8 The vibration direction of the ultrasonic wave USW explained refers to the vibration direction of the ultrasonic wave applied in the wire bonding step, which is different from the vibration direction of the scrubbing action.

[0130] In the wire bonding step, first, as Fig.15 As shown, the tip of the wire BW held by the capillary CAP is heated and melted to form a spherical portion BWb.

[0131] Next, if Fig.16 As shown, the capillary CAP holding the wire BW moves toward the electrode pad PD, pressing the spherical portion BWb onto the upper surface PDt of the electrode pad PD. At this time, ultrasonic waves USW are applied through the wire BW. Fig.16In the example shown, the ultrasonic wave USW vibrates in the X direction. Fig.16 In the example shown, although the vibration direction of the ultrasonic wave USW is along the X direction, as a modified example, there may be a case where the vibration direction of the ultrasonic wave USW is along the X direction. Figure 7 The situation in the Y direction is shown.

[0132] In this step, if Figure 4 As shown, the wire BW is bonded at a position where the outer edge of the spherical portion BWb overlaps with the region R3 in a plan view. Figure 6 and Fig.16 As shown, on the upper surface SSt of the semiconductor substrate SS, the region R4 overlaps with the region R3. Figure 4 and Figure 5 It can be understood that the entire region R4 overlaps with the region R3. Therefore, in this step, the wire BW is bonded at a position where the outer edge of the spherical portion BWb overlaps with the region R4 in a plan view.

[0133] Herein, as already explained, the groove TR1 is not formed in the region R4, which may cause cracking. Although the groove TR1 is formed in the region R5, the groove TR1 formed in the region R5 is less likely to cause cracking. As a result, according to the method for manufacturing a semiconductor package of the present embodiment, even if the groove TR1 as DTI is formed at a position overlapping the electrode pad PD, the frequency of crack occurrence can be reduced.

[0134] Next, release Fig.16 The capillary CAP is shown holding the wire BW, and the capillary CAP moves upward. At this time, since the ball portion BWb is bonded to the electrode pad PD, the wire BW in which the ball portion BWb is bonded to the electrode pad PD is obtained.

[0135] Next, move the capillary CAP to Figure 3 After the wire bonding area of ​​the lead LD is formed, the wire BW is bonded to the lead LD. Then, by cutting the excess wire, a Figure 2 and 3 Wire BW shown.

[0136] As a modified example of the present embodiment, there may be a case where a columnar bump is bonded to the electrode pad PD. Fig.16 After the explained steps, the wire BW is cut on the top of the ball portion BWb. As a result, the ball portion BWb remains on the electrode pad PD, and this ball portion BWb can be used as a stud bump.

[0137] <Sealing Step>

[0138] Next, in Fig.13 In the sealing step shown, the insulating resin is used to seal Figure 2 The semiconductor chip CP, the die pad DP, the plurality of leads LD (each inner lead portion ILD) and the plurality of wires BW are formed as shown in FIG. Figure 1 and Figure 2 In this step, for example, the sealing body MR is formed by a so-called transfer molding method using a molded die including an upper mold (first mold) and a lower mold (second mold). Fig.14 The die pad DP and the lead frame LF of the plurality of leads LD of the device forming section LFd are shown to be located in the cavity of the molded die. Then, the lead frame LF is sandwiched between the upper molding and the lower molding. In this state, when the softened (plasticized) thermosetting resin (insulating resin) is pressed into the cavity of the molded die, the insulating resin is molded in the shape of the cavity.

[0139] At this time, a portion of each of the plurality of leads LD (outer lead portion OLD) is in contact with the molded die. Figure 2 As shown, after this step, the outer lead portions OLD of the plurality of leads LD are exposed from the sealing body MR.

[0140] After the sealing body MR is formed, a portion of the thermosetting resin contained in the sealing body MR is heated until it hardens (referred to as temporary hardening). Once the lead frame LF becomes removable from the molded die due to this temporary hardening, the lead frame LF is removed from the molded die. Then, it is transported to a heating furnace for additional heat treatment (curing baking). As a result, the remaining thermosetting resin hardens and a sealing body MR is obtained.

[0141] <Single chip step>

[0142] Next, in Fig.13 In the singulation step shown, the structures formed in the device formation section LFd are separated and individualized. Fig.14 The tie bar TB and the tips of the outer lead portions OLD of the plurality of leads LD are shown. Figure 2 As shown in FIG. 1 , the shape of the outer lead portion OLD is formed. As a result, Figures 1 to 3 The semiconductor package PKG1 is shown.

[0143] In use Figures 13 to 16 In the method of manufacturing a semiconductor package described, any one or any combination of the first to fourth modified examples that have been explained can be applied.

[0144] <Modification Example of Manufacturing Method>

[0145] Next, we will explain how to use Figures 13 to 16A modified example of the method of manufacturing a semiconductor device described in the following. Except for the predetermined direction of ultrasonic vibration and the different divisions in the exposed portion of the electrode pad, the modified example described below is similar to the method of manufacturing a semiconductor device using Figures 13 to 16 Therefore, the differences from the aforementioned manufacturing method will be explained below.

[0146] Fig.17 is shown with Figure 4 An enlarged plan view of a related modified example. Fig.18 It is shown Fig.17 The semiconductor substrate of the semiconductor chip shown in FIG. Fig.17 An enlarged plan view of a portion of the enlarged planes shown overlapping. Fig.17 In FIG, the boundaries of regions R1, R2 and R3 are indicated by dotted lines. Fig.18 In FIG. 1 , the boundaries of regions R4, R5 and R6 are indicated by dotted lines. Fig.18 It is a plan view of a semiconductor substrate, but the outline of the electrode pad PD is illustrated using a dotted line.

[0147] Fig.17 The semiconductor chip CP1 shown is Figure 4 The semiconductor chip CP shown is different in the following points.

[0148] First, if Fig.17 As shown, the exposed portion PDE of the electrode pad PD includes a region R1 including the center of the opening portion PVk, a region R2 located outside the region R1, and a plurality of regions R3 located on both sides of the region R1 and between the region R1 and the region R2 in a plan view. Fig.17 The planar shape of the exposed portion of the electrode pad PD is a square, similar to Figure 4 The semiconductor chip CP is shown.

[0149] Each of the plurality of regions R3 is provided in a belt shape (strip shape) along the sides (sides Pks2 and Pks4 ) of the exposed portion of the electrode pad PD extending in the Y direction in a plan view.

[0150] In addition, if Fig.18 As shown, the upper surface SSt of the semiconductor substrate SS3 includes a plurality of regions R4 overlapping with any one of the plurality of regions R3 but not overlapping with each of the regions R1 and R2, and a region R5 overlapping with the region R1 or the region R2 but not overlapping with the plurality of regions R3.

[0151] The groove TR1 formed on the upper surface SSt of the semiconductor substrate SS3 includes at least one of a groove TRY extending in the Y direction and a groove TRX extending in the X direction intersecting the Y direction. Fig.18In the example shown, the groove TR1 includes both the grooves TRY and TRX. One of the grooves TRY and TRX is formed at the region R5 in the semiconductor substrate SS3. Fig.17 In the example shown, the groove TRX is formed at the region R5 in the semiconductor substrate SS3 .

[0152] The groove TRY is not formed at each of the plurality of regions R4 in the semiconductor substrate SS3, and the end portion of the groove TRX is not formed at each of the plurality of regions R4 in the semiconductor substrate SS3. Herein, the end portion of the groove TRX refers to a portion where the extension direction of the groove TRX changes. Fig.18 In the example shown, the groove TR1 has an annular shape. However, the grooves TRX and TRY, each forming the groove TR1, intersect with each other. Each of the four intersection points where the groove TRX and the groove TRY intersect with each other is an end portion of the groove TRX and is also an end portion of the groove TRY. Similar to using Fig.16 The example described is that in the wire bonding step of the method for manufacturing a semiconductor package of this modified example, while the spherical portion formed at the tip of the wire is in contact with the electrode pad PD, the ultrasonic wave USW vibrating in the X direction is applied.

[0153] If already used Figure 8 As explained, the groove TRB extends in the vibration direction of the ultrasonic wave USW, and the end portion of the groove TRB does not overlap with the outer edge of the spherical part BWb. In this case, although a part of the groove TRB overlaps with the outer edge of the spherical part BWb, the groove TRB is unlikely to cause cracks.

[0154] According to this finding, when the vibration direction of the ultrasonic wave USW can be defined, the region R4 (refer to Fig.18 ) area, which is a forbidden area for DTI placement. In other words, the area where DTI can be placed can be expanded. As a result, for semiconductor substrate SS3, Figure 7 Compared with the semiconductor substrate SS shown, the area ratio of the active region on the upper surface SSt can be improved.

[0155] In this modified example, Fig.18 As shown, Figure 7 Compared to the example shown, the grooves TR1 are placed at a higher density. However, since conditions that increase the frequency of crack occurrence are avoided, the occurrence of cracks can be suppressed.

[0156] In the case of this modified example, each groove in the plurality of grooves TR1 includes grooves TRX and TRY, but the length of the groove TRX is longer than the length of the groove TRY.

[0157] exist Fig.17 and Fig.18 In the case of applying ultrasonic wave USW vibrating in the X direction, it is explained that Fig.16 However, as a modified example, there may be a case where ultrasonic waves USW vibrating in the Y direction are applied.

[0158] Although not shown, in a modified example in which the vibration direction of the ultrasonic wave USW is along the Y direction, Fig.17 Each of the regions R1, R2 and R3 shown is arranged in a band extending in the X direction. Similarly, Fig.18 Each of the illustrated regions R4 , R5 , and R6 is arranged in a band extending in the direction X. Furthermore, in each of the plurality of regions R4 , the groove TRX is not formed, and the end portion of the groove TRY is not formed.

[0159] The invention made by the present inventors has been described in detail above based on the embodiments, but the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the gist thereof.

Claims

1. A semiconductor device, comprising: A semiconductor substrate having a first surface; a first insulating layer formed on the first surface of the semiconductor substrate; an electrode pad formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover a peripheral portion of the electrode pad; as well as A plurality of grooves are formed in the semiconductor substrate. The electrode pad comprises: an exposed portion exposed in the opening portion of the second insulating layer; and the peripheral portion, located around the exposed portion and covered by the second insulating layer, Wherein, in a plan view, the exposed portion of the electrode pad includes: A first region including a center of the opening portion; a second area located around the first area; and a third region, located around the first region and between the first region and the second region, wherein the planar shape of the exposed portion of the electrode pad is a square, wherein in a plan view, the third region is arranged in a ring shape along each side of the exposed portion of the electrode pad so that the planar shape of the third region is formed as a hollow square, wherein the plurality of grooves include a first groove that separates a plurality of semiconductor elements formed in the semiconductor substrate from each other, The semiconductor substrate comprises: a fourth area that overlaps with the third area but does not overlap with each of the first area and the second area, and a fifth region overlapping the first region but not overlapping the third region, and The first groove is formed at the fifth region in the semiconductor substrate instead of the fourth region. 2 . The semiconductor device according to claim 1 , wherein the first groove extends to a position deeper than each of the plurality of semiconductor elements with the first surface of the semiconductor substrate as a reference surface.

3. The semiconductor device according to claim 2, in, In a plan view, a boundary between the fourth region and the fifth region has four sides and four corners, wherein any two of the four sides intersect each other, and Wherein, on the first surface of the semiconductor substrate, a hole having an opening area smaller than an opening area of ​​the first groove is arranged between each of the four corners and the first groove.

4. The semiconductor device according to claim 2, in, In a plan view, a boundary between the fourth region and the fifth region has four sides and four corners, wherein any two of the four sides intersect each other, and Wherein, in a plan view, each of the four corners has an arc shape.

5. The semiconductor device according to claim 2, wherein: In the first groove, there is an insulating material layer covering an inner wall of the first groove and an air layer surrounded by the insulating material layer.

6. The semiconductor device according to claim 2, wherein: Taking the first surface of the semiconductor substrate as the reference surface, the plurality of grooves include a second groove that is shallower than the first groove.

7. The semiconductor device according to claim 2, wherein a wire having a spherical portion is bonded to the exposed portion of the electrode pad, and in, In a plan view, an outer edge of the spherical portion of the wire overlaps each of the third region and the fourth region.

8. A method for manufacturing a semiconductor device, comprising: (a) preparing a semiconductor chip having electrode pads; as well as (b) bonding a wire to the electrode pad of the semiconductor chip, The semiconductor chip comprises: A semiconductor substrate having a first surface; a first insulating layer formed on the first surface of the semiconductor substrate; an electrode pad formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover a peripheral portion of the electrode pad; and A plurality of grooves are formed in the semiconductor substrate. The electrode pad comprises: an exposed portion exposed in the opening portion of the second insulating layer; and the peripheral portion, located around the exposed portion and covered by the second insulating layer, Wherein, in a plan view, the exposed portion of the electrode pad includes: A first region including a center of the opening portion; a second area located around the first area; and a third region, located around the first region and between the first region and the second region, wherein the planar shape of the exposed portion of the electrode pad is a square, wherein in a plan view, the third region is arranged in a ring shape along each side of the exposed portion of the electrode pad so that the planar shape of the third region is formed as a hollow square, wherein the plurality of grooves include a first groove that separates a plurality of semiconductor elements formed in the semiconductor substrate from each other, The semiconductor substrate comprises: a fourth area that overlaps with the third area but does not overlap with each of the first area and the second area, and a fifth region overlapping the first region but not overlapping the third region, and wherein the first groove is formed at the fifth region in the semiconductor substrate instead of the fourth region, and Wherein, in (b), ultrasonic waves are applied while a spherical portion formed at the tip of the wire is in contact with the electrode pad.

9. The method according to claim 8, wherein: In (b), the wire is bonded to the electrode pad so that an outer edge of the spherical portion overlaps each of the third region and the fourth region in a plan view.

10. The method according to claim 8, wherein the first groove extends to a position deeper than each of the plurality of semiconductor elements, taking the first surface of the semiconductor substrate as a reference surface.

11. The method according to claim 10, in, In a plan view, a boundary between the fourth region and the fifth region has four sides and four corners, wherein any two of the four sides intersect each other, and Wherein, on the first surface of the semiconductor substrate, a hole having an opening area smaller than an opening area of ​​the first groove is arranged between each of the four corners and the first groove.

12. The method according to claim 10, in, In a plan view, a boundary between the fourth region and the fifth region has four sides and four corners, wherein any two of the four sides intersect each other, and Wherein, in a plan view, each of the four corners has an arc shape.

13. The method according to claim 10, wherein: In the first groove, there is an insulating material layer covering an inner wall of the first groove and an air layer surrounded by the insulating material layer.

14. The method according to claim 10, wherein: Taking the first surface of the semiconductor substrate as the reference surface, the plurality of grooves include a second groove that is shallower than the first groove.

15. A method for manufacturing a semiconductor device, comprising: (a) preparing a semiconductor chip having electrode pads; as well as (b) bonding a wire to the electrode pad of the semiconductor chip, The semiconductor chip comprises: A semiconductor substrate having a first surface; a first insulating layer formed on the first surface of the semiconductor substrate; an electrode pad formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover a peripheral portion of the electrode pad; and A plurality of grooves are formed in the semiconductor substrate. The electrode pad comprises: an exposed portion exposed in the opening portion of the second insulating layer; and the peripheral portion, located around the exposed portion and covered by the second insulating layer, Wherein, in a plan view, the exposed portion of the electrode pad includes: A first region including a center of the opening portion; a second region located outside the first region; and a plurality of third regions located on both sides of the first region and between the first region and the second region, wherein the planar shape of the exposed portion of the electrode pad is a square, wherein, in a plan view, the plurality of third regions are arranged in a strip shape along a side extending in a first direction among sides of the exposed portion of the electrode pad, wherein the plurality of grooves include a first groove that separates a plurality of semiconductor elements formed in the semiconductor substrate from each other, The semiconductor substrate comprises: a plurality of fourth regions overlapping with any third region of the plurality of third regions but not overlapping with each of the first region and the second region, and a fifth area, overlapping with the first area but not overlapping with the plurality of third areas, The first groove includes at least one of the following: a first direction groove extending in the first direction; and a second direction groove extending in a second direction intersecting the first direction, wherein one of the first direction groove and the second direction groove is formed in the fifth region, and Wherein, in (b), ultrasonic waves are applied in the second direction while a spherical portion formed at the tip of the wire is in contact with the electrode pad.

16. The method according to claim 15, wherein: In (b), the wire is bonded to the electrode pad so that an outer edge of the spherical portion overlaps each of the plurality of third regions and the plurality of fourth regions in a plan view.

17. The method according to claim 16, wherein, with the first surface of the semiconductor substrate as a reference surface, the first groove extends to a position deeper than each of the plurality of semiconductor elements.

18. The method according to claim 16, wherein: In the first groove, there is an insulating material layer covering an inner wall of the first groove and an air layer surrounded by the insulating material layer.

19. The method according to claim 16, wherein: Taking the first surface of the semiconductor substrate as a reference surface, the plurality of grooves include a second groove that is shallower than the first groove.

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