Broadband high-isolation on-chip small-size power divider applied to 5G

Abstract

The invention discloses a broadband high-isolation on-chip small-size power divider applied to 5G, and the power divider comprises two branches, and the first branch and the second branch are respectively provided with a series capacitor, an on-chip grounding spiral inductor, a transmission line, an isolation capacitor, an isolation inductor and an isolation resistor. The isolation capacitor, the isolation inductor and the isolation resistor are electrically connected between the first branch circuit and the second branch circuit, and the transmission line is less than a quarter wavelength. The spiral inductors on the ground lugs connected in parallel are used for improving even mode matching of the power divider, and the isolation capacitors and the isolation resistors are used for improving odd mode matching of the power divider. By adopting the transmission line with the wavelength smaller than 1 / 4, the power divider provided by the invention effectively reduces the circuit size and can realize two-path power synthesis. The technical problem that a power divider in the prior art is difficult to adapt to the high integration level of a 5G radio frequency system can be solved, and the provided power divider also has the characteristics of wide band and high isolation.

Description

Technical Field

[0001] The present invention relates to the technical field of a broadband, high-isolation, on-chip, small-size power divider for 5G applications. Background Art

[0002] In 5G wireless communication systems, millimeter wave technology, which is widely used in high-frequency bands, places higher demands on the performance of power dividers. In particular, broadband and high-isolation on-chip power dividers have become key components for realizing high-efficiency 5G base stations and terminal devices due to their effectiveness in signal distribution and power transmission. Traditional power dividers often face problems such as limited bandwidth, insufficient isolation, and large size, which is particularly prominent under the conditions of high data rates and low latency that 5G technology increasingly emphasizes. Summary of the invention

[0003] Purpose of the invention:

[0004] The present invention proposes an on-chip small-size power divider with broadband and high isolation characteristics, aiming to effectively address the technical challenges faced by existing 5G technologies, such as limited bandwidth, insufficient isolation, and large size, so as to meet the requirements of the increasing development trend of radio frequency systems towards high integration.

[0005] Technical solution:

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A broadband, high-isolation, on-chip, small-size power divider for 5G applications:

[0008] It includes a signal input port IN1, a first signal output port OUT2, a second signal output port OUT3, a first branch and a second branch; one end of the first branch is connected to the input port IN1, and the other end is connected to the first signal output port OUT2; one end of the second branch is connected to the input port IN1, and the other end is connected to the second signal output port OUT3, and the first branch and the second branch are respectively provided with an input capacitor, a π-type network and an output capacitor; an isolation capacitor, an isolation inductor, and an isolation resistor are connected between the first branch and the second branch.

[0009] Furthermore, the transmission lines of the first branch and the second branch are transmission lines with a length less than a quarter of a wavelength.

[0010] Further, the input capacitor of the first branch is capacitor C1, the π-type network of the first branch includes spiral inductor L1, spiral inductor L2 and capacitor C2, and the output capacitor of the first branch is capacitor C3; the first end of capacitor C2 is electrically connected to the signal input port IN1; the first end of the spiral inductor L1 is electrically connected to the second end of capacitor C1, and the second end of spiral inductor L1 is connected to the ground; the first end of capacitor C2 is electrically connected to the second end of the first capacitor C1 and the first end of spiral inductor L1; the first end of spiral inductor L2 is electrically connected to the second end of capacitor C2, and the second end of spiral inductor L2 is grounded; the first end of capacitor C3 is electrically connected to the second end of capacitor C2 and the first end of spiral inductor L2; the first signal output port OUT2 is electrically connected to the second end of capacitor C3.

[0011] Further, the input capacitor of the second branch is capacitor C4, the π-type network of the second branch includes spiral inductor L3, spiral inductor L4 and capacitor C5, and the output capacitor of the second branch is capacitor C6; the first end of capacitor C4 is electrically connected to the signal input port IN1; the first end of the spiral inductor L3 is electrically connected to the second end of the first capacitor C4, and the second end of the spiral inductor L3 is connected to the ground; the first end of capacitor C5 is electrically connected to the second end of capacitor C4 and the first end of spiral inductor L3; the first end of spiral inductor L4 is electrically connected to the second end of capacitor C5, and the second end of spiral inductor L4 is grounded; the first end of capacitor C6 is electrically connected to the second end of capacitor C5 and the first port of spiral inductor L4, and the second signal output port OUT3 is electrically connected to the second end of capacitor C6.

[0012] Furthermore, the isolation capacitor connected between the first branch and the second branch is an isolation capacitor C7, a first end of the isolation capacitor C7 is connected to the second end of the capacitor C2, and a second end of the isolation capacitor C7 is electrically connected to the second end of the capacitor C5.

[0013] Furthermore, the isolation resistor connected between the first branch and the second branch is an isolation resistor R1, and the isolation inductor includes an isolation inductor L5 and an isolation inductor L6, the first end of the isolation inductor L5 is electrically connected to the second end of the capacitor C3; the first end of the isolation inductor L6 is electrically connected to the second end of the capacitor C6; the first end of the isolation resistor R1 is electrically connected to the second end of the isolation inductor L5; and the second end of the isolation resistor R1 is electrically connected to the second end of the isolation inductor L6.

[0014] In the technical solution disclosed in the present invention, compared with the traditional power divider, the technical solution of the present application adopts a parallel-connected on-chip spiral inductor, the main purpose of which is to enhance the even-mode matching of the power divider; and the isolation capacitor and isolation resistor are used to improve the odd-mode matching performance of the power divider. Through this design, the power divider can have wide-band characteristics while meeting high isolation requirements. By adopting a transmission line less than a quarter wavelength, the proposed power divider effectively reduces the circuit size and can realize two-way power synthesis. The technical solution provided by the present invention can solve the technical problem that the power divider in the prior art is difficult to adapt to the high integration of the 5G radio frequency system, and the proposed power divider also has broadband and high isolation characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a circuit schematic diagram of a broadband, high-isolation, small-size on-chip power divider of the present invention;

[0016] Figure 2 It is a simulation diagram of reflection coefficients of input port and output port of the broadband high isolation on-chip small size power divider of the present invention;

[0017] Figure 3 This is a simulation diagram of the insertion loss of the broadband high isolation on-chip small-size power divider of the present invention;

[0018] Figure 4 This is a simulation diagram of the isolation of the broadband high-isolation on-chip small-size power divider of the present invention. DETAILED DESCRIPTION

[0019] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0020] like Figure 1 As shown, the present invention relates to a broadband, high-isolation, on-chip, small-size power divider, which mainly consists of a first branch and a second branch. Each branch is respectively configured with a series capacitor, an on-chip grounded spiral inductor, a transmission line, an isolation capacitor, an isolation inductor and an isolation resistor. Among them, the isolation capacitor and the isolation resistor are placed between branch one and branch two of the output port by electrical connection. The selected transmission line length is less than a quarter wavelength. In addition, the on-chip spiral inductor connected in parallel to the ground is used to improve the even-mode matching performance of the power divider, while the isolation capacitor and the isolation resistor are used to improve the odd-mode matching characteristics of the power divider. Through the above design, the power divider not only meets the requirements of high isolation, but also obtains wide-band characteristics.

[0021] In Example 1, Figure 1As shown, when the power distribution ratio is 1:2, this embodiment is a two-equal power divider, including a signal input port IN1 and a first signal output port OUT2 and a second signal output port OUT3. Two branches are separated from the signal input port IN1. The two branches are first connected in series with capacitors C1 and C4, and then two grounded spiral inductors L1 and L3 are connected in parallel, respectively. Then, capacitors C2 and C5 are connected in series, and then two grounded spiral inductors L2 and L4 are connected in parallel, and then capacitors C3 and C6 are connected in series. Finally, the isolation inductor L5, the isolation inductor L6 and the isolation resistor R1 are connected in series and bridged between the two branches of the output port, so that the first signal output port OUT2 and the second output port OUT3 each obtain half of the input power of the input port IN1.

[0022] In this embodiment, a broadband, high-isolation, small-size on-chip power divider is provided, which mainly comprises a first branch and a second branch, wherein the first branch and the second branch are respectively composed of an input capacitor, a π-type network and an output capacitor. The main function of these three parts is to achieve impedance matching of the two signals to ensure the maximum power transmission and minimum reflection loss of the signal. In addition, two-stage isolation is adopted between branch one and branch two, respectively, and the first-stage isolation is mainly realized by the isolation capacitor C7; the second-stage isolation is realized by a series network of inductors and resistors, mainly by a series network of isolation inductors L5, isolation inductors L6 and isolation resistors R1. In this embodiment, grounded spiral inductors L1, L2, L3 and L4 are used to effectively suppress parasitic inductance and reduce grounding requirements. This design has shown significant application potential in radar systems and satellite communication systems.

[0023] The present application also experiments with a small-size on-chip power divider with broadband and high isolation, such as Figure 2 , Figure 3 as well as Figure 4 shown. Figure 2 The figure shows the simulation result of the return loss of the input and output ports of the on-chip small-size power divider with broadband high isolation. The results show that the input and output matching of the power divider in the embodiment reaches a relatively good value, and the input and output return losses are better than -17.2dB in the frequency range of 20~30GHz; Figure 3 The insertion loss simulation result diagram of the broadband high-isolation on-chip small-size power divider in this embodiment is shown in the figure. It can be seen from the figure that due to the use of a thicker metal layer to implement the on-chip spiral inductor in the power divider, the insertion loss is low. In the frequency range of 20~30GHz, the insertion loss of a single-ended signal to a double-ended signal is better than 3.7dB; Figure 4The simulation result diagram of the isolation between the output ports (OUT2 and OUT3) of the broadband high-isolation on-chip small-size power divider in this embodiment is shown. Since the output port adopts the structure of the isolation inductor L5, the isolation inductor L6 and the isolation resistor R1 in series, there is a better isolation between the ports. The isolation between the output ports is greater than 26.4dB within 23-27GHz. Compared with other broadband power divider structures, the structure proposed by the present invention has a wider bandwidth and higher isolation.

[0024] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A broadband high-isolation on-chip small-size power divider for 5G, characterized by: The invention comprises a signal input port (IN1), a first signal output port (OUT2), a second signal output port (OUT3), a first branch and a second branch; one end of the first branch is connected to the input port (IN1), and the other end is connected to the first signal output port (OUT2); one end of the second branch is connected to the input port (IN1), and the other end is connected to the second signal output port (OUT3); the first branch and the second branch are respectively provided with an input capacitor, a π-type network and an output capacitor; an isolation capacitor, an isolation inductor and an isolation resistor are connected between the first branch and the second branch.

2. According to the small-size on-chip power divider for 5G broadband high-isolation according to claim 1, the transmission lines of the first branch and the second branch are transmission lines with a length less than a quarter of the wavelength.

3. The on-chip small-size power divider for 5G broadband high isolation according to claim 1 is characterized in that: The input capacitor of the first branch is a capacitor (C1), the π-type network of the first branch includes a spiral inductor (L1), a spiral inductor (L2) and a capacitor (C2), and the output capacitor of the first branch is a capacitor (C3); the first end of the capacitor (C2) is electrically connected to the signal input port (IN1); the first end of the spiral inductor (L1) is electrically connected to the second end of the capacitor (C1), and the second end of the spiral inductor (L1) is connected to the ground; the first end of the capacitor (C2) is electrically connected to the second end of the first capacitor (C1) and the first end of the spiral inductor (L1); the first end of the spiral inductor (L2) is electrically connected to the second end of the capacitor (C2), and the second end of the spiral inductor (L2) is grounded; the first end of the capacitor (C3) is electrically connected to the second end of the capacitor (C2) and the first end of the spiral inductor (L2); and the first signal output port (OUT2) is electrically connected to the second end of the capacitor (C3).

4. The on-chip small-size power divider for 5G broadband high isolation according to claim 3 is characterized in that: The input capacitor of the second branch is a capacitor (C4), the π-type network of the second branch includes a spiral inductor (L3), a spiral inductor (L4) and a capacitor (C5), and the output capacitor of the second branch is a capacitor (C6); the first end of the capacitor (C4) is electrically connected to the signal input port (IN1); the first end of the spiral inductor (L3) is electrically connected to the second end of the first capacitor (C4), and the second end of the spiral inductor (L3) is connected to the ground; the first end of the capacitor (C5) is electrically connected to the second end of the capacitor (C4) and the first end of the spiral inductor (L3); the first end of the spiral inductor (L4) is electrically connected to the second end of the capacitor (C5), and the second end of the spiral inductor (L4) is grounded; the first end of the capacitor (C6) is electrically connected to the second end of the capacitor (C5) and the first port of the spiral inductor (L4), and the second signal output port (OUT3) is electrically connected to the second end of the capacitor (C6).

5. The on-chip small-size power divider for 5G broadband high isolation according to claim 4 is characterized in that: The isolation capacitor connected between the first branch and the second branch is an isolation capacitor (C7), the first end of the isolation capacitor (C7) is connected to the second end of the capacitor (C2), and the second end of the isolation capacitor (C7) is electrically connected to the second end of the capacitor (C5).

6. The on-chip small-size power divider for 5G broadband high isolation according to claim 4 is characterized in that: The isolation resistor connected between the first branch and the second branch is an isolation resistor (R1), and the isolation inductor comprises an isolation inductor (L5) and an isolation inductor (L6), wherein the first end of the isolation inductor (L5) is electrically connected to the second end of the capacitor (C3); the first end of the isolation inductor (L6) is electrically connected to the second end of the capacitor (C6); the first end of the isolation resistor (R1) is electrically connected to the second end of the isolation inductor (L5); and the second end of the isolation resistor (R1) is electrically connected to the second end of the isolation inductor (L6).

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