Printed circuit board

Abstract

The invention provides a printed circuit board, and relates to the technical field of semiconductors. The printed circuit board includes: a first power supply layer; a first dielectric layer; the first ground layer is isolated from the first power supply layer through the first dielectric layer; the first via hole pair penetrates through the first dielectric layer, the first via hole pair comprises a first ground hole and a first power supply hole which are arranged along a first direction, the first ground hole is isolated from the first power supply layer and connected with the first ground layer, the first power supply hole is connected with the first power supply layer and isolated from the first ground layer, and the first via hole pair is arranged along the first direction; wherein on the cross section, parallel to the first power supply layer, of the printed circuit board, the adjacent first via hole pairs in the first direction are in mirror symmetry. According to the embodiment of the invention, the electromagnetic compatibility of the printed circuit board can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a printed circuit board. Background Art

[0002] With the rapid development of high-performance computing applications such as artificial intelligence (AI), and the development of electronic devices towards higher frequencies, higher densities, and more complex functions, electromagnetic compatibility (EMC) issues on printed circuit boards (PCBs), especially electromagnetic shielding (EMI Shielding), have become an important topic in the design and manufacturing process.

[0003] In order to improve the electromagnetic compatibility (EMC) characteristics of a printed circuit board (PCB), the prior art often adds a ground ring around the printed circuit board (PCB) and adds a series of ground holes on the ground ring, or uses power holes on the power plane. The above methods reduce the impact of electromagnetic shielding (EMI Shielding) to a certain extent, but in actual applications, due to the existence of ground holes and loop ground currents, the printed circuit board (PCB) will still suffer from greater common-mode and differential-mode interference.

[0004] Therefore, there is an urgent need for a technical solution to effectively improve the electromagnetic compatibility of printed circuit boards to meet the needs of high-performance computing for higher frequencies, higher densities, and more complex functions.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The present disclosure provides a printed circuit board, which can effectively improve the electromagnetic compatibility of the printed circuit board.

[0007] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0008] According to one aspect of the present disclosure, a printed circuit board is provided.

[0009] include:

[0010] First power layer;

[0011] a first dielectric layer;

[0012] A first ground layer, the first ground layer is isolated from the first power layer by a first dielectric layer;

[0013] A first via pair, the first via pair penetrates the first dielectric layer, the first via pair comprises a first ground hole and a first power hole arranged along a first direction, the first ground hole is isolated from the first power layer and connected to the first ground layer, the first power hole is connected to the first power layer and isolated from the first ground layer, and the first via pair is arranged along the first direction;

[0014] In the cross section of the printed circuit board parallel to the first power supply layer, the first via holes adjacent to each other in the first direction are mirror-symmetrical.

[0015] In one embodiment, on a cross section of the printed circuit board parallel to the first power layer, the first via pair in the first direction is mirror-symmetric with the center line of the cross section as the center line.

[0016] In one embodiment, the intervals between adjacent first via holes in the first direction are the same.

[0017] In one embodiment, the spacing between adjacent first via hole pairs in the first direction is greater than the spacing between the first ground holes and the first power holes in the first via hole pairs in the first direction.

[0018] In one embodiment, the first ground hole and the first power hole have the same shape and substantially the same size.

[0019] In one embodiment, the printed circuit board also includes a second via pair, the second via pair passes through the first dielectric layer, the second via pair includes a second ground hole and a second power hole arranged along the second direction, the second ground hole is isolated from the first power layer and connected to the first ground layer, the second power hole is connected to the first power layer and isolated from the first ground layer, and the second via pair is arranged along the second direction; the first direction intersects with the second direction; wherein, on a cross section of the printed circuit board parallel to the first power layer, the adjacent second via pairs in the second direction are mirror-symmetric.

[0020] In one embodiment, on a cross section of the printed circuit board parallel to the first power layer, the second via pair in the second direction is mirror-symmetric with the center line of the cross section as the center line.

[0021] In one embodiment, the intervals between adjacent second via holes in the second direction are the same.

[0022] In one embodiment, the spacing between adjacent second via holes in the second direction is greater than the spacing between the second ground holes and the second power holes in the second via holes in the second direction.

[0023] In one embodiment, one end of the first power hole is connected to the first power layer, and the other end is connected to the first power hole pad; and / or one end of the second power hole is connected to the first power layer, and the other end is connected to the second power hole pad.

[0024] In one embodiment, the printed circuit board further includes a first shielding layer, which surrounds the first power layer and is located on the same plane as the first power layer. The first shielding layer electrically isolates the first power layer and has a first recess.

[0025] In one embodiment, one end of the first ground hole is connected to the first shielding layer, and the other end is connected to the first ground layer; the orthographic projection of the first power hole on the first dielectric layer partially overlaps with the orthographic projection of the first recess on the first dielectric layer.

[0026] In one embodiment, one end of the second ground hole is connected to the first shielding layer, and the other end is connected to the first ground layer; the orthographic projection of the second power hole on the first dielectric layer partially overlaps with the orthographic projection of the first recess on the first dielectric layer.

[0027] In one embodiment, the printed circuit board also includes a second power layer; a second dielectric layer; a second ground layer, the second ground layer is isolated from the second power layer by the second dielectric layer; a third via pair, the third via pair passes through the second dielectric layer, the third via pair includes a third ground hole and a third power hole arranged along the first direction, the third ground hole is isolated from the second power layer and connected to the second ground layer, the third power hole is connected to the second power layer and isolated from the second ground layer, and the third via pair is arranged along the first direction; wherein, on a cross section of the printed circuit board perpendicular to the first power layer, the first via pair is centrally symmetrical with the third via pair.

[0028] In one embodiment, on a cross section of the printed circuit board parallel to the second power layer, the third via pair in the first direction is mirror-symmetric with the center line of the cross section as the center line.

[0029] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0031] Figure 1 A schematic cross-sectional view of a printed circuit board provided by an embodiment of the present disclosure and parallel to a first power supply layer is shown;

[0032] Figure 2 The printed circuit board provided by the embodiment of the present disclosure is Figure 1 Schematic diagram of the cross section along the aa direction;

[0033] Figure 3The printed circuit board provided by the embodiment of the present disclosure is Figure 1 Schematic diagram of the cross section along the bb direction;

[0034] Figure 4 A schematic cross-sectional view of a printed circuit board parallel to a first power supply layer provided by another embodiment of the present disclosure is shown;

[0035] Figure 5 A printed circuit board provided by another embodiment of the present disclosure Figure 4 Schematic diagram of the cross section in the cc direction;

[0036] Figure 6 A printed circuit board provided by another embodiment of the present disclosure Figure 4 Schematic diagram of the cross section along the dd direction;

[0037] Figure 7 A schematic cross-sectional view of a printed circuit board parallel to a first power supply layer provided by another embodiment of the present disclosure is shown;

[0038] Figure 8 A printed circuit board provided by another embodiment of the present disclosure Figure 7 Schematic diagram of the cross section in the ee direction;

[0039] Fig. 9 A printed circuit board provided by another embodiment of the present disclosure Figure 7 Schematic diagram of the cross section along the ff direction;

[0040] Fig.10 A schematic cross-sectional view of a printed circuit board parallel to a first power supply layer provided by another embodiment of the present disclosure is shown;

[0041] Fig.11 A schematic cross-sectional view of a printed circuit board parallel to a second power supply layer provided by another embodiment of the present disclosure is shown;

[0042] Fig.12 A printed circuit board provided by another embodiment of the present disclosure Fig.11 Schematic diagram of the cross section along the aa direction.

[0043] Fig.13 A schematic cross-sectional view of a printed circuit board parallel to a second power supply layer provided by another embodiment of the present disclosure is shown; DETAILED DESCRIPTION

[0044] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0045] With the rapid development of high-performance computing, such as artificial intelligence (AI), electronic devices are moving towards higher frequencies, higher densities, and more complex functions. This often means that electronic devices require higher signal frequencies and denser circuit layouts. Electromagnetic compatibility (EMC) issues on printed circuit boards (PCBs), especially electromagnetic shielding (EMI Shielding), have indeed become an important topic in the design and manufacturing process.

[0046] In order to improve the electromagnetic compatibility (EMC) of the printed circuit board, the existing technology adds a ground ring around the printed circuit board and adds a series of ground vias (Ground Vias) on the ground ring to form a continuous low-impedance path, which helps to absorb and guide the electromagnetic energy generated inside the package and reduce its interference with the external environment of the package. At the same time, in order to reduce the inductance of the power delivery network (PDN), the existing technology can reduce the area of ​​the power loop by reducing the distance between the power via and the ground via, thereby reducing the inductance.

[0047] However, in practical applications, due to the presence of ground holes and loop ground currents, for example, ground holes are vias used to connect different layers of ground planes in printed circuit boards. They will exhibit antenna effects under high-frequency signals, generate unnecessary radiation, and thus become the source of EMI. In addition, the current loop around the ground hole will also generate a magnetic field, further increasing EMI. In addition, the current loop between the power supply and the ground line will generate an electromagnetic field, especially at high frequencies, and this loop current will become the main source of EMI. The loop ground current will not only increase the radiation of the printed circuit board, but also interfere with other signal lines through mutual inductance and capacitive coupling, reducing signal integrity. Therefore, the printed circuit board will still suffer from large common-mode and differential-mode interference. Among them, common-mode interference refers to interference signals that appear simultaneously on the signal line and the reference ground line (usually the ground line), while differential-mode interference refers to interference signals between signal lines or between signal lines and reference ground lines.

[0048] In view of this, an embodiment of the present disclosure provides a printed circuit board, which can effectively improve the electromagnetic compatibility of the printed circuit board by setting a first via pair, that is, a first power hole and a first ground hole set along a first direction are arranged in pairs, and the adjacent first via pairs in the first direction are mirror-symmetrical.

[0049] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] Figure 1 A schematic cross-sectional view of a printed circuit board provided by an embodiment of the present disclosure and parallel to a first power supply layer is shown; Figure 2 The printed circuit board provided by the embodiment of the present disclosure is Figure 1 Schematic diagram of the cross section along the aa direction; Figure 3 The printed circuit board provided by the embodiment of the present disclosure is Figure 1 Schematic diagram of the cross section along the bb direction;

[0051] Reference Figure 1 As shown, in one embodiment, a printed circuit board 100,

[0052] include:

[0053] A first power supply layer 110;

[0054] A first dielectric layer 120;

[0055] A first ground layer 130 , wherein the first ground layer 130 is isolated from the first power layer 110 by a first dielectric layer 120 ;

[0056] A first via pair 140, the first via pair 140 penetrates the first dielectric layer 120, the first via pair 140 comprises a first ground hole 141 and a first power hole 142 arranged along the first direction X, the first ground hole 141 is isolated from the first power layer 110 and connected to the first ground layer 130, the first power hole 142 is connected to the first power layer 110 and isolated from the first ground layer 130, and the first via pair 140 is arranged along the first direction X;

[0057] In the cross section of the printed circuit board 100 parallel to the first power layer 110 , the first via pairs 140 adjacent to each other in the first direction X are mirror-symmetrical.

[0058] Reference Figure 1-Figure 3 , the printed circuit board 100 is described in detail.

[0059] The first power layer 110 is a layer for providing stable power in the printed circuit board 100. The power layer is usually designed as a large-area metal layer, which can be copper, to ensure stable power supply in the circuit and reduce voltage drop and power noise.

[0060] The first dielectric layer 120 is an insulating material layer used to isolate different metal layers in the printed circuit board 100. It is usually made of dielectric materials, such as epoxy resin, polytetrafluoroethylene (PTFE), etc. These materials have good insulation properties and low dielectric constants, which help reduce losses and crosstalk during signal transmission.

[0061] The first ground layer 130 is a layer used to provide a reference ground for the circuit in the printed circuit board 100, and is also a layer used to absorb and dissipate electromagnetic energy. The ground layer is also designed as a large-area metal layer, which can be copper, to form a low-impedance path and reduce electromagnetic interference (EMI).

[0062] The first via pair 140 is used in the printed circuit board 100 to connect a combination of two or more vias in different layers. The first ground via 141 is a via in the first via pair 140, and is used to connect the first ground layer 130. The first ground via 141 is isolated from the first power layer 110, that is, the first ground via 141 does not directly contact the first power layer 110, but is connected to the first ground layer 130 to form a low impedance path for the flow of ground current. The first power via 142 is another via in the first via pair 140, and is used to connect the first power layer 110. The first power via 142 is connected to the first power layer 110 and isolated from the first ground layer 130, and is used to provide a stable power supply and reduce voltage drop and power noise in the power network. In addition, the first ground hole 141 and the first power hole 142 in the same via pair are arranged along the first direction X. At the same time, different via pairs 140 are also arranged along the first direction X, wherein the X direction is parallel to the short side direction of the printed circuit board, and can also be parallel to the long side direction of the printed circuit board. In this way, by optimizing the arrangement of the vias in the via pair and the arrangement between the via pairs, more effective electromagnetic shielding can be achieved, the radiation capability of the printed circuit board 100 can be reduced, and its anti-interference characteristics to the external environment can be enhanced.

[0063] Among them, on the cross section of the printed circuit board 100 parallel to the first power layer 110, the adjacent first via pairs 140 in the first direction X are mirror-symmetrical. That is to say, when the adjacent first via pairs 140 are arranged in a mirror-symmetrical manner, the electromagnetic radiation they generate will cancel each other out in the far field. This is because the radiation fields generated by the symmetrical power holes and ground holes have opposite phases, thereby forming destructive interference in space and reducing the overall radiation level. Similarly, when the adjacent first via pairs 140 are arranged in a mirror-symmetrical manner, their anti-interference ability to the external environment is also enhanced.

[0064] The disclosed embodiment arranges a first via pair, that is, a first power hole and a first ground hole arranged in a first direction are arranged in pairs, and the adjacent first via pairs in the first direction are mirror-symmetrical. In this way, the radiation fields generated by the symmetrical power hole and ground hole pairs have opposite phases, thereby forming destructive interference in space, reducing the overall radiation level, and thus effectively improving the electromagnetic compatibility of the printed circuit board.

[0065] In one embodiment, referring to Figure 1-Figure 3 In the cross section of the printed circuit board 100 parallel to the first power layer 110, the first via pair 140 in the first direction X is mirror-symmetric with the center line 111 of the cross section as the center line. In other words, the first via pair 140 is mirror-symmetric with respect to the center line 111 of the cross section, thus forming a balanced layout, thereby ensuring uniform current distribution between the power supply and the ground line, reducing loop current, and thus reducing electromagnetic radiation.

[0066] In one embodiment, referring to Figure 1-Figure 3 , the spacing between adjacent first via pairs 140 in the first direction X is the same. Keeping the spacing between adjacent first via pairs 140 the same can ensure that the current distribution between the power supply and the ground line is more uniform, reduce the local peak value of the current density, thereby reducing electromagnetic radiation, and also help to reduce the crosstalk between signal lines and improve signal integrity. In addition, the layout of via pairs with equal spacing helps to form a consistent electromagnetic environment, reduce the electromagnetic radiation of the package, and enhance its anti-interference ability to the external environment. It also helps to optimize the layout of signal lines, reduce crosstalk between signal lines, and improve signal integrity.

[0067] In one embodiment, referring to Figure 1-Figure 3 , the spacing between adjacent first via pairs 140 in the first direction X is greater than the spacing between the first ground holes 141 and the first power holes 142 in the first via pairs 140 in the first direction X. By increasing the spacing between adjacent first via pairs 140, the electromagnetic coupling between adjacent first via pairs 140 can be reduced, thereby reducing the electromagnetic radiation of the package and the crosstalk between signal lines. At the same time, keeping the spacing between the first ground holes 141 and the first power holes 142 in the first via pairs 140 small can ensure a close connection between the power supply and the ground line, reduce the inductance of the power supply network, improve the power supply efficiency, and reduce the crosstalk between signal lines, thereby improving the integrity of the signal.

[0068] In one embodiment, referring to Figure 1-Figure 3, the first ground hole 141 and the first power hole 142 have the same shape and are basically the same in size. The shapes of the first ground hole 141 and the first power hole 142 can be various in the design of the printed circuit board (PCB). Common via shapes include: round, round vias are easy to manufacture and can achieve good electrical performance in most printed circuit board (PCB) manufacturing processes; square or rectangular, square or rectangular vias may be more conducive to signal integrity in some cases, especially when a larger area connection or a higher density layout is required. However, the edges of square or rectangular vias may cause higher edge field effects, thereby increasing the risk of radiation and signal reflection; elliptical, elliptical vias combine the advantages of circular and square vias, can provide a larger connection area, and reduce the edge field effect. Basically the same size means that, if it is a circular via, its diameter is basically the same, if it is a rectangular or square via, its side length is basically the same, and if it is an elliptical via, its major axis and minor axis are basically the same. The consistency of the shape and size of the first ground hole 141 and the first power hole 142 helps to form a consistent electromagnetic environment, reduce the electromagnetic radiation of the package, and enhance its anti-interference ability to the external environment.

[0069] Figure 4 A schematic cross-sectional view of a printed circuit board parallel to a first power supply layer provided by another embodiment of the present disclosure is shown; Figure 5 A printed circuit board provided by another embodiment of the present disclosure Figure 4 Schematic diagram of the cross section in the cc direction; Figure 6 A printed circuit board provided by another embodiment of the present disclosure Figure 4 Schematic diagram of the cross section along the dd direction;

[0070] In one embodiment, referring to Figure 4-Figure 6The printed circuit board 100 further includes a second via pair 150, the second via pair 150 penetrates the first dielectric layer 120, the second via pair 150 includes a second ground hole 151 and a second power hole 152 arranged along the second direction Y, the second ground hole 151 is isolated from the first power layer 110 and connected to the first ground layer 130, the second power hole 152 is connected to the first power layer 110 and isolated from the first ground layer 130, and the second via pair 150 is arranged along the second direction Y; the first direction X intersects with the second direction Y; wherein, on the cross section of the printed circuit board 100 parallel to the first power layer 110, the second via pairs 150 adjacent to each other in the second direction Y are mirror-symmetrical. The second ground hole 151 is a via in the second via pair 150, and is used to connect the first ground layer 130. The second ground hole 151 is isolated from the first power layer 110, that is, the second ground hole 151 does not directly contact the first power layer 110, but is connected to the first ground layer 130 to form a low impedance path for the flow of ground current. The second power hole 152 is another via in the second via pair 150, and is used to connect the first power layer 110. The second power hole 152 is connected to the first power layer 110 and isolated from the first ground layer 130, and is used to provide a stable power supply and reduce the voltage drop and power noise in the power network. In addition, the second ground holes 151 and the second power holes 152 in the same via pair are arranged along the second direction Y. At the same time, different via pairs 150 are also arranged along the first direction Y, wherein the Y direction intersects with the X direction, such as being perpendicular, that is, the Y direction is parallel to the short side direction of the printed circuit board, and can also be parallel to the long side direction of the printed circuit board. In this way, by optimizing the arrangement of the vias in the via pair and the arrangement between the via pairs, more effective electromagnetic shielding can be achieved, the radiation capability of the printed circuit board 100 can be reduced, and its anti-interference characteristics to the external environment can be enhanced. Further, on the cross section of the printed circuit board 100 parallel to the first power layer 110, the second via pairs 150 adjacent in the second direction Y are mirror-symmetrical. That is, when the adjacent second via pairs 150 are arranged in a mirror-symmetrical manner, the electromagnetic radiation they generate will cancel each other out in the far field. This is because the radiation fields generated by the symmetrical power holes and ground holes have opposite phases, thus forming destructive interference in space and reducing the overall radiation level. Similarly, when the adjacent second via pairs 150 are arranged in a mirror-symmetrical manner, their anti-interference ability to the external environment is also enhanced.

[0071] In one embodiment, referring to Figure 4-Figure 6 In the cross section of the printed circuit board 100 parallel to the first power layer 110, the second via pair 150 in the second direction Y is mirror-symmetric with the center line 112 of the cross section as the center line. In other words, the second via pair 150 is mirror-symmetric with respect to the center line 112 of the cross section, thus forming a balanced layout, thereby ensuring uniform current distribution between the power supply and the ground line, reducing loop current, and thus reducing electromagnetic radiation.

[0072] In one embodiment, referring to Figure 4-Figure 6 , the spacing between adjacent second via pairs 150 in the second direction Y is the same. Keeping the spacing between adjacent second via pairs 150 the same can ensure that the current distribution between the power supply and the ground line is more uniform, reduce the local peak value of the current density, thereby reducing electromagnetic radiation, and also help to reduce the crosstalk between signal lines and improve signal integrity. In addition, the layout of via pairs with equal spacing helps to form a consistent electromagnetic environment, reduce the electromagnetic radiation of the package, and enhance its anti-interference ability to the external environment. It also helps to optimize the layout of signal lines, reduce crosstalk between signal lines, and improve signal integrity.

[0073] In one embodiment, referring to Figure 4-Figure 6 , the spacing between adjacent second via pairs 150 in the second direction Y is greater than the spacing between the second ground holes 151 and the second power holes 152 in the second via pairs 150 in the second direction Y. By increasing the spacing between adjacent second via pairs 150, the electromagnetic coupling between the second via pairs 150 can be reduced, thereby reducing the electromagnetic radiation of the package and the crosstalk between the signal lines. At the same time, keeping the spacing between the second ground holes 151 and the second power holes 152 in the second via pairs 150 small can ensure a close connection between the power supply and the ground line, reduce the inductance of the power supply network, improve the power supply efficiency, and reduce the crosstalk between the signal lines, thereby improving the integrity of the signal.

[0074] In one embodiment, referring to Figure 4-Figure 6 The second ground hole 151 in the second via hole pair 150 has the same shape and substantially the same size as the second power hole 152; the second ground hole 151 in the second via hole pair 150 has the same shape and substantially the same size as the first ground hole 141 in the first via hole pair 140; the second power hole 152 in the second via hole pair 150 has the same shape and substantially the same size as the second power hole 152 in the first via hole pair 140; this helps to form a consistent electromagnetic environment, reduce the electromagnetic radiation of the package, and enhance its anti-interference ability to the external environment.

[0075] In one embodiment, referring to Figure 2 or Figure 5 One end of the first power hole 142 is connected to the first power layer 110, and the other end is connected to the first power hole pad 162 (at Figure 1 One end of the first ground hole 141 is connected to the first ground layer 130, and the other end is connected to the first ground hole pad 161; and / or one end of the second power hole 152 is connected to the first power layer 110, and the other end is connected to the second power hole pad 164 (in Figure 4(not shown); one end of the second ground hole 151 is connected to the first ground layer 130, and the other end is connected to the second ground hole pad 163. One end of the first power hole 142 is connected to the first power layer 110 inside the package, which is part of the power network inside the package and is used to supply power to the chip. The other end is connected to the first power hole pad 162 outside the package, which is part of the bottom or side of the package and is used to connect to the power pad on the PCB. Such a connection ensures that the power layer inside the package can be seamlessly connected to the power network on the PCB to provide a stable power supply. One end of the first ground hole 141 is connected to the first ground layer 130 inside the package, which is part of the ground wire network inside the package and is used to provide a reference ground for the circuit. The other end is connected to the first ground hole pad 161 outside the package, which is also located at the bottom or side of the package and is used to connect to the ground wire pad on the PCB. Such a connection ensures that the ground layer inside the package can be connected to the ground wire network on the PCB to form a complete ground wire loop. Through the connection of the above-mentioned vias, the power supply and ground wires inside the package can form a low-impedance connection with the power supply and ground wire networks on the external circuit board, which can effectively reduce signal interference and improve electromagnetic compatibility.

[0076] Figure 7 A schematic cross-sectional view of a printed circuit board parallel to a first power supply layer provided by another embodiment of the present disclosure is shown; Figure 8 A printed circuit board provided by another embodiment of the present disclosure Figure 7 Schematic diagram of the cross section in the ee direction; Fig. 9 A printed circuit board provided by another embodiment of the present disclosure Figure 7 Schematic diagram of the cross section along the ff direction;

[0077] In one embodiment, referring to Figure 7-Figure 9The printed circuit board 100 further includes a first shielding layer 170, which surrounds the first power layer 110 and is located on the same plane layer as the first power layer 110. The first shielding layer 170 electrically isolates the first power layer 110, and the first shielding layer 170 has a first recess 180. The first shielding layer 170 is a structure used to reduce electromagnetic interference (EMI) and improve electromagnetic compatibility (EMC) in a printed circuit board (PCB). The first shielding layer 170 is usually made of a conductive material, such as copper, and is placed on a specific layer of the PCB to absorb and reflect electromagnetic waves to reduce the electromagnetic radiation of the package and enhance its anti-interference ability to the external environment. The first shielding layer 170 and the first power layer 110 are on the same layer of the PCB, but they are electrically isolated to prevent direct electrical connection. The function of the first shielding layer 170 is to provide additional electromagnetic shielding, reduce the electromagnetic radiation of the package, and enhance its anti-interference ability to the external environment. The first shielding layer 170 has a first recess 180, which can adapt to a specific component layout on the PCB, such as avoiding direct contact with certain components or vias, thereby ensuring good electrical isolation. The first recess 180 can also optimize the shape of the first shielding layer 170 to reduce the edge effect of the electromagnetic field and further reduce the electromagnetic radiation of the package.

[0078] In one embodiment, referring to Figure 7-Figure 9 , one end of the first ground hole 141 is connected to the first shielding layer 170, and the other end is connected to the first ground layer 130; that is, the orthographic projection of the first ground hole 141 on the first shielding layer 170 falls within the first shielding layer 170; the orthographic projection of the first power hole 142 on the first dielectric layer 120 partially overlaps with the orthographic projection of the first recess 180 on the first dielectric layer 120, that is, the first recess 180 provides a partial space for setting the first power hole 142. In this way, it can be ensured that there is sufficient electrical isolation between the first power hole 142 and the first shielding layer 170, and at the same time, the first power hole 142 and the first ground hole 141 cooperate to reduce electromagnetic radiation.

[0079] Fig.10 A schematic cross-sectional view of a printed circuit board parallel to a first power supply layer provided by another embodiment of the present disclosure is shown;

[0080] In one embodiment, referring to Fig.10, one end of the second ground hole 151 is connected to the first shielding layer 170, and the other end is connected to the first ground layer 130; that is, the orthographic projection of the second ground hole 151 on the first shielding layer 170 falls within the first shielding layer 170; the orthographic projection of the second power hole 152 on the first dielectric layer 120 partially overlaps with the orthographic projection of the first recess 180 on the first dielectric layer 120, that is, the first recess 180 provides a partial space for setting the second power hole 152. In this way, it can be ensured that there is sufficient electrical isolation between the second power hole 152 and the first shielding layer 170, and at the same time, the second power hole 152 and the second ground hole 151 cooperate to reduce electromagnetic radiation.

[0081] Fig.11 A schematic cross-sectional view of a printed circuit board parallel to a second power supply layer provided by another embodiment of the present disclosure is shown; Fig.12 A printed circuit board provided by another embodiment of the present disclosure Fig.11 Schematic diagram of the cross section along the aa direction;

[0082] In one embodiment, referring to Figure 11-Figure 12 The printed circuit board 100 further includes a second power layer 210; a second dielectric layer 220; a second ground layer 230, wherein the second ground layer 230 is isolated from the second power layer 210 by the second dielectric layer 220; a third via pair 240, wherein the third via pair 240 penetrates the second dielectric layer 220, and the third via pair 240 includes a third ground hole 241 and a third power hole 242 arranged along the first direction X, wherein the third ground hole 241 is isolated from the second power layer 210 and connected to the second ground layer 230, and the third power hole 242 is connected to the second power layer 210 and isolated from the second ground layer 230, and the third via pair 240 is arranged along the first direction; wherein, on a cross section of the printed circuit board 100 perpendicular to the first power layer 110, the first via pair 140 is centrally symmetrical to the third via pair 240. That is, the first ground hole 141 in the first via hole pair 140 is symmetrical with the third ground hole 241 in the third via hole pair 240, and the first power hole 142 in the first via hole pair 140 is symmetrical with the third power hole 242 in the third via hole pair 240. In other words, see Fig.12 As shown, the third power hole 242 in the third via pair 240 is located directly below the first ground hole 141 in the first via pair 140, and the third ground hole 241 in the third via pair 240 is located directly below the first power hole 142 in the first via pair 140. In this way, in the direction of the printed circuit board 100 perpendicular to the first power layer 110, the electromagnetic radiation generated by the first via pair 140 and the third via pair 240 can form destructive interference in space, thereby reducing the overall radiation level.

[0083] In one embodiment, referring to Figure 11-Figure 12, on the cross section of the printed circuit board 100 parallel to the second power layer 210, the third via pair 240 in the first direction X is mirror-symmetrical with the center line 111 of the cross section as the center line. That is to say, when adjacent third via pairs 240 are arranged in a mirror-symmetrical manner, the electromagnetic radiation they generate will cancel each other out in the far field. This is because the radiation fields generated by the symmetrical power holes and ground holes have opposite phases, thereby forming destructive interference in space and reducing the overall radiation level. Similarly, when adjacent third via pairs 240 are arranged in a mirror-symmetrical manner, their anti-interference ability to the external environment is also enhanced.

[0084] In one embodiment, referring to Figure 11-Figure 12 The printed circuit board 100 also includes a fourth via pair 250, the fourth via pair 250 penetrates the second dielectric layer 220, the fourth via pair 250 includes a fourth ground hole 251 and a fourth power hole 252 arranged along the second direction Y, the fourth ground hole 251 is isolated from the second power layer 210 and connected to the second ground layer 230, the fourth power hole 252 is connected to the second power layer 210 and isolated from the second ground layer 230, and the fourth via pair 250 is arranged along the second direction Y; the first direction X intersects the second direction Y; wherein, on the cross section of the printed circuit board 100 parallel to the second power layer 210, the fourth via pairs 250 adjacent to each other in the second direction Y are mirror-symmetrical.

[0085] Fig.13 A schematic cross-sectional view of a printed circuit board parallel to a second power supply layer provided by another embodiment of the present disclosure is shown;

[0086] In one embodiment, referring to Figure 12-13 The printed circuit board 100 further includes a second shielding layer 270 , which surrounds the second power layer 210 and is located on the same plane as the second power layer 210 . The second shielding layer 270 electrically isolates the second power layer 210 , and has a second recess 280 .

[0087] In one embodiment, referring to Figure 12-13 , one end of the third ground hole 241 is connected to the second shielding layer 270, and the other end is connected to the second ground layer 230; that is, the orthographic projection of the third ground hole 241 on the second shielding layer 270 falls within the second shielding layer 270; the orthographic projection of the third power hole 242 on the second dielectric layer 220 partially overlaps with the orthographic projection of the second recess 280 on the second dielectric layer 220, that is, the second recess 280 provides a partial space for setting the third power hole 242. In this way, it can be ensured that there is sufficient electrical isolation between the third power hole 242 and the second shielding layer 270, and at the same time, the third power hole 242 and the third ground hole 241 cooperate to reduce electromagnetic radiation.

[0088] In one embodiment, referring to Figure 12-13 , one end of the fourth ground hole 251 is connected to the second shielding layer 270, and the other end is connected to the second ground layer 230; that is, the orthographic projection of the fourth ground hole 251 on the second shielding layer 270 falls within the second shielding layer 270; the orthographic projection of the fourth power hole 252 on the second dielectric layer 220 partially overlaps with the orthographic projection of the second recess 280 on the second dielectric layer 220, that is, the second recess 280 provides a partial space for setting the fourth power hole 252. In this way, it can be ensured that there is sufficient electrical isolation between the fourth power hole 252 and the second shielding layer 270, and at the same time, the fourth power hole 252 and the fourth ground hole 251 cooperate to reduce electromagnetic radiation.

[0089] In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0090] In the description of the present disclosure, it should be understood that the terms "including" and "having" and any variations thereof used herein are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products or apparatuses.

[0091] Unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense, for example, it can be fixedly connected, detachably connected, or integrated; it can be directly connected, or indirectly connected through an intermediate medium, and it can make the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. In addition, the terms "first", "second", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A printed circuit board, characterized in that: include: First power supply layer; a first dielectric layer; a first ground layer, wherein the first ground layer is isolated from the first power layer by the first dielectric layer; a first via pair, the first via pair passing through the first dielectric layer, the first via pair comprising a first ground hole and a first power hole arranged along a first direction, the first ground hole being isolated from the first power layer and connected to the first ground layer, the first power hole being connected to the first power layer and isolated from the first ground layer, and the first via pair being arranged along the first direction; Wherein, on a cross section of the printed circuit board parallel to the first power supply layer, the first via holes adjacent to each other in a first direction are mirror-symmetrical.

2. The printed circuit board according to claim 1, characterized in that: On a cross section of the printed circuit board parallel to the first power layer, the first via pair in a first direction is mirror-symmetric with a center line of the cross section as a center line.

3. The printed circuit board according to claim 1, characterized in that: The intervals between adjacent pairs of the first via holes in the first direction are the same.

4. The printed circuit board according to claim 1, characterized in that: The spacing between adjacent first via hole pairs in the first direction is greater than the spacing between the first ground holes and the first power holes in the first via hole pairs in the first direction.

5. The printed circuit board according to claim 1, characterized in that: The first ground hole and the first power hole have the same shape and substantially the same size.

6. The printed circuit board according to claim 1, characterized in that: The printed circuit board further includes a second via pair, the second via pair penetrates the first dielectric layer, the second via pair includes a second ground hole and a second power hole arranged along a second direction, the second ground hole is isolated from the first power layer and connected to the first ground layer, the second power hole is connected to the first power layer and isolated from the first ground layer, and the second via pair is arranged along a second direction; the first direction intersects with the second direction; Wherein, on a cross section of the printed circuit board parallel to the first power supply layer, the second via holes adjacent to each other in the second direction are mirror-symmetrical.

7. The printed circuit board according to claim 6, characterized in that: On the cross section of the printed circuit board parallel to the first power layer, the second via pair in the second direction is mirror-symmetrical with the center line of the cross section as the center line.

8. The printed circuit board according to claim 6, characterized in that: The intervals between adjacent pairs of the second via holes in the second direction are the same.

9. The printed circuit board according to claim 6, characterized in that: The spacing between adjacent pairs of the second via holes in the second direction is greater than the spacing between the second ground holes and the second power holes in the second via holes in the second direction.

10. The printed circuit board according to claim 6, characterized in that: One end of the first power hole is connected to the first power layer, and the other end is connected to the first power hole pad; and / or one end of the second power hole is connected to the first power layer, and the other end is connected to the second power hole pad.

11. The printed circuit board according to claim 6, characterized in that: The printed circuit board further includes a first shielding layer, which surrounds the first power layer and is located on the same plane layer as the first power layer. The first shielding layer electrically isolates the first power layer, and the first shielding layer has a first recess.

12. The printed circuit board according to claim 11, characterized in that: One end of the first ground hole is connected to the first shielding layer, and the other end is connected to the first ground layer; the orthographic projection of the first power hole on the first dielectric layer partially overlaps with the orthographic projection of the first recess on the first dielectric layer.

13. The printed circuit board according to claim 11, characterized in that: One end of the second ground hole is connected to the first shielding layer, and the other end is connected to the first ground layer; the orthographic projection of the second power hole on the first dielectric layer partially overlaps with the orthographic projection of the first recess on the first dielectric layer.

14. The printed circuit board according to claim 1, characterized in that: The printed circuit board further comprises: Second power supply layer; a second dielectric layer; a second ground layer, wherein the second ground layer is isolated from the second power layer by the second dielectric layer; a third via pair, the third via pair passing through the second dielectric layer, the third via pair comprising a third ground hole and a third power hole arranged along the first direction, the third ground hole being isolated from the second power layer and connected to the second ground layer, the third power hole being connected to the second power layer and isolated from the second ground layer, and the third via pair being arranged along the first direction; Wherein, on a cross section of the printed circuit board perpendicular to the first power supply layer, the first via pair is centrally symmetrical with the third via pair.

15. The printed circuit board according to claim 14, characterized in that: On a cross section of the printed circuit board parallel to the second power supply layer, the third via pair in the first direction is mirror-symmetric with the center line of the cross section as the center line.

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