Method for manufacturing semiconductor device

Abstract

The invention relates to a manufacturing method of a semiconductor device. Provided is a semiconductor device having a high operating speed. A method of manufacturing a semiconductor device includes: forming a first coating film on a first insulator and a second coating film on the first coating film; removing a part of the second coating film to form a first layer; forming a second layer by removing a portion of the first coating film using the first layer as a mask; performing a heat treatment process; forming a first oxide semiconductor so as to cover the top surface of the first insulator, the side surfaces of the second layer, and the side surfaces and the top surface of the first layer; processing the first oxide semiconductor by anisotropic etching to form a second oxide semiconductor in contact with a side surface of the second layer; removing the first layer; the second layer is removed to expose a side surface of the second oxide semiconductor covered by the second layer.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device, a storage device, and an electronic device using an oxide semiconductor layer. In addition, one embodiment of the present invention relates to a method for manufacturing the semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. As an example of the technical field of one embodiment of the present invention, a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch panel), a driving method or a manufacturing method of the above-mentioned device can be cited.

[0003] Note that in this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, and storage devices are also a form of semiconductor devices. Sometimes it can be said that display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, camera devices, electronic devices, etc. include semiconductor devices. Background Art

[0004] In recent years, semiconductor devices have been developed, and LSI, CPU, memory, etc. are mainly used for semiconductor devices. CPU is an aggregate of semiconductor elements including a semiconductor integrated circuit (including at least transistors and memory) processed into a chip by a semiconductor wafer and having electrodes formed as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as one of the components of various electronic devices.

[0006] In addition, the technology of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply recorded as display devices). As semiconductor thin films that can be used for transistors, silicon-based semiconductor materials are widely known, and as other materials, oxide semiconductors have attracted attention.

[0007] In addition, it is known that the leakage current of a transistor using an oxide semiconductor is extremely small in a non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the small leakage current characteristic of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 discloses a storage device that utilizes the small leakage current characteristic of a transistor using an oxide semiconductor and can retain stored content for a long time.

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 Summary of the invention

[0009] One of the purposes of one embodiment of the present invention is to provide a semiconductor device with a high operating speed. One of the purposes of one embodiment of the present invention is to provide a semiconductor device that can achieve miniaturization or high integration. One of the purposes of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. One of the purposes of one embodiment of the present invention is to provide a semiconductor device with less variation in the electrical characteristics of a transistor. One of the purposes of one embodiment of the present invention is to provide a semiconductor device with high reliability. One of the purposes of one embodiment of the present invention is to provide a semiconductor device with a large on-state current. One of the purposes of one embodiment of the present invention is to provide a semiconductor device with low power consumption. One of the purposes of one embodiment of the present invention is to provide a novel semiconductor device. One of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with a high operating speed. One of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device that can achieve miniaturization or high integration. One of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with good electrical characteristics. One of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with less variation in the electrical characteristics of a transistor. One of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high reliability. One of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with a large on-state current. One of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with low power consumption. One object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. One object of one embodiment of the present invention is to provide a novel method for manufacturing a semiconductor device.

[0010] One of the purposes of one embodiment of the present invention is to provide a storage device that can be miniaturized or highly integrated. One of the purposes of one embodiment of the present invention is to provide a storage device with a large storage capacity. One of the purposes of one embodiment of the present invention is to provide a storage device with a fast operating speed. One of the purposes of one embodiment of the present invention is to provide a storage device with low power consumption. One of the purposes of one embodiment of the present invention is to provide a novel storage device.

[0011] Note that the description of these purposes does not prevent the existence of other purposes. One embodiment of the present invention does not need to achieve all of the above purposes. Purposes other than the above can be extracted from the description of the specification, drawings, and claims.

[0012] One embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first coating film on a first insulator and a second coating film on the first coating film; forming a first layer by removing a portion of the second coating film; forming a second layer by removing a portion of the first coating film using the first layer as a mask; performing a heat treatment process; forming a first oxide semiconductor in a manner covering a top surface of the first insulator, a side surface of the second layer, and a side surface and a top surface of the first layer; forming a second oxide semiconductor in a manner contacting with a side surface of the second layer by processing the first oxide semiconductor using anisotropic etching; removing the first layer; and exposing a side surface of the second oxide semiconductor covered by the second layer by removing the second layer.

[0013] In the above embodiment, preferably, the first coating film is an organic resin, and the second coating film is a film containing silicon, oxygen, and carbon.

[0014] In the above aspect, it is preferable that a part of the first insulator is removed when the first layer is removed.

[0015] In the above embodiment, the heat treatment step is preferably performed at a temperature of 200° C. or higher and 400° C. or lower.

[0016] In the above-mentioned embodiment, it is preferable to use microwave treatment when removing the second layer.

[0017] In addition, in the above method, preferably, the first oxide semiconductor is formed by a process of forming a third oxide semiconductor, a process of forming a fourth oxide semiconductor on the third oxide semiconductor, and a process of forming a fifth oxide semiconductor on the fourth oxide semiconductor, the third oxide semiconductor and the fifth oxide semiconductor are formed using a precursor and an oxidant containing indium and using an ALD method, and the fourth oxide semiconductor is formed using a sputtering target containing zinc and using a sputtering method.

[0018] In addition, one embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a second insulator on a first insulator; forming a first coating film on the second insulator and a second coating film on the first coating film; forming a first layer by removing a portion of the second coating film; forming a second layer by removing a portion of the first coating film using the first layer as a mask; performing a heat treatment step; forming a first oxide semiconductor in a manner covering a top surface of the second insulator, a side surface of the second layer, and a side surface and a top surface of the first layer; forming a second oxide semiconductor in a manner contacting with a side surface of the second layer by processing the first oxide semiconductor using anisotropic etching; removing the first layer and an area in the second insulator that does not overlap with the second layer and the second oxide semiconductor; by removing the second layer, the side of the second oxide semiconductor covered by the second layer is exposed; a first conductor is formed in a manner covering the top surface of the first insulator and the side of the second oxide semiconductor; a third insulator is formed on the first conductor; an opening is provided in the third insulator by removing a part of the third insulator; a region of the first conductor that overlaps with the opening is removed; a fourth insulator is formed on the third insulator and in the opening of the third insulator; the fourth insulator is formed in a manner covering the side of the second oxide semiconductor in the opening; and a second conductor is formed on the fourth insulator.

[0019] In the above embodiment, preferably, the first coating film is an organic resin, and the second coating film is a film containing silicon, oxygen, and carbon.

[0020] In the above embodiment, the heat treatment step is preferably performed at a temperature of 200° C. or higher and 400° C. or lower.

[0021] In the above-mentioned embodiment, it is preferable to use microwave treatment when removing the second layer.

[0022] According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with less variation in electrical characteristics of transistors can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device capable of miniaturization or high integration can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with less variation in electrical characteristics of transistors can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a novel method for manufacturing a semiconductor device can be provided.

[0023] According to one embodiment of the present invention, a storage device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a storage device with a large storage capacity can be provided. According to one embodiment of the present invention, a storage device with a fast operating speed can be provided. According to one embodiment of the present invention, a storage device with low power consumption can be provided. According to one embodiment of the present invention, a novel storage device can be provided.

[0024] Note that the description of these effects does not prevent the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. In addition, effects other than the above can be extracted from the description of the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1A is a plan view showing an example of a semiconductor device, Figures 1B to 1D is a cross-sectional view showing an example of a semiconductor device; FIG. 2A to FIG. 2C is a cross-sectional view showing an example of a semiconductor device; FIG. 3A to FIG. 3Cis a cross-sectional view showing an example of a semiconductor device; Figure 4A and Figure 4B is a plan view showing an example of a portion of a semiconductor device; Figure 5A is a plan view showing an example of a semiconductor device, FIG. 5B to FIG. 5D is a cross-sectional view showing an example of a semiconductor device; Fig. 6A is a plan view showing an example of a semiconductor device, FIG. 6B to FIG. 6D is a cross-sectional view showing an example of a semiconductor device; 7A to 7C is a cross-sectional view showing an example of a semiconductor device; FIG. 8A to FIG. 8D is a cross-sectional view showing an example of a method for manufacturing an oxide semiconductor; 9A to 9D is a cross-sectional view showing an example of an oxide semiconductor; FIG. 10A to FIG. 10C is a cross-sectional view showing an example of a portion of a semiconductor device; FIG. 11A to FIG. 11C is a cross-sectional view showing an example of a semiconductor device; Fig. 12A is a plan view showing an example of a semiconductor device, FIG. 12B to FIG. 12D is a cross-sectional view showing an example of a semiconductor device; Fig.13A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 13B to FIG. 13D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Fig.14A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 14B to FIG. 14D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Fig.15A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 15B to FIG. 15D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Fig.16A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 16B to FIG. 16D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Fig.17A is a plan view showing an example of a method for manufacturing a semiconductor device, Fig. 17B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Fig.18Ais a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 18B to FIG. 18D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Fig.19A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 19B to FIG. 19D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Fig. 20A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 20B to FIG. 20D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Fig.21A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 21B to FIG. 21D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Fig.22A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 22B to FIG. 22D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Fig.23A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 23B to FIG. 23D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Fig.24A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 24B to FIG. 24D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Fig.25A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 25B to FIG. 25D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Fig.26A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 26B to FIG. 26D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Fig.27A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 27B to FIG. 27D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Fig.28A is a plan view showing an example of a method for manufacturing a semiconductor device, FIG. 28B to FIG. 28D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device; Fig.29 is a cross-sectional view showing an example of a semiconductor device; FIG. 30A to FIG. 30C is a cross-sectional view showing an example of a semiconductor device; Fig.31A and Fig.31B is a cross-sectional view showing an example of a semiconductor device; Fig.32 is a block diagram illustrating a structural example of a semiconductor device; FIG. 33A to FIG. 33H is a diagram illustrating an example of a circuit configuration of a memory cell; Fig.34A and Fig.34B is a perspective view illustrating a structural example of a semiconductor device; Fig.35 is a block diagram illustrating a CPU; Fig.36 is a block diagram illustrating a CPU; Fig.37A and Fig.37B is a three-dimensional diagram of a semiconductor device; Fig.38A and Fig.38B is a three-dimensional diagram of a semiconductor device; Fig.39A and Fig.39B is a diagram illustrating a hierarchy of a memory device in a semiconductor device; Fig.40A and Fig.40B is a diagram showing an example of an electronic device, FIG. 40C to FIG. 40E is a diagram showing an example of a large computer; Fig.41 is a diagram showing an example of a space device; Fig.42 is a diagram showing an example of a storage system that can be used in a data center. DETAILED DESCRIPTION

[0026] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person skilled in the art can easily understand that the mode and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0027] Note that in the structure of the invention described below, the same symbols are used in common between different drawings to show the same parts or parts with the same function, and their repeated descriptions are omitted. In addition, when showing parts with the same function, the same hatching is sometimes used without special additional symbols.

[0028] In addition, for ease of understanding, the positions, sizes, and ranges of various components shown in the drawings may not represent their actual positions, sizes, and ranges. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and ranges disclosed in the drawings.

[0029] In addition, in particular, in a plan view (also referred to as a “top view”) or a perspective view, some components may be omitted to facilitate understanding of the invention. In addition, some hidden lines may be omitted.

[0030] Note that in this specification, etc., ordinal numbers such as "first" and "second" are added for convenience, but they do not limit the number of components or the order of components (for example, the order of processes or the order of stacking). In addition, the ordinal numbers added to components in one part of this specification may not be consistent with the ordinal numbers added to the components in other parts of this specification or claims.

[0031] In addition, depending on the situation or condition, "film" and "layer" may be interchanged. For example, "conductive layer" may be interchanged with "conductive film". In addition, "insulating film" may be interchanged with "insulating layer". In addition, depending on the situation or condition, "conductive body" may be interchanged with "conductive layer" or "conductive film". In addition, depending on the situation or condition, "insulator" may be interchanged with "insulating layer" or "insulating film".

[0032] In addition, in this specification, etc., "parallel" refers to a state in which two straight lines are arranged at an angle of more than -10 degrees and less than 10 degrees. Therefore, a state in which the angle is more than -5 degrees and less than 5 degrees is also included. In addition, "approximately parallel" refers to a state in which two straight lines are arranged at an angle of more than -20 degrees and less than 20 degrees. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is more than 80 degrees and less than 100 degrees. Therefore, a state in which the angle is more than 85 degrees and less than 95 degrees is also included. In addition, "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of more than 70 degrees and less than 110 degrees.

[0033] The opening includes, for example, a groove, a slit, etc. In addition, a region where the opening is formed may be referred to as an opening portion.

[0034] In addition, the drawings used in this specification and the like show the case where the side wall in the opening of the insulator is perpendicular or substantially perpendicular to the substrate surface or the formed surface, but the side wall may also be tapered.

[0035] Note that in this specification, etc., a tapered shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to a substrate surface or a formed surface. For example, it is preferable to have a region in which the angle formed by the inclined side surface and the substrate surface or the formed surface (hereinafter, sometimes referred to as a taper angle) is less than 90°. Note that the side surface and the substrate surface of a constituent element do not necessarily have to be completely flat, and may be a substantially planar shape with a slight curvature or a substantially planar shape with fine concave-convex shapes.

[0036] In addition, in this specification, etc., "high consistency or approximately consistency" refers to a structure in which the height from a reference plane (for example, a flat surface such as a substrate surface) is equal when viewed from a cross section. For example, in the manufacturing process of a storage device, sometimes the surface of a single layer or multiple layers is exposed due to a flattening process (typically a CMP process). In this case, the processed surface treated by CMP has a structure in which the height from the reference plane is equal. However, depending on the processing device, processing method or material of the processed surface used in the CMP process, the heights of multiple layers may sometimes be different. In this specification, etc., this situation is also regarded as "high consistency or approximately consistency". For example, the following situation is also referred to as "high consistency or approximately consistency": including two layers (here, the first layer and the second layer) with different heights from the reference plane, wherein the difference between the top surface height of the first layer and the top surface height of the second layer is less than 20nm.

[0037] In this specification, etc., "side ends are aligned or roughly aligned" means that at least a portion of the outline of each layer in the stack overlaps when viewed from above. For example, this includes the case where the upper layer and the lower layer are processed by the same mask pattern or a portion of the same mask pattern. However, strictly speaking, sometimes the outlines do not overlap and the outline of the upper layer is located inside the outline of the lower layer or the outline of the upper layer is located outside the outline of the lower layer. These cases are also called "side ends are aligned or roughly aligned".

[0038] Implementation Method 1 In this embodiment, refer to Figures 1A to 31B A semiconductor device including an oxide semiconductor layer and a method for manufacturing the semiconductor device are described.

[0039] <Structural Example 1 of Semiconductor Device> Reference Figures 1A to 11C A structural example of a semiconductor device will be described. Figures 1A to 1D 1 and 2 are plan views and cross-sectional views of a semiconductor device including a transistor 200 on a substrate (not shown).

[0040] Figure 1A is a plan view of the semiconductor device. Figures 1B to 1D is a cross-sectional view of the semiconductor device. Figure 1B It is along Figure 1AThe cross-sectional view of the portion along the dot-dash line A1-A2 in FIG. 1 is also a cross-sectional view of the transistor 200 in the channel width direction. Figure 1C It is along Figure 1A The cross-sectional view of the portion along the dashed line A3-A4 in FIG. 1 is also a cross-sectional view along the channel width direction of the transistor 200. Figure 1D It is along Figure 1A The cross-sectional view of the portion along the dot-dash line A5-A6 in FIG. 1 is also a cross-sectional view along the channel length direction of the transistor 200. Here, the dot-dash line A5-A6 is orthogonal to the dot-dash line A1-A2 and the dot-dash line A3-A4, and the dot-dash line A1-A2 and the dot-dash line A3-A4 are parallel to each other. Note that Figure 1A In the plan view, for the sake of clarity, some components are omitted to show through some components.

[0041] The semiconductor device of this embodiment includes an insulator 216 on a substrate (not shown), an insulator 221 on the insulator 216, an insulator 222 on the insulator 221, an insulator 224 on the insulator 222, an oxide semiconductor 230 on the insulator 224, a conductor 242a and a conductor 242b on the oxide semiconductor 230 and the insulator 224, an insulator 250 on the oxide semiconductor 230, and a conductor 260 (a conductor 260a and a conductor 260b) on the insulator 250. Hereinafter, the conductor 242a and the conductor 242b may be collectively referred to as the conductor 242.

[0042] An insulator 275 is provided on the conductor 242, and an insulator 280 is provided on the insulator 275. The insulator 250 and the conductor 260 are arranged inside openings provided in the insulator 280 and the insulator 275. The opening reaches the oxide semiconductor 230, and the insulator 250 is in contact with the oxide semiconductor 230 in the opening. In addition, an insulator 282 is provided on the insulator 280 and the conductor 260. In addition, an insulator 283 is provided on the insulator 282. In addition, the insulator 215 is provided under the insulator 216.

[0043] Insulator 241a is provided in contact with the inner wall of the opening in insulator 280 or the like, and conductor 240a is provided in contact with the side surface of insulator 241a. The bottom surface of conductor 240a is in contact with the top surface of conductor 242a. Insulator 241b is provided in contact with the inner wall of the opening in insulator 280 or the like, and conductor 240b is provided in contact with the side surface of insulator 241b. The bottom surface of conductor 240b is in contact with the top surface of conductor 242b. Hereinafter, conductor 240a and conductor 240b are sometimes collectively referred to as conductor 240. In addition, insulator 241a and insulator 241b are sometimes collectively referred to as insulator 241.

[0044] The oxide semiconductor 230 has a region serving as a channel formation region of the transistor 200. The conductor 260 has a region serving as a first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 has a region serving as a first gate insulator of the transistor 200.

[0045] The conductor 242a has a region serving as one of the source electrode and the drain electrode of the transistor 200. The conductor 240a is used as a plug connected to the conductor 242a. The conductor 242b has a region serving as the other of the source electrode and the drain electrode of the transistor 200. The conductor 240b is used as a plug connected to the conductor 242b.

[0046] Figure 2A yes Figure 1D An enlarged view of the vicinity of the conductor 260. In addition, Figure 2A The insulator 250 includes an insulator 250a, an insulator 250b, an insulator 250c, and an insulator 250d. The detailed structures of the insulator 250a, the insulator 250b, the insulator 250c, and the insulator 250d will be described later.

[0047] Figure 2B and Figure 3A yes Figure 1B An enlarged view of the vicinity of the oxide semiconductor 230 . Figure 2B and Figure 3A An example is shown in which the oxide semiconductor 230 includes an oxide semiconductor 230a, an oxide semiconductor 230b, and an oxide semiconductor 230c. Figure 3A An example is shown in which the insulator 250 includes an insulator 250a, an insulator 250b, an insulator 250c, and an insulator 250d.

[0048] Figure 3C yes Figure 1C An enlarged view of the vicinity of the oxide semiconductor 230 . Figure 3C An example is shown in which the oxide semiconductor 230 includes an oxide semiconductor 230a, an oxide semiconductor 230b, and an oxide semiconductor 230c. Figure 3C The conductor 240a includes the conductor 240a1 and the conductor 240a2. The conductors such as the conductor 260, the conductor 240a, the conductor 240b, the conductor 242a, and the conductor 242b preferably have a laminated structure. The detailed structure of the laminated structure of the conductor will be described later.

[0049] The oxide semiconductor 230 is formed in contact with the insulator 224. Figure 2B , Figure 3A and Figure 3CAs shown in FIG. 1 , the oxide semiconductor 230 has a shape with a high aspect ratio when viewed from a cross section in the channel width direction. Therefore, it can be said that the oxide semiconductor 230 has a fin-like shape.

[0050] Here, the aspect ratio of the oxide semiconductor 230 when viewed from a cross section in the channel width direction refers to the ratio of the length L in the A1-A2 direction of the oxide semiconductor 230 (which may also be referred to as the width L of the oxide semiconductor 230) to the length H in the direction perpendicular to the formed surface of the oxide semiconductor 230 (for example, the insulator 224) (which may also be referred to as the height H of the oxide semiconductor 230). The aspect ratio of the oxide semiconductor 230 is preferably as high as possible within a range in which the oxide semiconductor 230 does not fall during the manufacturing process of the transistor 200. In the oxide semiconductor 230, the height H of the oxide semiconductor 230 is at least greater than the width L of the oxide semiconductor 230. The height H of the oxide semiconductor 230 is set to be greater than 1 times and less than 400 times the width L of the oxide semiconductor 230, preferably greater than 2 times and less than 100 times, more preferably greater than 5 times and less than 40 times, and further preferably greater than 10 times and less than 20 times. In addition, for example, the height H may also be greater than 2 times and less than 10 times the width L. For example, the width L is set to be greater than 5 nm and less than 100 nm, preferably greater than 5 nm and less than 50 nm, and more preferably greater than 10 nm and less than 30 nm. In addition, for example, the height H is set to be greater than 50 nm and less than 2000 nm, preferably greater than 100 nm and less than 1000 nm. In addition, for example, the height H may also be greater than 50 nm and less than 100 nm.

[0051] In addition, if Figure 2B As shown, when viewed from a cross section in the channel width direction, the side surface of the oxide semiconductor 230 is preferably perpendicular or substantially perpendicular to the top surface of the insulator 224. The angle formed by the side surface of the oxide semiconductor 230 and the top surface of the insulator 224 is denoted as angle θ. For example, angle θ is preferably greater than or equal to 80° and less than or equal to 100°, and more preferably greater than or equal to 85° and less than or equal to 95°.

[0052] The insulator 250, the conductor 260, and the conductor 242 are provided so as to cover the oxide semiconductor 230 having a high aspect ratio. Figure 1B , Figure 2B and Figure 3AAs shown, the insulator 250 and a portion of the conductor 260 are arranged in a folded state with the oxide semiconductor 230 sandwiched therebetween. Thus, when viewed from the cross section in the channel width direction, the oxide semiconductor 230 and the conductor 260 are arranged opposite to each other with the insulator 250 sandwiched therebetween at the upper portion of the oxide semiconductor 230, the side surface on the A1 side, and the side surface on the A2 side. That is, the upper portion of the oxide semiconductor 230, the side surface on the A1 side, and the side surface on the A2 side are all used as channel formation regions. Thus, compared with the case where the oxide semiconductor 230 is formed into a flat plate, the channel width of the transistor 200 is increased by the size of the side surface on the A1 side and the side surface on the A2 side of the oxide semiconductor 230.

[0053] As described above, by increasing the channel width, the on-state current, mutual conductance, frequency characteristics, etc. of the transistor 200 can be improved. Thus, a semiconductor device with a fast operating speed can be provided. In addition, the operating speed of a storage device using the semiconductor device can be improved. In addition, in the above structure, by providing an oxide semiconductor 230, the channel width can be increased without increasing the occupied area of ​​the transistor 200. Thus, miniaturization or high integration of semiconductor devices can be achieved. In addition, the storage capacity of a storage device using the semiconductor device can be increased. In addition, by adopting the above structure, the area relative to the conductor 260 and the oxide semiconductor 230 becomes larger, so the threshold can be controlled to make the transistor 200 normally closed.

[0054] like Figure 2B and Figure 3A As shown in FIG. 1 and FIG. 2 , the upper portion of the oxide semiconductor 230 preferably has a curved shape. By having such a curved shape, defects such as voids can be prevented from being formed in the insulator 250 and the conductor 242 near the upper portion of the oxide semiconductor 230. Figure 2B and Figure 3A In the above, a left-right symmetrical structure is used in which both the A1 side (A3 side) and the A2 side (A4 side) of the upper portion of the oxide semiconductor 230 have a curved shape, but the present invention is not limited thereto. For example, a left-right asymmetrical structure is sometimes used in which one of the A1 side (A3 side) and the A2 side (A4 side) of the upper portion of the oxide semiconductor 230 has a curved shape. Figure 3B and Figure 3A The main difference is that: Figure 3B In the illustrated structural example, one of the A1 side and the A2 side of the upper portion of the oxide semiconductor 230 has a bent shape only on the A1 side.

[0055] In one embodiment of the present invention, a sidewall-shaped oxide semiconductor 230 is formed on the side surface of the pillar. This allows an oxide semiconductor having a high aspect ratio to be formed.

[0056] After the oxide semiconductor 230 is formed, the pillars used in forming the oxide semiconductor 230 are removed. The pillars can be removed by dry etching, ashing, plasma processing, wet etching, or the like.

[0057] The process used when removing the pillars preferably has a high etching selectivity ratio with the oxide semiconductor 230. Here, a high etching selectivity ratio refers to a state in which the etching rate of the pillars in the etching process when removing the pillars is higher than the etching rate of the oxide semiconductor 230. By sufficiently increasing the selectivity ratio, it is possible to suppress the partial or entire disappearance of the oxide semiconductor 230 when removing the pillars.

[0058] In addition, the damage to the oxide semiconductor 230 caused by the process used when removing the pillar is preferably small. For example, when dry etching is performed, plasma damage may be caused to the oxide semiconductor 230. In addition, when removing the pillar, the reaction products deposited on the surface of the oxide semiconductor 230 due to etching are preferably small. The damage to the surface of the oxide semiconductor 230, the deposited reaction products, etc. may cause the characteristics and reliability of semiconductor devices such as transistors using the oxide semiconductor 230 to be reduced.

[0059] Therefore, it is preferable to remove the pillars by using a simple process so as to have little influence on the oxide semiconductor 230 .

[0060] In one embodiment of the present invention, by using the later-described Fig. 14B , Fig. 14C The stacked body of the layer 293 and the layer 292 on the layer 293 shown in the figure can suppress damage to the oxide semiconductor 230 in the step of removing the pillar.

[0061] The layer 293 is, for example, a layer containing carbon. A non-photosensitive organic resin can be used as the layer 293. In one embodiment of the present invention, SOC (Spin On Carbon) is preferably used as the layer 293.

[0062] Layer 292 is, for example, a layer containing silicon and carbon. Layer 292 is, for example, a layer containing silicon and oxygen. As layer 292, a layer containing a polymer of silicon and oxygen can be used. In addition, layer 292 preferably contains carbon in addition to silicon and oxygen. In one embodiment of the present invention, SOG (Spin On Glass) is preferably used as layer 292. In addition, as layer 292, a non-photosensitive organic resin can be used.

[0063] The layer 292 can be used as a mask for processing the layer 293. By forming the layer 292 on the layer 293, it is easy to form the layer 293 with a fine pattern.

[0064] Layer 293 is a layer containing carbon, and an organic resin or the like can be used as layer 293. A layer composed of an organic resin or the like is more susceptible to damage caused by plasma treatment or the like than an inorganic insulating layer. Therefore, it is preferred to form the oxide semiconductor 230 using a method with less damage. For example, the oxide semiconductor 230 is preferably formed using an ALD method. In addition, when the oxide semiconductor 230 has a stacked structure, it is preferred to form at least one layer using an ALD method, and the layer is preferably a layer in contact with the pillars (layers 293 and 292).

[0065] In addition, the ALD method has high coverage, so the ALD method can also appropriately deposit on the sidewalls of pillars with a high aspect ratio.

[0066] By forming the oxide semiconductor 230 into a sidewall shape in contact with the side surfaces of the plurality of pillars, as shown in FIG. Figure 1A As shown, multiple fin regions can be formed simultaneously in the oxide semiconductor 230. In this way, by forming multiple fin regions, the distance between each fin region can be set according to the size and shape of the pillar. Thus, the distance between each fin region can be shortened and the occupied area of ​​the transistor 200 can be reduced, thereby realizing high integration of the semiconductor device.

[0067] Since the oxide semiconductor 230 is formed in a sidewall shape in contact with the pillar, Figure 1A As shown in FIG. 1 , the top surface of the oxide semiconductor 230 is in a circular shape (also referred to as a frame shape, a ring shape, a doughnut shape, or a closed curve shape) with both ends aligned. Alternatively, the oxide semiconductor 230 may be said to have a shape including an opening in the center. Figure 1A In the embodiment, the top surface of the oxide semiconductor 230 is a line-symmetric shape with A1-A2 as the center, but the present invention is not limited thereto. For example, the top surface of the oxide semiconductor 230 may also be an asymmetric shape.

[0068] exist Figure 1A In the structure shown in FIG. 1 , two pillars are arranged in the A1-A2 direction, and a peripheral oxide semiconductor 230 is formed in contact with the side surface of each pillar. Figure 1A As shown in FIG. 1 , the oxide semiconductor 230 preferably overlaps with the conductor 260 at two or more locations when viewed from above. That is, the structure has two or more regions where the oxide semiconductor 230 overlaps with the conductor 260. By adopting such a structure, Figure 1B As shown, when viewed in a cross section in the channel width direction, a plurality of fin-shaped regions are formed in the oxide semiconductor 230. Each of the plurality of fin-shaped regions is used as a channel formation region. In other words, the transistor 200 is used as a multi-channel transistor. Therefore, the channel width can be further increased in the transistor 200.

[0069] In addition, in the above description, a structure in which two circumferential oxide semiconductors 230 are provided is described, but the present invention is not limited thereto. For example, a structure in which one or more circumferential oxide semiconductors 230 are provided may be adopted. In addition, the circumferential oxide semiconductors 230 may be connected to form an oxide semiconductor 230 having a shape including a plurality of openings. For example, Figure 4A As shown in FIG. 1 , an oxide semiconductor 230 having a shape with three openings arranged in the A1-A2 direction when viewed from above may also be formed. In this case, three pillars are formed adjacent to each other at a short distance, and the oxide semiconductor 230 is formed between the pillars. In addition, for example, Figure 4B As shown, an oxide semiconductor 230 having a lattice-like shape when viewed from above may also be formed. In this case, a lattice-like groove is formed in the column and the oxide semiconductor 230 is formed in a manner embedded in the groove. Note that the number of oxide semiconductors 230 is not limited to two, and a structure in which one or more than three oxide semiconductors 230 are provided may also be adopted. In this way, as the oxide semiconductor 230, a structure having a plurality of portions extending in the channel width direction (A1-A2 direction) and a plurality of portions extending in the channel length direction (A5-A6 direction) is preferably adopted. In this way, when the oxide semiconductor 230 has a structure with a high aspect ratio, the oxide semiconductor 230 can be prevented from falling down during the manufacturing process of the transistor.

[0070] Note that Figures 1A to 1D In the semiconductor device shown, the top surface shape of the insulator 224 is the same as that of the oxide semiconductor 230, and when viewed from above, the insulator 224 overlaps with the oxide semiconductor 230. The bottom surface of the insulator 224 is in contact with the insulator 222, the side surface of the insulator 224 is in contact with the insulator 250 and the conductor 242a, and the top surface of the insulator 224 is in contact with the bottom surface of the oxide semiconductor 230.

[0071] Here, if Figure 2B As shown in FIG. 1 , the thickness t2 of the insulator 250 in the openings of the insulators 280 and 275 is preferably smaller than the thickness t1 of the insulator 224. With this structure, the bottom surface of the conductor 260 (conductor 260a) located in the opening can be lower than the bottom surface of the oxide semiconductor 230 by the difference between the thickness t1 and the thickness t2 (t1-t2). By changing the thickness t1 of the insulator 224, the degree to which the conductor 260 is lower than the bottom surface of the oxide semiconductor 230 can be changed.

[0072] By configuring the bottom surface of the conductor 260 below the bottom surface of the oxide semiconductor 230, a sufficient gate electric field can be applied to the upper end to the lower end of the oxide semiconductor 230. In other words, the entire oxide semiconductor 230 can be surrounded by the electric field of the conductor 260 in the opening of the insulator 280 and the like and used as a channel formation region. By adopting this structure, the lower end of the oxide semiconductor 230 can be prevented from being used as a parasitic channel, thereby reducing the leakage current between the source electrode and the drain electrode. In addition, poor characteristics such as the normally-on state of the transistor caused by the parasitic channel can be suppressed. In other words, the electrical characteristics of the transistor 200 can be improved.

[0073] As described above, by using the upper and lower ends of the oxide semiconductor 230 as a channel formation region, the channel width can be increased, thereby improving the on-state current, mutual conductance, frequency characteristics, and the like of the transistor 200.

[0074] Note that in this specification, etc., the structure of the transistor in which the electric field of the gate electrode surrounds the channel formation region is referred to as a surrounded channel (S-channel) structure. In the S-channel structure, the gate electrode is configured in a manner that surrounds at least two or more sides of the channel (specifically, two sides, three sides, or four sides, etc.). By adopting the S-channel structure, the resistance to the short channel effect can be improved, in other words, a transistor that is not prone to the short channel effect can be realized.

[0075] The S-channel structure is a structure that electrically surrounds the channel formation region, so it can also be said that the structure is essentially the same as the GAA (Gate All Around: full-surround gate) structure or the LGAA (Lateral Gate All Around: lateral full-surround gate) structure. By making the transistor 200 have an S-channel structure, a GAA structure, or a LGAA structure, the channel formation region formed at the interface or near the interface between the oxide semiconductor 230 and the gate insulator can be regarded as the entire bulk of the oxide semiconductor 230. Therefore, the current density flowing through the transistor can be increased, so an increase in the on-state current of the transistor or an increase in the field effect mobility of the transistor can be expected. In addition, in one embodiment of the present invention, the oxide semiconductor 230 has a CAAC structure and a fin shape. In addition, the CAAC structure is formed in a manner that makes the ab plane parallel or approximately parallel to the channel length direction. By adopting this structure, it is possible that the current path flowing between the source and drain of the transistor is parallel to the ab plane of the CAAC structure. In other words, the oxide semiconductor having a CAAC structure and a fin shape has a conduction path equal to that of a two-dimensional semiconductor material. Furthermore, by using an oxide semiconductor for a semiconductor layer of such a transistor, a device having two-dimensional conduction properties can be manufactured.

[0076] exist Figures 1B to 1D , Figure 2B and Figure 3A In the examples shown in FIG. 1 and FIG. 2 , the insulator 224 has the same top surface shape as the oxide semiconductor 230. However, Figure 2C As shown, the insulator 224 may also include a convex portion and the convex portion may also have the same top surface shape as the oxide semiconductor 230. Here, Figure 2C yes Figure 2B A modified example in which the shape of the insulator 224 is Figure 2B In this case, the thickness t2 of the insulator 250 in the openings of the insulators 280 and 275 is preferably smaller than the height t3 of the convex portion of the insulator 224. With this structure, the bottom surface of the conductor 260 (conductor 260a) located in the opening can be lower than the bottom surface of the oxide semiconductor 230 by the difference between the height t3 and the thickness t2 (t3-t2).

[0077] In addition, when etching the insulator 224, the etching rate of the insulator 224 is preferably higher than the etching rate of the insulator 222. By making the etching rate of the insulator 224 sufficiently higher than the etching rate of the insulator 222 (that is, by making the etching rate of the insulator 222 sufficiently lower than the etching rate of the insulator 224), the insulator 222 is not processed into the same top surface shape as the oxide semiconductor 230. Note that due to excessive etching of the insulator 224, a convex portion with a small step may be formed in the insulator 222. The convex portion has the same top surface shape as the oxide semiconductor 230.

[0078] In one embodiment of the present invention, the pillars used when processing the oxide semiconductor 230 are preferably removed after processing the oxide semiconductor 230. In the etching process when removing the pillars, a part of the insulator 224 can be processed while removing the pillars.

[0079] In addition, the insulator 224 may have a shape different from that of the oxide semiconductor 230 . FIG. 5A to FIG. 5D The semiconductor device shown in FIG. 1 shows that the shape of the insulator 224 is Figures 1A to 1D Examples of different structures. Fig. 7A yes Figure 5B An enlarged view of the oxide semiconductor 230 and its vicinity. FIG. 5A to FIG. 5D In the embodiment, the oxide semiconductor 230 has a circumferential structure and has a shape including an opening in the center when viewed from above, while the insulator 224 does not include an opening in the center and has a plate-like (or, also called, island-like) shape. FIG. 5A to FIG. 5DIn the structure shown, the shape of the outer periphery of the oxide semiconductor 230 is substantially consistent with the shape of the top surface of the insulator 224. The insulator 250 has a region in contact with the top surface of the insulator 224.

[0080] In the following FIG. 19A to FIG. 19D The manufacturing process shown is not performed after FIG. 20A to FIG. 20D The manufacturing process shown hereby forms FIG. 5A to FIG. 5D The structure shown. FIG. 5A to FIG. 5D The structure shown can be manufactured by fewer steps. By reducing the number of steps, the yield of semiconductor devices can be improved, and reliability can sometimes be improved.

[0081] On the other hand, FIG. 5A to FIG. 5D In the structure shown, the gate electric field is more easily applied to the lower end of the outer side of the circular oxide semiconductor 230 than to the inner side. That is, in the circular oxide semiconductor 230, the gate electric field is applied to the outer side and the inner side in different ways. As a result, there may be a region at the lower end of the oxide semiconductor 230 where the gate electric field is insufficiently applied. Therefore, it can be considered that FIG. 5A to FIG. 5D Compared with the structure shown in Figures 1A to 1D In the structure shown, the gate electric field is easily applied to the lower end portions of both the outer side surface and the inner side surface of the peripheral oxide semiconductor 230 , so the on-state current is further increased.

[0082] In addition, in a semiconductor device according to one embodiment of the present invention, FIG. 6A to FIG. 6D As shown, the insulator under the oxide semiconductor 230 may not be formed to have the same top surface shape as the oxide semiconductor 230 and may not have a convex portion.

[0083] FIG. 6A to FIG. 6D and Figures 1A to 1D The main difference is that: FIG. 6A to FIG. 6D In the semiconductor device shown, an insulator 224 b is provided under the oxide semiconductor 230 .

[0084] In the etching process when processing the oxide semiconductor 230 and the etching process when removing the pillars, the etching rate of the insulator 224b is preferably sufficiently low. Therefore, the insulator 224b and the insulator 224 are not processed into the same top surface shape as the oxide semiconductor 230. FIG. 6A to FIG. 6D Corresponds to Figures 1A to 1D , so the detailed structure can refer to the above records. Figure 7B yes Figure 6B An enlarged view of the vicinity of the oxide semiconductor 230 .

[0085] Note that when the etching process when processing the oxide semiconductor 230 and the etching process when removing the pillars have a sufficiently low etching rate similarly to the insulator 222 and the insulator 224b, as shown in FIG. Figure 7C As shown, the insulator 224 and the insulator 224b may be omitted in the semiconductor device. Figure 7C yes Figure 7B The modified example does not include the insulator 224 and the insulator 224b, which is the same as Figure 7B different.

[0086] [Oxide semiconductor layer] Here, an oxide semiconductor layer which can be used for the oxide semiconductor 230 is described. The oxide semiconductor layer includes a metal oxide.

[0087] When a metal oxide is used in a semiconductor layer of a transistor, lattice defects in the metal oxide may lead to the generation or capture of carriers. Therefore, when a metal oxide with many lattice defects is used in a semiconductor layer of a transistor, the electrical characteristics of the transistor may be unstable. Therefore, the lattice defects in the metal oxide used in the semiconductor layer of the transistor are preferably few. Lattice defects refer to point defects such as atomic vacancies and heterogeneous atoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids.

[0088] By using a crystalline metal oxide layer for an oxide semiconductor layer, the defect state density in the semiconductor layer can be reduced. Examples of the structure of a crystalline metal oxide include a CAAC (c-axis aligned crystal) structure, a polycrystalline (Poly-crystal) structure, and a microcrystalline (nc: nano-crystal) structure.

[0089] The metal oxide included in the oxide semiconductor layer of one embodiment of the present invention has a plurality of microcrystals. In addition, no clear grain boundary is observed between the plurality of microcrystals. Preferably, the metal oxide included in the oxide semiconductor layer of one embodiment of the present invention has a plurality of oriented microcrystals, and has a crystal structure in which the plurality of microcrystals are connected without clear grain boundaries when observed from the oriented direction.

[0090] The oxide semiconductor layer of one embodiment of the present invention includes a metal oxide having a crystal structure different from both a single crystal structure and a polycrystalline structure. The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure.

[0091] The CAAC structure refers to a crystal structure in which a plurality of crystallites (typically, a plurality of crystallites having a hexagonal crystal structure) have a c-axis orientation and are connected on the ab plane without clear grain boundaries. When a cross-section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM: Transmission Electron Microscope) image, it can be confirmed that the metal atoms are arranged in layers in the crystal part. Therefore, it can also be said that the oxide semiconductor layer having a CAAC structure has a layered crystal part. In the cross-section of the oxide semiconductor layer observed using a TEM image, metal atoms arranged in layers can be observed as bright spots. The bright spots are arranged, for example, in a direction parallel to the formed surface of the oxide semiconductor layer.

[0092] Note that a structure in which the metal atoms in each of the plurality of microcrystals are arranged in layers in a direction parallel or approximately parallel to the formed surface and the layers in which the metal atoms are arranged are stacked in a direction perpendicular or approximately perpendicular to the formed surface is sometimes referred to as a CAAC structure. When the microcrystal has the above structure, the crystal structure of the microcrystal is not limited to the hexagonal system. For example, a portion of the plurality of microcrystals may also have a crystal structure other than the hexagonal system (for example, a cubic system crystal structure).

[0093] The CAAC structure is formed, for example, in such a way that the c-axis is perpendicular or approximately perpendicular to the formed surface. In the CAAC structure, the metal atoms are arranged in layers in a direction parallel or approximately parallel to the formed surface. In the region having the CAAC structure, the angle of the c-axis relative to the formed surface is preferably within 90°±20° (above 70° and below 110°), more preferably within 90°±15° (above 75° and below 105°), more preferably within 90°±10° (above 80° and below 100°), and further preferably within 90°±5° (above 85° and below 95°).

[0094] The polycrystalline structure has a grain boundary. In addition, when a heat treatment is performed after the oxide semiconductor layer of the polycrystalline structure is formed, a small gap (also called nanocrack or microcrack) or a small space (also called nanospace or microspace) may be formed between the crystal part and the crystal part. If a small gap or a small space is formed in the oxide semiconductor layer, the resistance of the oxide semiconductor layer becomes high. This is because the resistance of the small gap or the small space is very high, for example, the resistance is infinite. When an oxide semiconductor layer with a small gap or a small space is used in the channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of the source electrode and the drain electrode becomes high. Therefore, this will have a negative impact on the initial characteristics or reliability of the transistor. On the other hand, no clear grain boundary is observed on the ab plane of the CAAC structure, so a semiconductor device with high reliability can be realized. In addition, since there are few grain boundaries, the barrier to carrier conduction in the channel of the transistor is small, and an increase in the on-state current can be expected. In addition, the increase in the resistance of the semiconductor layer of the transistor using the oxide semiconductor layer is suppressed, or the initial characteristics of the transistor (especially the on-state current) are improved, thereby expecting a transistor suitable for high-speed driving.

[0095] The channel formation region of the transistor preferably uses a metal oxide that increases the on-state current of the transistor. In order to increase the on-state current of the transistor, it is preferred to increase the mobility of the metal oxide used for the transistor. In order to increase the mobility of the metal oxide, it is necessary to increase the transmission of carriers (electrons in the case of n-channel transistors) or reduce the scattering factors that affect the transmission of carriers. In addition, carriers flow from the source to the drain through the channel formation region. Therefore, by setting a channel formation region where carriers easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0096] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED), or a combination of a plurality of the above methods.

[0097] When electron diffraction is performed on an oxide semiconductor layer having a CAAC structure, spots (bright spots) indicating c-axis orientation are observed in the electron diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to the normal vector of the formed surface of the oxide semiconductor layer or the normal vector of the surface of the oxide semiconductor layer.

[0098] Furthermore, an FFT pattern obtained by performing a fast Fourier transform (FFT) process on a TEM image reflects the same reciprocal spatial information as the electron diffraction pattern.

[0099] By obtaining a cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure and performing FFT processing on each region in the cross-sectional TEM pattern to manufacture an FFT pattern, the direction of the crystal axis of each region can be calculated based on the manufactured FFT pattern. Specifically, the direction of the line segment connecting two spots with high brightness and approximately equal distances from the center in the spots observed in the manufactured FFT pattern can be set as the direction of the crystal axis. The angle of the direction of the crystal axis of each region calculated from the FFT pattern relative to the formed surface is preferably 70° or more and 110° or less (within 90°±20°), more preferably 75° or more and 105° or less (within 90°±15°), more preferably 80° or more and 100° or less (within 90°±10°), and further preferably 85° or more and 95° or less (within 90°±5°) The region is regarded as a CAAC structure.

[0100] When the oxide semiconductor layer having the CAAC structure is observed from a direction perpendicular to the formed surface using a TEM image, a triangular or hexagonal atomic arrangement is observed on the ab plane, and it has crystallinity. In addition, in the Voronoi map produced by image analysis of the TEM image when the oxide semiconductor layer having the CAAC structure is observed from a direction perpendicular to the formed surface, pentagonal, hexagonal and heptagonal Voronoi regions are mainly observed, and hexagonal Voronoi regions are typically observed. For example, the proportion of hexagonal Voronoi regions in the Voronoi regions observed in the Voronoi map is greater than 30% and less than 100%.

[0101] The method for producing a Voronoi diagram is described below. First, when performing image analysis on a TEM image, after performing FFT processing, only a certain range of information is left through filtering, and an inverse fast Fourier transform is performed to produce an FFT filtered image. Lattice points are extracted from the produced FFT filtered image to produce perpendicular bisectors of line segments connecting adjacent lattice points. The points where three perpendicular bisectors intersect are set as Voronoi points, and the polygonal area surrounded by the line segments connecting the Voronoi points is set as the Voronoi area. In this way, a Voronoi diagram can be produced.

[0102] Note that, as an example, the observation range of the TEM when producing the Voronoi diagram may be a rectangular region with a vertical length of 50 nm and a horizontal length of 50 nm. Note that the observation range is not limited to this.

[0103] In addition, when the lattice points extracted by image analysis of the planar TEM image were used to analyze the distribution of the direction of the hexagonal lattice, the following state was observed: the difference in the direction of the hexagonal lattice at the boundary of two structures with different directions of the hexagonal lattice was small, the boundary was blurred, and the two structures were entangled and connected to each other. In other words, in the CAAC structure, no clear boundary was observed.

[0104] Note that the direction of the hexagonal lattice can be calculated from the direction of a hexagon formed by the six lattice points closest to each lattice point.

[0105] Note that there is no particular limitation on the crystallinity of the semiconductor material included in the oxide semiconductor layer. The oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystal region in part thereof). When the oxide semiconductor layer has crystallinity, degradation of transistor characteristics may be suppressed.

[0106] The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as the main component. Here, the metal oxide may contain indium as the main component, and may further contain element M. In addition, the metal oxide preferably contains two or three selected from indium, element M and zinc, and particularly preferably contains indium and zinc as the main components. Here, the metal oxide may contain indium and zinc as the main components, and may further contain element M. Note that element M is a metal element or a semi-metal element with a high bond energy with oxygen, for example, a metal element or a semi-metal element with a bond energy with oxygen higher than that of indium. As element M, specifically, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from gallium, tin, yttrium and aluminum, and further preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains any one or more selected from indium, gallium and zinc. Note that in this specification, etc., metal elements and semi-metal elements are sometimes collectively referred to as "metal elements", and the "metal elements" described in this specification, etc. sometimes include semi-metal elements.

[0107] The main component of the metal oxide refers to, for example, a metal element whose ratio with respect to all metal elements contained in the metal oxide is, for example, 0.1 atomic % or more or 1 atomic % or more.

[0108] In the cross section of the oxide semiconductor layer observed using the TEM image, it is observed that the metal atoms are arranged in a layered state in a direction parallel or approximately parallel to the formed surface. The metal atoms are observed as bright spots in the TEM image. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in a layered state. In addition, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in a layered state.

[0109] As a metal oxide of one embodiment of the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide (also referred to as ITSO) containing silicon, gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be cited. In addition, indium oxide can be used as a metal oxide in one embodiment of the present invention. In addition, gallium oxide, zinc oxide, etc. can be used as a metal oxide in one embodiment of the present invention.

[0110] When the ratio of the number of indium atoms to the total number of atoms of all metal elements in the metal oxide is increased, the transistor can obtain a large on-state current and high frequency characteristics.

[0111] Furthermore, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements in the metal oxide, the metal oxide can be made highly crystalline, thereby suppressing the diffusion of impurities in the metal oxide. As a result, the variation of the electrical characteristics of the transistor can be suppressed, and the reliability can be improved.

[0112] In addition, by increasing the ratio of the number of atoms of the element M to the total number of atoms of all metal elements in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers due to oxygen vacancies is suppressed, thereby realizing a transistor with a small off-state current. In addition, the variation of the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0113] Note that the metal oxide may also contain one or more metal elements with a large period number in the periodic table instead of indium. Alternatively, the metal oxide may also contain one or more metal elements with a large period number in addition to indium. There is a tendency that the greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large period number, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large period number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0114] In addition, the metal oxide may also contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field effect mobility of the transistor may sometimes be improved. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, fluorine, chlorine, bromine, and hydrogen.

[0115] [Method for producing oxide semiconductor layer] The oxide semiconductor layer according to one embodiment of the present invention can be produced by forming a metal oxide using two deposition methods.

[0116] When manufacturing an oxide semiconductor layer of one embodiment of the present invention, a metal oxide having a CAAC structure is deposited. At this time, by using a sputtering method as a deposition method, a metal oxide with high crystallinity can be formed. In addition, a deposition method such as a pulsed laser deposition (PLD) method can also be used.

[0117] Here, when the metal oxide is formed by the above-mentioned deposition method (hereinafter, the first deposition method), a mixed layer is sometimes formed at the interface between the metal oxide and the formed surface. This mixed layer may hinder the crystallization of the metal oxide. In advance, a metal oxide is formed as a first layer on the formed surface using a deposition method (hereinafter, the second deposition method) that causes less damage than the sputtering method, PLD method, etc. shown as the first deposition method, and then a metal oxide is formed as a second layer using the first deposition method, thereby suppressing the formation of a mixed layer at the interface between the oxide semiconductor layer and the formed surface. In addition, impurities contained in the formed surface can be suppressed from entering the second layer. As a result, the crystallinity of the second layer can be improved.

[0118] Compared with the sputtering method, the atomic layer deposition (ALD: Atomic Layer Deposition) method and the chemical vapor deposition (CVD: Chemical Vapor Deposition) method can suppress the damage to the formed surface, and are therefore suitable for use as a second deposition method. In addition, as the second deposition method, molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, wet method, etc. can be cited. As the CVD method, plasma CVD (PECVD: Plasma Enhanced CVD) method, thermal CVD method, optical CVD method, organic metal CVD (MOCVD: Metal Organic CVD) method, etc. can be cited. The MBE method is a deposition method that grows a thin film that reflects the crystal structure of the crystal system of the substrate, and can be said to be one of the deposition methods that causes less damage to the formed surface. The wet method is one of the deposition methods that causes less damage to the formed surface. As a wet method, for example, a spraying method can be cited.

[0119] In addition, a third layer may be further provided on the second layer. When forming the third layer, for example, the second deposition method may be used.

[0120] After the oxide semiconductor layer is deposited, heat treatment is preferably performed.

[0121] In a deposition method of an oxide semiconductor layer of one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductor layers (the first layer and the third layer) can be improved by using the second layer (i.e., CAAC) with high crystallinity as a core or seed. Thus, the crystallinity of the entire oxide semiconductor layer can be improved. In other words, by using the second layer as a core or seed to solid-phase grow metal oxides in the upper and lower oxide semiconductor layers, a highly crystalline oxide semiconductor layer can be formed. The oxide semiconductor layer formed by using this deposition method, specifically, the oxide semiconductor layer having a CAAC structure can also be referred to as axial growth (Axial Growth) CAAC (AG CAAC).

[0122] Even when a method that easily forms a metal oxide with high crystallinity is not used as a deposition method for the first layer and the third layer, the crystallinity of the first layer and the third layer can be improved by using the deposition method of the oxide semiconductor layer of one embodiment of the present invention. In addition, the heat treatment plays an auxiliary role in improving the crystallinity of the first layer and the third layer.

[0123] Below, refer to FIG. 8A to FIG. 8D An example of a method for manufacturing the oxide semiconductor 30 is described.

[0124] First, layer 29 is formed. Layer 29 corresponds to an insulating film or a conductive film included in the semiconductor device. As layer 29, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film can be used. Alternatively, as layer 29, for example, a conductive film used as an electrode of a semiconductor device can also be used. Layer 29 may not have crystallinity. In other words, layer 29 may have an amorphous structure. In addition, when layer 29 has crystallinity, it may have a crystal structure with low lattice matching with the metal oxide included in the oxide semiconductor 30.

[0125] Next, an oxide semiconductor 30a ( Fig. 8A ).

[0126] As described later, in a manufacturing method of one embodiment of the present invention, an oxide semiconductor 30b is formed by sputtering. In the case of depositing a metal oxide film by sputtering, a mixed layer (also referred to as alloying) of the components of the deposited metal oxide and the components of the layer of the formed surface is sometimes formed due to sputtering particles released from a target material or the like or energy applied to one side of the substrate by sputtering particles or the like. Due to alloying, the crystallization of the oxide semiconductor layer on the upper layer may be blocked. In addition, in the case of alloying, it is difficult to improve the crystallinity of the alloyed region even when the heat treatment described later is performed. In addition, there is a concern that by using an oxide semiconductor layer having an alloyed region for a transistor, the initial characteristics or reliability of the transistor are negatively affected.

[0127] Therefore, before forming the oxide semiconductor 30b, the oxide semiconductor 30a is formed in advance by a deposition method that causes little damage to the formed surface. In this way, the alloying of the components in the oxide semiconductor 30 and the components in the layer 29 can be suppressed to reduce the thickness of the alloyed region or to reduce the alloyed region to a level that is not observed. Here, the oxide semiconductor 30a is formed by the ALD method.

[0128] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant react using only thermal energy and a plasma ALD (PEALD: Plasma Enhanced ALD) method using a reactant excited by plasma.

[0129] The ALD method is different from a deposition method in which particles released from a target material are deposited. It is a deposition method in which a film is formed due to a reaction on the surface of the object being processed. The ALD method can deposit atoms layer by layer, thereby having the following effects: it can deposit extremely thin films; it can deposit on structures with high aspect ratios or surfaces with large steps; it can deposit in a manner with few defects such as pinholes; it can deposit with high coverage; it can deposit at low temperatures, etc. When the ALD method is used as a deposition method for the oxide semiconductor 30a and the oxide semiconductor 30c described later, the coverage of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be used to well cover steps, openings, etc. with high aspect ratios.

[0130] In addition, in the PEALD method, deposition can be performed at a lower temperature by using plasma, so it is sometimes preferred. In addition, the precursor used in the ALD method sometimes contains elements such as carbon or chlorine. Therefore, the film set by the ALD method sometimes contains more elements such as carbon or chlorine than the film set by other deposition methods.

[0131] Here, a method of forming an In-M-Zn oxide as the oxide semiconductor 30 a using the ALD method is described.

[0132] First, a source gas including a precursor containing indium is introduced into the processing chamber, and the precursor is adsorbed on the surface of layer 29. Next, an oxidant is introduced into the processing chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than indium are desorbed while indium is adsorbed on the substrate, thereby forming a layer in which indium and oxygen are bonded.

[0133] Next, a source gas including a precursor containing element M is introduced into the processing chamber, and adsorbed onto the layer in which indium and oxygen are bonded. Next, an oxidant is introduced into the processing chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than element M are desorbed while element M is adsorbed onto the substrate, thereby forming a layer in which element M and oxygen are bonded.

[0134] Next, a source gas including a precursor containing zinc is introduced into the processing chamber, and adsorbed onto the layer in which the element M and oxygen are bonded. Next, an oxidant is introduced into the processing chamber as a reactant, and the oxidant reacts with the adsorbed precursor, and components other than zinc are desorbed while zinc is adsorbed onto the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0135] By repeatedly performing the above method, an In—M—Zn oxide can be formed as the oxide semiconductor 30 a on the layer 29 by the ALD method.

[0136] The substrate heating temperature is preferably a temperature corresponding to the decomposition temperature of the precursor. Here, in a thermal ALD method using triethylindium as a precursor containing indium, triethylgallium as a precursor containing gallium, and diethylzinc as a precursor containing zinc, for example, the substrate heating temperature is 100° C. to 350° C., preferably 150° C. to 300° C.

[0137] In the above, it is preferred that after the precursor is adsorbed, the introduction of the source gas including the precursor is stopped, the process chamber is purged, and then the remaining precursor and reaction products, etc. are removed from the process chamber. In addition, in the above, it is preferred that after the adsorbed precursor and the oxidant are reacted, the introduction of the oxidant is stopped, the process chamber is purged, and then the remaining reactant and reaction products, etc. are removed from the process chamber.

[0138] In addition, in the description of this specification, etc., unless otherwise specified, when ozone (O3), oxygen (O2), and water (H2O) are used as reactants or oxidants, they also include a plasma state, a free radical state, and an ion state and are not limited to a gas state or a molecular state.

[0139] In addition, when the oxide semiconductor 30 a is formed by the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure whose crystallinity is lower than that of a CAAC structure may be formed.

[0140] Next, an In-M-Zn oxide ( Figure 8B ). The oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure.

[0141] Here, when the oxide semiconductor 30b is formed by sputtering, the mixed layer 31 is formed on the surface or near the surface of the oxide semiconductor 30a. In addition, due to sputtered particles or energy applied to the substrate side by the sputtered particles when the oxide semiconductor 30b is formed, a tiny crystalline region may be formed in the mixed layer 31. In the subsequent heat treatment process, at least a part of the oxide semiconductor 30a may be crystallized with the mixed layer 31 or the tiny crystalline region formed in the mixed layer 31 as a nucleus.

[0142] As a sputtering method, there can be cited an RF sputtering method in which a high-frequency power supply is used as a sputtering power supply, a DC sputtering method using a direct current power supply, and a pulsed DC sputtering method in which the voltage applied to the electrode is changed in a pulsed manner. The DC sputtering method can be suitable for the case of depositing a metal conductive film, and its deposition rate is high, so the productivity can be improved. The pulsed DC sputtering method can be suitable for the case of depositing a metal conductive film and a semiconductor film. In addition, when depositing an insulating film, the RF sputtering method can be appropriately utilized. Compounds such as oxides, nitrides, and carbides can be deposited by a reactive sputtering method using a reactive gas. When depositing a metal oxide for an oxide semiconductor layer of one embodiment of the present invention, it can be appropriately selected and deposited from the above methods according to the conductivity of the target material of the sputtering method, etc.

[0143] As a target material for the sputtering method, In-M-Zn oxide can be used. For example, when a metal oxide is formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas can be used as a sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the deposited oxide film can be increased.

[0144] In some cases, a metal oxide with higher crystallinity can be formed as the flow rate ratio of the oxygen gas to the entire deposition gas used in formation (hereinafter also referred to as the oxygen flow rate ratio) is higher.

[0145] In the case of forming a metal oxide by sputtering, an oxygen-excess metal oxide can sometimes be formed by depositing under the condition that the proportion of oxygen contained in the sputtering gas is higher than 30% and lower than 100%, preferably higher than 70% and lower than 100%. A transistor using an oxygen-excess oxide semiconductor layer in a channel formation region can obtain higher reliability. Note that one embodiment of the present invention is not limited to this. An oxygen-deficient metal oxide is formed by depositing under the condition that the proportion of oxygen contained in the sputtering gas is higher than 1% and lower than 30%, preferably higher than 5% and lower than 20%. A transistor using an oxygen-deficient metal oxide in a channel formation region can have a higher field effect mobility.

[0146] When the metal oxide is formed by sputtering, the composition of the formed metal oxide may be different from that of the sputtering target. In particular, the zinc content of the formed metal oxide may be reduced to about 50% of the zinc content in the sputtering target.

[0147] When the oxide semiconductor 30b is deposited by sputtering, the substrate is preferably heated. When a metal oxide is formed, a metal oxide with high crystallinity can sometimes be formed by increasing the substrate temperature (stage temperature) when the metal oxide is formed. When the oxide semiconductor 30b is deposited by sputtering, the substrate heating temperature is preferably, for example, 100°C or more and 400°C or less, and more preferably 200°C or more and 300°C or less.

[0148] Here, the formation model of the CAAC structure using the sputtering method is described. First, when sputtering deposition is performed, microcrystals are formed. Sometimes the microcrystals are formed due to sputtered particles (sometimes also referred to as atomic particles) or energy applied to one side of the substrate by gas particles, etc. In addition, sometimes planar or granular sputtered particles (sometimes also referred to as nanoclusters) that are peeled off from the sputtering target and deposited on the formed surface become the microcrystals. Then, the sputtered particles are adsorbed to the ends of the microcrystals, and the microcrystals grow in the lateral direction (a direction roughly parallel to the formed surface). When the microcrystals grow in the lateral direction, adjacent microcrystals are connected to each other, and the ends of the microcrystals disappear. When the ends of the microcrystals disappear, the sputtered particles are adsorbed to the microcrystals, and the microcrystals grow in the longitudinal direction (a direction roughly perpendicular to the formed surface). The sputtered particles are adsorbed to the ends of the microcrystals growing in the longitudinal direction, and the microcrystals grow in the lateral direction. In this way, the microcrystals repeatedly grow in the lateral direction and the longitudinal direction, thereby forming a CAAC structure. That is, the CAAC structure is formed by growing microcrystals using microcrystals in the oxide semiconductor as nuclei or seeds.

[0149] Note that it is not easy to form a CAAC structure in an oxide semiconductor mixed with impurities such as silicon, carbon, and water. Therefore, the oxide semiconductor 30b is preferably formed using a deposition method that does not easily mix with the above impurities. By using a sputtering target with a reduced impurity concentration and a deposition gas with a reduced impurity amount, an oxide semiconductor with a low impurity concentration can be formed, so the sputtering method can be suitable for the formation of the oxide semiconductor 30b.

[0150] Next, an oxide semiconductor 30c ( Figure 8C Here, the oxide semiconductor 30 c is formed by the ALD method. The formation method of the oxide semiconductor 30 a can be referred to for the formation of the oxide semiconductor 30 c by the ALD method.

[0151] When an oxide semiconductor 30c having a CAAC structure and having lower crystallinity than that of the CAAC structure is formed by the ALD method on the oxide semiconductor 30b having the CAAC structure, the oxide semiconductor 30c sometimes grows epitaxially with the oxide semiconductor 30b as a core. Therefore, when the oxide semiconductor 30c is formed, the oxide semiconductor 30c sometimes includes a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed in the entire oxide semiconductor 30c.

[0152] The oxide semiconductor 30c can be used as, for example, a layer in contact with a gate insulating layer of a transistor. By improving the crystallinity of the layer in contact with the gate insulating layer, the carrier mobility when the transistor is in an on state can be improved.

[0153] Furthermore, by forming the oxide semiconductor 30 c using the ALD method, damage to the oxide semiconductor 30 b can be reduced, so that the entire oxide semiconductor 30 can have high crystallinity.

[0154] By using the ALD method with high coverage as the deposition method of the oxide semiconductor 30a and the oxide semiconductor 30c, the entire oxide semiconductor layer can have high coverage. In addition, the oxide semiconductor 30b with high crystallinity is formed by sputtering, and the crystallinity of the upper and lower oxide semiconductor layers (oxide semiconductor 30a and oxide semiconductor 30c) is also improved due to the epitaxial growth of this layer, thereby improving the crystallinity of the entire layer of the oxide semiconductor 30. As a result, the oxide semiconductor 30 can have both high coverage and high crystallinity.

[0155] Next, a heat treatment step may be performed.

[0156] The heat treatment temperature can be, for example, above 100°C and below 800°C, preferably above 250°C and below 650°C, and more preferably above 350°C and below 550°C. Typically, it can be 400°C±25°C (above 375°C and below 425°C). In addition, the treatment time can be below 10 hours, above 1 minute and below 5 hours, or above 1 minute and below 2 hours. In addition, when using an RTA (Rapid Thermal Anneal) device, the treatment time can be, for example, above 1 second and below 5 minutes. Through this heat treatment, it can be expected that the gaps in the atomic-level crystal parts of the CAAC structure of the oxide semiconductor 30b will be repaired by the oxide semiconductor 30c (in other words, each crystal molecule formed by the ALD method).

[0157] There are no particular restrictions on the heating device used for heat treatment, and a device that heats the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element may also be used. For example, an electric furnace or an RTA device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device may be used. The LRTA device is a device that heats the object to be treated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment.

[0158] Through this heat treatment process, the crystallinity of the region having the CAAC structure in the oxide semiconductor 30c is sometimes improved. In addition, after deposition using the ALD method, when the region is formed only below the oxide semiconductor 30c, the region sometimes expands upward due to the heat treatment process ( Fig.8D ) That is, by performing this heat treatment, a region having a CAAC structure may be formed in the entire oxide semiconductor 30c.

[0159] In addition, by this heat treatment step, the oxide semiconductor 30 b may be further repaired by the oxide semiconductor 30 c (in other words, each crystal molecule formed by the ALD method) filling the gaps between the atomic-level crystal parts of the CAAC structure of the oxide semiconductor 30 b.

[0160] In addition, it is preferable that at least a portion of the oxide semiconductor 30a is converted into CAAC by the heat treatment step ( Fig.8D ). It can be expected that CAAC formation is easily caused by using the mixed layer 31 formed in the oxide semiconductor 30a when the oxide semiconductor 30b is deposited as a core or a seed. The CAAC formation region in the oxide semiconductor 30a is preferably large, preferably reaching the vicinity of the layer 29.

[0161] In addition, since CAAC is formed from the upper part to the lower part of the oxide semiconductor 30a, the vicinity of the layer 29 can also be CAAC-formed without being limited by the material or crystallinity of the layer 29. For example, even if the layer 29 has an amorphous structure, a highly crystalline oxide semiconductor 30a can be formed. Therefore, the method for manufacturing an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where the layer to be formed has an amorphous structure.

[0162] Alternatively, microwave treatment may be performed after the oxide semiconductor 30 c is formed.

[0163] Here, microwave treatment refers to, for example, treatment using a device including a power source for generating high-density plasma using microwaves. In addition, in this specification, microwave refers to electromagnetic waves having a frequency of more than 300 MHz and less than 300 GHz. Microwave treatment may also be referred to as microwave-excited high-density plasma treatment.

[0164] It is preferred to reduce the impurity concentration in the oxide semiconductor 30 by performing microwave treatment in an oxygen-containing atmosphere. As impurities, hydrogen and carbon can be cited in particular. Note that the above shows a structural example in which a metal oxide is subjected to microwave treatment in an oxygen-containing atmosphere, but is not limited to this. For example, an insulating film located near the metal oxide, more specifically a silicon oxide film, can also be subjected to microwave treatment in an oxygen-containing atmosphere. In addition, the heat during microwave treatment sometimes improves the crystallinity of the oxide semiconductor layer.

[0165] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably 10Pa or more and 1000Pa or less, more preferably 300Pa or more and 700Pa or less. The microwave treatment is preferably carried out in a state where the substrate is heated. The substrate temperature may be room temperature (e.g., 25°C) or more and 750°C or less, preferably 100°C or more and 500°C or less, more preferably 200°C or more and 500°C or less, further preferably 300°C or more and 500°C or less, further preferably 400°C or more and 500°C or less. For example, it may be 400°C or more and 450°C or less.

[0166] In addition, the heat treatment may be continuously performed after the microwave treatment without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100°C to 750°C, more preferably 300°C to 500°C, and further preferably 400°C to 450°C.

[0167] Microwave treatment can be performed using oxygen gas and argon gas, for example. By performing microwave treatment in an oxygen-containing atmosphere, microwaves or high frequencies such as RF can be used to ionize the oxygen gas, thereby allowing the oxygen plasma to act on the oxide semiconductor layer. Through the action of plasma, microwaves, etc., hydrogen enters the oxygen vacancy defects (hereinafter sometimes referred to as V O H) is split into oxygen vacancies and hydrogen, and hydrogen as an impurity is removed from the oxide semiconductor layer. In this way, V in the oxide semiconductor layer can be reduced. O H. In addition, at this time, carbon bonded to oxygen or hydrogen may be removed. In this way, impurities such as carbon or hydrogen can be reduced by microwave treatment. In addition, oxygen vacancies in the oxide semiconductor layer can be further reduced by supplying oxygen free radicals generated in the above-mentioned oxygen plasma to oxygen vacancies formed in the oxide semiconductor layer.

[0168] As oxygen injected into the oxide semiconductor layer, there are various states such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules or ions having unpaired electrons, also called O radicals). In addition, the oxygen injected into the oxide semiconductor layer can be in any one or more of the above states, and oxygen radicals are particularly preferred.

[0169] As described above, impurities in the oxide semiconductor layer can be reduced. By performing crystal growth in a state where the impurity concentration in the oxide semiconductor layer is reduced, crystallinity can be further improved.

[0170] Note that either or both of the above-mentioned heat treatment and microwave treatment may be performed directly on the oxide semiconductor layer, or may be performed after forming an insulating film or the like over the oxide semiconductor layer.

[0171] In addition, compared with an oxide semiconductor layer having a CAAC structure formed using one deposition method, any one or more of the relative dielectric constant, film density, and film hardness of the oxide semiconductor layer having a CAAC structure formed using the above-mentioned two deposition methods is sometimes higher.

[0172] By using an oxide semiconductor layer having a CAAC structure formed using the two deposition methods described above for the channel formation region of a transistor, a transistor having excellent characteristics (for example, a transistor with a large on-state current, a transistor with a high field effect mobility, a transistor with a small S value, a transistor with a high frequency characteristic (also called f characteristic) , a transistor with high reliability, etc.) can be realized.

[0173] In the oxide semiconductor 30 , the region having the CAAC structure preferably exists widely in the entire layer including the oxide semiconductor 30 a and the oxide semiconductor 30 c . Fig. 9A The oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c are all crystallized. The crystals of the region having the CAAC structure in the oxide semiconductor 30a are connected to the crystals of the region having the CAAC structure in the oxide semiconductor 30b. The crystals of the region having the CAAC structure in the oxide semiconductor 30c are connected to the crystals of the region having the CAAC structure in the oxide semiconductor 30b. Sometimes the oxide semiconductor 30 can be described as a layer in which no clear interface is observed. Sometimes the oxide semiconductor 30 can be described as a single layer.

[0174] The regions having the CAAC structure in the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c can be observed as bright spots arranged in a direction parallel to the formed surface, for example, in cross-sectional observation using a high-resolution TEM. In addition, the c-axis of the CAAC structure of the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c is preferably substantially parallel to the normal direction of the formed surface of the oxide semiconductor layer.

[0175] In addition, a part of the oxide semiconductor 30a or the oxide semiconductor 30c may not be crystallized. Fig. 9B In the example shown, the oxide semiconductor 30 a is in a non-crystallized state near the interface with the layer 29 . Fig. 9C The oxide semiconductor 30 c is shown in a state where the vicinity of the surface is not crystallized. Fig.9D The vicinity of the interface between the oxide semiconductor 30 a and the layer 29 and the vicinity of the surface of the oxide semiconductor 30 c are not crystallized.

[0176] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity as a whole. Therefore, in the oxide semiconductor 30, the boundaries between the stacked films in the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c are sometimes not confirmed. In particular, after heat treatment, it is sometimes difficult to confirm the boundaries between the stacked films. For example, the presence or absence of the boundaries between the stacked films can be confirmed using cross-sectional TEM, cross-sectional STEM, etc.

[0177] In addition, the lattice mismatch between the crystals included in the oxide semiconductor 30b and the crystals included in the oxide semiconductor 30a or the oxide semiconductor 30c is preferably small. Thus, the oxide semiconductor 30a or the oxide semiconductor 30c can form a crystal that reflects the orientation of the crystals included in the oxide semiconductor 30b. At this time, for example, when the cross-section of the oxide semiconductor 30 is observed using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formed surface are confirmed in the oxide semiconductor 30a or the oxide semiconductor 30c.

[0178] As long as the lattice mismatch between the crystal included in the oxide semiconductor 30b and the crystal included in the oxide semiconductor 30a or the oxide semiconductor 30c is small, there is no particular limitation on the crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c. The crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c may be any one of a cubic system, a tetragonal system, an orthorhombic system, a hexagonal system, a monoclinic system, and a trigonal system.

[0179] When or after the oxide semiconductor layer is deposited, it is preferred to perform a treatment for improving the crystallinity of the oxide semiconductor layer. As the above-mentioned treatment for improving the crystallinity of the oxide semiconductor layer, for example, heat treatment, plasma treatment, microwave treatment and light (for example, ultraviolet light) irradiation treatment can be cited. Note that multiple of the above-mentioned treatments can be performed simultaneously or in sequence. For example, heat treatment and microwave treatment can be performed simultaneously. Alternatively, microwave treatment can be performed after heat treatment.

[0180] In addition, it is more preferable to perform a treatment for improving the crystallinity of the oxide semiconductor layer multiple times when depositing the oxide semiconductor layer. For example, in the case of forming an oxide semiconductor layer by atomic layer deposition (ALD: Atomic Layer Deposition) method (hereinafter also referred to as ALD method), it is preferable to perform microwave treatment each time an atomic layer is formed. Alternatively, by performing a treatment for improving crystallinity each time an oxide semiconductor layer having a thickness in a predetermined range is formed, productivity can be improved, so it is preferred. Specifically, it is preferable to form a first oxide semiconductor layer of more than 1 nm and less than 10 nm and perform a first microwave treatment, and then form a second oxide semiconductor layer of more than 1 nm and less than 10 nm and perform a second microwave treatment. Note that there is no particular limitation on the deposition method of the first oxide semiconductor layer and the second oxide semiconductor layer, and the ALD method or sputtering method can be used respectively. In particular, by depositing the first oxide semiconductor layer by the ALD method, it is possible to prevent the elements of the layer constituting the formed surface from being mixed into the first oxide semiconductor layer and the second oxide semiconductor layer (also referred to as mixing), so it is preferred. In particular, it is suitable for the case where the element in the layer constituting the formed surface blocks the crystallization of the oxide semiconductor (for example, the case where silicon, carbon, etc. are included). In addition, the first oxide semiconductor layer and the second oxide semiconductor layer may also have different compositions. In addition, the stacked structure of the first oxide semiconductor layer and the second oxide semiconductor layer is shown here, but it is not limited to this. The same treatment can also be used when the oxide semiconductor layer has a single-layer structure or a stacked structure of three or more layers.

[0181] In addition, the treatment for improving the crystallinity of the oxide semiconductor layer may also be performed after the oxide semiconductor layer is deposited. Specifically, the treatment may be performed directly on the oxide semiconductor layer after deposition, or the treatment may be performed with other films such as an insulating film deposited on the oxide semiconductor layer interposed therebetween. For example, microwave treatment may be performed after the oxide semiconductor layer is deposited, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc.) may be deposited after the oxide semiconductor layer is deposited, and then one or more of heat treatment, plasma treatment, and microwave treatment may be performed on the oxide semiconductor layer with the insulating film interposed therebetween.

[0182] Note that the above-mentioned treatment for improving the crystallinity of the oxide semiconductor layer may also serve as a treatment for removing impurities in the oxide semiconductor layer. For example, carbon, hydrogen, nitrogen, etc. in the oxide semiconductor layer may be appropriately removed. Alternatively, by performing a treatment for improving the crystallinity of the oxide semiconductor layer in an oxygen gas atmosphere, oxygen vacancies in the oxide semiconductor layer may be reduced.

[0183] When performing a treatment for improving the crystallinity of the oxide semiconductor layer, the temperature of the substrate is preferably set to room temperature (e.g., 25° C.) or higher, 100° C. or higher and 600° C. or higher and 450° C. or lower. In addition, the temperature of the heat treatment is preferably 100° C. or higher and 700° C. or higher and 450° C. or lower.

[0184] The oxide semiconductor layer of one embodiment of the present invention can be used as a semiconductor layer of a transistor.

[0185] When the oxide semiconductor 30 is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor 30 is, for example, 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, further preferably 10 nm or more and 100 nm or less, further preferably 10 nm or more and 70 nm or less, further preferably 15 nm or more and 70 nm or less, further preferably 15 nm or more and 50 nm or less, further preferably 20 nm or more and 50 nm or less. In addition, in a transistor used for a more micro-sized semiconductor device, the thickness of the oxide semiconductor 30 is preferably 1 nm or more and 20 nm or less, more preferably 3 nm or more and 15 nm or less, further preferably 5 nm or more and 12 nm or less.

[0186] The oxide semiconductor 30 b is preferably 200 nm or less, for example. When the oxide semiconductor 30 b is in a layered state, the thickness is preferably 1 nm to 200 nm, more preferably 1 nm to 100 nm, and further preferably 2 nm to 100 nm.

[0187] Alternatively, if the oxide semiconductor 30 b can function as a crystal nucleus, the oxide semiconductor 30 b may exist not as a layer but as a collection of island-shaped regions. In this case, for example, the island-shaped regions included in the oxide semiconductor 30 b exist dispersedly.

[0188] The oxide semiconductor 30 a and the oxide semiconductor 30 c have a thickness of, for example, preferably 1 nm to 50 nm, more preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and even more preferably 2 nm to 20 nm.

[0189] The thickness of the region where the components in the oxide semiconductor 30 and the components in the layer 29 are alloyed is 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and even more preferably 0 nm to less than 0.3 nm. Note that Fig. 8A and Figure 8B An example is shown in which no alloyed region is formed between the layer 29 and the oxide semiconductor 30 a .

[0190] Note that the thickness of the alloyed region may be calculated by line analysis of the composition of the region and its periphery using secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX).

[0191] For example, the EDX line analysis is performed on the above-mentioned region and its periphery with the direction perpendicular to the formed surface of the oxide semiconductor 30a as the depth direction. Next, in the distribution of the quantitative values ​​of each element relative to the depth direction obtained by the analysis, the depth at which the quantitative value of the metal (In when the oxide semiconductor 30a contains In) which is the main component of the oxide semiconductor 30a but not the main component of the layer (here, layer 29) as the formed surface reaches half value is defined as the depth (position) of the interface between the above-mentioned region and the oxide semiconductor 30a. In addition, the depth at which the quantitative value of the element (e.g., Si) which is the main component of the layer as the formed surface but not the main component of the oxide semiconductor 30a reaches half value is defined as the depth (position) of the interface between the above-mentioned region and the layer as the formed surface. Through the above steps, the thickness of the alloyed region can be calculated.

[0192] For example, when a silicon oxide layer is used as the layer 29 and the oxide semiconductor 30 formed on the layer 29 is subjected to SIMS analysis, the depth at which the silicon concentration reaches 50% of the maximum concentration in the layer 29 is regarded as the interface, and the depth at which the silicon concentration decreases to 1.0×10 21 atoms / cm 3 , preferably reduced to 5.0×10 20 atoms / cm 3 , more preferably reduced to 1.0×10 20 atoms / cm 3The distance between the depth of and the interface is the thickness t_s. The thickness t_s is preferably 3 nm or less, more preferably 2 nm or less.

[0193] In addition, by reducing the alloying area, a CAAC structure can be formed near the formed surface. Here, near the formed surface refers to, for example, a region greater than 0 nm and less than 3 nm, preferably greater than 0 nm and less than 2 nm, and more preferably greater than 1 nm and less than 2 nm in a substantially vertical direction from the formed surface of the oxide semiconductor 30.

[0194] The oxide semiconductor 30a has, for example, a region that is 0 nm or more and 3 nm or less from the top surface of the layer 29. In addition, the oxide semiconductor 30c is, for example, located at a distance of 0 nm or more and 3 nm or less from the top surface of the oxide semiconductor 30. In addition, the thicknesses of the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c are, for example, substantially the same. Alternatively, the thicknesses of the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c may be different from each other.

[0195] Note that although the oxide semiconductor 30 has a three-layer structure of the oxide semiconductors 30a to 30c, the present invention is not limited thereto. The oxide semiconductor 30 may have a two-layer structure or a stacked-layer structure of four or more layers.

[0196] When the oxide semiconductor 30 has a two-layer structure, the oxide semiconductor 30 may have a structure in which an oxide semiconductor 30a and an oxide semiconductor 30b are stacked in sequence. By adopting the above structure, alloying of the components in the oxide semiconductor 30 and the components in the layer 29 can be suppressed, so that the thickness of the alloyed region can be reduced or the alloyed region can be reduced to a level that cannot be observed.

[0197] In addition, in the case where the oxide semiconductor 30 has a five-layer structure, the oxide semiconductor 30 may have a structure in which a first oxide semiconductor, a second oxide semiconductor, a third oxide semiconductor, a fourth oxide semiconductor, and a fifth oxide semiconductor are stacked in sequence. For example, the first oxide semiconductor, the third oxide semiconductor, and the fifth oxide semiconductor are preferably formed using the second deposition method, and more preferably formed using the ALD method. The second oxide semiconductor and the fourth oxide semiconductor are preferably formed using the first deposition method, and more preferably formed using the sputtering method. By adopting the above structure, even if the third oxide semiconductor has a composition that is not easy to form a CAAC structure, the crystal growth is promoted by one or both of the second oxide semiconductor and the fourth oxide semiconductor, thereby improving the crystallinity of the third oxide semiconductor.

[0198] When the oxide semiconductor 30 has a stacked structure of two or more layers, typically any stacked structure of two to five layers, it is preferred to continuously deposit each layer without being exposed to the atmosphere. For example, each layer may be continuously deposited using a multi-chamber deposition apparatus. Thus, the oxide semiconductor 30 can be deposited while suppressing impurities that may be mixed into each layer.

[0199] [c-axis orientation] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. For example, the crystal orientation can be used to evaluate the crystallinity of the oxide semiconductor layer of one embodiment of the present invention.

[0200] The CAAC structure of the oxide semiconductor layer can be evaluated using a graph showing crystal orientation in some cases. In a region having the CAAC structure, for example, a state in which crystals are oriented along the c-axis is observed.

[0201] For example, a cross-sectional TEM image is obtained, each region in the cross-sectional TEM image is subjected to a fast Fourier transform (FFT: Fast Fourier Transform) process to produce an FFT pattern, and the crystal axis direction of each region is calculated, thereby obtaining a diagram showing the crystal orientation. Specifically, for example, two spots with high intensity are observed in the FFT pattern of a region having a layered crystal portion. The crystal axis direction of the region can be obtained from the angle of the line segment connecting the two spots. The FFT pattern reflects the same reciprocal space information as the electron diffraction pattern.

[0202] By calculating the ratio of the c-axis oriented region in the graph showing the crystal orientation, the c-axis orientation degree can be calculated.

[0203] In the oxide semiconductor layer of one embodiment of the present invention, for example, a cross-sectional or planar TEM observation of the oxide semiconductor layer can be performed, and the c-axis orientation degree can be calculated using the above-mentioned diagram showing the crystal orientation. In addition, the region where FFT is performed (also referred to as the FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0204] When analyzing using a cross-sectional TEM image, for example, the observation range of the cross-sectional TEM image can be set to a region having a vertical direction perpendicular to the formed surface and a width of 100 nm in the horizontal direction. Note that the observation range is not limited to this.

[0205] In the oxide semiconductor layer of one embodiment of the present invention, when the c-axis orientation degree is calculated as the ratio of the area within 20° of the c-axis difference, the c-axis orientation degree is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and further preferably 95% or more.

[0206] In addition, the c-axis orientation degrees of the region deposited as the oxide semiconductor 30a, the region deposited as the oxide semiconductor 30b, and the region deposited as the oxide semiconductor 30c are Rc1, Rc2, and Rc3, respectively. Here, the c-axis orientation degree is preferably calculated as the proportion of the region whose difference with the c-axis is within 20°, for example. Rc2 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and further preferably 95% or more. In addition, Rc3 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and further preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. In addition, Rc2 / Rc1 is preferably greater than 1.

[0207] [Composition of Oxide Semiconductor Layer] The composition of the oxide semiconductor 30a is preferably different from the composition of the oxide semiconductor 30b. In addition, the composition of the oxide semiconductor 30c is preferably different from the composition of the oxide semiconductor 30b. In addition, the oxide semiconductor 30a can use the same composition as the oxide semiconductor 30c. Alternatively, the composition of the oxide semiconductor 30a can also be different from the composition of the oxide semiconductor 30c.

[0208] The oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 30b preferably contains zinc, for example. By containing zinc, a metal oxide with high crystallinity can be obtained. In addition, the oxide semiconductor 30b preferably contains an element M in addition to zinc. By making the oxide semiconductor 30b contain the element M, for example, the formation of oxygen vacancies in the metal oxide can be suppressed. As the oxide semiconductor 30b, specifically, a metal oxide having the following composition can be used: In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto. In addition, the nearby composition includes a range of ±30% of the desired atomic ratio. In addition, as the element M, one or more of gallium, tin, yttrium and aluminum are preferably used.

[0209] The oxide semiconductor 30b may not contain the element M. For example, In-Zn oxide may also be used. Specifically, it may be a composition of In:Zn=1:1 [atomic ratio] or a composition near it, a composition of In:Zn=2:1 [atomic ratio] or a composition near it, or a composition of In:Zn=4:1 [atomic ratio] or a composition near it. Alternatively, indium oxide may also be used. In addition, a trace amount of element M may also be contained. For example, it may be a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition near it, or a composition of In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition near it. In addition, for example, it may be a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition near it, or a composition of In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition near it.

[0210] The oxide semiconductor 30a and the oxide semiconductor 30c can use a metal oxide with a high In ratio. It is particularly preferred that the oxide semiconductor 30a and the oxide semiconductor 30c use a metal oxide with a high In ratio compared to the oxide semiconductor 30b. The oxide semiconductor 30a and the oxide semiconductor 30c can be formed, for example, using an ALD method. In addition, it is particularly preferred to use a metal oxide with a higher In ratio than the element M. By using a metal oxide with a high In ratio, when the oxide semiconductor layer is used for a transistor, the on-state current can be increased and the frequency characteristics can be improved.

[0211] The oxide semiconductor with a high content of In has a polycrystallization inclination. When a metal oxide with a polycrystalline structure is used in a transistor, it has a negative impact on the initial characteristics or reliability of the transistor. The oxide semiconductor layer of one embodiment of the present invention can reflect the crystal orientation of the oxide semiconductor 30b to the oxide semiconductor 30a and the oxide semiconductor 30c with a high content of In. Thus, even when a metal oxide with a high content of In is used as the oxide semiconductor 30a and the oxide semiconductor 30c, polycrystallization can be suppressed.

[0212] In addition, the oxide semiconductor 30a and the oxide semiconductor 30c may not contain the element M. For example, In-Zn oxide may also be used. Specifically, it may be a composition of In:Zn=1:1 [atomic ratio] or a composition near it, In:Zn=2:1 [atomic ratio] or a composition near it, or In:Zn=4:1 [atomic ratio] or a composition near it. Alternatively, indium oxide may also be used. In addition, the oxide semiconductor 30a and the oxide semiconductor 30c may also contain a trace amount of the element M. Specifically, it may be a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition near it, In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition near it, In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition near it, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition near it.

[0213] In addition, a metal oxide with a high Ga ratio can be used as the oxide semiconductor 30a and the oxide semiconductor 30c. For example, a metal oxide with a high Ga ratio compared to the oxide semiconductor 30b can be used as the oxide semiconductor 30a and the oxide semiconductor 30c. For example, the oxide semiconductor 30a and the oxide semiconductor 30c preferably use a metal oxide with a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition near it, a metal oxide with a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition near it, or a metal oxide with a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition near it. By increasing the Ga ratio, the band gaps of the oxide semiconductors 30a and 30c can sometimes be made larger than the oxide semiconductor 30b. As a result, the oxide semiconductor 30b is sandwiched by the oxide semiconductors 30a and 30c with large band gaps, and the oxide semiconductor 30b can be mainly used as a current path (channel). In addition, the trap energy levels at the interface of the oxide semiconductor 30b and its vicinity can be reduced. Thus, a buried channel transistor with a channel away from the insulating layer interface can be realized, thereby improving the field effect mobility. In addition, the influence of the interface state formed on the back channel side is reduced, and the light degradation of the transistor (for example, light negative bias degradation) can be suppressed, thereby improving the reliability of the transistor.

[0214] Alternatively, a metal oxide having a higher In content than the oxide semiconductor 30 b may be used as one of the oxide semiconductor 30 a and the oxide semiconductor 30 c , and a metal oxide having a higher Ga content than the oxide semiconductor 30 b may be used as the other.

[0215] Alternatively, a plurality of layers having the above composition may be stacked in the oxide semiconductors 30a, 30b, and 30c. For example, the oxide semiconductor 30c may have a structure in which a metal oxide having a high In content is stacked on a metal oxide having a high Ga content.

[0216] Alternatively, the oxide semiconductor 30a and the oxide semiconductor 30c may use a metal oxide having the same composition as the oxide semiconductor 30b. By using the same composition, CAAC formation after heat treatment may be easily achieved.

[0217] In addition, in the oxide semiconductor layer of one embodiment of the present invention, even if the oxide semiconductor 30a and the oxide semiconductor 30c have a composition that does not easily form a CAAC structure when formed as a single layer, the entire oxide semiconductor layer including the oxide semiconductor 30a and the oxide semiconductor 30c can have a CAAC structure by causing crystal growth with the oxide semiconductor 30b as a core. Alternatively, the region including at least a portion of each of the oxide semiconductor 30a and the oxide semiconductor 30c to the region of the oxide semiconductor 30b can have a CAAC structure.

[0218] In the composition analysis of the metal oxide used for the oxide semiconductor 30, for example, EDX, X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy), inductively coupled plasma mass spectrometry (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry) or inductively coupled plasma atomic emission spectrometry (ICP-AES: Inductively Coupled Plasma-Atomic Emission Spectrometry) can be used. In addition, multiple of the above methods can also be combined for analysis. Note that elements with low contents are sometimes affected by the accuracy of analysis, and the actual contents are different from the contents obtained by analysis. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content.

[0219] [Impurities in oxide semiconductors] Here, the influence of each impurity in the oxide semiconductor is described. Quantification of impurities in the oxide semiconductor can be performed using XPS, SIMS, EDX, ICP-MS, ICP-AES, or the like.

[0220] In the channel formation region of a transistor using an oxide semiconductor as a semiconductor layer, it is preferred that the channel formation region has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the source region and the drain region. O ) and impurities, the electrical characteristics are likely to change and may lead to a decrease in reliability. In addition, hydrogen near the oxygen vacancy forms V O H may generate electrons that become carriers. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor tends to have a normally-on characteristic. Therefore, in the channel formation region, V O H is also preferably reduced. Thus, the channel formation region of the transistor is a high resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0221] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. As impurities, hydrogen, carbon, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to elements other than the main components of oxide semiconductors. For example, elements whose concentration is less than 1 atomic% or less than 0.1 atomic% are sometimes called impurities.

[0222] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, a defect state is formed in the oxide semiconductor. Thus, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 In addition, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS was set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19atoms / cm 3 Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 the following.

[0223] In addition, when the oxide semiconductor contains nitrogen, electrons as carriers are generated, which increases the carrier concentration and is easily converted to n-type. As a result, transistors using oxide semiconductors containing nitrogen as semiconductors tend to have normally-on characteristics. Alternatively, when the oxide semiconductor contains nitrogen, trap states are sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0224] In addition, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, thereby sometimes forming oxygen vacancies. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to oxygen bonded to metal atoms. Therefore, transistors using oxide semiconductors containing hydrogen tend to have normally-on characteristics. Therefore, it is preferred to reduce the hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19 atoms / cm 3 , and more preferably less than 5×10 18 atoms / cm 3 , and further preferably less than 1×10 18 atoms / cm 3, and further preferably less than 1×10 17 atoms / cm 3 .

[0225] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to generate carriers. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Thus, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0226] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0227] [Structural example of transistor] The average thickness of the oxide semiconductor 30 in the channel formation region is preferably 30 nm or less, more preferably 15 nm or less, and further preferably 10 nm or less.

[0228] The oxide semiconductor 30 a is an oxide semiconductor layer formed on a surface to be formed. The thickness of the oxide semiconductor 30 a is preferably not less than 0.5 nm and not more than 3 nm.

[0229] In addition, in a semiconductor device of one embodiment of the present invention, when observing a cross section of the oxide semiconductor 230, it is sometimes possible to confirm that metal atoms of the metal oxide are arranged in layers in a region having a CAAC structure. In this case, for example, the metal atoms are arranged in a direction perpendicular or substantially perpendicular to the substrate surface.

[0230] In the cross section of the oxide semiconductor layer observed using the TEM image, the metal atoms arranged in layers in the region having the CAAC structure can be observed as bright spots. Thus, in the semiconductor device of one embodiment of the present invention, when observing the cross section of the oxide semiconductor 230, it is sometimes possible to observe that the bright spots are arranged in a direction perpendicular or substantially perpendicular to the substrate surface.

[0231] The oxide semiconductor 30 of AG CAAC can be used as the oxide semiconductor 230 of the transistor 200. For example, Figure 2B and Figure 3AAs shown, the oxide semiconductor 230 may have a structure including an oxide semiconductor 230a, an oxide semiconductor 230b in contact with the oxide semiconductor 230a, and an oxide semiconductor 230c in contact with the oxide semiconductor 230b. Here, the oxide semiconductor 230a corresponds to the oxide semiconductor 30a, the oxide semiconductor 230b corresponds to the oxide semiconductor 30b, and the oxide semiconductor 230c corresponds to the oxide semiconductor 30c.

[0232] Here, the above-mentioned pillar (a stack of layer 293 and layer 292) corresponds to layer 29. That is, the formed surface of the oxide semiconductor 230 is a pillar, and the pillar is removed in the transistor 200. In the manufacturing process, one side of the oxide semiconductor 230a is in contact with the pillar and the other side is in contact with the oxide semiconductor 230b. After removing the pillar, one side of the oxide semiconductor 230a is in contact with the insulator 250. One side of the oxide semiconductor 230b is in contact with the oxide semiconductor 230a and the other side is in contact with the oxide semiconductor 230c. One side of the oxide semiconductor 230c is in contact with the oxide semiconductor 230b and the other side is in contact with the insulator 250. Here, the side of the pillar is formed perpendicularly or approximately perpendicularly to the substrate surface (which may also be referred to as the surface of the insulator 222), whereby the side of the oxide semiconductor 230 (oxide semiconductors 230a to oxide semiconductors 230c) is also perpendicularly or approximately perpendicular to the substrate surface.

[0233] As described above, in the cross section of the oxide semiconductor 230 (oxide semiconductor 230a to oxide semiconductor 230c) observed using the TEM image, it is confirmed that the metal atoms are arranged in layers in a direction parallel or approximately parallel to the formed surface. In other words, in the cross section of the oxide semiconductor 230 (oxide semiconductor 230a to oxide semiconductor 230c) observed using the TEM image, it is confirmed that the metal atoms are arranged in layers in a direction perpendicular or approximately perpendicular to the substrate surface. In addition, it can also be said that the c-axis of the Axial Growth CAAC is approximately parallel to the normal direction of the side surface of the oxide semiconductor 230.

[0234] In this way, by using the oxide semiconductor 230 of AG CAAC in the channel formation region of the transistor 200 , a transistor having excellent on-state current, field effect mobility, S value, frequency characteristics, and reliability can be provided.

[0235] In addition, as described above, when the oxide semiconductor 230 has a three-layer structure of the oxide semiconductor 230a to the oxide semiconductor 230c, the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are sequentially formed around the region where the pillar is formed. Fig. 10A As shown, when viewed in a cross section in the channel width direction, oxide semiconductor 230c, oxide semiconductor 230b, oxide semiconductor 230a, oxide semiconductor 230a, oxide semiconductor 230b, and oxide semiconductor 230c are symmetrically arranged in order. That is, in order to make oxide semiconductor 230 have a bilaterally symmetrical structure when viewed in a cross section, oxide semiconductor 230a and oxide semiconductor 230c preferably have substantially the same composition. In addition, oxide semiconductor 230a and oxide semiconductor 230c preferably have substantially the same thickness. In addition, in Figure 2B When the angle θ is greater than or equal to 80° and less than 90°, that is, when the side surface of the oxide semiconductor 230 is slightly inclined, as shown in FIG. Fig. 10B As shown in FIG. 1 , the inclinations of the oxide semiconductors 230 are arranged symmetrically. In addition, when the oxide semiconductors 230 are formed obliquely, as shown in FIG. Fig. 10B As shown, the upper portion of the oxide semiconductor 230 is sometimes thinner than the lower portion of the oxide semiconductor 230. Fig. 10C An example is shown in which the angle θ exceeds 90°.

[0236] The oxide semiconductor 230 includes a channel formation region of the transistor 200 and a source region and a drain region disposed so as to sandwich the channel formation region. At least a portion of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region may be swapped.

[0237] Since the channel formation region has fewer oxygen vacancies or lower impurity concentration than the source region and the drain region, the channel formation region is a high resistance region with low carrier concentration. Therefore, the channel formation region can be said to be an i-type (intrinsic) or substantially i-type region.

[0238] In addition, due to the large number of oxygen vacancies or the high concentration of impurities such as hydrogen, nitrogen, and metal elements, the source region and the drain region are low-resistance regions with high carrier concentration. That is, the source region and the drain region are n-type regions (low-resistance regions) with higher carrier concentration than the channel formation region.

[0239] The carrier concentration in the channel formation region is preferably 1×10 18 cm -3 Below, less than 1×10 17 cm -3 , less than 1×10 16 cm -3 , less than 1×10 15 cm -3 , less than 1×10 14 cm -3 , less than 1×1013 cm -3 , less than 1×10 12 cm -3 , less than 1×10 11 cm -3 or less than 1×10 10 cm -3 Note that there is no particular restriction on the lower limit of the carrier concentration in the channel formation region, and it can be, for example, 1×10 -9 cm -3 .

[0240] In the case where the purpose is to reduce the carrier concentration of the oxide semiconductor 230, the impurity concentration in the oxide semiconductor 230 can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor (or metal oxide) with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).

[0241] In order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the channel formation region of the oxide semiconductor 230. In order to reduce the impurity concentration of the oxide semiconductor 230, it is preferable to also reduce the impurity concentration in the nearby film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc. Note that the impurities in the oxide semiconductor 230 refer to, for example, elements other than the main components constituting the oxide semiconductor 230. For example, an element having a concentration of less than 0.1 atomic % can be said to be an impurity.

[0242] In addition, it is sometimes difficult to clearly observe the boundaries between regions in the oxide semiconductor 230. The concentrations of the metal elements and impurity elements such as hydrogen and nitrogen detected in each region are not limited to changing in stages for each region, but may also change gradually in each region. That is, the closer to the channel formation region, the lower the concentration of the metal elements and impurity elements such as hydrogen and nitrogen may be.

[0243] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in the region where the oxide semiconductor forms a channel, the electrical characteristics are easily changed, and reliability is sometimes reduced. In addition, hydrogen near the oxygen vacancy forms a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H) and may generate electrons that become carriers. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor is likely to have a normally-on characteristic (a characteristic in which a channel exists and current flows in the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V OH. In other words, the channel formation region in the oxide semiconductor is preferably a region in which the carrier concentration is reduced and the region is made i-type (intrinsic) or substantially i-type.

[0244] In contrast, by providing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen can be supplied from the insulator to the oxide semiconductor to reduce oxygen vacancies and V O H. Note that when too much oxygen is supplied to the source region or the drain region, the on-state current of the transistor 200 may decrease or the field effect mobility may decrease. Furthermore, when the amount of oxygen supplied to the source region or the drain region is uneven within the substrate surface, the characteristics of the semiconductor device including the transistor become uneven. In addition, when the oxygen supplied from the insulator to the oxide semiconductor diffuses to the conductor such as the gate electrode, the source electrode and the drain electrode, the conductor is sometimes oxidized, which leads to a loss of conductivity, thereby having a negative impact on the electrical characteristics and reliability of the transistor.

[0245] Therefore, in the oxide semiconductor, it is preferred that the channel formation region is an i-type or substantially i-type region with a reduced carrier concentration, and the source region and the drain region are n-type regions with a high carrier concentration. In other words, it is preferred to reduce oxygen vacancies and V O H. In addition, it is preferable that the source region and the drain region are not supplied with excessive oxygen and that V O The amount of H is not excessively reduced. In addition, it is preferable to have a structure that suppresses reduction in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor may form V O H, so in order to reduce V O H amount, it is necessary to reduce the hydrogen concentration.

[0246] Therefore, in this embodiment, the semiconductor device has a structure in which the hydrogen concentration in the channel formation region is reduced, oxidation of the conductors 242a, 242b, and 260 is suppressed, and reduction in the hydrogen concentration in the source region and the drain region is suppressed.

[0247] As a material surrounding the oxide semiconductor layer, for example, as a material for an insulator in contact with the oxide semiconductor layer, it is preferred to use a material with a small amount of released hydrogen. As the material with a small amount of released hydrogen, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, etc. can be cited. Thus, hydrogen can be suppressed from mixing into the oxide semiconductor layer. In particular, when silicon nitride is used for at least one of the insulators in contact with the oxide semiconductor layer, the reliability of the transistor can be improved. Note that the material with a small amount of released hydrogen sometimes has the function of capturing or fixing hydrogen (also called doping) inside the insulator.

[0248] In addition, the insulator 250 in contact with the channel formation region in the oxide semiconductor 230 preferably has a function of trapping or fixing hydrogen. Thus, the hydrogen concentration in the channel formation region of the oxide semiconductor 230 can be reduced. Therefore, the V O H makes the channel formation region i-type or substantially i-type.

[0249] Here, if Figure 2A As shown, the insulator 250 preferably has a stacked structure of an insulator 250a in contact with the oxide semiconductor 230, an insulator 250b on the insulator 250a, an insulator 250c on the insulator 250b, and an insulator 250d on the insulator 250c. At this time, the insulator 250a and the insulator 250c preferably have a function of capturing or fixing hydrogen.

[0250] As an insulator having the function of capturing or fixing hydrogen, a metal oxide having an amorphous structure can be cited. As the insulator 250a and the insulator 250c, for example, a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium is preferably used. The above-mentioned metal oxide having an amorphous structure sometimes has the following property: the oxygen atom has a dangling bond and hydrogen is captured or fixed by the dangling bond. That is, it can be said that the metal oxide having an amorphous structure has a high ability to capture or fix hydrogen.

[0251] Insulator 250a and insulator 250c preferably use a high dielectric constant (high-k) material. In addition, as an example of a high-k material, there is an oxide containing one or both of aluminum and hafnium. When a high-k material is used as insulator 250a and insulator 250c, the gate potential applied when the transistor is operating can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0252] As the insulator 250 a and the insulator 250 c , it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0253] In this embodiment, an aluminum oxide film is used as the insulator 250a. In addition, the aluminum oxide film preferably has an amorphous structure. Here, by providing the insulator 250a in contact with the oxide semiconductor 230, hydrogen contained in the oxide semiconductor 230 and the like can be more effectively captured and fixed.

[0254] In this embodiment, hafnium oxide is used as the insulator 250c. Here, by providing the insulator 250c between the insulator 250b and the insulator 250d, hydrogen contained in the insulator 250b and the like can be more effectively captured and fixed.

[0255] Next, as the insulator 250 b, a thermally stable insulator such as silicon oxide or silicon oxynitride is preferably used. Note that in this specification, etc., oxynitride refers to a material whose oxygen content is higher than the nitrogen content, and oxynitride refers to a material whose nitrogen content is higher than the oxygen content. For example, when silicon oxynitride is described, this refers to a material whose oxygen content is higher than the nitrogen content, and when silicon nitride oxide is described, this refers to a material whose nitrogen content is higher than the oxygen content.

[0256] The silicon oxide film used as the insulator 250b is preferably formed by a PEALD method.

[0257] Furthermore, in order to suppress oxidation of the conductors 242a, 242b, and 260, an oxygen blocking insulator is preferably provided near each of the conductors 242a, 242b, and 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulators 250a, 250d, 250c, and 275.

[0258] Note that in this specification, etc., a blocking insulator refers to an insulator having a barrier property. In this specification, etc., having a barrier property means having a property of hindering the penetration of a corresponding substance (also referred to as low permeability). For example, an insulator having a barrier property has a property that a corresponding substance does not easily diffuse into the inside of the insulator. For example, an insulator having a barrier property has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulator.

[0259] As the oxygen blocking insulator, for example, an oxide containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon oxynitride can be cited. In addition, as the oxide containing one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate) can be cited. For example, the insulator 250a, the insulator 250c, the insulator 250d, and the insulator 275 preferably have a single-layer structure or a stacked-layer structure of the above-mentioned oxygen blocking insulator.

[0260] The insulator 250a preferably has an oxygen barrier property. The insulator 250a is preferably at least less likely to allow oxygen to penetrate than the insulator 280. The insulator 250a has a region in contact with the side surface of the conductor 242a and the side surface of the conductor 242b. When the insulator 250a has an oxygen barrier property, it is possible to suppress the side surfaces of the conductor 242a and the conductor 242b from being oxidized and forming an oxide film on the side surfaces. Therefore, it is possible to suppress a decrease in the on-state current of the transistor 200 or a decrease in the field effect mobility.

[0261] In addition, the insulator 250a is provided in contact with the top surface and the side surface of the oxide semiconductor 230 and the top surface of the insulator 222. When the insulator 250a has oxygen barrier properties, it is possible to suppress the release of oxygen from the channel formation region of the oxide semiconductor 230 during heat treatment or the like. Thus, oxygen vacancies formed in the oxide semiconductor 230 can be reduced.

[0262] In addition, by providing the insulator 250a, excessive oxygen is suppressed from being supplied from the insulator 280 to the oxide semiconductor 230, and an appropriate amount of oxygen can be supplied to the oxide semiconductor 230. Thus, a decrease in the on-state current or a decrease in the field effect mobility of the transistor 200 due to excessive oxidation of the source region and the drain region can be suppressed.

[0263] Since an oxide containing one or both of aluminum and hafnium has an oxygen barrier property, it can be suitably used as the insulator 250 a .

[0264] The insulator 250d also preferably has oxygen barrier properties. The insulator 250d is provided between the channel formation region of the oxide semiconductor 230 and the conductor 260 and between the insulator 280 and the conductor 260. By adopting this structure, it is possible to suppress the diffusion of oxygen in the channel formation region of the oxide semiconductor 230 into the conductor 260 and the formation of oxygen vacancies in the channel formation region of the oxide semiconductor 230. In addition, it is possible to suppress the diffusion of oxygen in the oxide semiconductor 230 and oxygen in the insulator 280 into the conductor 260 and the oxidation of the conductor 260. The insulator 250d is preferably at least less likely to allow oxygen to penetrate than the insulator 280. For example, a silicon nitride film is preferably used as the insulator 250d. In this case, the insulator 250d is an insulator containing at least nitrogen and silicon.

[0265] In addition, the insulator 250 d preferably has a hydrogen barrier property, so that impurities such as hydrogen contained in the conductor 260 can be prevented from diffusing into the oxide semiconductor 230 .

[0266] The insulator 275 also preferably has oxygen barrier properties. The insulator 275 is provided between the insulator 280 and the conductor 242a and between the insulator 280 and the conductor 242b. The insulator 275 is provided in a manner in contact with the side surface of the conductor 242, the side surface of the oxide semiconductor 230, and the top surface of the insulator 222. By adopting this structure, it is possible to suppress the diffusion of oxygen contained in the insulator 280 into the conductor 242. Therefore, it is possible to suppress the oxidation of the conductor 242 due to the oxygen contained in the insulator 280, so that the resistivity increases. The insulator 275 is preferably at least less likely to allow oxygen to penetrate than the insulator 280. For example, silicon nitride is preferably used as the insulator 275. At this time, the insulator 275 is an insulator containing at least nitrogen and silicon.

[0267] In order to suppress a decrease in the hydrogen concentration in the source region and the drain region of the oxide semiconductor 230 , a hydrogen blocking insulator is preferably provided near the source region and the drain region. In the semiconductor device described in this embodiment, the hydrogen blocking insulator is, for example, the insulator 275 .

[0268] Examples of the hydrogen barrier insulator include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 preferably has a single-layer structure or a stacked-layer structure of the above hydrogen barrier insulators.

[0269] By providing the insulator 275, the diffusion of hydrogen from the source region and the drain region to the outside can be reduced, thereby suppressing the reduction of the hydrogen concentration in the source region and the drain region. Therefore, the source region and the drain region can be made n-type.

[0270] By adopting the above structure, the channel forming region can be made i-type or substantially i-type and the source region and the drain region can be made n-type, thereby providing a semiconductor device with good electrical characteristics. By adopting the above structure, even if the semiconductor device is miniaturized or highly integrated, it can have good electrical characteristics. In addition, by miniaturizing the transistor 200, the high-frequency characteristics can be improved. Specifically, the cut-off frequency can be increased.

[0271] Insulators 250a to 250d are used as part of the gate insulator. Insulators 250a to 250d are arranged in an opening formed in insulator 280 together with conductor 260. In order to achieve miniaturization of transistor 200, the thickness of insulators 250a to 250d is preferably small. The thickness of insulators 250a to 250d is preferably 0.1nm or more and 10nm or less, more preferably 0.1nm or more and 5.0nm or less, further preferably 0.5nm or more and 5.0nm or less, further preferably 1.0nm or more and less than 5.0nm, and further preferably 1.0nm or more and 3.0nm or less. In addition, at least a portion of each of insulators 250a to 250d includes a region having the above-mentioned thickness.

[0272] In addition, the thickness of the silicon oxide film used as the insulator 250 is preferably greater than or equal to 0.7 nm and less than or equal to 3 nm.

[0273] In order to reduce the thickness of the insulators 250a to 250d as described above, it is preferred to use an atomic layer deposition (ALD) method for deposition. In addition, in order to set the insulators 250a to 250d in the openings of the insulator 280, etc., it is preferred to use an ALD method for deposition. The ALD method includes a thermal ALD method that uses only thermal energy to react precursors and reactants, and a PEALD (Plasma Enhanced ALD) method that uses reactants excited by plasma. In the PEALD method, deposition can be performed at a lower temperature by using plasma, so it is sometimes preferred.

[0274] The ALD method can deposit atoms layer by layer, and thus has the advantages of being able to deposit extremely thin films, being able to deposit structures with high aspect ratios, being able to deposit with fewer defects such as pinholes, being able to deposit with high coverage, and being able to deposit at low temperatures. Therefore, the insulator 250 with a small thickness can be deposited with high coverage on the side surfaces of the opening formed in the insulator 280 and the side ends of the conductors 242a and 242b.

[0275] Note that the precursor used in the ALD method sometimes contains carbon, etc. Therefore, a film formed by the ALD method sometimes contains more impurities such as carbon than a film formed by other deposition methods. In addition, the quantitative analysis of impurities can be performed using secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy), or Auger electron spectroscopy (AES: Auger Electron Spectroscopy).

[0276] Note that in the above description, the insulator 250 has a four-layer structure of the insulators 250a to 250d, but the present invention is not limited thereto. The insulator 250 may have a structure including at least one of the insulators 250a to 250d. By forming the insulator 250 with one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified, thereby improving productivity.

[0277] For example, Fig.11A As shown, the insulator 250 may also have a three-layer structure. In this case, the insulator 250 preferably has a stacked structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. Figure 2A The structure shown is a structure in which the insulator 250d is removed.

[0278] When forming the insulator 250, it is preferred to perform the ALD process twice or more. For example, it is preferred that the insulator 250 has a stacked structure consisting of a plurality of insulating films, and two or more of the plurality of insulating films are formed by the ALD process. By forming at least two or more insulating films by the ALD process, the coverage and thickness uniformity of the insulator 250 can be improved. In addition, by continuously forming two or more different films such as two or more insulating films by the ALD process, productivity can be improved.

[0279] In addition to the above structure, it is preferred to have a structure that suppresses hydrogen from being mixed into the transistor 200, etc. For example, it is preferred that an insulator having a function of suppressing hydrogen diffusion is provided in a manner that covers one or both of the top and bottom of the transistor 200, etc. In the semiconductor device described in this embodiment, the insulator is, for example, an insulator 283, an insulator 282, an insulator 222, and an insulator 221, etc. In addition, the insulator 215 provided under the transistor 200 may also have the same structure as either or both of the insulator 282 and the insulator 283. In this case, the insulator 215 may have a stacked structure of the insulator 282 and the insulator 283, a structure in which the insulator 282 is located below and the insulator 283 is located above, or a structure in which the insulator 282 is located above and the insulator 283 is located below.

[0280] One or more of the insulator 283, the insulator 282, the insulator 222, and the insulator 221 are preferably used as a blocking insulator for inhibiting the diffusion of impurities such as water and hydrogen from the substrate side or the top of the transistor 200 to the transistor 200. Therefore, one or more of the insulator 283, the insulator 282, the insulator 222, and the insulator 221 preferably include an insulating material having a function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (not allowing the above impurities to pass through). In addition, it is preferred to include an insulating material having a function of inhibiting the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (not allowing the above oxygen to pass through).

[0281] Insulator 283, insulator 282, insulator 222, and insulator 221 preferably all include an insulator having a function of inhibiting the diffusion of impurities such as water and hydrogen and oxygen, and for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon oxynitride, etc., can be used. For example, silicon nitride with higher hydrogen barrier properties is preferably used for insulator 283 and insulator 221. In addition, for example, aluminum oxide with high ability to capture or fix hydrogen is preferably used for insulator 282. In addition, for example, hafnium oxide with high ability to capture or fix hydrogen and a high dielectric constant (high-k) material is preferably used for insulator 222.

[0282] Note that, in addition to the materials described above, a stacked structure of silicon oxide or silicon oxynitride may be used as at least one of the insulator 221 and the insulator 222. For example, a stacked structure of silicon nitride and silicon oxide may be used as the insulator 221. Also, for example, a stacked structure of hafnium oxide and silicon oxide may be used as the insulator 222.

[0283] By adopting such a structure, it is possible to suppress impurities such as water and hydrogen from diffusing from an interlayer insulating film or the like disposed above the insulator 283 to the transistor 200 or the like. In addition, it is possible to suppress impurities such as water and hydrogen from diffusing from an interlayer insulating film or the like disposed below the insulator 221 to the transistor 200 or the like. In addition, hydrogen in the insulator 280 and the insulator 250 or the like can be captured or fixed to the insulator 282 or the insulator 222. In addition, by providing the insulator 282 and the insulator 283, it is possible to suppress oxygen in the insulator 280 or the like from diffusing to the top of the transistor 200 or the like. In addition, by providing the insulator 222 and the insulator 221, it is possible to suppress oxygen in the oxide semiconductor 230 or the like from diffusing to the bottom of the transistor 200 or the like. In this way, by adopting a structure in which the upper and lower parts of the transistor 200 are surrounded by an insulator having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen, it is possible to reduce the diffusion of excess oxygen and hydrogen to the oxide semiconductor. Thus, it is possible to achieve improvement in the electrical characteristics and reliability of the semiconductor device.

[0284] Insulator 275 and insulator 250d are preferably made of silicon nitride or the like having a higher hydrogen barrier property. Insulator 250a is preferably made of aluminum oxide or the like having a high ability to capture or fix hydrogen. Insulator 250c is preferably made of hafnium oxide or the like having a high ability to capture or fix hydrogen.

[0285] As the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to use a conductive material that is not easily oxidized or a conductive material having a function of inhibiting oxygen diffusion. As the conductive material, for example, a conductive material containing nitrogen and a conductive material containing oxygen can be cited. Thus, the conductivity of the conductor 242a, the conductor 242b, and the conductor 260 can be suppressed from decreasing. When a conductive material containing metal and nitrogen is used as the conductor 242a, the conductor 242b, and the conductor 260, the conductor 242a, the conductor 242b, and the conductor 260 are conductors containing at least metal and nitrogen.

[0286] The conductor 242a and the conductor 242b are arranged to be separated from each other and are provided in contact with the oxide semiconductor 230. Figure 3C As shown in FIG. 1 and FIG. 2 , the conductor 242 is provided so as to cover the oxide semiconductor 230 having a high aspect ratio. Figure 1C As shown, the conductor 242 a (conductor 242 b ) preferably has a structure in contact with two or more fin-shaped regions of the oxide semiconductor 230 when viewed in cross section.

[0287] Here, near the source or drain of the transistor 200, such as Figure 3CAs shown in FIG. 1 , the conductor 242a is provided in a folded state sandwiching the oxide semiconductor 230. Thus, when viewed in a cross section in the channel width direction, the conductor 242a is in contact with the oxide semiconductor 230 at the upper portion of the oxide semiconductor 230, the side surface on the A3 side, and the side surface on the A4 side. Thus, compared with the case where the oxide semiconductor 230 is formed into a flat plate, the contact area between the conductor 242a and the oxide semiconductor 230 is increased by the size of the side surface on the A3 side and the side surface on the A4 side of the oxide semiconductor 230. Furthermore, as Figure 1C As shown in FIG. 1 , when a structure is adopted in which a plurality of fin-shaped regions of the oxide semiconductor 230 are in contact with the conductor 242 a, the contact area can be further increased. Figure 3C and Figure 1C 2 shows the vicinity of the conductor 242a, but the same is true for the conductor 242b. That is, similar to the conductor 242a and the oxide semiconductor 230 described above, the contact area between the conductor 242b and the oxide semiconductor 230 is increased.

[0288] As described above, when the contact area between the conductor 242 and the oxide semiconductor 230 is increased, the on-state current, frequency characteristics, etc. of the transistor 200 can be improved without increasing the occupied area of ​​the transistor 200. Thus, a semiconductor device with a fast operating speed can be provided. In addition, the operating speed of a storage device using the semiconductor device can be increased. Thus, miniaturization or high integration of the semiconductor device can be achieved. In addition, the storage capacity of the storage device using the semiconductor device can be increased.

[0289] Since the conductor 242a and the conductor 242b are in contact with the oxide semiconductor 230, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion. Thus, the conductivity of the conductor 242a and the conductor 242b can be suppressed from decreasing. In addition, it is possible to suppress the extraction of oxygen from the oxide semiconductor 230 to form excessive oxygen vacancies. In addition, when a material that is easy to absorb (extract) hydrogen is used as the conductor 242a and the conductor 242b, the hydrogen concentration of the oxide semiconductor 230 can be reduced, so it is preferred.

[0290] As the conductor 242, metal nitrides are preferably used, for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. In one embodiment of the present invention, nitrides containing tantalum are particularly preferably used. In addition, for example, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. can also be used. These materials are conductive materials that are not easily oxidized or materials that maintain conductivity even if oxygen is absorbed, so they are preferred.

[0291] Note that hydrogen contained in the oxide semiconductor 230 or the like may diffuse into the conductor 242a or the conductor 242b. In particular, when a nitride containing tantalum is used as the conductor 242a or the conductor 242b, hydrogen contained in the oxide semiconductor 230 or the like may easily diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide semiconductor 230 or the like may be absorbed by the conductor 242a or the conductor 242b.

[0292] In addition, in order to suppress the decrease in the conductivity of the conductor 242a and the conductor 242b, a crystalline oxide such as CAAC-OS can be used as the oxide semiconductor 230. In particular, it is preferable to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. When CAAC-OS is used, it is possible to suppress the conductor 242a or the conductor 242b from extracting oxygen from the oxide semiconductor 230. In addition, it is possible to suppress the decrease in the conductivity of the conductor 242a and the conductor 242b.

[0293] In addition, if Fig. 11B As shown, the conductor 242a and the conductor 242b may also have a two-layer structure. The conductor 242a may be a laminated film of the conductor 242a1 and the conductor 242a2 on the conductor 242a1, and the conductor 242b may be a laminated film of the conductor 242b1 and the conductor 242b2 on the conductor 242b1. At this time, as the layer in contact with the oxide semiconductor 230 (the conductor 242a1 and the conductor 242b1), it is preferred to use the above-mentioned conductive material that is not easily oxidized or a conductive material having a function of inhibiting oxygen diffusion. Thus, the conductivity of the conductor 242a and the conductor 242b can be suppressed from decreasing. In addition, it is possible to suppress the extraction of oxygen from the oxide semiconductor 230 to form excessive oxygen vacancies. In addition, when a material that easily absorbs (extracts) hydrogen is used as the layer in contact with the oxide semiconductor 230 (the conductor 242a1 and the conductor 242b1), the hydrogen concentration of the oxide semiconductor 230 can be reduced, so it is preferred.

[0294] The electrical conductivity of the conductor 242a2 and the conductor 242b2 is preferably higher than that of the conductor 242a1 and the conductor 242b1. For example, the thickness of the conductor 242a2 and the conductor 242b2 is preferably greater than that of the conductor 242a1 and the conductor 242b1. As the conductor 242a2 and the conductor 242b2, a conductor that can be used for the conductor 260b described later can be used. By adopting the above structure, the resistance of the conductor 242a2 and the conductor 242b2 can be reduced. As a result, the on-state current of the transistor 200 can be increased to improve the operating speed of the semiconductor device according to this embodiment.

[0295] For example, tantalum nitride or titanium nitride can be used as the conductor 242 a 1 and the conductor 242 b 1 , and tungsten can be used as the conductor 242 a 2 and the conductor 242 b 2 .

[0296] In addition, if Fig. 11C As shown, when viewed from a cross section in the channel length direction of transistor 200, conductor 242a1 and conductor 242b1 may also protrude more than conductor 242a2 and conductor 242b2, respectively. The protruding portions of conductor 242a1 and conductor 242b1 are covered by insulator 250. Here, the distance between conductor 242a1 and conductor 242b1 is smaller than the distance between conductor 242a2 and conductor 242b2. By adopting this structure, the distance between the source and the drain can be further reduced and the channel length can be reduced accordingly. Therefore, the frequency characteristics of transistor 200 can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0297] like Figure 1B and Figure 1D As shown, the conductor 260 is disposed in the opening formed in the insulator 280 and the insulator 275. The conductor 260 covers the top surface of the insulator 222, the side surface of the oxide semiconductor 230, and the top surface of the oxide semiconductor 230 via the insulator 250 in the opening. In addition, the height of the top surface of the conductor 260 is consistent or substantially consistent with the height of the uppermost portion of the insulator 250 and the top surface of the insulator 280.

[0298] In the above-mentioned opening where the conductor 260 and the insulator 250 are arranged, the side wall of the opening may be vertical or substantially vertical to the top surface of the insulator 222, or may have a tapered shape. By making the side wall have a tapered shape, the coverage of the insulator 250 and the like provided in the opening of the insulator 280 is improved, so defects such as voids can be reduced.

[0299] The conductor 260 is used as a first gate electrode of the transistor 200. Figure 1A and Figure 1B As shown in FIG. 1 , the conductor 260 is preferably arranged to extend in the channel width direction. By adopting such a structure, the conductor 260 can be used as wiring when a plurality of transistors are arranged.

[0300] A portion of the conductor 260 is provided so as to be folded in half across the fin-shaped oxide semiconductor 230. Figure 2B and Figure 3AAs shown, when viewed in a cross section in the channel width direction, the oxide semiconductor 230 and the conductor 260 are arranged opposite to each other via the insulator 250 on the upper part of the oxide semiconductor 230, the side surface on the A1 side, and the side surface on the A2 side. That is, the upper part of the oxide semiconductor 230, the side surface on the A1 side, and the side surface on the A2 side are all used as channel formation regions. Therefore, compared with the case where the oxide semiconductor 230 is formed in a flat plate shape, the channel width of the transistor 200 is increased by the size of the side surface on the A1 side and the side surface on the A2 side of the oxide semiconductor 230.

[0301] exist Figure 1D In the embodiment, the conductor 260 has a two-layer structure. Here, the conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom surface and the side surface of the conductor 260b. At this time, as the conductor 260a, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion.

[0302] As the conductor 260a, it is preferred to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. In addition, it is preferred to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0303] In addition, when the conductor 260a has a function of suppressing oxygen diffusion, it is possible to suppress the decrease in conductivity caused by oxidation of the conductor 260b by oxygen contained in the insulator 280, etc. As a conductive material having a function of suppressing oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0304] In addition, the conductor 260b preferably uses a conductor with high conductivity. For example, the conductor 260b can use a conductive material with tungsten, copper or aluminum as a main component. In addition, the conductor 260b can have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive materials.

[0305] In addition, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to be embedded in an opening formed in the insulator 280 or the like. Here, the side surface of the insulator 280 in the above-mentioned opening is aligned or substantially aligned with the side surface of the conductor 242a and the side surface of the conductor 242b. Therefore, the conductor 260 can be arranged so as to overlap with the region between the conductor 242a and the conductor 242b without performing position alignment.

[0306] The relative dielectric constant of each of the insulator 216 and the insulator 280 is preferably lower than that of the insulator 222. By using a material having a low relative dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0307] For example, the insulator 216 and the insulator 280 preferably include one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having holes.

[0308] In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they easily form a region containing oxygen released by heating.

[0309] In addition, the top surfaces of the insulator 216 and the insulator 280 may also be planarized.

[0310] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. For example, an oxide containing silicon, such as silicon oxide or silicon oxynitride, is preferably used as the insulator 280 .

[0311] The conductor 240a and the conductor 240b are both formed in the openings of the insulators 275, 280, 282, and 283. The bottom surface of the conductor 240a is in contact with the top surface of the conductor 242a, and the bottom surface of the conductor 240b is in contact with the top surface of the conductor 242b. Here, the height of the top surface of the conductor 240 is substantially the same as the height of the top surface of the insulator 283.

[0312] The conductor 240 preferably uses a conductive material mainly composed of tungsten, copper or aluminum. Alternatively, the conductor 240 may also have a laminated structure in which a first conductive material is provided in contact with the side of the insulator 241 and a second conductive material is provided inside the first conductive material. In this case, the above conductive material may be used as the second conductive material. Here, the above first conductive material corresponds to Figure 3C The conductor 240a1 shown, the second conductor corresponds to Figure 3C Conductor 240a2 is shown.

[0313] In addition, when a stacked structure is used as the conductor 240, a conductive material having a function of inhibiting the penetration of impurities such as water and hydrogen is preferably used as the first conductor disposed near the insulator 283, the insulator 282, the insulator 280, and the insulator 275. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. are preferably used. In addition, a single layer or a stacked layer of a conductive material having a function of inhibiting the penetration of impurities such as water and hydrogen may also be used. By adopting such a structure, impurities such as water and hydrogen contained in the layer above the insulator 283 can be inhibited from mixing into the oxide semiconductor 230 through the conductor 240a and the conductor 240b.

[0314] Insulators 241a and 241b are formed to contact the inner walls of the openings of insulators 275, 280, 282, and 283. The inner side surface of insulator 241a contacts conductor 240a, and the inner side surface of insulator 241b contacts conductor 240b.

[0315] As the insulator 241, a blocking insulating film that can be used for the insulator 275 or the like can be used. For example, as the insulator 241, an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride can be used. By providing the insulator 241, it is possible to suppress impurities such as water and hydrogen contained in the insulator 280 or the like from being mixed into the oxide semiconductor 230 through the conductors 240a and 240b. In particular, silicon nitride is preferred because it has a high hydrogen barrier property. In addition, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b.

[0316] The insulator 241 has a Figure 1D In the case of a stacked structure as shown, it is preferable to use an oxygen blocking insulating film and a hydrogen blocking insulating film in combination as a first insulator in contact with the inner wall of the opening such as the insulator 280 and a second insulator inside the first insulator.

[0317] For example, aluminum oxide deposited by thermal ALD may be used as the first insulator, and silicon nitride deposited by PEALD may be used as the second insulator. By adopting such a structure, oxidation of the conductor 240 can be suppressed, and hydrogen entering the conductor 240 can be reduced.

[0318] Note that, although the above example shows that the insulator 241 has a two-layer stacked structure, the present invention is not limited to this. For example, the insulator 241 may also have a single-layer structure or a stacked structure of three or more layers. In addition, although the above example shows that the conductor 240 has a two-layer stacked structure, the present invention is not limited to this. For example, the conductor 240 may also have a single-layer structure or a stacked structure of three or more layers.

[0319] For example, Figure 3CAs shown, the conductor 240a may also have a structure that covers the oxide semiconductor 230 and the conductor 242a that is folded in half by sandwiching the oxide semiconductor 230. Thus, when viewed in a cross section in the channel width direction, the conductor 240a is in contact with the conductor 242a at the upper portion of the oxide semiconductor 230, the side surface on the A3 side, and the side surface on the A4 side. Therefore, compared with the case where the oxide semiconductor 230 is formed into a flat plate, the contact area between the conductor 240a and the conductor 242a is increased by the size of the side surface on the A3 side and the side surface on the A4 side of the oxide semiconductor 230. Furthermore, as Figure 1C As shown, by adopting a structure in which the conductor 240a covers a plurality of fin-shaped regions of the oxide semiconductor 230, the contact area between the conductor 240a and the conductor 242a can be further increased. Note that Figure 3C and Figure 1C Although the vicinity of the conductor 240a and the conductor 242a is shown, the same is true for the conductor 240b and the conductor 242b. That is, similar to the conductor 240a and the conductor 242a described above, the contact area between the conductor 240b and the conductor 242b is increased.

[0320] As described above, when the contact area between the conductor 240 and the conductor 242 increases, the contact resistance between the conductor 240 and the conductor 242 can be reduced. Thus, the on-state current, frequency characteristics, etc. of the transistor 200 can be improved without increasing the occupied area of ​​the transistor 200. Thus, a semiconductor device with a fast operating speed can be provided. In addition, the operating speed of a storage device using the semiconductor device can be increased. Thus, miniaturization or high integration of the semiconductor device can be achieved. In addition, the storage capacity of the storage device using the semiconductor device can be increased.

[0321] Note that in the above, Figure 1A As shown, the shape of the opening provided with the conductor 240 and the insulator 241 when viewed from above is a quadrangular shape, but is not limited to this. For example, the shape of the opening when viewed from above may also be a circular shape, an ellipse or other approximate circular shape, a quadrangular shape or other polygonal shape, or a quadrangular shape or other polygonal shape with an arc at the corner. In addition, the opening is formed in a manner overlapping with the multiple fin-shaped regions of the oxide semiconductor 230, but is not limited to this, and may be formed in a manner overlapping with at least the conductor 242a or the conductor 242b. When a portion of the conductor 240 overlaps with the oxide semiconductor 230, the configuration space of the conductor 240 can be increased. In addition, the opening and the conductor 240 may also be provided in an area that does not overlap with the oxide semiconductor 230.

[0322] In addition, Figure 1DIn the embodiment, the conductor 240a and the conductor 240b are symmetrically arranged with the conductor 260 as the center, but the present invention is not limited to this. When viewed from the cross section in the channel length direction, a portion of the conductor 240a may overlap with the oxide semiconductor 230, and the conductor 240b may not overlap with the oxide semiconductor 230. In addition, when viewed from the cross section in the channel length direction, the conductor 240a may be arranged at a position overlapping with the oxide semiconductor 230, and the conductor 240b may be arranged at a position not overlapping with the oxide semiconductor 230.

[0323] <Variation Example 1 of Semiconductor Device> like FIG. 12A to FIG. 12D As shown, the semiconductor device of this embodiment may also have a structure in which a conductor 205 is provided under an insulator 221. The conductor 205 has a region that serves as a second gate electrode (lower gate electrode) of the transistor 200. In addition, the insulator 224, the insulator 222, and the insulator 221 all have a region that serves as a second gate insulator of the transistor 200. Here, FIG. 12A to FIG. 12D Corresponds to Figures 1A to 1D , so the detailed structure can refer to the above records.

[0324] In the transistor 200, the conductor 205 is arranged so as to overlap with the oxide semiconductor 230 and the conductor 260. Here, the conductor 205 is preferably provided so as to be embedded in the opening formed in the insulator 216. Fig. 12A and Fig. 12B As shown in FIG. 1 , the conductor 205 is preferably arranged to extend in the channel width direction. By adopting such a structure, the conductor 205 can be used as wiring when a plurality of transistors are arranged.

[0325] like Fig. 12B and Fig.12D As shown, the conductor 205 preferably includes a conductor 205a and a conductor 205b. The conductor 205a is provided in a manner of contacting the bottom surface and the side wall of the above-mentioned opening. The conductor 205b is provided in a manner of being embedded in the concave portion of the conductor 205a formed along the above-mentioned opening. Here, the height of the top surface of the conductor 205 is consistent or substantially consistent with the height of the top surface of the insulator 216.

[0326] Here, as the conductor 205a, it is preferred that the conductor 205a includes a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. Alternatively, it is preferred that the conductor 205a includes a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0327] By using a conductive material having a function of reducing hydrogen diffusion as the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing to the oxide semiconductor 230 through the insulator 216 and the like. In addition, by using a conductive material having a function of inhibiting oxygen diffusion as the conductor 205a, it is possible to inhibit the conductor 205b from being oxidized and the conductivity from being reduced. As the conductive material having a function of inhibiting oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide can be cited. The conductor 205a can have a single-layer structure or a stacked-layer structure of the above-mentioned conductive material. For example, the conductor 205a preferably contains titanium nitride.

[0328] In addition, the conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 205b preferably contains tungsten.

[0329] The conductor 205 can be used as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by independently changing the potential applied to the conductor 205 without linking it with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be further increased and the off-state current can be reduced. Thus, compared with the case where the negative potential is not applied to the conductor 205, when the negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0V can be reduced.

[0330] In addition, the resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the thickness of the conductor 205 is set according to the resistivity. In addition, the thickness of the insulator 216 is substantially the same as that of the conductor 205. Here, it is preferred to reduce the thickness of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205. By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so the diffusion of the impurities into the oxide semiconductor 230 can be suppressed.

[0331] Note that in the above structure, a stacked structure of the conductor 205a and the conductor 205b is shown, but the present invention is not limited thereto, and the conductor 205 may have a single-layer structure or a stacked structure of three or more layers. For example, when the conductor 205 has a three-layer stacked structure, a stacked structure may be adopted in the conductor 205a and the conductor 205b, and a conductor made of the same material as the conductor 205a may be provided on the conductor 205b. In this case, the conductor may be formed in a manner embedded in a recess formed by the conductor 205a and the conductor 205b, and the recess is formed in a manner such that the top surface of the conductor 205b is lower than the uppermost portion of the conductor 205a.

[0332] <Materials Constituting Semiconductor Devices> The constituent materials that can be used for the semiconductor device are described below. Note that each layer constituting the semiconductor device may have a single-layer structure or a stacked-layer structure.

[0333] <<Substrate>> As a substrate for forming a transistor, for example, an insulator substrate, a semiconductor substrate or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.) and a resin substrate can be cited. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide or gallium oxide can be cited. In addition, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate can also be cited, such as an SOI (Silicon On Insulator) substrate. As a conductor substrate, for example, a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate can be cited. In addition, as a substrate, for example, a substrate containing a metal nitride, a substrate containing a metal oxide, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator can be cited. Alternatively, the above-mentioned substrate provided with one or more elements can also be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light emitting element, and a memory element.

[0334] <<Insulator>> Insulators such as insulator 215, insulator 216, insulator 221, insulator 222, insulator 224, insulator 224b, insulator 250, insulator 275, insulator 280, insulator 282, and insulator 283 may include, for example, insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0335] As an insulator, a single layer or a stack of insulators containing one or more of aluminum, magnesium, germanium, indium, gallium, zinc, yttrium, neodymium, tantalum, hafnium, zirconium, lanthanum, chromium, manganese, iron, cobalt, nickel, molybdenum, tungsten, cerium, calcium, strontium, tin, titanium, vanadium, barium, antimony, silicon, germanium, boron and phosphorus can be used.

[0336] For example, when miniaturization and high integration of transistors are being carried out, problems such as leakage current may occur due to the thin filming of the gate insulator. By using a high-k material as an insulator used as a gate insulator, it is possible to achieve a low voltage when the transistor is operating while maintaining the physical thickness. On the other hand, by using a material with a low relative dielectric constant for an insulator used as an interlayer film, it is possible to reduce the parasitic capacitance generated between wirings. Therefore, it is preferable to select a material according to the function of the insulator.

[0337] Examples of insulators having a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0338] Examples of insulators having a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having vacancies, and resins.

[0339] In addition, by surrounding a transistor using a metal oxide with an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, a single layer or stack of an insulator containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium and tantalum can be used. Specifically, as an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be cited.

[0340] In addition, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, when a structure is adopted in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide semiconductor 230, oxygen vacancies contained in the oxide semiconductor 230 can be filled.

[0341] <<Conductor>> As the conductors such as the conductor 240a, the conductor 240b, the conductor 242a, the conductor 242b, the conductor 260, and the conductor 205, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the above metal elements as a component or an alloy combining the above metal elements. Examples of the conductor include tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred. In addition, semiconductors with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus or silicides such as nickel silicide can also be used.

[0342] In the case of using a conductor with a stacked structure, for example, a stacked structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen, a stacked structure combining a material containing the above-mentioned metal element and a conductive material containing nitrogen, or a stacked structure combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

[0343] In addition, when an oxide is used in the channel formation region of the transistor, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen is preferably used as a conductor used as a gate electrode. In this case, the conductive material containing oxygen is preferably arranged on one side of the channel formation region. By arranging the conductive material containing oxygen on one side of the channel formation region, oxygen separated from the conductive material is easily supplied to the channel formation region.

[0344] In particular, as a conductor used as a gate electrode, it is preferred to use a conductive material containing a metal element contained in a metal oxide forming a channel and oxygen. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide forming the channel can sometimes be captured. Alternatively, hydrogen mixed from an external insulator can sometimes be captured.

[0345] <Example 1 of Method for Manufacturing Semiconductor Device> Reference FIG. 13A to FIG. 28D An example of a method for manufacturing a semiconductor device according to one embodiment of the present invention is described. Figures 1A to 1D The case of the semiconductor device shown in FIG. 1 is described as an example.

[0346] A of each figure is a plan view. In addition, B of each figure is a cross-sectional view of a portion along the dashed line A1-A2 in A of each figure, and is also a cross-sectional view in the channel width direction of transistor 200. In addition, C of each figure is a cross-sectional view of a portion along the dashed line A3-A4 in A of each figure, and is also a cross-sectional view in the channel width direction of transistor 200. In addition, D of each figure is a cross-sectional view of a portion along the dashed line A5-A6 in A of each figure, and is also a cross-sectional view in the channel length direction of transistor 200. Note that for the sake of clarity, some components are omitted in the plan view of A of each figure.

[0347] Hereinafter, the insulating material used to form an insulator, the conductive material used to form a conductor, or the semiconductor material used to form a semiconductor can be appropriately deposited using sputtering, chemical vapor deposition (CVD: Chemical Vapor Deposition), molecular beam epitaxy (MBE: Molecular Beam Epitaxy), pulsed laser deposition (PLD: Pulsed Laser Deposition), ALD, or the like.

[0348] Note that as a sputtering method, there can be cited an RF sputtering method using a high frequency power supply as a sputtering power supply, a DC sputtering method using a direct current power supply, and a pulsed DC sputtering method in which the voltage applied to an electrode is changed in a pulsed manner. The RF sputtering method is mainly used when depositing an insulating film, and the DC sputtering method is mainly used when depositing a metal conductive film. In addition, the pulsed DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, and carbides using a reactive sputtering method.

[0349] Note that the CVD method can be divided into a plasma CVD (PECVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, and a photo CVD (Photo CVD) method using light, etc. Furthermore, it can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method according to the source gas used.

[0350] By utilizing the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since plasma is not used in the thermal CVD method, the plasma damage caused to the object to be processed can be reduced. For example, the wiring, electrodes, components (transistors, capacitors, etc.) included in the semiconductor device sometimes generate charge accumulation due to receiving charges from the plasma. At this time, the wiring, electrodes, components, etc. included in the semiconductor device are sometimes damaged due to the accumulated charges. On the other hand, since the above-mentioned plasma damage does not occur in the case of the thermal CVD method without using plasma, the yield of the semiconductor device can be improved. In addition, in the thermal CVD method, plasma damage during deposition is not generated, so a film with fewer defects can be obtained.

[0351] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method using a reactant excited by plasma, or the like is used.

[0352] The CVD method and the ALD method are different from the sputtering method in which particles released from a target material or the like are deposited. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has high step coverage and thickness uniformity, so it is suitable for covering the surface of an opening with a high aspect ratio. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferred to be used in combination with other deposition methods such as the CVD method with a fast deposition rate.

[0353] In addition, when the CVD method is used, a film of any composition can be deposited according to the flow ratio of the source gas. For example, when the CVD method is used, a film whose composition continuously changes can be deposited by changing the flow ratio of the source gas while performing deposition. When deposition is performed while changing the flow ratio of the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of the semiconductor device can sometimes be improved.

[0354] When the ALD method is used, a film of any composition can be deposited by introducing different precursors at the same time. Alternatively, when introducing different precursors, a film of any composition can be deposited by controlling the number of cycles of each precursor.

[0355] In addition, dry etching, wet etching, or the like can be used as the etching process below.

[0356] As an etching gas used for the dry etching process, for example, a gas containing halogen can be used.

[0357] As the halogen-containing gas, for example, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. Fluorocarbon gas, hydrofluorocarbon gas, SF6 gas, Cl2 gas, BCl3 gas, SiCl4 gas, or BBr3 gas can be used alone or in a mixture of two or more gases. As the fluorine-containing gas, a gas represented by C x F y (y≤2x+2) Gas. Examples of fluorocarbon gases satisfying y=2x+2 include CF4, C2F6, C3F8, C4F 10 、C5F 12 In addition, examples of fluorocarbon gases satisfying y<2x+2 include C2F4, C2F2, C3F7, C3F4, C4F8, C4F6, C4F4, C4F2, C5F 10 , C5F8, C5F6, C5F4 and other unsaturated fluorocarbons. Examples of hydrofluorocarbon gases include CHF3 gas, CH2F2 gas and the like.

[0358] In addition, when using a gas containing halogen as an etching gas, oxygen (O 2 ) gas, carbon dioxide gas, nitrogen (N 2 ) gas, helium gas, argon gas, hydrogen gas, hydrocarbon gas, or the like may be appropriately added.

[0359] In addition, as the etching gas, a gas containing no halogen gas but containing hydrocarbon gas or hydrogen gas may be used.

[0360] As the hydrocarbon gas, for example, methane (CH4), ethane (C2H6), propane (C3H8), butane (C4H 10 ), one or more of ethylene (C2H4), propylene (C3H6), acetylene (C2H2) and propyne (C3H4).

[0361] When a hydrocarbon gas is used as an etching gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or the like may be appropriately added.

[0362] In addition, as a dry etching device, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching device including parallel plate electrodes can be used. The capacitively coupled plasma etching device including parallel plate electrodes can also adopt a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, a structure in which multiple different high-frequency voltages are applied to one of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage with the same frequency is applied to each of the parallel plate electrodes can be adopted. Alternatively, a structure in which high-frequency voltages with different frequencies are applied to each of the parallel plate electrodes can be adopted. Alternatively, a dry etching device with a high-density plasma source can be used. For example, as a dry etching device with a high-density plasma source, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching device can be used. The etching device can be appropriately set according to the etching object.

[0363] First, a substrate (not shown) is prepared, and an insulator 215 is deposited on the substrate (see Figures 13A to 13D ). As described above, the insulator 215 may use the same insulator as the laminated film of any one or more of the insulators 282 and the insulator 283. For example, the insulator 215 may be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. By using a sputtering method that does not require the use of molecules containing hydrogen for the deposition gas, the hydrogen concentration in the insulator 215 can be reduced, so it is preferred.

[0364] Next, an insulator 216 is deposited on the insulator 215 (see FIG. 13A to FIG. 13D ). The insulator 216 is preferably deposited by sputtering. By using a sputtering method that does not require molecules containing hydrogen to be used for the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. Note that the deposition method of the insulator 216 is not limited to the sputtering method, and for example, a CVD method, an MBE method, a PLD method, an ALD method, etc. can also be used appropriately. In this embodiment, silicon oxide is deposited as the insulator 216 by sputtering.

[0365] The insulator 215 and the insulator 216 are preferably deposited continuously without being exposed to the atmosphere. For example, a multi-chamber deposition apparatus may be used. Thus, the insulator 215 and the insulator 216 can be deposited while reducing hydrogen in the film, and the mixing of hydrogen into the film between each deposition step can be suppressed.

[0366] Here, an opening that reaches the insulator 215 is formed in the insulator 216 and the conductor 205 is formed in the opening. FIG. 12A to FIG. 12DThe transistor 200 is shown. When the conductor 205 is formed, a conductive film for the conductor 205 may be deposited in such a manner as to be embedded in the opening and a CMP treatment may be performed on the conductive film to remove a portion of the conductive film.

[0367] Next, an insulator 221 is deposited on the insulator 216 (see FIG. 13A to FIG. 13D ).

[0368] The insulator 221 may be any of the above-mentioned insulators that have barrier properties to oxygen, hydrogen, and water. The insulator 221 may be deposited, for example, by sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon nitride is deposited by PEALD as the insulator 221 .

[0369] Next, an insulator 222 is deposited on the insulator 221 (see FIG. 13A to FIG. 13D ).

[0370] As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited. As an insulator containing an oxide of one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. Alternatively, hafnium zirconium oxide is preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water. When the insulator 222 has a barrier property to hydrogen and water, the hydrogen and water contained in the surrounding structure of the transistor can be suppressed from diffusing through the insulator 222 to the inside of the transistor, thereby suppressing the generation of oxygen vacancies in the oxide semiconductor 230.

[0371] The insulator 222 can be deposited by, for example, sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, hafnium oxide is deposited as the insulator 222 by thermal ALD.

[0372] Next, an insulator 224 is deposited on the insulator 222 (see FIG. 13A to FIG. 13D ).

[0373] As the insulator 224, a thermally stable insulator such as silicon oxide or silicon oxynitride is preferably used. In addition, when etching the insulator 224, the etching rate of the insulator 222 is preferably low. In addition, as the insulator 224, a material that can be etched when removing the layer 292 described later can also be used. The insulator 224 can be deposited by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, as the insulator 224, silicon oxide is deposited by a PEALD method.

[0374] By using silicon nitride having a function of suppressing hydrogen diffusion as the insulator 221, hydrogen diffusion from a lower layer of the transistor 200 can be suppressed. Furthermore, by using hafnium oxide having a function of capturing or fixing hydrogen as the insulator 222, hydrogen in the oxide semiconductor 230 can be captured or fixed by the insulator 222. Thus, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0375] Next, a coating film 293f is deposited on the insulator 224. Next, a coating film 292f is deposited on the coating film 293f (see FIG. 13A to FIG. 13D ). The coating film 293f and the coating film 292f may also have a function of improving the adhesion between the resist mask described later and the insulator 224. In addition, the coating film 293f may also have a function of improving the adhesion between the coating film 292f and the insulator 224. When depositing the coating film 293f and the coating film 292f, for example, a spin coating method may be used. As the coating film 293f and the coating film 292f, a non-photosensitive organic resin may be used.

[0376] Here, the coating film 292f is used as a mask in the etching process for processing the coating film 293f. Therefore, in the etching conditions of the coating film 293f, the etching rate of the coating film 292f is preferably lower than the etching rate of the coating film 293f. For example, a film containing carbon is used for the coating film 293f and a film containing silicon and carbon is used for the coating film 292f. Specifically, as the coating film 292f, for example, a film containing silicon, oxygen and carbon can be used. For example, a film having a polymer containing silicon and oxygen can be used. In the present embodiment, a SOC film is deposited as the coating film 293f, and a SOG film is deposited as the coating film 292f. As SOG, for example, a film containing polysiloxane can be formed by spin coating.

[0377] Note that the coating film 293f and the coating film 292f contain an organic solvent such as alcohol or ether when applied, but the organic matter contained therein may be reduced or removed in a subsequent process or when the semiconductor device is completed. For example, by using an SOG film as the coating film 292f and performing a heat treatment or the like after coating, an inorganic insulating film may be formed depending on the composition of the SOG film and the processing conditions. In addition, the coating film may be provided as required, and a single-layer coating film may be provided, or a coating film may not be provided when only a resist mask described later is sufficient.

[0378] Next, a resist mask 291 is formed on the coating film 292f by photolithography (see FIG. 13A to FIG. 13D). A photosensitive organic resin also called a photoresist can be used as the resist mask 291. For example, a positive photoresist or a negative photoresist can be used. The photoresist that becomes the resist mask 291 can be deposited with a uniform thickness by, for example, depositing using a spin coating method or the like.

[0379] Note that in photolithography, first, the resist is exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, an etching process is performed through the resist mask to process the conductor, semiconductor, or insulator into a desired shape. For example, a KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. can be used to expose the resist to form a resist mask. In addition, a liquid immersion technique can be used in which the exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens. In addition, an electron beam or an ion beam can also be used instead of the above-mentioned light. Note that when an electron beam or an ion beam is used, a mask may sometimes not be used.

[0380] Note that heat treatment may be performed after the coating film 293f, the coating film 292f, and the film to be the resist mask 291 are applied. For example, the heat treatment may be performed at a temperature of 60°C or higher.

[0381] First, the coating film 292f is processed using the resist mask 291 to form the layer 292. For example, when a SOG film is used as the coating film 292f, a fluorocarbon gas, a hydrofluorocarbon gas, etc., specifically, CF4, CHF3, etc., can be used as an etching gas. In addition, oxygen gas, nitrogen gas, argon gas, helium gas, etc. can also be used.

[0382] Next, the coating film 293f is processed using the layer 292 as a mask, thereby forming the layer 293 (see FIG. 14A to FIG. 14D ). For example, when an SOC film is used as the coating film 293f, H2 gas and N2 gas can be used as etching gases. In addition, oxygen and nitrogen, carbon dioxide and carbon monoxide, etc. can also be used as etching gases. Here, since an SOG film is used as the layer 292, it is possible to prevent the layer 292 from disappearing during the etching process of the coating film 293f. In addition, the shape of the layer 292 changes very little during the etching process of the coating film 293f, so the side surface of the layer 293 can be formed into a shape that is vertical or approximately vertical to the formed surface (here, the insulator 224). By adopting this structure, it is possible to achieve a small area and a high density when setting a plurality of transistors.

[0383] It is preferable to remove the resist mask 291 while processing the coating film 293f. By using an organic film containing carbon such as an SOC film as the coating film 293f, the resist mask 291 can be easily removed. Note that if the resist mask 291 remains after the layer 293 is formed, it is preferable to remove the resist mask 291.

[0384] The layer 293 and the layer 292 are used as a template for forming the oxide semiconductor 230 .

[0385] Organic resins sometimes adsorb gases. In addition, organic resins sometimes have residual solvents from coating. Therefore, it is possible that the gas is detached from layer 293 and layer 292 by heat applied in subsequent processes, such as heat applied when depositing a film to become the oxide semiconductor 230 (the oxide semiconductor film 230f described later). Therefore, it is preferred to perform heat treatment after forming layer 293. For example, heat treatment is preferably performed at a temperature of 150°C or more, more preferably 200°C or more and 400°C or less, typically 300°C or thereabouts. In addition, when the temperature of the heat treatment is 300°C or thereabouts, the time of the heat treatment is, for example, 30 seconds or more and 1 hour or less. In addition, the atmosphere for the heat treatment can be an atmosphere containing one or more of nitrogen gas and noble gas. In addition, the treatment can also be performed under reduced pressure.

[0386] By performing this heat treatment, the amount of gas released from layer 293 and layer 292 is suppressed during the deposition of the oxide semiconductor film 230f performed below, thereby suppressing the influence of the release of gas on the deposition atmosphere and deposition pressure when the oxide semiconductor film 230f is deposited. In addition, film peeling of the oxide semiconductor film 230f or deformation of layer 293 and layer 292 caused by the release of gas can also be suppressed. Note that by performing this heat treatment, the volume of layer 293 is sometimes particularly reduced. For example, the volume is sometimes reduced by more than 2% and less than 15%. Preferably, the shape of layer 293 does not change due to the volume reduction.

[0387] Next, the cap layer 293 and the layer 292 are deposited to form an oxide semiconductor film 230f of the oxide semiconductor 230 (see FIG. 15A to FIG. 15D The oxide semiconductor film 230f is a metal oxide film that becomes the oxide semiconductor 230 in a later step, and any of the above-mentioned metal oxide films can be used. The oxide semiconductor film 230f can be deposited by sputtering, CVD, MBE, PLD, or ALD.

[0388] The oxide semiconductor film 230f is deposited along the layer 293 and the layer 292. An organic resin is particularly suitable for the layer 293. Compared with an inorganic insulator, the organic resin can be easily removed. As a result, the damage to the oxide semiconductor 230 can be reduced in the subsequent process of removing the layer 293. On the other hand, compared with an inorganic insulator, an organic resin is sometimes more susceptible to damage caused by plasma treatment, etc. Therefore, it is preferred to form the oxide semiconductor film 230f using a method that causes less damage. For example, the layer in the oxide semiconductor film 230f that is in contact with the layer 293 is preferably formed using the ALD method.

[0389] In addition, the ALD method has high coverage, and thus deposition can be appropriately performed even on the side walls of layers having a high aspect ratio, such as the layer 293 .

[0390] In addition, the aspect ratio of the oxide semiconductor 230 is preferably high, and therefore the thickness of the oxide semiconductor film 230f is preferably thin. Therefore, the oxide semiconductor film 230f is preferably deposited by an ALD method that can adjust the thickness to be thin.

[0391] When the oxide semiconductor film 230 f is deposited in this manner, the oxide semiconductor film 230 f is in contact with the side surfaces of the layer 293 and the layer 292 , and the top surface of the layer 292 .

[0392] Here, when depositing the oxide semiconductor film 230f, it is preferable to use the same method as that described above when depositing the oxide semiconductor 30. When the oxide semiconductor film 230f is formed in this way, the oxide semiconductor film 230f and the oxide semiconductor 230 are parallel or substantially parallel to the surface on which they are formed.

[0393] For example, Figure 2B As shown in the figures, when the oxide semiconductor 230 has a three-layer structure of oxide semiconductors 230a to 230c, the films of oxide semiconductors 230a and 230c can be deposited by the ALD method, and the film of oxide semiconductor 230b can be deposited by the sputtering method. Specifically, the film of oxide semiconductor 230a can be deposited in a manner having a composition of In:Zn=2:1 [atomic ratio] or thereabouts. Alternatively, indium oxide can be used to form the film of oxide semiconductor 230a. In addition, the film of oxide semiconductor 230b can be deposited using an oxide target having a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or thereabouts. In addition, the film of oxide semiconductor 230c can be deposited in a manner having a composition of In:Zn=2:1 [atomic ratio] or thereabouts. Alternatively, indium oxide can be used to form the film of oxide semiconductor 230c.

[0394] Next, heat treatment is preferably performed. The heat treatment is preferably performed within a temperature range in which the oxide semiconductor film 230 f is not polycrystallized. The heat treatment of the oxide semiconductor film 230 f can be performed using the same method as the heat treatment of the oxide semiconductor 30 described above.

[0395] For example, as the heat treatment, a treatment may be performed at a temperature of 450° C. for 1 hour at a flow ratio of nitrogen gas to oxygen gas of 4:1.

[0396] By depositing the oxide semiconductor 230 by the above method and performing a heat treatment, the oxide semiconductor 230 can be made into an axially grown CAAC. Thus, the on-state current, S value, field effect mobility, and frequency characteristics of the transistor 200 can be improved, and a semiconductor device with good electrical characteristics can be provided. In addition, a semiconductor device with high reliability can be provided.

[0397] The heat treatment is performed in a nitrogen gas or inert gas atmosphere or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may also be performed under reduced pressure. Alternatively, the heat treatment may also be performed in a nitrogen gas or inert gas atmosphere, and then the heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the oxygen that has been separated.

[0398] In addition, the gas used in the above-mentioned heat treatment is preferably highly purified. For example, the water content in the gas used in the above-mentioned heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and further preferably 0.05 ppb or less. By using a highly purified gas for heat treatment, it is possible to prevent moisture and the like from being absorbed by the oxide semiconductor film 230f and the like as much as possible. In addition, the heat treatment before this step and the heat treatment after this step can also use a highly purified gas.

[0399] By such a heat treatment containing an oxygen gas, impurities such as carbon, water, and hydrogen in the oxide semiconductor film 230f can be reduced. By reducing the impurities in the film in this way, the crystallinity of the oxide semiconductor film 230f is improved, and a denser structure with a higher density can be achieved. Therefore, the crystallized area in the oxide semiconductor film 230f can be increased, and the in-plane unevenness of the crystallized area in the oxide semiconductor film 230f can be reduced. Therefore, the in-plane unevenness of the electrical characteristics of the transistor can be reduced.

[0400] In addition, by performing the heat treatment, oxygen can be supplied to the oxide semiconductor film 230 f and oxygen vacancies in the oxide semiconductor film 230 f can be reduced. Thus, the reliability of the transistor 200 can be improved.

[0401] In addition, by performing the heat treatment, hydrogen in the oxide semiconductor film 230f moves to the insulator 222 and the hydrogen is absorbed by the insulator 222. In other words, the hydrogen in the oxide semiconductor film 230f diffuses into the insulator 222. Therefore, the hydrogen concentration of the insulator 222 increases, while the hydrogen concentration in the oxide semiconductor film 230f decreases. Here, when the insulator 221 is provided in contact with the bottom surface of the insulator 222, impurities such as moisture and hydrogen can be prevented from entering from below the insulator 221 due to the heat treatment.

[0402] In particular, the oxide semiconductor film 230f (hereinafter referred to as the oxide semiconductor 230) is used as a channel formation region of the transistor 200. The transistor 200 formed using the oxide semiconductor film 230f in which the hydrogen concentration is reduced has high reliability and is therefore preferable.

[0403] Next, a portion of the oxide semiconductor film 230f is removed by anisotropic etching (see FIG. 16A to FIG. 16D ). The portion of the oxide semiconductor film 230f parallel to the substrate surface is mainly etched, thereby forming a sidewall-shaped oxide semiconductor 230 in contact with the side surfaces of the layer 293 and the layer 292. Here, Fig. 16B and Fig. 16C The structure shows that both the A1 side (A3 side) and the A2 side (A4 side) of the upper part of the oxide semiconductor 230 are formed into a curved shape, but is not limited to this. Sometimes only the side of the oxide semiconductor 230 that is not in contact with layer 292 and layer 293 is formed into a curved shape.

[0404] By utilizing anisotropic etching, an oxide semiconductor 230 having a high aspect ratio can be formed. By using the oxide semiconductor 230, the channel width of the transistor 200 can be increased without increasing the occupied area, thereby improving the on-state current and frequency characteristics of the transistor 200. In addition, the contact area between the oxide semiconductor 230 and the conductors 242a and 242b can be increased without increasing the occupied area, thereby improving the on-state current and frequency characteristics of the transistor 200.

[0405] In addition, if Fig.16A As shown, the top surface shape of the oxide semiconductor 230 has a circular shape with both ends aligned. The oxide semiconductor 230 can also be said to have a shape including an opening in the center. In addition, as described above, in the case where the oxide semiconductor 230 has a three-layer structure of oxide semiconductors 230a to 230c, the circular oxide semiconductor 230 is formed in sequence with the oxide semiconductor 230a, oxide semiconductor 230b, and oxide semiconductor 230c centered on the region where the stacked body of layer 293 and layer 292 is formed. As a result, as Fig. 10AAs shown, when viewed in a cross section along the channel width direction, the oxide semiconductor 230c, the oxide semiconductor 230b, the oxide semiconductor 230a, the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are symmetrically arranged in order.

[0406] Note that in the above description, a structure in which two oxide semiconductors 230 are provided in a circular shape is described, but the present invention is not limited thereto. For example, one or more than three circular oxide semiconductors 230 may be provided. In addition, an oxide semiconductor 230 having a shape including a plurality of openings may be formed by combining the oxide semiconductors 230. For example, Figure 4A As shown in FIG. 1 , an oxide semiconductor 230 having a shape having three openings arranged in the A1-A2 direction in a plan view may also be formed. In this case, FIG. 14A to FIG. 14D In the process shown in FIG. 1 , three stacked layers of layer 293 and layer 292 are formed adjacent to each other at a short distance. Figure 4B As shown in FIG. 1 , the oxide semiconductor 230 may be formed to have a lattice shape in a plan view. In this case, FIG. 14A to FIG. 14D In the process shown, it is sufficient to form grid-shaped grooves in the stacked body of the layer 293 and the layer 292.

[0407] In addition, Fig.16A The oxide semiconductor 230 has a circumferential structure in a plan view, but an etching process may be further performed to remove a portion of the oxide semiconductor 230. For example, by removing Fig.16A In the illustrated part of the structure, the oxide semiconductor 230 has a rectangular shape extending in the A5 - A6 direction in a plan view.

[0408] When anisotropically etching the oxide semiconductor film 230f, a dry etching method is preferably used.

[0409] Note that, as this anisotropic etching, it is preferable to use a condition with a high selectivity with respect to the layer 292 and the insulator 224. That is, it is preferable that the etching rate of the oxide semiconductor film 230f is higher than the etching rate of the layer 292 and the insulator 224. When etching the oxide semiconductor film 230f by dry etching, as etching gas, hydrofluorocarbon, CH4, BBr, HBr, SiCl4, BCl3, Cl2, etc. can be used. In addition to the above-mentioned gases, Ar, O2, H2, N2, etc. can also be used. Specifically, for example, a mixed gas of CH4 and Ar can be used.

[0410] In addition, FIG. 16A to FIG. 16D In the embodiment, two stacked layers of layer 293 and layer 292 and two oxide semiconductors 230 are provided for transistor 200, but the present invention is not limited thereto. Fig.17AAs shown in FIG. 2 , two stacked layers of the layer 293 and the layer 292 and two oxide semiconductors 230 may be provided for each of the two transistors (the transistor 200_1 and the transistor 200_2). Fig. 17B As shown, the following structure may be adopted: by providing a stacked body of layers 293 and 292 having different widths, three fin-shaped oxide semiconductors 230 are provided for each of the transistors 200_1 and 200_2 when the cross section is viewed in the A1-A2 direction. In this case, the oxide semiconductor 230 of the transistor 200_1 and the oxide semiconductor 230 of the transistor 200_2 are divided in such a manner that a part of the oxide semiconductor 230 is removed and the top surface shape becomes a straight line extending in the A5-A6 direction.

[0411] Next, the layer 292 is removed (see 18A to 18D ). At this time, if FIG. 18B to FIG. 18D As shown, a portion of the insulator 224 may also be etched by etching the layer 292. For example, by using a material containing oxygen and silicon as the insulator 224, the layer 292 and the insulator 224 may be etched at the same time. In this embodiment, for example, SOG is used as the layer 292 and silicon oxide is used as the insulator 224, so that the layer 292 and the insulator 224 are etched at the same time. Here, the insulator 224 is etched using the layer 293 and the oxide semiconductor 230 as masks.

[0412] Dry etching or wet etching can be used to etch the layer 292. When SOG is used as the layer 292, dry etching containing fluorocarbon gas, hydrofluorocarbon gas, or the like as etching gas can be used as etching conditions.

[0413] Next, the layer 293 is removed (see FIG. 19A to FIG. 19D ). When removing layer 293, the conditions used when processing layer 293 can be used. In particular, it is preferable to use a condition where the etching rate of oxide semiconductor 230 is small. When SOC is used as layer 293, as an etching condition, for example, dry etching containing one or more of oxygen, carbon dioxide and carbon monoxide as an etching gas can be used. In addition, as an etching condition, for example, plasma treatment performed in an atmosphere containing oxygen, ozone, nitrogen, nitrous oxide, argon, etc. can be used. Here, as plasma treatment, microwave treatment can be used.

[0414] By removing the layer 293 under the above-mentioned etching conditions, damage to the surface of the oxide semiconductor 230, deposition of reaction products, etc. can be suppressed. In addition, depending on the etching conditions of the layer 293, the crystallinity of the oxide semiconductor 230 may be improved. In particular, plasma treatment using microwaves can improve the crystallinity of the oxide semiconductor 230, which is preferred.

[0415] Next, a region of the insulator 224 that does not overlap with the oxide semiconductor 230 is etched (see FIG. 20A to FIG. 20D ). By performing this etching, the oxide semiconductor 230 and the insulator 224 can have substantially the same top surface shape.

[0416] Note that without FIG. 20A to FIG. 20D In the case of the etching step of the insulator 224 shown, it is possible to produce FIG. 5A to FIG. 5D The semiconductor device shown. FIG. 20A to FIG. 20D In the process shown, for example, the insulator 224 can be etched using the oxide semiconductor 230 as a mask. In this etching, the oxide semiconductor 230 used as a mask may be damaged. In addition, the shape, height H, width L, etc. of the oxide semiconductor 230 may be changed due to the etching of a part of the oxide semiconductor 230 used as a mask during the etching process of the insulator 224. FIG. 20A to FIG. 20D The etching process shown in the figure can simplify the process. In addition, the damage to the oxide semiconductor 230 can be reduced, thereby improving the reliability of the semiconductor device. FIG. 20A to FIG. 20D The process can form Figures 1A to 1D Thus, the gate electric field from the conductor 260 can be sufficiently applied to the lower end of the oxide semiconductor 230 both outside and inside the circumferential oxide semiconductor 230 .

[0417] Next, a conductive film 242f is deposited on the insulator 222 and the oxide semiconductor 230 (see FIG. 21A to FIG. 21D As the conductive film 242f, a conductor corresponding to the above-mentioned conductor 242a and the conductor 242b may be used.

[0418] The conductive film 242f can be deposited by, for example, sputtering, CVD, MBE, PLD, or ALD. For example, as the conductive film 242f, tantalum nitride can be deposited by sputtering. Fig. 11B As shown in the figures, the conductor 242a and the conductor 242b may also have a stacked structure. In the above case, for example, the conductive film 242f may have a stacked structure. As the conductive film 242f, for example, a stacked structure of tantalum nitride and tungsten on tantalum nitride may be used. By depositing the conductive film 242f in a manner covering the oxide semiconductor 230, the contact area between the oxide semiconductor 230 and the conductor 242a and the conductor 242b may be increased without increasing the occupied area of ​​the transistor 200. Thus, the on-state current and frequency characteristics of the transistor 200 may be improved.

[0419] Next, the conductive film 242f is processed into an island shape by photolithography, thereby forming the conductive body 242A (see FIG. 22A to FIG. 22D In this case, the conductor 242A is preferably formed to cover the oxide semiconductor 230. In addition, the insulator 222 is exposed in a region that does not overlap with the conductor 242A.

[0420] The above processing can be performed by dry etching or wet etching. Processing by dry etching is suitable for micro-processing. Note that the dry etching conditions and dry etching apparatus can refer to the above description.

[0421] The side surface of the conductor 242A may be perpendicular or substantially perpendicular to the top surface of the insulator 222. By adopting such a structure, it is possible to realize a reduction in area and a high density when arranging a plurality of transistors.

[0422] However, the structure is not limited to the above, and the side surfaces of the oxide semiconductor 230 and the conductor 242A may also have a tapered shape. The taper angle of the side surfaces of the oxide semiconductor 230 and the conductor 242A may be, for example, greater than 60° and less than 90°. In this way, when the side surfaces have a tapered shape, the coverage of the insulator 275 and the like is improved in the subsequent process, and defects such as voids can be reduced.

[0423] Note that in photolithography, first, the resist is exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, an etching process is performed through the resist mask to process the conductor, semiconductor, or insulator into a desired shape. For example, a KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. can be used to expose the resist to form a resist mask. In addition, a liquid immersion technique can be used in which the exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens. In addition, an electron beam or an ion beam can be used instead of the above-mentioned light. Note that when an electron beam or an ion beam is used, a mask may sometimes not be used.

[0424] The resist mask that is unnecessary after processing can be removed by dry etching treatment such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), wet etching treatment, dry etching treatment followed by wet etching treatment, or wet etching treatment followed by dry etching treatment.

[0425] Furthermore, a hard mask made of an insulator or a conductor can also be used under the resist mask. When a hard mask is used, an insulating film or a conductive film that becomes a hard mask material can be formed on the conductive film 242f and a resist mask can be formed thereon, and then the hard mask material is etched to form a hard mask of a desired shape. The etching of the conductive film 242f and the like can be performed after removing the resist mask or without removing the resist mask. In the case of the latter, the resist mask sometimes disappears during etching. In addition, the hard mask can also be removed by etching after etching the conductive film 242f. On the other hand, when the hard mask material does not affect the subsequent process or can be used in the subsequent process, it is not necessary to remove the hard mask.

[0426] In addition, a structure in which an SOC film and an SOG film are deposited between the workpiece and the resist mask may also be adopted. By using the SOC film and the SOG film as a mask, the durability of the mask pattern may be improved. For example, a SOC film, an SOG film, and a resist mask may be deposited sequentially on the workpiece for photolithography.

[0427] Next, an insulator 275 is deposited to cover the conductor 242A, and an insulator 280 is deposited on the insulator 275 (see FIG. 23A to FIG. 23D ). As the insulator 275 and the insulator 280, the above-mentioned insulators can be used.

[0428] Here, the insulator 275 is preferably in contact with the top surface of the insulator 222 .

[0429] Insulator 280 is preferably formed by forming an insulating film to be insulator 280 and then subjecting the insulating film to CMP to form an insulator with a flat top surface. Alternatively, silicon nitride may be deposited on insulator 280 by sputtering, for example, and then subjected to CMP until it reaches insulator 280.

[0430] The insulator 275 and the insulator 280 can each be deposited by, for example, sputtering, CVD, MBE, PLD, or ALD.

[0431] The insulator 275 preferably uses an insulator that has a function of inhibiting oxygen transmission. For example, silicon nitride is preferably deposited by the PEALD method as the insulator 275. In addition, aluminum oxide is preferably deposited by the sputtering method and silicon nitride is deposited thereon by the PEALD method as the insulator 275. When the insulator 275 has the above structure, the function of inhibiting the diffusion of impurities such as water and hydrogen and oxygen can be improved.

[0432] In this manner, the oxide semiconductor 230 and the conductor 242A can be covered by the insulator 275 having the function of suppressing oxygen diffusion. Thus, direct diffusion of oxygen from the insulator 280 or the like into the oxide semiconductor 230 and the conductor 242A in a subsequent step can be suppressed.

[0433] In addition, silicon oxide is preferably deposited by sputtering as the insulator 280. By depositing an insulating film to be the insulator 280 by sputtering in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. By using a sputtering method that does not require the use of molecules containing hydrogen for the deposition gas, the hydrogen concentration in the insulator 280 can be reduced. In addition, a heat treatment may also be performed before depositing the insulating film. The heat treatment may also be performed under reduced pressure, and the insulating film is continuously deposited without being exposed to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 275, etc. can be removed, and the moisture concentration and hydrogen concentration in the oxide semiconductor 230 can be reduced. The heat treatment may adopt the conditions of the above-mentioned heat treatment.

[0434] Next, the conductor 242A, the insulator 275, and the insulator 280 are processed by photolithography to form openings reaching the oxide semiconductor 230 and the insulator 222 (see FIG. 2 ). FIG. 24A to FIG. 24D Here, the conductor 242A is divided into a conductor 242a and a conductor 242b. The above-mentioned opening is formed in a region overlapping with the oxide semiconductor 230.

[0435] The above-mentioned method can be appropriately used as the photolithography method. In order to finely process the opening of the insulator 280, it is preferable to use a photolithography method using light with a short wavelength such as EUV light or an electron beam.

[0436] The above processing is preferably performed by dry etching. In the dry etching method, anisotropic etching can be performed, so the dry etching method is suitable for forming an opening with a high aspect ratio. Note that the dry etching conditions and dry etching apparatus can refer to the above description.

[0437] In addition, in the formation Fig. 11C In the case of the structure shown in FIG. 1 , it is preferable to perform etching after forming the conductors 242a2 and 242b2 to form the conductors 242a1 and 242b1. In addition, when this structure is adopted, the following can be manufactured in parallel. Fig.29 The transistor 200 and the capacitor 460 are shown. The details will be described later.

[0438] After processing the conductor 242A, an ashing treatment using oxygen plasma may also be performed. By performing such an oxygen plasma treatment, impurities generated in the above-mentioned etching process and diffused into the oxide semiconductor 230 and the like can be removed. As such impurities, there can be cited impurities of components in the workpiece resulting from the above-mentioned etching process and impurities of components in the gas used in etching and the like. For example, chlorine, fluorine, tantalum, silicon, hafnium, and the like can be cited. In particular, as shown in the above-mentioned etching process, when chlorine gas is used in the processing of the conductor 242A, the oxide semiconductor 230 is exposed to an atmosphere containing chlorine gas, and therefore it is preferred to remove the chlorine attached to the oxide semiconductor 230. By removing impurities attached to the oxide semiconductor 230 in this way, the electrical characteristics and reliability of the transistor can be improved.

[0439] In addition, in order to remove impurities and the like attached to the surface of the oxide semiconductor 230 in the above-mentioned etching step, a cleaning process may be performed. As a cleaning method, there are wet cleaning using a cleaning liquid or the like (which may also be referred to as a wet etching process), plasma treatment using plasma, cleaning using a heat treatment, etc., and the above cleaning may be appropriately combined. Note that the above-mentioned groove portion may become deeper by performing this cleaning process.

[0440] As wet cleaning, an aqueous solution, pure water or carbonated water etc. formed by diluting one or more of ammonia, oxalic acid, phosphoric acid or hydrofluoric acid with carbonated water or pure water can be used. Alternatively, ultrasonic cleaning can be performed using the above aqueous solution, pure water or carbonated water. In addition, the above cleaning can also be appropriately combined.

[0441] Note that in this specification, etc., an aqueous solution of hydrofluoric acid diluted with pure water is sometimes referred to as dilute hydrofluoric acid, and an aqueous solution of ammonia diluted with pure water is sometimes referred to as dilute ammonia water. In addition, the concentration, temperature, etc. of the aqueous solution are appropriately adjusted according to the impurities to be removed, the structure of the semiconductor device to be washed, etc. The ammonia concentration of the dilute ammonia water is preferably set to 0.01% or more and 5% or less, and more preferably set to 0.1% or more and 0.5% or less. In addition, the hydrogen fluoride concentration of the dilute hydrofluoric acid is preferably set to 0.01ppm or more and 100ppm or less, and more preferably set to 0.1ppm or more and 10ppm or less.

[0442] In addition, it is preferable to use a frequency of 200 kHz or higher, and more preferably a frequency of 900 kHz or higher for ultrasonic cleaning. By using such a frequency, damage to the oxide semiconductor 230 and the like can be reduced.

[0443] In addition, the above-mentioned washing treatment may be performed multiple times, and the washing liquid may be changed for each washing treatment. For example, the first washing treatment may be a treatment using dilute hydrofluoric acid or dilute ammonia water, and the second washing treatment may be a treatment using pure water or carbonated water.

[0444] In this embodiment, the cleaning process is performed by wet cleaning using dilute ammonia water. This cleaning process can remove impurities attached to the surface of the oxide semiconductor 230 or diffused into the inside thereof. In addition, the crystallinity of the oxide semiconductor 230 can be improved.

[0445] It is preferred to perform heat treatment after the above-mentioned etching or after the above-mentioned washing. The temperature of the heat treatment is not less than 100°C and not more than 650°C, preferably not less than 250°C and not more than 600°C, more preferably not less than 300°C and not more than 550°C, and further preferably not less than 350°C and not more than 400°C. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas or an oxidizing gas containing not less than 10 ppm, not less than 1% or not more than 10%. For example, it is preferred to perform the heat treatment in an oxygen-containing atmosphere, preferably at a flow ratio of nitrogen gas to oxygen gas of 4:1 and a temperature of 350°C for 1 hour. Thus, oxygen is supplied to the oxide semiconductor 230, so that oxygen vacancies can be reduced. In addition, by performing the above-mentioned heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. Furthermore, when the residual hydrogen in the oxide semiconductor 230 reacts with the supplied oxygen, the hydrogen can be removed (dehydrated) in the form of H2O. Thus, the hydrogen remaining in the oxide semiconductor 230 can be inhibited from recombinating with oxygen vacancies to form V O H. Thus, the electrical characteristics of the transistor provided with the oxide semiconductor 230 can be improved and the reliability can be improved. In addition, the non-uniformity of the electrical characteristics of the plurality of transistors formed on the same substrate can be suppressed. In addition, the above-mentioned heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in an oxygen atmosphere, and then the heat treatment can be continuously performed in a nitrogen atmosphere without being exposed to the atmosphere. In addition, the above-mentioned heat treatment can also serve as the heat treatment after the deposition of the oxide semiconductor 30c when the oxide semiconductor 30 is formed. Therefore, sometimes the crystalline region of the oxide semiconductor 230 grows by the above-mentioned heat treatment.

[0446] Note that when heat treatment is performed in a state where the conductor 242a and the conductor 242b are in contact with the oxide semiconductor 230, the sheet resistance of the region overlapping with the conductor 242a and the region overlapping with the conductor 242b in the oxide semiconductor 230 may be reduced. In addition, the carrier concentration may be increased. Therefore, the resistance of the region overlapping with the conductor 242a and the region overlapping with the conductor 242b in the oxide semiconductor 230 can be reduced in a self-aligned manner.

[0447] Next, an insulating film 250A (see FIG. 25A ) which will become the insulator 250 is deposited so as to be embedded in the opening formed in the insulator 280 or the like. FIG. 25A to FIG. 25DHere, the insulating film 250A is in contact with the insulator 280 , the insulator 275 , the conductor 242 a , the conductor 242 b , the insulator 222 , and the oxide semiconductor 230 .

[0448] The insulating film 250A can be deposited by sputtering, CVD, MBE, PLD or ALD. For example, the insulating film 250A is preferably deposited by the ALD method. Like the above-mentioned insulator 250, the insulating film 250A is preferably formed thin, and the thickness non-uniformity needs to be suppressed to a small value. In this regard, the ALD method is a deposition method that alternately introduces precursors and reactants (for example, oxidants, etc.), and the thickness can be adjusted according to the number of times the cycle is repeated, so the thickness can be precisely adjusted. In addition, the insulating film 250A needs to be deposited on the bottom and side surfaces of the above-mentioned opening with high coverage. By using the ALD method, atomic layers can be deposited layer by layer on the bottom and side surfaces of the above-mentioned opening, so the insulating film 250A can be formed in the opening with high coverage.

[0449] When the insulating film 250A is deposited by the ALD method, ozone, oxygen, water, or the like can be used as an oxidant. By using ozone, oxygen, or the like that does not contain hydrogen as an oxidant, hydrogen diffused into the oxide semiconductor 230 can be reduced.

[0450] The insulator 250 may have a laminated structure. Figure 2A As shown, the insulator 250 may adopt a stacked structure of insulators 250a to 250d. In this case, aluminum oxide may be deposited as the insulator 250a by thermal ALD, silicon oxide may be deposited as the insulator 250b by PEALD, hafnium oxide may be deposited as the insulator 250c by thermal ALD, and silicon nitride may be deposited as the insulator 250d by PEALD.

[0451] In addition, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after the insulating film 250A is deposited or after any insulator constituting the insulating film 250A is deposited. Here, microwave treatment refers to, for example, treatment using an apparatus including a power source for generating high-density plasma using microwaves. In addition, in this specification, etc., microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0452] Microwave treatment, for example, preferably uses a microwave processing device that includes a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave processing device is preferably set to be greater than 300 MHz and less than 300 GHz, more preferably greater than 2.4 GHz and less than 2.5 GHz, for example, it can be 2.45 GHz. By using high-density plasma, a high density of oxygen free radicals can be generated. In addition, the power of the power supply that applies microwaves in the microwave processing device is preferably greater than 1000 W and less than 10000 W, more preferably greater than 2000 W and less than 5000 W. In addition, the microwave processing device may also include a power supply that applies RF to one side of the substrate. In addition, by applying RF to one side of the substrate, oxygen ions generated by high-density plasma can be efficiently introduced into the oxide semiconductor 230.

[0453] In addition, the microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably 10Pa or more and 1000Pa or less, more preferably 300Pa or more and 700Pa or less. In addition, the treatment temperature is preferably 750°C or less, more preferably 500°C or less, for example, about 250°C. In addition, it is also possible to continuously perform heat treatment without being exposed to the outside air after the oxygen plasma treatment. The temperature of the heat treatment is, for example, preferably 100°C or more and 750°C or less, more preferably 300°C or more and 500°C or less.

[0454] In addition, for example, the above-mentioned microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 40%. Further preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 30%. In this way, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in the oxide semiconductor 230 can be reduced. In addition, by preventing excessive oxygen from being introduced into the processing chamber during microwave treatment, the carrier concentration in the oxide semiconductor 230 can be prevented from being excessively reduced.

[0455] By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be converted into plasma using microwaves or high frequencies such as RF, and the oxygen plasma can be applied to a region between the conductor 242a and the conductor 242b of the oxide semiconductor 230. The V O H is separated into oxygen vacancies and hydrogen, and hydrogen is removed from the region. Figure 2AWhen the structure shown in the figure is used, it is preferable to use an insulating film (e.g., aluminum oxide) having the function of capturing or fixing hydrogen as the insulator 250a. By adopting this structure, the insulating film 250A can capture or fix hydrogen generated by microwave treatment. In this way, the V contained in the channel formation region can be reduced. O H. Thus, oxygen vacancies and V O H and thus reduce the carrier concentration. In addition, by supplying oxygen radicals generated in the above oxygen plasma to oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, thereby reducing the carrier concentration.

[0456] As oxygen injected into the channel formation region, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions and oxygen free radicals (also called O free radicals, atoms, molecules or ions containing unpaired electrons). The oxygen injected into the channel formation region can be any one or more of the above forms, and oxygen free radicals are particularly preferred. In addition, since the film quality of the insulator 250 can be improved, the reliability of the transistor is improved.

[0457] In addition, by performing microwave treatment, impurities such as carbon in the oxide semiconductor 230 can also be removed. By removing carbon as an impurity in the oxide semiconductor 230, the crystallinity of the oxide semiconductor 230 can be improved. Thus, the oxide semiconductor 230 can be formed into a CAAC-OS. In particular, when the oxide semiconductor 230 is deposited by the ALD method, carbon in the precursor is sometimes introduced into the oxide semiconductor 230, so it is preferable to remove carbon by microwave treatment.

[0458] On the other hand, the oxide semiconductor 230 has a region overlapping with any one of the conductors 242a and 242b. This region can be used as a source region or a drain region. Here, the conductors 242a and 242b are preferably used as shielding films for protecting from microwaves, high frequencies such as RF, or oxygen plasma when microwave treatment is performed in an oxygen-containing atmosphere. Thus, the conductors 242a and 242b preferably have a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0459] The conductors 242a and 242b shield the microwaves, high frequencies such as RF, oxygen plasma, etc., and thus do not act on the region of the oxide semiconductor 230 that overlaps with either the conductors 242a and 242b. Thus, V is not generated in the source region and the drain region by the microwave treatment. O The decrease in H and the supply of excessive oxygen can prevent the decrease in carrier concentration.

[0460] As described above, oxygen vacancies and V can be selectively removed in the channel formation region of the oxide semiconductor. O H makes the channel formation region become i-type or substantially i-type. In addition, it is possible to suppress the region used as the source region or the drain region from being supplied with excessive oxygen and maintain the conductivity (the state of the low resistance region) before the microwave treatment. Thus, it is possible to suppress the change of the electrical characteristics of the transistor and suppress the non-uniformity of the electrical characteristics of the transistor within the substrate surface.

[0461] Furthermore, by performing microwave treatment to improve the film quality of the insulator 250, diffusion of hydrogen, water, impurities, etc. can be suppressed. Thus, diffusion of hydrogen, water, impurities, etc. through the insulator 250 to the oxide semiconductor 230, etc., due to post-processes such as deposition of a conductive film to become the conductor 260 or post-processes such as heat treatment, can be suppressed. In this way, by improving the film quality of the insulator 250, the reliability of the transistor can be improved.

[0462] When the insulator 250 adopts a stacked structure of insulators 250a to 250d, it is preferred to perform microwave treatment after depositing the insulator 250b. Furthermore, microwave treatment may be performed again after depositing the insulator 250c. In this way, microwave treatment in an oxygen-containing atmosphere may also be performed multiple times (at least twice or more). In addition, the above-mentioned microwave treatment may sometimes also serve as a heat treatment after the oxide semiconductor 230 is deposited. Therefore, sometimes the crystalline region of the oxide semiconductor 230 grows by the above-mentioned microwave treatment.

[0463] In addition, the heating treatment may be performed while maintaining a reduced pressure state after the microwave treatment. By performing such a treatment, hydrogen in the insulating film and the oxide semiconductor 230 can be efficiently removed. In addition, the step of maintaining a reduced pressure state after the microwave treatment and performing the heating treatment may be repeated. By repeatedly performing the heating treatment, hydrogen in the insulating film and the oxide semiconductor 230 can be further efficiently removed. Note that the heating treatment temperature is preferably above 300° C. and below 500° C. In addition, the above-mentioned heating treatment may also serve as the heating treatment after the oxide semiconductor 230 is deposited. Therefore, sometimes a crystalline region of the oxide semiconductor 230 grows by the above-mentioned heating treatment.

[0464] Next, a conductive film 260A to be the conductor 260a and a conductive film 260B to be the conductor 260b are sequentially deposited (see FIG. 25A to FIG. 25D). The conductive film 260A and the conductive film 260B can be deposited, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, an electroplating method, or an ALD method. In this embodiment, titanium nitride is deposited as the conductive film 260A by a CVD method, and tungsten is deposited as the conductive film 260B by a CVD method. Note that the conductive film 260A and the conductive film 260B can also be deposited while heating the substrate. In addition, the heating of the substrate can also serve as a heat treatment after the oxide semiconductor 230 is deposited. Therefore, sometimes the crystalline region of the oxide semiconductor 230 grows by the above-mentioned substrate heating.

[0465] Next, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed. That is, the portion of the insulating film 250A, the conductive film 260A, and the conductive film 260B exposed from the above-mentioned opening is removed. Thus, the insulator 250 and the conductor 260 (conductor 260a and conductor 260b) are formed in the opening (see FIG. 26A to FIG. 26D ).

[0466] Thus, the insulator 250 is provided in the opening in contact with the insulator 280, the insulator 275, the conductor 242a, the conductor 242b, the oxide semiconductor 230, and the insulator 222. The conductor 260 is disposed so as to be embedded in the opening via the insulator 250. Thus, the transistor 200 is formed.

[0467] Next, an insulator 282 is formed on the insulator 250, the conductor 260, and the insulator 280 (see Figures 1A to 1D ). The insulator 282 can be deposited, for example, by sputtering, CVD, MBE, PLD, or ALD. The insulator 282 is preferably deposited by sputtering. In addition, when depositing the insulator 282, the first layer can be formed by ALD and the second layer can be formed thereon by sputtering.

[0468] In addition, by depositing the insulator 282 in an oxygen-containing atmosphere by sputtering, oxygen can be added to the insulator 280 while the deposition is being performed. Thus, the insulator 280 can contain excess oxygen. At this time, it is preferable to deposit the insulator 282 while heating the substrate. By depositing the insulator 282 in this way, an appropriate amount of oxygen can be supplied from the insulator 280 to the oxide semiconductor 230 via the insulator 250. In addition, by providing the insulator 250a in the insulator 250, it is possible to prevent the conductor 242a and the conductor 242b from being excessively oxidized near the insulator 250 due to excessive oxygen being supplied to the insulator 250.

[0469] Aluminum oxide is deposited using an aluminum target in an atmosphere containing an oxygen gas. The amount of oxygen injected into the insulator 280 can be controlled by the magnitude of the bias power applied to the substrate by the sputtering method. For example, the smaller the bias power, the less oxygen is injected into the insulator 280, and the oxygen amount is easily saturated even if the thickness of the insulator 282 is small. In addition, the greater the bias power, the more oxygen is injected into the insulator 280. By reducing the RF bias power, the amount of oxygen injected into the insulator 280 can be suppressed. Note that when a substrate bias is applied using an RF power supply, the frequency of the RF is preferably above 10 MHz. Typically, it is 13.56 MHz. The higher the frequency of the RF, the less damage to the substrate can be caused.

[0470] In addition, by depositing the second layer by sputtering on the first layer formed by the ALD method, the upper end of the insulator 250 and the top surface of the conductor 260 can be protected from the impact of ion collision caused by sputtering deposition.

[0471] In addition, a heat treatment may be performed before depositing the insulator 282. The heat treatment may be performed under reduced pressure, and the insulator 282 may be continuously deposited without being exposed to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 may be removed, and the moisture concentration and hydrogen concentration in the insulator 280 may be reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is set to 250° C.

[0472] Next, an insulator 283 is formed on the insulator 282 (see Figures 1A to 1D ). The insulator 283 can be deposited, for example, by sputtering, CVD, MBE, PLD, or ALD. The insulator 283 is preferably deposited by sputtering. By using a sputtering method that does not require molecules containing hydrogen to be used for the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In this embodiment, silicon nitride is deposited by sputtering as the insulator 283.

[0473] Here, it is preferable to continuously deposit insulator 282 and insulator 283 without exposing them to the atmosphere. By depositing them without exposing them to the atmosphere, impurities or moisture from the atmosphere can be prevented from adhering to insulator 282 and insulator 283, so that the interface between insulator 282 and insulator 283 or the vicinity of the interface can be kept clean.

[0474] In this embodiment, silicon nitride is deposited as the insulator 283, and aluminum oxide is deposited as the insulator 282. In this way, by using silicon nitride having a function of suppressing hydrogen diffusion as the insulator 283, diffusion of hydrogen from an upper layer of the transistor 200 can be suppressed. Furthermore, by using aluminum oxide having a function of capturing or fixing hydrogen as the insulator 282, hydrogen contained in the insulator 280 or the like can be captured or fixed by the insulator 282. Thus, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0475] Next, an opening reaching the conductor 242a and an opening reaching the conductor 242b are formed in the insulator 275, the insulator 280, the insulator 282, and the insulator 283 (see Figures 1A to 1D ). The opening can be formed by photolithography. When forming the opening, it is preferred to process the workpiece by dry etching. Anisotropic etching can be performed in dry etching, so dry etching is suitable for forming an opening with a high aspect ratio. When anisotropic etching is performed, for example, reactive ion etching is preferably performed. Note that the dry etching conditions and dry etching apparatus can refer to the above description. Note that in Figure 1A The shape of the opening when viewed from above is a quadrangular shape, but is not limited to this. For example, when viewed from above, the opening may also have a circular shape, an ellipse or other approximate circular shape, or a quadrangular or other polygonal shape, or a shape in which the corners of a quadrangular or other polygonal shape are curved.

[0476] Next, heat treatment may be performed after the above-mentioned opening is formed. The temperature of the heat treatment may be above 100°C and below 600°C, preferably above 250°C and below 550°C, and more preferably above 350°C and below 450°C. The heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere. In addition, since the heat treatment is performed in a state where the conductor 242a and the conductor 242b are exposed, it is preferably performed in an atmosphere that does not contain an oxidizing gas and an oxygen gas. For example, it is preferred to perform a heat treatment at a temperature of 400°C for 1 hour in a nitrogen gas atmosphere. The above-mentioned heat treatment may also be performed under reduced pressure. Through the above-mentioned heat treatment, the oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 through the insulator 250. Thus, oxygen vacancies in the channel formation region of the oxide semiconductor 230 can be reduced. In addition, the above-mentioned heat treatment may also serve as a heat treatment after the oxide semiconductor 230 is deposited. Therefore, sometimes a crystalline region of the oxide semiconductor 230 grows through the above-mentioned heat treatment.

[0477] Here, since the side of the insulator 280 is exposed in the above-mentioned opening, the above-mentioned heat treatment can be used to control the amount of oxygen contained in the insulator 280 by causing the oxygen contained in the insulator 280 to diffuse outward. On the other hand, since the insulator 280 is provided with the insulator 282 and the insulator 283 having oxygen barrier properties, oxygen does not diffuse outward from the top surface of the insulator 280. Thus, it is possible to prevent excessive oxygen from diffusing outward from the insulator 280 and forming oxygen vacancies in the insulator 280. In addition, the oxide semiconductor 230, the conductor 242a, and the conductor 242b are covered by the insulator 275. Thus, it is possible to prevent excessive oxygen from diffusing directly from the insulator 280 to the oxide semiconductor 230, the conductor 242a, and the conductor 242b during the above-mentioned heat treatment.

[0478] In this way, the oxygen in the insulator 280 is adjusted to a more appropriate amount, and an appropriate amount of oxygen can be supplied to the oxide semiconductor 230. As a result, oxygen vacancies in the oxide semiconductor 230 can be reduced and excessive oxygen can be prevented from being supplied to the oxide semiconductor 230. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved. In addition, the process of exposing the side surface of the insulator 280 can also be used as the process of forming the opening for embedding the conductor 240a and the conductor 240b, so the manufacturing process of the semiconductor device can be simplified.

[0479] Next, an insulating film to be the insulator 241 is deposited, and the insulating film is anisotropically etched to form the insulator 241a in the opening that reaches the conductor 242a and the insulator 241b in the opening that reaches the conductor 242b (see FIG. 24). Figures 1A to 1D ). The insulating film that becomes the insulator 241 can be deposited by sputtering, CVD, MBE, PLD, or ALD. As the insulating film that becomes the insulator 241, an insulating film having a function of suppressing the permeation of oxygen is preferably used. For example, silicon nitride is preferably deposited by PEALD. Silicon nitride has a high hydrogen barrier property and is therefore preferred.

[0480] In addition, when performing anisotropic etching on the insulating film to be the insulator 241, for example, a dry etching method or the like can be used. By providing the insulator 241 on the side wall portion of the opening, it is possible to suppress the penetration of oxygen from the outside and prevent oxidation of the conductors 240a and 240b to be formed next. In addition, it is possible to prevent impurities such as water and hydrogen in the insulator 280 from diffusing into the conductors 240a and 240b. Note that a concave portion may be formed on a portion of the top surface of the conductors 242a and 242b due to this anisotropic etching.

[0481] Next, a conductive film to be the conductor 240a and the conductor 240b is deposited. The conductive film to be the conductor 240a and the conductor 240b preferably has a laminated structure including a conductor having a function of suppressing the permeation of impurities such as water and hydrogen. For example, it may be a laminated structure of tantalum nitride, titanium nitride, etc. and tungsten, molybdenum, copper, etc. The conductive film to be the conductor 240a and the conductor 240b can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like.

[0482] Next, a portion of the conductive film to be the conductors 240a and 240b is removed by CMP treatment, thereby exposing the top surface of the insulator 283. As a result, the conductive film remains only in the opening, thereby forming the conductors 240a and 240b with flat top surfaces (see FIG. Figures 1A to 1D ). Note that sometimes a portion of the top surface of the insulator 283 is removed by this CMP process.

[0483] As described above, by providing the conductor 240a in contact with the conductor 242a, the conductor 240a serving as one of the source and the drain of the transistor 200 can be electrically connected to the wiring. In addition, by providing the conductor 240b in contact with the conductor 242b, the conductor 240b serving as the other of the source and the drain of the transistor 200 can be electrically connected to the wiring.

[0484] In addition, a conductive film serving as wiring or a conductive film serving as a plug can be formed over the conductors 240a and 240b.

[0485] Through the above process, it is possible to produce Figures 1A to 1D The semiconductor device shown.

[0486] <Example 2 of Method for Manufacturing Semiconductor Device> Reference FIG. 27A to FIG. 28D An example of a method for manufacturing a semiconductor device according to one embodiment of the present invention is described. FIG. 6A to FIG. 6D The case of the semiconductor device shown in FIG. 1 is described as an example.

[0487] A substrate (not shown) is prepared, and insulator 215, insulator 216, insulator 221, insulator 222, and insulator 224 are sequentially deposited on the substrate. Next, insulator 224b is deposited on insulator 224 (see FIG. 27A to FIG. 27D ).

[0488] Next, a layer 293 and a layer 292 are formed on the insulator 224b (see FIG. 27A to FIG. 27D ).

[0489] Next, an oxide semiconductor film that becomes the oxide semiconductor 230 is deposited on the capping layer 293 and the layer 292, and a portion of the film is removed by anisotropic etching, thereby forming the oxide semiconductor 230 in contact with the side surfaces of the layer 293 and the layer 292 (see FIG. 27A to FIG. 27D ).

[0490] Next, the layer 292 is removed (see FIG. 28A to FIG. 28D At this time, it is preferable to use a material having a low etching rate in the etching process when removing the layer 292 as the insulator 224b.

[0491] As the insulator 224b, for example, the material exemplified as the insulator 222 can be used. For example, a material difficult to etch, such as hafnium oxide, can be appropriately used as an etching stopper when the layer 292 is removed.

[0492] Next, the layer 293 is removed. Next, referring to FIG. 21A to FIG. 26D By forming the conductor 242a, the conductor 242b, the insulator 250, the conductor 260, etc. on the oxide semiconductor 230 and the insulator 224b, it is possible to manufacture FIG. 6A to FIG. 6D The semiconductor device shown.

[0493] <Semiconductor Device Structure Example 2> Fig.29 FIG. 2 shows a structural example in which the transistor 200, the capacitor 460, and the transistor 310 formed on a silicon substrate are used as a 2T (transistor) 1C (capacitor) type memory cell. Fig.29 As shown, a structure in which a layer including transistor 200 and capacitor 460 is provided on a layer including transistor 310 may also be adopted. Fig. 30A is a cross-sectional view of the transistor 200 when viewed in the channel width direction. Fig. 30B is a cross-sectional view of capacitor 460 when viewed from this direction, Fig. 30C It is a cross-sectional view of the transistor 310 when viewed in the channel width direction.

[0494] The transistor 310 is provided on a substrate 311 and includes a conductor 316 used as a gate, an insulator 315 used as a gate insulator, a semiconductor region 313 including a portion of the substrate 311, and a low resistance region 314a and a low resistance region 314b used as a source region or a drain region. The transistor 310 may be a p-channel transistor or an n-channel transistor. As the substrate 311, for example, a single crystal silicon substrate may be used.

[0495] like Fig. 30CAs shown, the semiconductor region 313 (a part of the substrate 311) forming the channel in the transistor 310 has a convex shape. In addition, the conductor 316 is provided in a manner covering the side and top surfaces of the semiconductor region 313 via the insulator 315. In addition, the conductor 316 may also be made of a material that adjusts the work function. Since the above-mentioned transistor 310 utilizes the convex portion of the semiconductor substrate, it is also called a fin-type transistor. In addition, an insulator having a mask for forming the convex portion in a manner that contacts the top of the convex portion may also be provided. In addition, although the case where a part of the semiconductor substrate is processed to form the convex portion is shown here, the SOI (Silicon on Insulator) substrate may also be processed to form a semiconductor film having a convex shape.

[0496] Notice, Fig.29 The structure of the transistor 310 shown is just an example, and the present invention is not limited to this structure, and an appropriate transistor can be used according to the circuit structure or driving method.

[0497] A wiring layer including an interlayer film, wiring, and plugs may be provided between the structures. In addition, the wiring layer may be provided in a plurality of layers according to the design. In addition, in this specification, wiring and a plug electrically connected to the wiring may also be one component. That is, a part of the conductor may be used as wiring, and a part of the conductor may be used as a plug.

[0498] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on the transistor 310. In addition, a conductor 328 and the like are embedded in the insulator 320 and the insulator 322. In addition, a conductor 330 and the like are embedded in the insulator 324 and the insulator 326. In addition, the conductor 328 and the conductor 330 are used as contact plugs or wirings.

[0499] Furthermore, the insulator used as an interlayer film may also be used as a planarization film to cover the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulator 322, planarization may be achieved by a planarization process such as chemical mechanical polishing (CMP).

[0500] The transistor 200 and the capacitor 460 are provided on the insulator 326. Here, the transistor 200 uses Fig. 11CThe transistor 200 shown. The structure of the transistor 200 and the layer formed with the transistor 200 is the same as the above structure, so the same hatching and symbols are attached to them and shown. For the detailed structure, reference can be made to the above description. In addition, an insulator 285 is formed on the insulator 283, and a conductor 413 electrically connected to the conductor 240a is formed on the insulator 285. The insulating material that can be used for the insulator 216 can be used for the insulator 285. In addition, the conductive material that can be used for the conductor 242 can be used for the conductor 413.

[0501] The capacitor 460 includes an oxide semiconductor 452, a conductor 242b1 on the oxide semiconductor 452, an insulator 454 on the conductor 242b1, and a conductor 456 on the insulator 454. Fig.29 , Fig. 30A and Fig. 30B As shown, the oxide semiconductor 452 has the same structure as the oxide semiconductor 230 and can be formed using the same process. The capacitor 460 and the transistor 200 share the conductor 242b1. The insulator 454 has the same structure as the insulator 250 and can be formed using the same process. The conductor 456 has the same structure as the conductor 260 and can be formed using the same process.

[0502] In parallel manufacturing Fig.29 In the case of the transistor 200 and the capacitor 460 shown in the figure, when etching is performed on the conductor to be the conductor 242b1, the region of the capacitor 460 overlapping with the oxide semiconductor 452 is not subjected to the etching process, thereby forming a structure in which the oxide semiconductor 452 is covered with the conductor 242b1. Thus, the capacitor 460 including the conductor 242b1, the insulator 454, and the conductor 456 can be manufactured in parallel with the transistor 200.

[0503] Here, the capacitor 460 includes the conductor 242b1 serving as a first electrode, the conductor 456 serving as a second electrode, and the insulator 454 serving as a dielectric. That is, the capacitor 460 forms a MIM (Metal-Insulator-Metal) capacitor.

[0504] Capacitor 460 has a structure similar to transistor 200 and can be manufactured in parallel in the same layer as transistor 200. Thus, insulator 454 and conductor 456 are provided in openings formed in insulator 280 and insulator 275. However, capacitor 460 is different from transistor 200 in that, in the former, conductor 242b1 is provided to overlap conductor 456 and insulator 454. Therefore, the above-mentioned opening reaches conductor 242b1, and insulator 454 contacts the top surface of conductor 242b1 in the above-mentioned opening.

[0505] like Fig. 30B As shown, the oxide semiconductor 452 of the capacitor 460 has a structure with a high aspect ratio similar to the oxide semiconductor 230, so a plurality of oxide semiconductors 452 may be provided. Thus, the oxide semiconductor 452 is similar to the oxide semiconductor 230, and when the cross section is viewed from the channel width direction, the height of the oxide semiconductor 452 is greater than the width of the oxide semiconductor 452. In addition, similar to the oxide semiconductor 230, when viewed from above, the oxide semiconductor 452 has two or more regions overlapping with the conductor 456. Thus, the area where the conductor 242b1, the insulator 454, and the conductor 456 disposed along the top surface and the side surface of the oxide semiconductor 452 are opposite to each other can be increased. In this way, the electrostatic capacitance can be increased without increasing the occupied area of ​​the capacitor 460.

[0506] In addition, a conductor 458 is provided in the openings formed in the insulators 215, 216, and 221. The conductor 458 can have the same structure as the conductor 240, for example. The top surface of the conductor 458 is in contact with the bottom surface of the conductor 242b1, and can be electrically connected to the conductor 330. Fig.29 Although only one conductor 458 is shown in the figure, the present invention is not limited to this, and two or more conductors may be used to electrically connect the conductor 242b1 and the conductor 330. In addition, a part of the conductor 242b1 may be embedded in the openings of the insulators 215, 216, and 221.

[0507] By adopting the above structure, a 2T1C type memory cell can be formed by electrically connecting one of the source and drain of the transistor 200, one electrode of the capacitor 460, and the gate of the transistor 310. In addition, by adopting a structure without providing the transistor 310, a 1T1C type memory cell can be formed. In addition, by adopting a structure without providing the capacitor 460, a 2T0C type memory cell can be formed.

[0508] Here, the transistor 310 is preferably provided so as to overlap at least one of the transistor 200 and the capacitor 460. For example, a structure in which the transistor 310 overlaps the transistor 200 may be employed. By employing such a structure, the area occupied by the memory cell can be reduced.

[0509] In addition, Fig.29 In the structure shown in FIG. 1 , the transistor 200 and the capacitor 460 respectively include an oxide semiconductor 230 and an oxide semiconductor 452, but the present invention is not limited thereto. Fig. 30BAs shown in FIG. 1 , an insulator 250, a conductor 260, an insulator 454, and a conductor 456 may be formed on the oxide semiconductor 230. In other words, a structure may be adopted in which the transistor 200 and the capacitor 460 share the oxide semiconductor 230. In this way, it is not necessary to form a pattern in a manner of dividing the oxide semiconductor 230 into the transistor 200 and the capacitor 460, so that the occupied area of ​​the transistor 200 and the capacitor 460 can be reduced.

[0510] In addition, Fig.29 The structure shown in FIG. 1 shows a structure in which a transistor 310 formed on a silicon substrate is provided, but the present invention is not limited thereto. Fig.31A As shown, a structure in which two transistors (hereinafter referred to as transistor 200a and transistor 200b) having the same structure as the above-mentioned transistor 200 may be provided. Here, transistor 200a and transistor 200b are formed in the same layer and are arranged in a manner that their respective channel length directions intersect each other. Note that since transistor 200a and transistor 200b have the same structure as transistor 200, the same hatching and symbols are attached to the constituent elements and shown. For the detailed structure, reference can be made to the above description.

[0511] In addition, Fig.31A In the structure shown, a capacitor 400 is provided on an insulator 285. The capacitor 400 includes a conductor 410 on the insulator 285, an insulator 430 on the conductor 410, and a conductor 420 on the insulator 430. A conductor 240b, an insulator 241b, a conductor 240c, and an insulator 241c are provided in a manner in contact with the bottom surface of the conductor 410. Here, the conductor 240c and the insulator 241c are formed in a manner embedded in the openings of the insulator 282, the insulator 283, and the insulator 285, and have the same structure as the conductor 240b and the insulator 241b. The bottom surface of the conductor 240c is in contact with the top surface of the conductor 260 of the transistor 200b. By adopting this structure, one of the source and drain of the transistor 200a, one electrode of the capacitor 400, and the gate of the transistor 200b are electrically connected.

[0512] The capacitor 400 includes a conductor 410 serving as a first electrode, a conductor 420 serving as a second electrode, and an insulator 430 serving as a dielectric. That is, the capacitor 400 constitutes a MIM capacitor.

[0513] The conductive material that can be used for the conductive body 260 can be used for the conductive body 410 and the conductive body 420. For example, tungsten can be used for the conductive body 410 and the conductive body 420. Here, by adopting a structure in which the conductive body 420 covers the conductive body 410, the area sandwiched between the side surface of the conductive body 410 and the conductive body 420 can also be used as the capacitor 400. As a result, the electrostatic capacitance of the capacitor 400 can be increased. In addition, the conductive body 413 can be formed at the same time as the conductive body 410.

[0514] The conductors 410, 413, and 420 have a single-layer structure, but are not limited to this structure, and may have a stacked structure of two or more layers. For example, a stacked structure of a conductor having barrier properties and a conductor having high conductivity may be used. For example, a stacked structure of titanium nitride and tungsten on titanium nitride may be used.

[0515] The insulator 430 included in the capacitor 400 preferably uses a material with a high relative dielectric constant (high-k). As high-k materials, there are gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium. By using such a high-k material, the thickness of the insulator 430 can be set to a level that can suppress leakage current, and the electrostatic capacitance of the capacitor 400 can be fully ensured. In addition, the insulator 430 is formed in a manner that covers the conductor 410, so it is preferably deposited using a deposition method with high coverage such as the ALD method or the CVD method.

[0516] In addition, the insulator 430 may also have a stacked structure. It is preferable to use a stacked structure of a material with a high relative dielectric constant (high-k) and a material with a dielectric strength greater than that of the material with a high relative dielectric constant (high-k). As materials with a high dielectric strength (materials with a low relative dielectric constant), there are silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, etc. The insulator 430 may have a stacked structure of aluminum oxide, which is a material with a high relative dielectric constant (high-k), and silicon oxide with a high dielectric strength on the aluminum oxide.

[0517] In addition, for example, as the insulator 430, an insulator in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in sequence can be used. In addition, for example, an insulator in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in sequence can be used. In addition, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are stacked in sequence can be used. By stacking an insulator having a large dielectric strength such as aluminum oxide, the dielectric strength is increased and the electrostatic destruction of the capacitor 400 can be suppressed.

[0518] In addition, a material having ferroelectricity may be used for the insulator 430. Examples of the material having ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) and other metal oxides. In addition, as a material that can have ferroelectricity, a material in which an element J1 (herein, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide can be cited. Here, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be appropriately set. For example, the ratio of the number of atoms of hafnium to the number of atoms of element J1 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, a material in which an element J2 (herein, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide can be cited. In addition, the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be appropriately set. For example, the ratio of the number of atoms of zirconium to the number of atoms of element J2 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tant...

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: forming a first coating film on a first insulator and a second coating film on the first coating film; forming a first layer by removing a portion of the second coating film; forming a second layer by removing a portion of the first coating film using the first layer as a mask; Perform heat treatment; forming a first oxide semiconductor in a manner covering a top surface of the first insulator, a side surface of the second layer, and a side surface and a top surface of the first layer; Processing the first oxide semiconductor by anisotropic etching to form a second oxide semiconductor in contact with a side surface of the second layer; removing the first layer; as well as By removing the second layer, the side surfaces of the second oxide semiconductor covered by the second layer are exposed.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the first coating film is an organic resin, And the second coating film contains silicon, oxygen and carbon.

3. The method for manufacturing a semiconductor device according to claim 1, Part of the first insulator is removed when the first layer is removed.

4. The method for manufacturing a semiconductor device according to claim 1, The heat treatment is performed at a temperature of 200° C. to 400° C.

5. The method for manufacturing a semiconductor device according to claim 1, The second layer is removed by using microwave treatment.

6. The method for manufacturing a semiconductor device according to claim 1, wherein the first oxide semiconductor is formed by a process of forming a third oxide semiconductor, a process of forming a fourth oxide semiconductor on the third oxide semiconductor, and a process of forming a fifth oxide semiconductor on the fourth oxide semiconductor, The third oxide semiconductor and the fifth oxide semiconductor are formed by an ALD method using an oxidant and a precursor containing indium. And the fourth oxide semiconductor is formed by a sputtering method using a sputtering target including zinc.

7. A method for manufacturing a semiconductor device, comprising the following steps: forming a second insulator on the first insulator; forming a first coating film on the second insulator and a second coating film on the first coating film; forming a first layer by removing a portion of the second coating film; forming a second layer by removing a portion of the first coating film using the first layer as a mask; Perform heat treatment; forming a first oxide semiconductor in a manner covering a top surface of the second insulator, a side surface of the second layer, and a side surface and a top surface of the first layer; Processing the first oxide semiconductor by anisotropic etching to form a second oxide semiconductor in contact with a side surface of the second layer; removing regions of the first layer and the second insulator that do not overlap with the second layer and the second oxide semiconductor; By removing the second layer, a side surface of the second oxide semiconductor covered by the second layer is exposed; forming a first conductor in a manner of covering a top surface of the first insulator and a side surface of the second oxide semiconductor; forming a third insulator on the first conductor; forming an opening in the third insulator by removing a portion of the third insulator; removing a region of the first conductor that overlaps with the opening; forming a fourth insulator on the third insulator and in the opening of the third insulator, wherein the fourth insulator is formed in the opening to cover a side surface of the second oxide semiconductor; as well as A second conductor is formed on the fourth insulator.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the first coating film is an organic resin, And the second coating film contains silicon, oxygen and carbon.

9. The method for manufacturing a semiconductor device according to claim 7, The heat treatment is performed at a temperature of 200° C. to 400° C.

10. The method for manufacturing a semiconductor device according to claim 7, The second layer is removed by using microwave treatment.

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