Manufacturing method of field effect transistor and field effect transistor

Abstract

The invention discloses a manufacturing method of a field effect transistor and the field effect transistor, and the method comprises the steps: providing a semiconductor substrate, forming a semiconductor channel layer on the semiconductor substrate, and arranging a well region in the semiconductor substrate; a gate structure is formed, the gate structure is isolated from the semiconductor substrate through the semiconductor channel layer, and the gate structure is located on the well region; namely, on the basis of forming the semiconductor substrate with the well region, the semiconductor channel layer is formed on the semiconductor substrate and used for conducting electrons or holes, conduction of the electrons or the holes in the damaged area of the substrate under high-energy injection is avoided, the situation that the mobility is reduced due to impurity and defect scattering is further reduced, and the device performance is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a field effect transistor and a field effect transistor. Background Art

[0002] In the application process of integrated circuits, the performance of various devices will be affected by the order in which the layers of materials are formed, especially field-effect transistors, because the different formation times of the layers of materials affect the electrical performance of the device.

[0003] In current field effect transistors, high-energy injections, such as well injection, lightly doped injection, deep well injection, source-drain injection, etc., will damage silicon and cause defects in silicon, leading to impurity scattering and reduced mobility, affecting device performance. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a method for manufacturing a field effect transistor and a field effect transistor, which can effectively reduce the reduction in mobility caused by impurity scattering, thereby improving the performance of the device.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a method for manufacturing a field effect transistor, comprising: providing a semiconductor substrate and forming a semiconductor channel layer on the semiconductor substrate, wherein a well region is provided in the semiconductor substrate; forming a gate structure, wherein the gate structure is isolated from the semiconductor substrate by the semiconductor channel layer, wherein the gate structure is located above the well region.

[0006] In one embodiment of the present application, providing a semiconductor substrate and forming a semiconductor channel layer on the semiconductor substrate includes: providing a semiconductor substrate and forming the well region in the semiconductor substrate; forming the semiconductor channel layer on the semiconductor substrate to at least cover the well region in the semiconductor substrate.

[0007] In an embodiment of the present application, the material of the semiconductor channel layer is one or more of germanium, silicon germanium, germanium tin, and III-V group materials.

[0008] In one embodiment of the present application, the method further includes: forming an oxide layer to cover the semiconductor channel layer; forming the gate structure on the oxide layer in the well region, and forming isolation sidewalls on both sides of the gate structure.

[0009] In one embodiment of the present application, after forming the gate structure, it also includes: performing ion implantation at a preset angle from the semiconductor channel layer toward the well region to respectively form a first lightly doped region and a second lightly doped region; wherein the first lightly doped region and the second lightly doped region are located in the well region under the isolation side walls on both sides of the gate structure.

[0010] In one embodiment of the present application, a first source / drain region and a second source / drain region are further provided in the well region, which are respectively located in the well region on both sides of the gate structure; wherein the first source / drain region is in contact with the first lightly doped region, and the second source / drain region is in contact with the second lightly doped region.

[0011] In one embodiment of the present application, it also includes: forming an interlayer dielectric layer, and forming connecting pillars in the interlayer dielectric layer, the connecting pillars including gate connecting pillars and source / drain connecting pillars; wherein the gate connecting pillars correspond to connecting the gate structure, and the source / drain connecting pillars correspond to connecting the source / drain regions in the well region.

[0012] In one embodiment of the present application, it further includes: an isolation structure, which is disposed in the semiconductor substrate; wherein different field effect transistors are isolated by the isolation structure.

[0013] To solve the above technical problems, another technical solution adopted in the present application is: to provide a field effect transistor, comprising: a semiconductor substrate, wherein a well region is formed in the semiconductor substrate; a semiconductor channel layer, arranged on the semiconductor substrate; and a gate structure, arranged on the semiconductor channel layer in the well region.

[0014] In an embodiment of the present application, the material of the semiconductor channel layer is one or more of silicon, germanium, silicon germanium, germanium tin, and III-V group materials.

[0015] In one embodiment of the present application, it further includes: an oxide layer disposed on the semiconductor channel layer, and the gate structure is disposed on the oxide layer of the well region.

[0016] In one embodiment of the present application, it also includes: a first lightly doped region and a second lightly doped region, which are arranged in the well region; wherein at least a portion of the first lightly doped region is located under the isolation sidewall on one side of the gate structure, and at least a portion of the second lightly doped region is located under the isolation sidewall on the other side of the gate structure.

[0017] In one embodiment of the present application, it also includes: a first source / drain region and a second source / drain region, which are arranged in the well region; wherein the first source / drain region is in contact with the first lightly doped region, and the second source / drain region is in contact with the second lightly doped region.

[0018] In one embodiment of the present application, it also includes: an interlayer dielectric layer, and a connecting column is formed in the interlayer dielectric layer, and the connecting column includes a gate connecting column and a source / drain connecting column; wherein the gate connecting column corresponds to connecting the gate structure, and the source / drain connecting column corresponds to connecting the source / drain region in the well region.

[0019] In one embodiment of the present application, it further includes: an isolation structure disposed in the semiconductor substrate; wherein different field effect transistors are isolated by the isolation structure.

[0020] Different from the prior art, the manufacturing method of the field effect transistor provided in the present application includes: providing a semiconductor substrate and forming a semiconductor channel layer on the semiconductor substrate, wherein a well region is provided in the semiconductor substrate; forming a gate structure, wherein the gate structure is isolated from the semiconductor substrate by the semiconductor channel layer, wherein the gate structure is located above the well region; that is, in the present application, on the basis of a semiconductor substrate having a well region, a semiconductor channel layer is formed on the semiconductor substrate for the conduction of electrons or holes, and the semiconductor channel layer is formed after high-energy injection into the well region of the substrate, so as to avoid the conduction of electrons or holes in the damaged area of ​​the substrate under high-energy injection, thereby reducing the reduction in mobility caused by impurity and defect scattering, and effectively improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0022] Figure 1 This is a flow chart of an embodiment of a method for manufacturing a field effect transistor in the present application;

[0023] Figure 2 is a schematic structural diagram of an embodiment of a semiconductor substrate in the present application;

[0024] Figure 3 It is a structural schematic diagram of an embodiment of forming a semiconductor channel layer in the present application;

[0025] Figure 4 is a structural schematic diagram of an embodiment of forming a gate structure in the present application;

[0026] Figure 5 It is a structural schematic diagram of an embodiment of forming a lightly doped region and a source / drain region in the present application;

[0027] Figure 6is a schematic diagram of the structure of an embodiment of forming an interlayer dielectric layer and a connecting column in the present application; that is, a schematic diagram of the structure of the first embodiment of a field effect transistor in the present application;

[0028] Figure 7 It is a schematic structural diagram of the second embodiment of the field effect transistor in the present application.

[0029] In the accompanying drawings, there are a semiconductor substrate 100, a well region 110, a first well region 1101, a second well region 1102, an isolation structure 101, a first lightly doped region 111, a second lightly doped region 112, a first source / drain region 113, a second source / drain region 114, a semiconductor channel layer 200, a gate structure 300, a gate material filling layer 310, an isolation sidewall 301, a first gate structure 3101, a second gate structure 3102, an oxide layer 400, an interlayer dielectric layer 500, a gate connection column 501, a source / drain connection column 502, a first sub-doped region LDD1, a second sub-doped region LDD2, a third sub-doped region LDD3 and a fourth sub-doped region LDD4, a first sub-source / drain region SD1, a second sub-source / drain region SD2, a third sub-source / drain region SD3, and a fourth sub-source / drain region SD4. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0031] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0032] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0033] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0034] In existing field-effect transistors, the electron / hole mobility is related to scattering, impurity, lattice and defect scattering; usually, the 2X process (2xnm process) node will encounter multiple high-energy injection steps, such as well injection, lightly doped injection, deep well injection, source and drain injection, etc., which will damage the silicon and cause defects in the silicon, thereby causing impurity scattering and causing reduced mobility, affecting the performance of the device.

[0035] Therefore, a method for manufacturing a field effect transistor is provided, which can effectively reduce impurity and defect scattering, thereby improving device performance.

[0036] See also Figure 1 , Figure 1 FIG. 1 is a flow chart of an embodiment of a method for manufacturing a field effect transistor in the present application. Figure 1 As shown, the method for manufacturing the field effect transistor of the present application comprises the following steps:

[0037] S10, providing a semiconductor substrate, and forming a semiconductor channel layer on the semiconductor substrate, wherein a well region is provided in the semiconductor substrate.

[0038] Among them, the semiconductor substrate is any suitable substrate known in the semiconductor device, the semiconductor channel layer refers to any suitable semiconductor thin film layer known in the semiconductor device, that is, the channel layer for electron or hole conduction, and the well region refers to the doped region formed by ion implantation into the semiconductor substrate.

[0039] Specifically, a semiconductor substrate is provided, and a semiconductor channel layer is formed on the semiconductor substrate, so that the semiconductor channel layer covers the entire semiconductor substrate to form a complete crystal structure on the semiconductor substrate, and then the semiconductor channel layer conducts electrons or holes to reduce the conduction of electrons or holes in the damaged area of ​​the semiconductor substrate, wherein a well region is formed in the semiconductor substrate.

[0040] It can be understood that the semiconductor channel layer is formed after high-energy implantation into the semiconductor substrate, and therefore, the semiconductor channel layer is a complete crystal structure.

[0041] S20, forming a gate structure, wherein the gate structure is isolated from the semiconductor substrate by the semiconductor channel layer, wherein the gate structure is located above the well region.

[0042] The gate structure refers to a gate structure corresponding to the gate material filled therein.

[0043] Specifically, after a semiconductor channel layer is formed on a semiconductor substrate, a gate material is formed on the semiconductor channel layer to form a gate structure, and the gate structure is generated on a well region in the semiconductor substrate.

[0044] In this embodiment, on the basis of a semiconductor substrate with a well region, a semiconductor channel layer is covered on the semiconductor substrate. The semiconductor channel layer is used for the conduction of electrons or holes. The semiconductor channel layer is formed after high-energy injection into the well region of the substrate to prevent electrons or holes from being conducted in the damaged region of the substrate under high-energy injection, thereby effectively reducing impurity and defect scattering, improving the mobility of the device, and thus improving the device performance.

[0045] The following is described in conjunction with the accompanying drawings, and the operation flow of step S10 is as follows:

[0046] A semiconductor substrate 100 is provided, and a semiconductor channel layer 200 is formed on the semiconductor substrate 100 , wherein a well region 110 is disposed in the semiconductor substrate 100 .

[0047] Among them, the semiconductor substrate can be any suitable base material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI).

[0048] First, a semiconductor substrate is provided.

[0049] See also Figure 2 , Figure 2 It is a schematic structural diagram of an embodiment of a semiconductor substrate in the present application.

[0050] like Figure 2 As shown, a well region 110 is provided in the semiconductor substrate 100 , wherein the well region 110 may be an N-well region or a P-well region, for example, an N-well region is formed by N-type ion implantation, and a P-well region is formed by P-type ion implantation.

[0051] In some embodiments, an isolation structure 101 is also formed in the semiconductor substrate 100, wherein there are multiple isolation structures 101 for dividing the well region 110 from other parts of the semiconductor substrate; for example, in the case of a single transistor, the well region 110 is located in the central area of ​​the semiconductor substrate 100, and two isolation structures 101 are respectively on both sides of the well region 110 to divide the well region 110 from other parts of the semiconductor substrate 100; wherein the isolation structure 101 can be flush with the semiconductor substrate 100, or slightly higher than the semiconductor substrate 100.

[0052] Next, a semiconductor channel layer is formed on the semiconductor substrate.

[0053] See also Figure 3 , Figure 3 It is a structural schematic diagram of an embodiment of forming a semiconductor channel layer in the present application.

[0054] like Figure 3 As shown, in Figure 2 On the basis of the semiconductor substrate 100 , a semiconductor channel layer 200 is formed on the semiconductor substrate 100 .

[0055] Among them, the material of the semiconductor channel layer 200 can be a material that replaces the semiconductor substrate 100. For example, when the material of the semiconductor substrate 100 is silicon, the semiconductor channel layer 200 can be a combination of one or more materials such as silicon, germanium, silicon germanium, germanium tin, III-V group materials, etc., that is, when the semiconductor substrate 100 is damaged, the semiconductor channel layer 200 has a complete crystal structure, which can be a repair of the semiconductor substrate 100, and the semiconductor channel layer 200 is used for the conduction of electrons or holes to reduce the reduction of electron / hole mobility caused by impurity scattering, that is, a protective layer is covered on the semiconductor substrate 100.

[0056] In some embodiments, the semiconductor channel layer 200 may cover the entire surface of the semiconductor substrate 100 , or the isolation structure 101 may be exposed from the semiconductor channel layer 200 , while the semiconductor channel layer 200 covers other parts of the semiconductor substrate 100 except the isolation structure.

[0057] The specific operation process of step S20 is as follows:

[0058] On the basis of step S10 , a gate structure is formed, wherein the gate structure is isolated from the semiconductor substrate by the semiconductor channel layer, wherein the gate structure is located above the well region.

[0059] See also Figure 4 , Figure 4 It is a structural schematic diagram of an embodiment of forming a gate structure in the present application.

[0060] like Figure 4 As shown, in Figure 3On the basis of, a gate structure 300 is formed on the semiconductor channel layer 200 in the well region 110 .

[0061] The gate structure 300 includes a gate material filling layer 310 and an isolation spacer 301 , that is, the gate material filling layer 310 is formed on the semiconductor channel layer 200 of the well region 110 , and the isolation spacer 301 covers both side walls of the gate material filling layer 310 .

[0062] In some embodiments, before the gate structure 300 is formed, an oxide layer 400 may be formed on the semiconductor channel layer 200 , that is, the oxide layer 400 covers the semiconductor channel layer 200 , so that the semiconductor channel layer 200 is isolated from the subsequently formed gate structure 300 .

[0063] In some embodiments, the gate structure may further include a metal covering layer and a gate metal structure, wherein the metal covering layer is disposed between the semiconductor channel layer and the gate metal structure. Further, the metal covering layer may include a first sub-metal covering layer and a second sub-metal covering layer, wherein the first sub-metal covering layer is located in the central region of the gate metal structure, and the second sub-metal covering layer is located on at least one side of the first sub-metal covering layer, for example, the second sub-metal covering layer is located on one side of the first sub-metal covering layer, or the second sub-metal covering layer is located on both sides of the first sub-metal covering layer. The material of the second sub-metal covering layer is different from that of the first sub-metal covering layer, and the work function of the second sub-metal covering layer is different from the work function of the first sub-metal covering layer.

[0064] Specifically, when the gate structure is a gate structure of a P-type transistor, the work function of the second sub-metal covering layer is lower than the work function of the first sub-metal covering layer; when the gate structure is a gate structure of an N-type transistor, the work function of the second sub-metal covering layer is higher than the work function of the first sub-metal covering layer.

[0065] Furthermore, the gate metal structure includes a work function adjustment layer and a metal gate filling layer, wherein the metal gate filling layer can be a gate material filling layer 310; the work function adjustment layer covers the first sub-metal covering layer and the second sub-metal covering layer. In some embodiments, the work function adjustment layer and the metal gate filling layer can be formed by an atomic deposition process, and then a CMP (Chemical Mechanical Polishing) process is used for planarization.

[0066] Further, the work function adjustment layer may include a first sub-work function adjustment layer, a second sub-work function adjustment layer and a third sub-work function adjustment layer; that is, the first sub-work function adjustment layer, the second sub-work function adjustment layer and the third sub-work function adjustment layer are sequentially formed on the metal cover layer, wherein the material of the first sub-work function adjustment layer may be TaN, the material of the second sub-work function adjustment layer may be TiN, and the material of the third sub-work function adjustment layer may be TaN. In other embodiments, the first work function adjustment layer may also be set to other structures, or set to other materials according to different requirements and process parameters, such as TaAlN. In some embodiments, the material of the metal gate filling layer is Al. In other embodiments, the metal gate filling layer may also be set to other low-resistance metal materials.

[0067] Furthermore, after forming the gate structure, it is also necessary to form a lightly doped region and a source / drain region.

[0068] See also Figure 5 , Figure 5 It is a structural schematic diagram of an embodiment of forming lightly doped regions and source / drain regions in the present application.

[0069] like Figure 5 As shown, in Figure 4 On this basis, ion implantation is performed from the semiconductor channel layer 200 toward the well region 110 at a preset angle to form a lightly doped region, and the lightly doped region may include a first lightly doped region 111 and a second lightly doped region 112 .

[0070] The first lightly doped region 111 and the second lightly doped region 112 are located in the well region 110 under the isolation spacers 301 on both sides of the gate structure 300 .

[0071] In some embodiments, source / drain regions are further formed in the well region 110 . The source / drain regions include a first source / drain region 113 and a second source / drain region 114 , which are respectively located in the well region 110 on both sides of the gate structure 300 .

[0072] Among them, the first source / drain region 113 is in contact with the first lightly doped region 111, and the second source / drain region 114 is in contact with the second lightly doped region 112; for example, the first source / drain region 113 is a source region, and the second source / drain region 114 is a drain region, then the first lightly doped region 111 is in contact with the source region, and the second lightly doped region 112 is in contact with the drain region.

[0073] In some embodiments, when forming a lightly doped region and a source / drain region, the corresponding semiconductor channel layer is also ion-implanted to form a part of the lightly doped region or the source / drain region, that is, the semiconductor channel layer above the lightly doped region also forms a part of the lightly doped region, and the semiconductor channel layer above the source / drain region also forms a part of the source / drain region.

[0074] In some embodiments, a portion of the semiconductor substrate may be reserved between the source / drain region and the isolation structure and covered by the semiconductor channel layer.

[0075] In some embodiments, when forming the gate structure 300 , the oxide layer in the area outside the gate structure 300 may be etched away, that is, only the oxide layer in the area where the gate structure 300 is located is retained.

[0076] Furthermore, an interlayer dielectric layer is formed.

[0077] See also Figure 6 , Figure 6 It is a structural schematic diagram of an embodiment of forming an interlayer dielectric layer and a connecting column in the present application, that is, a structural schematic diagram of the first embodiment of a field effect transistor in the present application.

[0078] like Figure 6 As shown, in Figure 5 On the basis of, an interlayer dielectric layer 500 is formed, and connecting pillars are formed in the interlayer dielectric layer, the connecting pillars include a gate connecting pillar 501 and a source / drain connecting pillar 502, the source / drain connecting pillars may include a first source / drain connecting pillar and a second source / drain connecting pillar; wherein, the gate connecting pillar 501 corresponds to the gate structure 300, and the source / drain connecting pillars correspond to the source / drain regions in the well region 110, for example, the first source / drain connecting pillar corresponds to the first source / drain region 113, and the second source / drain connecting pillar corresponds to the second source / drain region 114.

[0079] In this embodiment, a single transistor structure is formed. On the basis of a semiconductor substrate with a well region, a semiconductor channel layer is formed on the semiconductor substrate to form a complete crystal structure for the conduction of electrons or holes. The semiconductor channel layer is formed after high-energy injection into the well region of the substrate to prevent electrons or holes from being conducted in damaged areas of the substrate under high-energy injection, thereby reducing the reduction in mobility caused by impurity and defect scattering, and effectively improving device performance.

[0080] In some embodiments, a dual-transistor structure is also possible.

[0081] See also Figure 7 , Figure 7 It is a schematic structural diagram of the second embodiment of the field effect transistor in the present application.

[0082] like Figure 7As shown, the field effect transistor has a dual transistor structure, that is, a first well region 1101 and a second well region 1102 are set in the semiconductor substrate 100. The first well region 1101 and the second well region 1102 can be formed in advance by ion implantation in the semiconductor substrate 100, and the doping types of the first well region 1101 and the second well region 1102 are opposite; for example, the first well region is an N-well region, and the second well region is a P-well region, or the first well region is a P-well region, and the second well region is an N-well region.

[0083] Continue reading Figure 7 The semiconductor substrate 100 also has an isolation structure 101 formed therein, which may be a shallow trench isolation structure. The first well region 1101 is divided from the second well region 1102 by the isolation structure 101, and the isolation structure 101 may be formed by pre-forming a groove in the semiconductor substrate 100 and filling it with an isolation material. When the semiconductor channel layer 200 is formed on the semiconductor substrate 100, the semiconductor channel layer 200 at least covers the first well region 1101 and the second well region 1102 at the same time.

[0084] In some embodiments, the gate structure 300 may also include a first gate structure 3101 and a second gate structure 3102 . For example, the first gate structure 3101 is located on the first well region 1101 , and the second gate structure 3102 is located on the second well region 1102 .

[0085] In some embodiments, an oxide layer 400 is further formed to cover the semiconductor channel layer, and the first gate structure 3101 is located on the oxide layer 400 of the first well region 1101 , and the second gate structure 3102 is located on the oxide layer 400 of the second well region 1102 .

[0086] Correspondingly, the lightly doped region in the first well region 1101 may include a first sub-doped region LDD1 and a second sub-doped region LDD2, and the source / drain region in the first well region 1101 may include a first sub-source / drain region SD1 and a second sub-source / drain region SD2. Then, the first sub-doped region LDD1 is located under the isolation sidewall on one side of the first gate structure 3101, and the second sub-doped region LDD2 is located under the isolation sidewall on the other side of the first gate structure 3101, and the first sub-doped region LDD1 is in contact with the first sub-source / drain region SD1, and the second sub-doped region LDD2 is in contact with the second sub-source / drain region SD2.

[0087] The lightly doped region in the second well region 1102 may include a third sub-doped region LDD3 and a fourth sub-doped region LDD4, and the source / drain region in the second well region 1102 may include a third sub-source / drain region SD3 and a fourth sub-source / drain region SD4. Then, the third sub-doped region LDD3 is located under the isolation sidewall on one side of the second gate structure 3102, and the fourth sub-doped region LDD4 is located under the isolation sidewall on the other side of the second gate structure 3102, and the third sub-doped region LDD3 is in contact with the third sub-source / drain region SD3, and the fourth sub-doped region LDD4 is in contact with the fourth sub-source / drain region SD4.

[0088] Furthermore, a gate connection column 501 and a source / drain connection column 502 are formed in the interlayer dielectric layer 500, wherein the gate connection column 501 includes a first gate connection column and a second gate connection column, the first gate connection column corresponds to the first gate structure 3101, and the second gate connection column corresponds to the second gate structure 3102; the source / drain connection column 502 includes a first source / drain connection column, a second source / drain connection column, a third source / drain connection column and a fourth source / drain connection column, the first source / drain connection column corresponds to the first sub-source / drain region SD1, the second source / drain connection column corresponds to the second sub-source / drain region SD2, the third source / drain connection column corresponds to the third sub-source / drain region SD3, and the fourth source / drain connection column corresponds to the fourth sub-source / drain region SD4.

[0089] In this embodiment, it is a dual-transistor structure with the same technical effect as a single-transistor structure. On the basis of a semiconductor substrate with a well region, a semiconductor channel layer is formed on the semiconductor substrate to form a complete crystal structure for the conduction of electrons or holes. The semiconductor channel layer is formed after high-energy injection into the well region of the substrate to prevent electrons or holes from being conducted in damaged areas of the substrate under high-energy injection, thereby reducing the reduction in mobility caused by impurity and defect scattering, and effectively improving device performance.

[0090] The present application also provides a field effect transistor, see Figure 2-Figure 6 .

[0091] The field effect transistor includes: a semiconductor substrate 100 , a semiconductor channel layer 200 and a gate structure 300 , wherein a well region 110 is formed in the semiconductor substrate 100 ; the semiconductor channel layer 200 is disposed on the semiconductor substrate 100 ; and the gate structure 300 is disposed on the semiconductor channel layer 200 in the well region 110 .

[0092] In some embodiments, the semiconductor channel layer 200 is made of one or more of silicon, germanium, silicon germanium, germanium tin, and III-V group materials.

[0093] In some embodiments, the field effect transistor further includes: an oxide layer 400 , the oxide layer 400 is disposed on the semiconductor channel layer 200 , and the gate structure 300 is disposed on the oxide layer 400 of the well region 110 .

[0094] In some embodiments, the field effect transistor also includes: a first lightly doped region 111 and a second lightly doped region 112, and the first lightly doped region 111 and the second lightly doped region 112 are arranged in the well region 110; wherein at least part of the first lightly doped region 111 is located under the isolation sidewall 301 on one side of the gate structure 300, and at least part of the second lightly doped region 112 is located under the isolation sidewall 301 on the other side of the gate structure 300.

[0095] In some embodiments, the field effect transistor further includes: a first source / drain region and a second source / drain region, which are arranged in the well region 110; wherein the first source / drain region is in contact with the first lightly doped region 111, and the second source / drain region is in contact with the second lightly doped region 112.

[0096] In some embodiments, the field effect transistor also includes: an interlayer dielectric layer 500, and a connecting column is formed in the interlayer dielectric layer 500, and the connecting column includes a gate connecting column 501 and a source / drain connecting column 502; wherein the gate connecting column 501 corresponds to connecting the gate structure 300, and the source / drain connecting column 502 corresponds to connecting the source / drain region in the well region 110.

[0097] In some embodiments, the field effect transistor further includes an isolation structure 101 disposed in the semiconductor substrate 100 ; wherein different field effect transistors are isolated by the isolation structure 101 .

[0098] The present application also provides a field effect transistor, see Figure 7 , which is a dual transistor structure.

[0099] The field effect transistor includes: a semiconductor substrate 100, a semiconductor channel layer 200 and a first gate structure 3101 and a second gate structure 3102, wherein a first well region 1101 and a second well region 1102 are formed in the semiconductor substrate 100; the semiconductor channel layer 200 is arranged on the semiconductor substrate 100 and at least covers the first well region 1101 and the second well region 1102 at the same time; the first gate structure 3101 is located on the oxide layer 400 of the first well region 1101, and the second gate structure 3102 is located on the oxide layer 400 of the second well region 1102.

[0100] Correspondingly, the lightly doped region in the first well region 1101 may include a first sub-doped region LDD1 and a second sub-doped region LDD2, and the source / drain region in the first well region 1101 may include a first sub-source / drain region SD1 and a second sub-source / drain region SD2. Then, the first sub-doped region LDD1 is located under the isolation sidewall on one side of the first gate structure 3101, and the second sub-doped region LDD2 is located under the isolation sidewall on the other side of the first gate structure 3101, and the first sub-doped region LDD1 is in contact with the first sub-source / drain region SD1, and the second sub-doped region LDD2 is in contact with the second sub-source / drain region SD2.

[0101] The lightly doped region in the second well region 1102 may include a third sub-doped region LDD3 and a fourth sub-doped region LDD4, and the source / drain region in the second well region 1102 may include a third sub-source / drain region SD3 and a fourth sub-source / drain region SD4. Then, the third sub-doped region LDD3 is located under the isolation sidewall on one side of the second gate structure 3102, and the fourth sub-doped region LDD4 is located under the isolation sidewall on the other side of the second gate structure 3102, and the third sub-doped region LDD3 is in contact with the third sub-source / drain region SD3, and the fourth sub-doped region LDD4 is in contact with the fourth sub-source / drain region SD4.

[0102] Furthermore, a gate connection column 501 and a source / drain connection column 502 are formed in the interlayer dielectric layer 500, wherein the gate connection column 501 includes a first gate connection column and a second gate connection column, the first gate connection column corresponds to the first gate structure 3101, and the second gate connection column corresponds to the second gate structure 3102; the source / drain connection column 502 includes a first source / drain connection column, a second source / drain connection column, a third source / drain connection column and a fourth source / drain connection column, the first source / drain connection column corresponds to the first sub-source / drain region SD1, the second source / drain connection column corresponds to the second sub-source / drain region SD2, the third source / drain connection column corresponds to the third sub-source / drain region SD3, and the fourth source / drain connection column corresponds to the fourth sub-source / drain region SD4.

[0103] In this embodiment, a well region is formed in the semiconductor substrate, and then a semiconductor channel layer 200 is formed on the semiconductor substrate to form a perfect crystal structure for the conduction of electrons or holes. The semiconductor channel layer 200 is formed after high-energy injection of the well region of the substrate to prevent electrons or holes from being conducted in the damaged region of the substrate under high-energy injection, thereby reducing the reduction in mobility caused by impurity and defect scattering, and effectively improving device performance. When the field effect transistor is a dual-transistor structure, the semiconductor channel layer 200 at least covers the first well region 1101 and the second well region 1102 at the same time, and can also simplify the device manufacturing process.

[0104] The above description is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing a field effect transistor, characterized in that: include: Providing a semiconductor substrate, and forming a semiconductor channel layer on the semiconductor substrate, wherein the semiconductor substrate is provided with a well region; A gate structure is formed, wherein the gate structure is isolated from the semiconductor substrate by the semiconductor channel layer, wherein the gate structure is located above the well region.

2. The method according to claim 1, characterized in that The step of providing a semiconductor substrate and forming a semiconductor channel layer on the semiconductor substrate comprises: Providing a semiconductor substrate, and forming the well region in the semiconductor substrate; The semiconductor channel layer is formed on the semiconductor substrate, covering at least the well region in the semiconductor substrate.

3. The method according to claim 1 or 2, characterized in that: The semiconductor channel layer is made of one or more materials including silicon, germanium, silicon germanium, germanium tin, and III-V group materials.

4. The method according to claim 1, characterized in that: Also includes: forming an oxide layer to cover the semiconductor channel layer; The gate structure is formed on the oxide layer of the well region, and isolation sidewalls are formed on both sides of the gate structure.

5. The method according to claim 1, characterized in that After forming the gate structure, it also includes: Performing ion implantation at a preset angle from the semiconductor channel layer toward the well region to form a first lightly doped region and a second lightly doped region respectively; The first lightly doped region and the second lightly doped region are located in the well region under the isolation sidewalls on both sides of the gate structure.

6. The method according to claim 5, characterized in that The well region is also provided with a first source / drain region and a second source / drain region, which are respectively located in the well region on both sides of the gate structure; The first source / drain region is in contact with the first lightly doped region, and the second source / drain region is in contact with the second lightly doped region.

7. The method according to claim 1, characterized in that Also includes: Forming an interlayer dielectric layer, and forming connection pillars in the interlayer dielectric layer, wherein the connection pillars include gate connection pillars and source / drain connection pillars; The gate connection column is connected to the gate structure, and the source / drain connection column is connected to the source / drain region in the well region.

8. The method according to claim 1, characterized in that Also includes: an isolation structure, wherein the isolation structure is disposed in the semiconductor substrate; Wherein, different field effect transistors are isolated by the isolation structure.

9. A field effect transistor, characterized in that: include: A semiconductor substrate, wherein a well region is formed in the semiconductor substrate; A semiconductor channel layer, disposed on the semiconductor substrate; A gate structure is arranged on the semiconductor channel layer in the well region.

10. The field effect transistor according to claim 9, characterized in that: The semiconductor channel layer is made of one or more materials selected from the group consisting of germanium, silicon germanium, germanium tin, and III-V materials.

11. The field effect transistor according to claim 9, characterized in that: Also includes: An oxide layer is disposed on the semiconductor channel layer, wherein the gate structure is disposed on the oxide layer in the well region.

12. The field effect transistor according to claim 9, characterized in that: Also includes: A first lightly doped region and a second lightly doped region are disposed in the well region; At least part of the first lightly doped region is located under the isolation sidewall on one side of the gate structure, and at least part of the second lightly doped region is located under the isolation sidewall on the other side of the gate structure.

13. The field effect transistor according to claim 12, characterized in that: Also includes: A first source / drain region and a second source / drain region are disposed in the well region; The first source / drain region is in contact with the first lightly doped region, and the second source / drain region is in contact with the second lightly doped region.

14. The field effect transistor according to claim 9, characterized in that: Also includes: An interlayer dielectric layer, wherein connection pillars are formed in the interlayer dielectric layer, and the connection pillars include gate connection pillars and source / drain connection pillars; The gate connection column is connected to the gate structure, and the source / drain connection column is connected to the source / drain region in the well region.

15. The field effect transistor according to claim 9, characterized in that: Also includes: An isolation structure, disposed in the semiconductor substrate; Wherein, different field effect transistors are isolated by the isolation structure.

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