Semiconductor device

Abstract

Embodiments relate to a semiconductor device. The on-resistance can be reduced. The semiconductor device includes a semiconductor layer including a first semiconductor region of a first conductivity type, a third semiconductor region, and a second semiconductor region of a second conductivity type, and a gate electrode provided in the semiconductor layer, the second semiconductor region including first, second, and third regions, the first region being provided between the second region and the first semiconductor region, and the third region being provided between the first region and the second semiconductor region. The gate electrode includes a first portion facing the first region, a second portion facing the second region, and a third portion facing the third region, the first portion including a first material, the second portion including a second material, the third portion including a third material, and when the first conductivity type is n-type, the first conductivity type is n-type, the second conductivity type is n-type, and the third conductivity type is n-type. When the first conductivity type is p-type, the work functions of the first material and the third material are smaller than those of the second material, and when the first conductivity type is p-type, the work functions of the first material and the third material are larger than those of the second material.

Description

[0001] Related Application:

[0002] This application claims priority from Japanese Patent Application No. 2023-137670 (filing date: August 28, 2023) as a prior application, and the present application incorporates the entire contents of the prior application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Art

[0004] In order to reduce the size of transistors or improve performance, vertical transistors are used in which a gate electrode is buried in a trench provided in a semiconductor layer. In vertical transistors, it is required to reduce on-resistance. Summary of the invention

[0005] A semiconductor device according to an embodiment comprises: a semiconductor layer having a first surface and a second surface opposite to the first surface, and including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type arranged between the first semiconductor region and the first surface, and a third semiconductor region of the first conductivity type arranged between the second semiconductor region and the first surface; a first electrode arranged on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region; a second electrode arranged on the second surface side of the semiconductor layer; a gate electrode arranged in the semiconductor layer and opposite to the first semiconductor region, the second semiconductor region and the third semiconductor region; and a gate insulating layer arranged between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region , the second semiconductor region includes a first region, a second region and a third region, the first region is arranged between the second region and the first semiconductor region, the third region is arranged between the second region and the third semiconductor region, the gate electrode includes a first part, a second part and a third part, the first part is opposite to the first region, the second part is opposite to the second region, and the third part is opposite to the third region, the first part contains a first material, the second part contains a second material, and the third part contains a third material, when the first conductivity type is n-type and the second conductivity type is p-type, the work function of the first material and the work function of the third material are smaller than the work function of the second material, and when the first conductivity type is p-type and the second conductivity type is n-type, the work function of the first material and the work function of the third material are larger than the work function of the second material.

[0006] According to this embodiment, a semiconductor device capable of reducing on-resistance can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a schematic plan view of the semiconductor device according to the first embodiment.

[0008] Figure 2 It is a schematic plan view of the semiconductor device according to the first embodiment.

[0009] Figure 3 It is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0010] Figure 4 It is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0011] Figure 5 This is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0012] Figure 6 This is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0013] Figure 7 This is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0014] Figure 8 This is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0015] Fig. 9 This is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0016] Fig.10 This is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0017] Fig.11 This is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0018] Fig.12 This is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0019] Fig.13 This is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0020] Fig.14 This is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0021] Fig.15 This is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0022] Fig.16 This is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0023] Fig.17 This is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0024] Fig.18 This is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0025] Fig.19 is a schematic cross-sectional view of a semiconductor device according to a comparative example.

[0026] Fig. 20 It is a schematic cross-sectional view of a semiconductor device according to a third modified example of the first embodiment.

[0027] Fig.21 It is a schematic cross-sectional view of a semiconductor device according to a second embodiment.

[0028] Fig. 22 It is a schematic cross-sectional view of a semiconductor device according to a third modified example of the second embodiment.

[0029] Fig.23 It is a schematic cross-sectional view of a semiconductor device according to a third embodiment.

[0030] Fig.24 It is a schematic cross-sectional view of a semiconductor device according to a third embodiment.

[0031] Fig.25 It is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment.

[0032] Fig.26 It is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment.

[0033] Fig. 27 It is a schematic cross-sectional view of a semiconductor device according to a second modified example of the fifth embodiment.

[0034] Fig.28 It is a schematic cross-sectional view of a semiconductor device according to a sixth embodiment.

[0035] Fig.29 It is a schematic cross-sectional view of a semiconductor device according to a second modified example of the sixth embodiment.

[0036] Description of reference numerals:

[0037] 10Silicon layer (semiconductor layer)

[0038] 12 Source electrode (1st electrode)

[0039] 14Drain electrode (second electrode)

[0040] 16Gate electrode

[0041] 16a Part 1

[0042] 16b Part 2

[0043] 16c Part 3

[0044] 18Gate insulation layer

[0045] 34 drift region (first semiconductor region)

[0046] 36 Main body region (second semiconductor region)

[0047] 36a Area 1

[0048] 36b Area 2

[0049] 36c Area 3

[0050] 38 source region (third semiconductor region)

[0051] 61 1st insulation film

[0052] 62 2nd insulation film

[0053] 100MOSFET (semiconductor device)

[0054] 101MOSFET(semiconductor device)

[0055] 200MOSFET (semiconductor device)

[0056] 201MOSFET(semiconductor device)

[0057] 300MOSFET (semiconductor device)

[0058] 400MOSFET (semiconductor device)

[0059] 500MOSFET (semiconductor device)

[0060] 501MOSFET(semiconductor device)

[0061] 600MOSFET (semiconductor device)

[0062] 601MOSFET(semiconductor device)

[0063] F1 Page 1

[0064] F2 Page 2

[0065] Px position

[0066] Py Location DETAILED DESCRIPTION

[0067] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following description, the same reference numerals are given to the same or similar components, and the description of components that have been described once is appropriately omitted.

[0068] In the following description, n is sometimes used. + 、n、n - and p + ,p,p - These marks show the relative level of impurity concentration in each conductivity type. + Indicates that the impurity concentration of n-type is relatively high compared to n. - Indicates that the impurity concentration of n-type is relatively low compared to n. + Indicates that the impurity concentration of p-type is relatively high compared to p-type. - Indicates that the p-type impurity concentration is relatively low compared to the p-type. + Type, n - The type is referred to as n type, and the p + Type, p - Type is referred to as p-type.

[0069] The impurity concentration of a semiconductor device can be measured, for example, by secondary ion mass spectrometry (SIMS). In addition, the relative level of the impurity concentration of a semiconductor device can also be determined, for example, based on the level of the carrier concentration obtained by scanning capacitance microscopy (SCM). In addition, the width or depth of the impurity region of a semiconductor device can be obtained, for example, by SIMS. In addition, the width or depth of the impurity region of a semiconductor device can be obtained, for example, based on an SCM image.

[0070] The depth of a trench of a semiconductor device, the thickness of an insulating layer, and the like can be measured, for example, on an image obtained by a transmission electron microscope (TEM).

[0071] For example, the material of a component constituting a semiconductor device can be identified by Energy Dispersive X-ray Spectroscopy (EDX).

[0072] (First embodiment)

[0073] The semiconductor device of the first embodiment comprises: a semiconductor layer having a first surface and a second surface opposite to the first surface, and including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type arranged between the first semiconductor region and the first surface, and a third semiconductor region of the first conductivity type arranged between the second semiconductor region and the first surface; a first electrode arranged on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region; a second electrode arranged on the second surface side of the semiconductor layer; a gate electrode arranged in the semiconductor layer and opposite to the first semiconductor region, the second semiconductor region and the third semiconductor region; and a gate insulating layer arranged between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region. The second semiconductor region includes a first region, a second region and a third region, the first region is arranged between the second region and the first semiconductor region, the third region is arranged between the second region and the third semiconductor region, the gate electrode includes a first part, a second part and a third part, the first part is opposite to the first region, the second part is opposite to the second region, and the third part is opposite to the third region, the first part contains a first material, the second part contains a second material, and the third part contains a third material, when the first conductivity type is n-type and the second conductivity type is p-type, the work function of the first material and the work function of the third material are smaller than the work function of the second material, and when the first conductivity type is p-type and the second conductivity type is n-type, the work function of the first material and the work function of the third material are larger than the work function of the second material.

[0074] The semiconductor device of the first embodiment is a vertical transistor in which a gate electrode is buried in a trench. The semiconductor device of the first embodiment is a vertical power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor device of the first embodiment is MOSFET100. The trench in this specification is a groove-shaped or concave structure of the semiconductor layer itself, and a structure other than the semiconductor layer can be set inside.

[0075] Hereinafter, a case where the first conductivity type is the n-type and the second conductivity type is the p-type will be described. That is, a case where an n-channel MOSFET uses electrons as carriers will be described.

[0076] Figure 1 and Figure 2 It is a schematic plan view of the semiconductor device according to the first embodiment. Figure 1 It is a plan view showing a layout pattern of electrodes and wirings of MOSFET 100 . Figure 2 FIG. 1 is a top view showing a layout pattern of the trenches of MOSFET 100. Figure 2In FIG. 1 , the layout pattern of electrodes and wiring is represented by dotted lines.

[0077] Figure 3 and Figure 4 It is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 3 yes Figure 1 and Figure 2 The cross section of region X is shown. In addition, Figure 4 yes Figure 1 and Figure 2 A cross section of region Y is shown. Figure 3 Indicates the impurity concentration distribution of a part of the semiconductor layer.

[0078] exist Figure 1 and Figure 2 In the diagram, the left-right direction is defined as a first direction, and the up-down direction is defined as a second direction. Figure 3 and Figure 4 is a cross section perpendicular to the first direction. Figure 3 and Figure 4 In the example, the up-down direction is defined as the third direction.

[0079] MOSFET 100 includes a silicon layer 10 , a source electrode 12 , a drain electrode 14 , a gate electrode 16 , a gate insulating layer 18 , an interlayer insulating layer 20 , a gate electrode pad 22 , and a gate wiring 24 .

[0080] The silicon layer 10 is an example of a semiconductor layer. The source electrode 12 is an example of a first electrode. The drain electrode 14 is an example of a second electrode.

[0081] The gate electrode 16 includes a first portion 16a, a second portion 16b, and a third portion 16c. The gate wiring 24 includes a contact portion 24a.

[0082] The silicon layer 10 includes a trench 30, n + The drain region 32, n - type drift region 34, p-type body region 36, n + Type source region 38, p + Type of contact area 40.

[0083] The drift region 34 is an example of a first semiconductor region. The body region 36 is an example of a second semiconductor region. The source region 38 is an example of a third semiconductor region.

[0084] The main body region 36 includes a first region 36a, a second region 36b, and a third region 36c.

[0085] The silicon layer 10 is located between the source electrode 12 and the drain electrode 14. The silicon layer 10 has a first surface ( Figure 3 "F1" in the middle) and side 2 (in Figure 3The second surface F2 is opposite to the first surface F1.

[0086] The first direction and the second direction are directions parallel to the first face F1. In addition, the second direction is a direction intersecting the first direction. The second direction is a direction perpendicular to the first direction. In addition, the third direction is a direction perpendicular to the first face F1. The third direction is a direction perpendicular to the first direction and the second direction. The third direction is a direction from the source electrode 12 toward the drain electrode 14.

[0087] Hereinafter, the “depth” means the depth based on the first surface F1 , that is, it means the distance in the third direction based on the first surface F1 .

[0088] The silicon layer 10 is single crystal silicon (Si). The surface of the silicon layer 10 is, for example, a plane inclined at 0 degrees or more and 8 degrees or less with respect to the (100) plane.

[0089] n + The drain region 32 of type is provided in the silicon layer 10. The drain region 32 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The concentration of the n-type impurities in the drain region 32 is, for example, 1×10 18 cm -3 Above and 1×10 21 cm -3 the following.

[0090] n - The drift region 34 of the type is provided in the silicon layer 10 . The drift region 34 is provided between the drain region 32 and the first surface F1 . The drift region 34 is provided on the drain region 32 .

[0091] The drift region 34 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The concentration of the n-type impurities in the drift region 34 is, for example, 1×10 15 cm -3 Above and 1×10 18 cm -3 The drift region 34 is, for example, + An epitaxial growth layer formed by epitaxial growth on the drain region 32 of the type.

[0092] The thickness of the drift region 34 in the third direction is, for example, not less than 5 μm and not more than 20 μm.

[0093] The p-type body region 36 is provided in the silicon layer 10. The body region 36 is provided between the drift region 34 and the first surface F1. When the MOSFET 100 is turned on, a channel is formed in a region of the body region 36 along the gate insulating layer 18.

[0094] The body region 36 includes a first region 36a, a second region 36b, and a third region 36c. The first region 36a is provided between the second region 36b and the drift region 34. The third region 36c is provided between the second region 36b and the source region 38.

[0095] The body region 36 contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration of the body region 36 is, for example, 1×10 16 cm -3 Above and 1×10 18 cm -3 the following.

[0096] The p-type impurity concentration of the second region 36 b is higher than the p-type impurity concentration of the first region 36 a. The p-type impurity concentration of the second region 36 b is higher than the p-type impurity concentration of the third region 36 c.

[0097] like Figure 3 As shown, the p-type impurity concentration in the depth direction of the region along the gate insulating layer 18 of the body region 36 is maximum at the position Px. The position Px is located in the second region 36b. The p-type impurity concentration distribution in the depth direction of the region along the gate insulating layer 18 of the body region 36 has the maximum peak in the second region 36b.

[0098] n + The source region 38 of the type is provided in the silicon layer 10. The source region 38 is provided between the body region 36 and the first surface F1.

[0099] The source region 38 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the source region 38 is, for example, 1×10 19 cm -3 Above and 1×10 21 cm -3 the following.

[0100] p + The contact region 40 of the type is provided in the silicon layer 10. The contact region 40 is provided between the body region 36 and the first surface F1.

[0101] The contact region 40 contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration of the contact region 40 is, for example, 1×10 19 cm -3 Above and 1×10 21 cm -3 The p-type impurity concentration of the contact region 40 is higher than the p-type impurity concentration of the body region 36 .

[0102] The trench 30 exists in the silicon layer 10 . The trench 30 is located on the first surface F1 side of the silicon layer 10 . The trench 30 is formed in the silicon layer 10 .

[0103] The trench 30 penetrates the source region 38 and the body region 36 and reaches the drift region 34. The depth of the trench 30 is, for example, not less than 0.5 μm and not more than 5 μm.

[0104] Groove 30 such as Figure 2 As shown, the grooves 30 extend along the first direction on the first surface F1. The grooves 30 are repeatedly arranged at a constant pitch in the second direction.

[0105] The gate electrode 16 is provided in the silicon layer 10. The gate electrode 16 is provided in the trench 30. The gate electrode 16 is sandwiched by the body regions 36 in the second direction. The gate electrode 16 extends in the first direction.

[0106] The gate electrode 16 includes a first portion 16a, a second portion 16b, and a third portion 16c. The second portion 16b is provided between the first portion 16a and the third portion 16c. The first portion 16a is provided on the second surface F2 side relative to the second portion 16b. The third portion 16c is provided on the first surface F1 side relative to the second portion 16b.

[0107] The second portion 16b is in contact with the first portion 16a and the third portion 16c. The first portion 16a, the second portion 16b, and the third portion 16c are electrically connected.

[0108] The first portion 16a faces the first region 36a of the body region 36 in the second direction. The second portion 16b faces the second region 36b of the body region 36 in the second direction. The third portion 16c faces the third region 36c of the body region 36 in the second direction.

[0109] The first portion 16a includes a first material. The second portion 16b includes a second material. The third portion 16c includes a third material.

[0110] The first portion 16a is formed of, for example, a first material. The second portion 16b is formed of, for example, a second material. The third portion 16c is formed of, for example, a third material.

[0111] The work function of the first material is smaller than the work function of the second material. The work function of the third material is smaller than the work function of the second material.

[0112] The work function is the energy difference between the Fermi level and the vacuum level. By determining the first material, the second material, and the third material, the work functions of each can be determined.

[0113] The difference between the work function of the first material and the work function of the second material is, for example, 0.2 eV to 4.0 eV. The difference between the work function of the third material and the work function of the second material is, for example, 0.2 eV to 4.0 eV.

[0114] The first material, the second material, and the third material are n-type polysilicon containing n-type impurities. The n-type impurity concentration of the first material is higher than that of the second material. The n-type impurity concentration of the third material is higher than that of the second material.

[0115] In n-type polysilicon, when the n-type impurity concentration is high, the energy difference between the Fermi level and the lower end of the conduction band is small, and the work function is small.

[0116] The length of the second portion 16b in the third direction ( Figure 3 d1) in the third direction is, for example, the length between the drift region 34 and the source region 38 ( Figure 3 20% or more and 70% or less of d2) in the experiment.

[0117] like Figure 3 As shown, a position Px where the p-type impurity concentration in the depth direction of the body region 36 along the gate insulating layer 18 becomes maximum faces the second portion 16 b in the second direction, for example.

[0118] The gate insulating layer 18 is disposed in the trench 30. The gate insulating layer 18 is disposed between the gate electrode 16 and the silicon layer 10.

[0119] The gate insulating layer 18 is disposed between the gate electrode 16 and the body region 36. The gate insulating layer 18 is disposed between the gate electrode 16 and the drift region 34. The gate insulating layer 18 is disposed between the gate electrode 16 and the source region 38. The gate insulating layer 18 is, for example, silicon oxide.

[0120] The interlayer insulating layer 20 is provided on the silicon layer 10. The interlayer insulating layer 20 is provided between the gate electrode 16 and the source electrode 12. The interlayer insulating layer 20 has a function of electrically isolating the gate electrode 16 from the source electrode 12.

[0121] The interlayer insulating layer 20 is made of, for example, silicon oxide.

[0122] The source electrode 12 is provided on the first surface F1 side of the silicon layer 10 . The source electrode 12 is provided on the first surface F1 of the silicon layer 10 .

[0123] The source electrode 12 is electrically connected to the source region 38 and the contact region 40. The source electrode 12 is in contact with the source region 38 and the contact region 40, for example.

[0124] When MOSFET 100 is mounted, source electrode 12 serves as a region to which a bonding wire is connected, for example.

[0125] The source electrode 12 is a metal electrode and has a stacked structure of, for example, titanium (Ti) and aluminum (Al).

[0126] The drain electrode 14 is provided on the second surface F2 side of the silicon layer 10. The drain electrode 14 is provided on the second surface F2 of the silicon layer 10. The drain electrode 14 is electrically connected to the drain region 32. The drain electrode 14 is in contact with the drain region 32, for example.

[0127] The drain electrode 14 is a metal electrode and has a laminated structure of a material selected from titanium (Ti), aluminum (Al), nickel (Ni), copper (Cu), silver (Ag), and gold (Au), for example.

[0128] The gate electrode pad 22 is provided on the first surface F1 side of the silicon layer 10. The gate electrode pad 22 is provided on the first surface F1 of the silicon layer 10.

[0129] The gate electrode pad 22 is electrically connected to the gate electrode 16. When the MOSFET 100 is mounted, the gate electrode pad 22 serves as a region for connection with a bonding wire, for example.

[0130] The gate electrode pad 22 is a metal electrode. The gate electrode pad 22 has, for example, a stacked structure of titanium (Ti) and aluminum (Al). The material of the gate electrode pad 22 is, for example, the same as that of the source electrode 12 .

[0131] The gate wiring 24 is as follows Figure 1 The gate wiring 24 is provided at the end of the source electrode 12 as shown.

[0132] The gate wiring 24 is a metal wiring. The gate wiring 24 has, for example, a stacked structure of titanium (Ti) and aluminum (Al). The material of the gate wiring 24 is, for example, the same as the material of the source electrode 12 and the material of the gate electrode pad 22 .

[0133] like Figure 4 As shown, the gate wiring 24 is connected to the gate electrode 16 in the region Y. The contact portion 24 a of the gate wiring 24 is connected to the gate electrode 16 in the region Y. The contact portion 24 a penetrates the interlayer insulating layer 20 and is connected to the gate electrode 16 , for example.

[0134] The contact portion 24a is in contact with, for example, the third portion 16c of the gate electrode 16. The contact portion 24a is electrically and physically connected to, for example, the third portion 16c of the gate electrode 16.

[0135] Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described. Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 and Fig.18 This is a cross-sectional view showing an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0136] Figures 5 to 18 yes Figure 1 and Figure 2 A cross section of area X. Figures 5 to 18 is with Figure 3 The corresponding cross section.

[0137] Initially, a silicon layer 10 ( Figure 5 ). The silicon layer 10 includes n + The drain region 32 and n - Type drift region 34.

[0138] The drift region 34 is formed on the drain region 32 by using, for example, an epitaxial growth method.

[0139] Next, a mask material 50 ( Figure 6 The mask material 50 is formed by, for example, using a chemical vapor deposition method (CVD method), a photolithography method, and a reactive ion etching method (RIE method). The mask material 50 is, for example, silicon nitride or silicon oxide.

[0140] Next, the trench 30 is formed using the mask material 50 as a mask. Figure 7 ). The trench 30 is formed by using, for example, the RIE method.

[0141] Next, a gate insulating layer 18 ( Figure 8 ). The gate insulating layer 18 is formed by, for example, thermal oxidation.

[0142] Next, the trench 30 is filled with the first n-type polysilicon 51 ( Fig. 9 ). The first polysilicon 51 is formed by, for example, a CVD method.

[0143] Next, the first polysilicon 51 is etched to form the first portion 16a ( Fig.10 ). The first portion 16a is formed by using, for example, the RIE method.

[0144] Next, the trench 30 is filled with the second n-type polysilicon 52 ( Fig.11The second polysilicon 52 is formed by, for example, a CVD method. The n-type impurity concentration of the second polysilicon 52 is lower than the n-type impurity concentration of the first polysilicon 51.

[0145] Next, the second polysilicon 52 is etched to form the second portion 16b ( Fig.12 ). The second portion 16b is formed by using, for example, the RIE method.

[0146] Next, the trench 30 is filled with the third n-type polysilicon 53 ( Fig.13 The third polysilicon 53 is formed by, for example, a CVD method. The n-type impurity concentration of the third polysilicon 53 is higher than the n-type impurity concentration of the second polysilicon 52.

[0147] Next, the third polysilicon 53 is etched to form the third portion 16c ( Fig.14 ). The third portion 16c is formed by using, for example, the RIE method.

[0148] Next, the mask material 50 is removed ( Fig.15 ). The mask material 50 is removed by, for example, a wet etching method.

[0149] Next, a p-type body region 36 and an n-type body region 36 are formed in the silicon layer 10. + Type source region 38 ( Fig.16 ). The body region 36 and the source region 38 are formed by using an ion implantation method.

[0150] Next, an interlayer insulating layer 20 having an opening is formed on the silicon layer 10 ( Fig.17 ) The interlayer insulating layer 20 is formed by using, for example, a CVD method, a photolithography method, and a RIE method.

[0151] Next, p is formed on the silicon layer 10 + The contact region 40 is formed by, for example, an ion implantation method using the interlayer insulating layer 20 having an opening as a mask material.

[0152] Next, the opening of the interlayer insulating layer 20 is expanded in the lateral direction so that n + The source region 38 of the type is exposed ( Fig.18 ) The opening of the interlayer insulating layer 20 is expanded in the lateral direction by using a wet etching method, for example.

[0153] Thereafter, the source electrode 12 , the gate electrode pad 22 , the gate wiring 24 , and the drain electrode 14 are formed using a known manufacturing method.

[0154] By the above-described manufacturing method, MOSFET 100 according to the first embodiment is manufactured.

[0155] The operation and effects of the semiconductor device according to the first embodiment will be described below.

[0156] In order to reduce the size of transistors or improve performance, vertical transistors are used in which a gate electrode is buried in a trench provided in a semiconductor layer. In vertical transistors, it is required to reduce on-resistance.

[0157] Fig.19 900 is a schematic cross-sectional view of a semiconductor device according to a comparative example. The semiconductor device according to the comparative example is a MOSFET 900 . Fig.19 The first embodiment Figure 3 The corresponding figure.

[0158] The MOSFET 900 is different from the MOSFET 100 of the first embodiment in that the gate electrode 16 does not include the first portion 16 a , the second portion 16 b , and the third portion 16 c .

[0159] The on-resistance of MOSFET 900 includes the channel resistance and the resistance of the drift region 34. For example, in a MOSFET used for low withstand voltage applications, the thickness of the drift region 34 is thin, so the resistance of the drift region 34 is low. Therefore, in a MOSFET used for low withstand voltage applications, the channel resistance accounts for a large proportion of the on-resistance.

[0160] In order to reduce the channel resistance of MOSFET 900, for example, it is conceivable to reduce the threshold voltage of MOSFET 900. By reducing the threshold voltage of MOSFET 900, the electron density of the inversion layer when MOSFET 900 is in the on state increases, and the channel resistance decreases.

[0161] However, if the threshold voltage of the MOSFET 900 is lowered, the MOSFET 900 may unexpectedly be turned on when in the off state, or the leakage current of the MOSFET 900 may increase when in the off state, thus causing problems.

[0162] In the MOSFET 100 of the first embodiment, the gate electrode 16 includes a first portion 16a, a second portion 16b, and a third portion 16c. The work function of the first material included in the first portion 16a is smaller than the work function of the second material included in the second portion 16b. In addition, the work function of the third material included in the third portion 16c is smaller than the work function of the second material included in the second portion 16b.

[0163] Since the work function of the first material is smaller than the work function of the second material, the threshold voltage of the MOSFET composed of the first portion 16a, the gate insulating layer 18 and the first region 36a is lower than the threshold voltage of the MOSFET composed of the second portion 16b, the gate insulating layer 18 and the second region 36b. In other words, the threshold voltage of the MOSFET using the first portion 16a as the gate electrode is lower than the threshold voltage of the MOSFET using the second portion 16b as the gate electrode.

[0164] Similarly, since the work function of the third material is smaller than the work function of the second material, the threshold voltage of the MOSFET composed of the third portion 16c, the gate insulating layer 18 and the third region 36c is lower than the threshold voltage of the MOSFET composed of the second portion 16b, the gate insulating layer 18 and the second region 36b. In other words, the threshold voltage of the MOSFET using the third portion 16c as the gate electrode is lower than the threshold voltage of the MOSFET using the second portion 16b as the gate electrode.

[0165] In the MOSFET 100 of the first embodiment, the threshold voltage of the MOSFET using the first portion 16a as the gate electrode and the threshold voltage of the MOSFET using the third portion 16c as the gate electrode are lowered, so that the channel resistance of the channel formed in the first region 36a and the channel resistance of the channel formed in the third region 36c are lowered. Therefore, the on-resistance of the MOSFET 100 is reduced.

[0166] On the other hand, the threshold voltage of the MOSFET using the second portion 16 b as the gate electrode is kept relatively high, so the threshold voltage of the MOSFET 100 can be kept high.

[0167] For example, Figure 3 As shown, consider the case where the p-type impurity concentration distribution in the depth direction of the region along the gate insulating layer 18 of the body region 36 has a maximum peak in the second region 36b. In this case, the position Px where the p-type impurity concentration becomes maximum is preferably opposite to the second portion 16b in the second direction. By arranging the position Px where the p-type impurity concentration becomes maximum opposite to the second portion 16b, the threshold voltage of the MOSFET using the second portion 16b as the gate electrode can be further increased.

[0168] From the viewpoint of reducing the on-resistance of MOSFET 100 , the difference between the work function of the first material and the work function of the second material is, for example, preferably 0.2 eV or more, more preferably 0.5 eV or more, and even more preferably 1.0 eV or more.

[0169] Similarly, from the viewpoint of reducing the on-resistance of MOSFET 100 , the difference between the work function of the third material and the work function of the second material is, for example, preferably 0.2 eV or more, more preferably 0.5 eV or more, and further preferably 1.0 eV or more.

[0170] The length of the second portion 16b in the third direction ( Figure 3 d1) is preferably the length between the drift region 34 and the source region 38 in the third direction ( Figure 3 The threshold voltage is preferably 20% or more and 70% or less of d2), more preferably 30% or more and 60% or less, and further preferably 40% or more and 50% or less. By exceeding the above lower limit, the reduction of the threshold voltage can be suppressed. In addition, by being lower than the above upper limit, the on-resistance is further reduced.

[0171] As described above, according to MOSFET 100 of the first embodiment, the on-resistance can be reduced.

[0172] (First Modification)

[0173] The semiconductor device according to the first modification of the first embodiment is different from the semiconductor device according to the first embodiment in that the second material is p-type polycrystalline silicon.

[0174] In the MOSFET of the first modification of the first embodiment, the second material included in the second portion 16b of the gate electrode 16 is p-type polysilicon. In addition, the first material included in the first portion 16a of the gate electrode 16 and the third material included in the third portion 16c of the gate electrode 16 are n-type polysilicon.

[0175] By making the second material p-type polysilicon, the work function of the second material is larger than that of the second material n-type polysilicon. Therefore, the difference between the work function of the first material and the work function of the second material and the difference between the work function of the third material and the work function of the second material can be made larger than that of the MOSFET 100 of the first embodiment.

[0176] Therefore, according to the MOSFET of the first modification of the first embodiment, for example, the on-resistance can be further reduced compared with the MOSFET 100 of the first embodiment.

[0177] (Second Modification)

[0178] The semiconductor device according to the second modification of the first embodiment is different from the semiconductor device according to the first embodiment in that the first material, the second material, or the third material is a metal or a metal semiconductor compound.

[0179] In the MOSFET of the second modification of the first embodiment, at least one of the first material included in the first portion 16a of the gate electrode 16, the second material included in the second portion 16b of the gate electrode 16, or the third material included in the third portion 16c of the gate electrode 16 is a metal or a metal semiconductor compound. Alternatively, all of the first material, the second material, and the third material may be metals or metal semiconductor compounds.

[0180] By making at least one of the first material, the second material, or the third material a metal or a metal semiconductor compound, for example, the difference between the work function of the first material and the work function of the second material and the difference between the work function of the third material and the work function of the second material can be made larger than the MOSFET 100 of the first embodiment. In addition, for example, the resistance of the gate electrode 16 can be reduced, and high-speed operation of the MOSFET can be achieved.

[0181] According to the MOSFET of the second modification of the first embodiment, for example, the on-resistance can be further reduced compared with the MOSFET 100 of the first embodiment. In addition, for example, high-speed operation of the MOSFET can be achieved.

[0182] (Third Modification)

[0183] The semiconductor device according to the third modification of the first embodiment is different from the semiconductor device according to the first embodiment in that a field plate electrode is provided.

[0184] Fig. 20 It is a schematic cross-sectional view of a semiconductor device according to a third modified example of the first embodiment. Fig. 20 The first embodiment Figure 3 The corresponding figure.

[0185] MOSFET 101 according to the third modification of the first embodiment includes silicon layer 10 , source electrode 12 , drain electrode 14 , gate electrode 16 , gate insulating layer 18 , interlayer insulating layer 20 , gate electrode pad 22 , gate wiring 24 , field plate electrode 26 , and field plate insulating layer 28 .

[0186] The field plate electrode 26 is provided in the trench 30. The field plate electrode 26 is provided between the gate electrode 16 and the second surface F2 in the third direction. The field plate electrode 26 extends in the first direction.

[0187] The field plate electrode 26 has a function of changing the electric field distribution in the drift region 34 when the MOSFET 101 performs a turn-off operation, thereby increasing the withstand voltage of the MOSFET 101 .

[0188] The field plate electrode 26 is a conductor and is, for example, polysilicon containing n-type impurities or p-type impurities.

[0189] The field plate insulating layer 28 is disposed between the field plate electrode 26 and the silicon layer 10. The field plate insulating layer 28 is disposed between the field plate electrode 26 and the drift region 34. The field plate insulating layer 28 is disposed between the field plate electrode 26 and the gate electrode 16. The field plate insulating layer 28 is, for example, silicon oxide.

[0190] The thickness of the field plate insulating layer 28 is, for example, thicker than the thickness of the gate insulating layer 18 .

[0191] The MOSFET 101 of the third modification of the first embodiment has, for example, improved breakdown voltage by including the field plate electrode 26. In addition, the MOSFET 101 of the third modification of the first embodiment has, for example, reduced impurity concentration in the drift region 34 by including the field plate electrode 26. Therefore, for example, the resistance of the drift region 34 can be reduced, and the on-resistance can be reduced.

[0192] According to the MOSFET 101 of the third modification of the first embodiment, for example, the withstand voltage can be further increased than that of the MOSFET 100 of the first embodiment. Also, for example, the on-resistance can be further reduced than that of the MOSFET 100 of the first embodiment.

[0193] As described above, according to the first embodiment and the modified example, a semiconductor device capable of reducing on-resistance can be realized.

[0194] (Second embodiment)

[0195] The semiconductor device of the second embodiment is different from the semiconductor device of the first embodiment in that the first conductivity type is p-type and the second conductivity type is n-type, and the work function of the first material and the work function of the third material are larger than the work function of the second material. Hereinafter, a part of the description of the contents repeated in the first embodiment may be omitted.

[0196] The following describes a case where the first conductivity type is p-type and the second conductivity type is n-type. That is, a case where a p-channel MOSFET uses holes as carriers is described.

[0197] Fig.21 It is a schematic cross-sectional view of a semiconductor device according to a second embodiment. Fig.21 The first embodiment Figure 3 The corresponding figure. Fig.21 Indicates the impurity concentration distribution of a part of the semiconductor layer.

[0198] MOSFET 200 includes a silicon layer 10 , a source electrode 12 , a drain electrode 14 , a gate electrode 16 , a gate insulating layer 18 , an interlayer insulating layer 20 , a gate electrode pad 22 , and a gate wiring 24 .

[0199] The silicon layer 10 is an example of a semiconductor layer. The source electrode 12 is an example of a first electrode. The drain electrode 14 is an example of a second electrode.

[0200] The gate electrode 16 includes a first portion 16a, a second portion 16b, and a third portion 16c. The gate wiring 24 includes a contact portion 24a.

[0201] The silicon layer 10 includes a trench 30, a p + The drain region 32 of the p - type drift region 34, n-type main region 36, p + Type source region 38, n + Type of contact area 40.

[0202] The drift region 34 is an example of a first semiconductor region. The body region 36 is an example of a second semiconductor region. The source region 38 is an example of a third semiconductor region.

[0203] The main body region 36 includes a first region 36a, a second region 36b, and a third region 36c.

[0204] p + The drain region 32 of the type contains a p-type impurity. The p-type impurity is, for example, boron (B). The concentration of the p-type impurity in the drain region 32 is, for example, 1×10 18 cm -3 Above and 1×10 21 cm -3 the following.

[0205] p - The drift region 34 of the type contains p-type impurities. The p-type impurities are, for example, boron (B). The p-type impurity concentration of the drift region 34 is, for example, 1×10 15 cm -3 Above and 1×10 18 cm -3 the following.

[0206] The n-type body region 36 includes a first region 36 a , a second region 36 b , and a third region 36 c .

[0207] The body region 36 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the body region 36 is, for example, 1×10 16 cm -3 Above and 1×10 18 cm -3 the following.

[0208] The n-type impurity concentration of the second region 36 b is higher than the n-type impurity concentration of the first region 36 a. The n-type impurity concentration of the second region 36 b is higher than the n-type impurity concentration of the third region 36 c.

[0209] like Fig.21 As shown, the n-type impurity concentration in the depth direction of the region along the gate insulating layer 18 of the body region 36 is maximum at the position Py. The position Py is located in the second region 36b. The n-type impurity concentration distribution in the depth direction of the region along the gate insulating layer 18 of the body region 36 has the maximum peak in the second region 36b.

[0210] p + The source region 38 of the type contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration of the source region 38 is, for example, 1×10 19 cm -3 Above and 1×10 21 cm -3 the following.

[0211] n + The contact region 40 of the type contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the contact region 40 is, for example, 1×10 19 cm -3 Above and 1×10 21 cm -3 The n-type impurity concentration of the contact region 40 is higher than the n-type impurity concentration of the body region 36 .

[0212] The gate electrode 16 includes a first portion 16a, a second portion 16b, and a third portion 16c. The first portion 16a includes a first material. The second portion 16b includes a second material. The third portion 16c includes a third material.

[0213] The work function of the first material is larger than the work function of the second material. The work function of the third material is larger than the work function of the second material.

[0214] The difference between the work function of the first material and the work function of the second material is, for example, 0.2 eV to 4.0 eV. The difference between the work function of the third material and the work function of the second material is, for example, 0.2 eV to 4.0 eV.

[0215] The first material, the second material, and the third material are p-type polysilicon containing p-type impurities. The p-type impurity concentration of the first material is higher than that of the second material. The p-type impurity concentration of the third material is higher than that of the second material.

[0216] In p-type polysilicon, when the p-type impurity concentration is high, the energy difference between the Fermi level and the upper end of the valence band is small, and the work function is large.

[0217] The length of the second portion 16b in the third direction ( Fig.21d1) in the third direction is, for example, the length between the drift region 34 and the source region 38 ( Fig.21 20% or more and 70% or less of d2) in the experiment.

[0218] like Fig.21 As shown, a position Py where the n-type impurity concentration in the depth direction of the body region 36 along the gate insulating layer 18 becomes maximum is opposed to the second portion 16 b in the second direction, for example.

[0219] In the MOSFET 200 of the second embodiment, the gate electrode 16 includes a first portion 16a, a second portion 16b, and a third portion 16c. The work function of the first material included in the first portion 16a is larger than the work function of the second material included in the second portion 16b. In addition, the work function of the third material included in the third portion 16c is larger than the work function of the second material included in the second portion 16b.

[0220] Since the work function of the first material is larger than the work function of the second material, the threshold voltage of the MOSFET composed of the first portion 16a, the gate insulating layer 18 and the first region 36a is lower than the threshold voltage of the MOSFET composed of the second portion 16b, the gate insulating layer 18 and the second region 36b. In other words, the threshold voltage of the MOSFET using the first portion 16a as the gate electrode is lower than the threshold voltage of the MOSFET using the second portion 16b as the gate electrode.

[0221] Similarly, since the work function of the third material is larger than the work function of the second material, the threshold voltage of the MOSFET composed of the third portion 16c, the gate insulating layer 18 and the third region 36c is lower than the threshold voltage of the MOSFET composed of the second portion 16b, the gate insulating layer 18 and the second region 36b. In other words, the threshold voltage of the MOSFET using the third portion 16c as the gate electrode is lower than the threshold voltage of the MOSFET using the second portion 16b as the gate electrode.

[0222] In the MOSFET 200 of the second embodiment, the threshold voltage of the MOSFET using the first portion 16a as the gate electrode and the threshold voltage of the MOSFET using the third portion 16c as the gate electrode are lowered, so that the channel resistance of the channel formed in the first region 36a and the channel resistance of the channel formed in the third region 36c are lowered. Therefore, the on-resistance of the MOSFET 200 is reduced.

[0223] On the other hand, the threshold voltage of the MOSFET using the second portion 16 b as the gate electrode is kept relatively high, so the threshold voltage of the MOSFET 200 can be kept high.

[0224] For example, Fig.21As shown, consider the case where the n-type impurity concentration distribution in the depth direction of the region along the gate insulating layer 18 of the body region 36 has a maximum peak in the second region 36b. In this case, the position Py where the n-type impurity concentration becomes maximum is preferably opposite to the second portion 16b in the second direction. By arranging the position Py where the n-type impurity concentration becomes maximum opposite to the second portion 16b, the threshold voltage of the MOSFET using the second portion 16b as the gate electrode can be further increased.

[0225] From the viewpoint of reducing the on-resistance of MOSFET 200 , the difference between the work function of the first material and the work function of the second material is, for example, preferably 0.2 eV or more, more preferably 0.5 eV or more, and further preferably 1.0 eV or more.

[0226] Similarly, from the viewpoint of reducing the on-resistance of MOSFET 200 , the difference between the work function of the third material and the work function of the second material is, for example, preferably 0.2 eV or more, more preferably 0.5 eV or more, and further preferably 1.0 eV or more.

[0227] The length of the second portion 16b in the third direction ( Fig.21 d1) is preferably the length between the drift region 34 and the source region 38 in the third direction ( Fig.21 The threshold voltage is preferably 20% or more and 70% or less of d2), more preferably 30% or more and 60% or less, and further preferably 40% or more and 50% or less. By exceeding the above lower limit, the reduction of the threshold voltage can be suppressed. In addition, by being lower than the above upper limit, the on-resistance is further reduced.

[0228] As described above, according to MOSFET 200 of the second embodiment, the on-resistance can be reduced.

[0229] (First Modification)

[0230] The semiconductor device according to the first modification of the second embodiment is different from the semiconductor device according to the second embodiment in that the second material is n-type polycrystalline silicon.

[0231] In the MOSFET of the second modification of the second embodiment, the second material included in the second portion 16b of the gate electrode 16 is n-type polysilicon. In addition, the first material included in the first portion 16a of the gate electrode 16 and the third material included in the third portion 16c of the gate electrode 16 are p-type polysilicon.

[0232] By making the second material n-type polysilicon, the work function of the second material is smaller than that of p-type polysilicon. Therefore, the difference between the work function of the first material and the work function of the second material and the difference between the work function of the third material and the work function of the second material can be made larger than that of the MOSFET 200 of the second embodiment.

[0233] According to the MOSFET of the first modified example of the second embodiment, the on-resistance can be further reduced compared with, for example, the MOSFET 200 of the second embodiment.

[0234] (Second Modification)

[0235] The semiconductor device according to the second modification of the second embodiment is different from the semiconductor device according to the second embodiment in that the first material, the second material, or the third material is a metal or a metal semiconductor compound.

[0236] In the MOSFET of the second modification of the second embodiment, at least one of the first material included in the first portion 16a of the gate electrode 16, the second material included in the second portion 16b of the gate electrode 16, or the third material included in the third portion 16c of the gate electrode 16 is a metal or a metal semiconductor compound. Alternatively, all of the first material, the second material, and the third material may be metals or metal semiconductor compounds.

[0237] By making at least one of the first material, the second material, or the third material a metal or a metal semiconductor compound, for example, the difference between the work function of the first material and the work function of the second material and the difference between the work function of the third material and the work function of the second material can be made larger than that of the MOSFET 200 of the second embodiment. In addition, for example, the resistance of the gate electrode 16 can be reduced, and high-speed operation of the MOSFET can be achieved.

[0238] According to the MOSFET of the second modification of the second embodiment, for example, the on-resistance can be further reduced compared with the MOSFET 200 of the second embodiment. In addition, for example, high-speed operation of the MOSFET can be achieved.

[0239] (Third Modification)

[0240] The semiconductor device according to the third modification of the second embodiment is different from the semiconductor device according to the second embodiment in that a field plate electrode is provided.

[0241] Fig. 22 It is a schematic cross-sectional view of a semiconductor device according to a third modified example of the second embodiment. Fig. 22 The second embodiment Fig.21 The corresponding figure.

[0242] MOSFET 201 of the third modification of the second embodiment includes silicon layer 10 , source electrode 12 , drain electrode 14 , gate electrode 16 , gate insulating layer 18 , interlayer insulating layer 20 , gate electrode pad 22 , gate wiring 24 , field plate electrode 26 , and field plate insulating layer 28 .

[0243] The field plate electrode 26 is provided in the trench 30. The field plate electrode 26 is provided between the gate electrode 16 and the second surface F2 in the third direction. The field plate electrode 26 extends in the first direction.

[0244] The field plate electrode 26 has a function of changing the electric field distribution in the drift region 34 when the MOSFET 201 performs an off operation, thereby increasing the withstand voltage of the MOSFET 201 .

[0245] The field plate electrode 26 is a conductor and is, for example, polysilicon containing n-type impurities or p-type impurities.

[0246] The field plate insulating layer 28 is disposed between the field plate electrode 26 and the silicon layer 10. The field plate insulating layer 28 is disposed between the field plate electrode 26 and the drift region 34. The field plate insulating layer 28 is disposed between the field plate electrode 26 and the gate electrode 16. The field plate insulating layer 28 is, for example, silicon oxide.

[0247] The thickness of the field plate insulating layer 28 is, for example, thicker than the thickness of the gate insulating layer 18 .

[0248] The MOSFET 201 of the third modification of the second embodiment has, for example, improved withstand voltage by including the field plate electrode 26. In addition, the MOSFET 201 of the third modification of the second embodiment has, for example, reduced impurity concentration in the drift region 34 by including the field plate electrode 26. Therefore, for example, the resistance of the drift region 34 can be reduced, and the on-resistance can be reduced.

[0249] According to the MOSFET 201 of the third modification of the second embodiment, for example, the withstand voltage can be further increased than that of the MOSFET 200 of the second embodiment. Also, for example, the on-resistance can be further reduced than that of the MOSFET 200 of the second embodiment.

[0250] As described above, according to the second embodiment and the modified example, a semiconductor device capable of reducing on-resistance can be realized.

[0251] (Third embodiment)

[0252] The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that a first insulating film is provided between the first portion and the second portion, and a second insulating film is provided between the second portion and the third portion. Hereinafter, description of contents overlapping with the first embodiment may be partially omitted.

[0253] Fig.23 and Fig.24 It is a schematic cross-sectional view of a semiconductor device according to a third embodiment. Fig.23 The first embodiment Figure 3 and Figure 4 The corresponding figure. Fig.23 Indicates the impurity concentration distribution of a part of the semiconductor layer.

[0254] The MOSFET 300 of the third embodiment includes a silicon layer 10 , a source electrode 12 , a drain electrode 14 , a gate electrode 16 , a gate insulating layer 18 , an interlayer insulating layer 20 , a gate electrode pad 22 , a gate wiring 24 , a first insulating film 61 , and a second insulating film 62 .

[0255] The first material, the second material, and the third material are, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0256] The first insulating film 61 is provided between the first portion 16a and the second portion 16b. The first insulating film 61 includes, for example, oxide, nitride, or oxynitride. The first insulating film 61 includes, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0257] The thickness of the first insulating film 61 is, for example, thinner than the thickness of the gate insulating layer 18 .

[0258] The first insulating film 61 has a function of, for example, suppressing diffusion of impurities between the first portion 16a and the second portion 16b. The first insulating film 61 suppresses, for example, diffusion of impurities between the first portion 16a and the second portion 16b, thereby suppressing the work functions of the first material and the second material from varying from desired values.

[0259] The second insulating film 62 is provided between the third portion 16c and the second portion 16b. The second insulating film 62 includes, for example, oxide, nitride, or oxynitride. The second insulating film 62 includes, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0260] The thickness of the second insulating film 62 is, for example, thinner than the thickness of the gate insulating layer 18 .

[0261] The second insulating film 62 has a function of suppressing diffusion of impurities between the third portion 16c and the second portion 16b, for example. The second insulating film 62 suppresses diffusion of impurities between the third portion 16c and the second portion 16b, for example, so that the work functions of the third material and the second material vary from desired values.

[0262] like Fig.24 As shown, the gate wiring 24 is connected to the gate electrode 16 in the region Y. The contact portion 24 a of the gate wiring 24 is connected to the gate electrode 16 in the region Y.

[0263] The contact portion 24 a penetrates the interlayer insulating layer 20 , the third portion 16 c , the second insulating film 62 , the second portion 16 b , and the first insulating film 61 , and reaches the first portion 16 a .

[0264] The contact portion 24a is in contact with, for example, the third portion 16c, the second portion 16b, and the first portion 16a of the gate electrode 16. The contact portion 24a is electrically and physically connected to, for example, the third portion 16c, the second portion 16b, and the first portion 16a of the gate electrode 16. The first portion 16a, the second portion 16b, and the third portion 16c are electrically connected via the contact portion 24a.

[0265] As described above, according to the third embodiment, similarly to the first embodiment, a semiconductor device capable of reducing on-resistance can be realized.

[0266] (Fourth embodiment)

[0267] The semiconductor device of the fourth embodiment is different from the semiconductor device of the second embodiment in that a first insulating film is provided between the first portion and the second portion, and a second insulating film is provided between the second portion and the third portion. In addition, the semiconductor device of the fourth embodiment is different from the semiconductor device of the third embodiment in that the first conductivity type is p-type and the second conductivity type is n-type, and the work function of the first material and the work function of the third material are larger than the work function of the second material. Hereinafter, a part of the description of the contents repeated in the second embodiment or the third embodiment may be omitted.

[0268] Fig.25 It is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. Fig.25 The second embodiment Fig.21 The corresponding figure. Fig.25 Indicates the impurity concentration distribution of a part of the semiconductor layer.

[0269] The MOSFET 400 of the fourth embodiment includes a silicon layer 10 , a source electrode 12 , a drain electrode 14 , a gate electrode 16 , a gate insulating layer 18 , an interlayer insulating layer 20 , a gate electrode pad 22 , a gate wiring 24 , a first insulating film 61 , and a second insulating film 62 .

[0270] The first material, the second material, and the third material are, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0271] The first insulating film 61 is provided between the first portion 16a and the second portion 16b. The first insulating film 61 includes, for example, oxide, nitride, or oxynitride. The first insulating film 61 includes, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0272] The thickness of the first insulating film 61 is, for example, thinner than the thickness of the gate insulating layer 18 .

[0273] The first insulating film 61 has a function of, for example, suppressing diffusion of impurities between the first portion 16a and the second portion 16b. The first insulating film 61 suppresses, for example, diffusion of impurities between the first portion 16a and the second portion 16b, thereby suppressing the work functions of the first material and the second material from varying from desired values.

[0274] The second insulating film 62 is provided between the third portion 16c and the second portion 16b. The second insulating film 62 includes, for example, oxide, nitride, or oxynitride. The second insulating film 62 includes, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0275] The thickness of the second insulating film 62 is, for example, thinner than the thickness of the gate insulating layer 18 .

[0276] The second insulating film 62 has a function of suppressing diffusion of impurities between the third portion 16c and the second portion 16b, for example. The second insulating film 62 suppresses diffusion of impurities between the third portion 16c and the second portion 16b, for example, so that the work functions of the third material and the second material vary from desired values.

[0277] The first portion 16 a , the second portion 16 b , and the third portion 16 c are electrically connected to each other via a contact portion (not shown).

[0278] As described above, according to the fourth embodiment, similarly to the second embodiment, a semiconductor device capable of reducing on-resistance can be realized.

[0279] (Fifth embodiment)

[0280] The semiconductor device of the fifth embodiment comprises: a semiconductor layer having a first surface and a second surface opposite to the first surface, and including an n-type first semiconductor region, a p-type second semiconductor region arranged between the first semiconductor region and the first surface, and an n-type third semiconductor region arranged between the second semiconductor region and the first surface; a first electrode arranged on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region; a second electrode arranged on the second surface side of the semiconductor layer; a gate electrode arranged in the semiconductor layer and opposite to the first semiconductor region, the second semiconductor region and the third semiconductor region; and a gate insulating layer arranged between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region. The second semiconductor region includes a first region and a second region, the first region is arranged between the second region and the first semiconductor region or between the second region and the third semiconductor region, the gate electrode includes a first part and a second part, the first part is opposite to the first region, and the second part is opposite to the second region, the first part contains a first material, and the second part contains a second material, the first material is n-type polycrystalline silicon, and the work function of the first material is smaller than the work function of the second material.

[0281] The semiconductor device of the fifth embodiment is different from the semiconductor device of the first embodiment in that the gate electrode does not include the third portion. Hereinafter, a part of the description of the contents overlapped with the first embodiment may be omitted.

[0282] Fig.26 It is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment. Fig.26 The first embodiment Figure 3 The corresponding figure. Fig.26 Indicates the impurity concentration distribution of a part of the semiconductor layer.

[0283] The MOSFET 500 according to the fifth embodiment includes a silicon layer 10 , a source electrode 12 , a drain electrode 14 , a gate electrode 16 , a gate insulating layer 18 , an interlayer insulating layer 20 , a gate electrode pad 22 , and a gate wiring 24 .

[0284] The gate electrode 16 includes a first portion 16 a and a second portion 16 b .

[0285] The silicon layer 10 includes a trench 30, n + The drain region 32, n - type drift region 34, p-type body region 36, n + Type source region 38, p + Type of contact area 40.

[0286] The p-type body region 36 is provided in the silicon layer 10. The body region 36 is provided between the drift region 34 and the first surface F1. When the MOSFET 500 is turned on, a channel is formed in a region of the body region 36 along the gate insulating layer 18.

[0287] The body region 36 includes a first region 36 a and a second region 36 b. The first region 36 a is provided between the second region 36 b and the drift region 34 .

[0288] The body region 36 contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration of the body region 36 is, for example, 1×10 16 cm -3 Above and 1×10 18 cm -3 the following.

[0289] The p-type impurity concentration of the second region 36 b is higher than the p-type impurity concentration of the first region 36 a .

[0290] like Fig.26 As shown, the p-type impurity concentration in the depth direction of the region along the gate insulating layer 18 of the body region 36 is maximum at the position Px. The position Px is located in the second region 36b. The p-type impurity concentration distribution in the depth direction of the region along the gate insulating layer 18 of the body region 36 has the maximum peak in the second region 36b.

[0291] The gate electrode 16 includes a first portion 16a and a second portion 16b. The first portion 16a is provided on the second surface F2 side with respect to the second portion 16b.

[0292] The second portion 16b is in contact with the first portion 16a. The first portion 16a and the second portion 16b are electrically connected.

[0293] The first portion 16a faces the first region 36a of the main body region 36 in the second direction. The second portion 16b faces the second region 36b of the main body region 36 in the second direction.

[0294] The first portion 16a includes a first material. The second portion 16b includes a second material. The first portion 16a is formed of, for example, the first material. The second portion 16b is formed of, for example, the second material.

[0295] The work function of the first material is smaller than the work function of the second material. The difference between the work function of the first material and the work function of the second material is, for example, 0.2 eV to 4.0 eV.

[0296] The first material and the second material are n-type polysilicon containing n-type impurities. The n-type impurity concentration of the first material is higher than the n-type impurity concentration of the second material.

[0297] like Fig.26 As shown, a position Px where the p-type impurity concentration in the depth direction of the body region 36 along the gate insulating layer 18 becomes maximum faces the second portion 16 b in the second direction, for example.

[0298] In the MOSFET 500 of the fifth embodiment, the gate electrode 16 includes a first portion 16a and a second portion 16b. The work function of the first material included in the first portion 16a is smaller than the work function of the second material included in the second portion 16b.

[0299] Since the work function of the first material is smaller than the work function of the second material, the threshold voltage of the MOSFET composed of the first portion 16a, the gate insulating layer 18 and the first region 36a is lower than the threshold voltage of the MOSFET composed of the second portion 16b, the gate insulating layer 18 and the second region 36b. In other words, the threshold voltage of the MOSFET using the first portion 16a as the gate electrode is lower than the threshold voltage of the MOSFET using the second portion 16b as the gate electrode.

[0300] In the MOSFET 500 of the fifth embodiment, since the threshold voltage of the MOSFET using the first portion 16 a as the gate electrode is lowered, the channel resistance of the channel formed in the first region 36 a is lowered. Therefore, the on-resistance of the MOSFET 500 is reduced.

[0301] On the other hand, the threshold voltage of the MOSFET using the second portion 16 b as the gate electrode is kept relatively high, so the threshold voltage of the MOSFET 500 can be kept high.

[0302] For example, Fig.26 As shown, by having the position Px where the p-type impurity concentration is maximum facing the second portion 16b, the threshold voltage of the MOSFET using the second portion 16b as the gate electrode can be further increased.

[0303] From the viewpoint of reducing the on-resistance of MOSFET 500 , the difference between the work function of the first material and the work function of the second material is, for example, preferably 0.2 eV or more, more preferably 0.5 eV or more, and even more preferably 1.0 eV or more.

[0304] As described above, according to the MOSFET 500 of the fifth embodiment, the on-resistance can be reduced.

[0305] (First Modification)

[0306] The semiconductor device according to the first modification of the fifth embodiment is different from the semiconductor device according to the fifth embodiment in that the second material is p-type polycrystalline silicon.

[0307] In the MOSFET of the first modified example of the fifth embodiment, the second material included in the second portion 16b of the gate electrode 16 is p-type polysilicon. Also, the first material included in the first portion 16a of the gate electrode 16 is n-type polysilicon.

[0308] By using p-type polysilicon as the second material, the work function of the second material is larger than when the second material is n-type polysilicon. Therefore, the difference between the work function of the first material and the work function of the second material can be made larger than that of the MOSFET 500 of the fifth embodiment.

[0309] According to the MOSFET of the first modification of the fifth embodiment, for example, the on-resistance can be further reduced compared with the MOSFET 500 of the fifth embodiment.

[0310] (Second Modification)

[0311] The semiconductor device according to the second modification of the fifth embodiment is different from the semiconductor device according to the fifth embodiment in that the first region of the second semiconductor region is provided between the second region and the third semiconductor region.

[0312] Fig. 27 It is a schematic cross-sectional view of a semiconductor device according to a second modified example of the fifth embodiment. Fig. 27 The fifth embodiment Fig.26 The corresponding figure. Fig. 27 Graph 1 shows the impurity concentration distribution of a part of the semiconductor layer. The semiconductor device according to the second modification of the fifth embodiment is a MOSFET 501 .

[0313] The p-type body region 36 includes a first region 36 a and a second region 36 b . The first region 36 a is provided between the second region 36 b and the source region 38 .

[0314] The body region 36 contains a p-type impurity. The p-type impurity is, for example, boron (B). The p-type impurity concentration of the body region 36 is, for example, 1×10 16 cm -3 Above and 1×10 18 cm -3 the following.

[0315] The p-type impurity concentration of the second region 36 b is higher than the p-type impurity concentration of the first region 36 a .

[0316] like Fig. 27 As shown, the p-type impurity concentration in the depth direction of the region along the gate insulating layer 18 of the body region 36 is maximum at the position Px. The position Px is located in the second region 36b. The p-type impurity concentration distribution in the depth direction of the region along the gate insulating layer 18 of the body region 36 has the maximum peak in the second region 36b.

[0317] The gate electrode 16 includes a first portion 16a and a second portion 16b. The first portion 16a is provided on the first surface F1 side with respect to the second portion 16b.

[0318] The second portion 16b is in contact with the first portion 16a. The first portion 16a and the second portion 16b are electrically connected.

[0319] The first portion 16a faces the first region 36a of the main body region 36 in the second direction. The second portion 16b faces the second region 36b of the main body region 36 in the second direction.

[0320] The first portion 16a includes a first material. The second portion 16b includes a second material. The first portion 16a is formed of, for example, the first material. The second portion 16b is formed of, for example, the second material.

[0321] The work function of the first material is smaller than the work function of the second material. The difference between the work function of the first material and the work function of the second material is, for example, 0.2 eV to 4.0 eV.

[0322] The first material and the second material are n-type polysilicon containing n-type impurities. The n-type impurity concentration of the first material is higher than the n-type impurity concentration of the second material.

[0323] like Fig. 27 As shown, a position Px where the p-type impurity concentration in the depth direction of the body region 36 along the gate insulating layer 18 becomes maximum faces the second portion 16 b in the second direction, for example.

[0324] In the MOSFET 501 of the second modification of the fifth embodiment, the gate electrode 16 includes a first portion 16a and a second portion 16b. The work function of the first material included in the first portion 16a is smaller than the work function of the second material included in the second portion 16b.

[0325] Since the work function of the first material is smaller than the work function of the second material, the threshold voltage of the MOSFET composed of the first portion 16a, the gate insulating layer 18 and the first region 36a is lower than the threshold voltage of the MOSFET composed of the second portion 16b, the gate insulating layer 18 and the second region 36b. In other words, the threshold voltage of the MOSFET using the first portion 16a as the gate electrode is lower than the threshold voltage of the MOSFET using the second portion 16b as the gate electrode.

[0326] In the MOSFET 501 of the second modification of the fifth embodiment, the threshold voltage of the MOSFET using the first portion 16a as the gate electrode is lowered, and the channel resistance of the channel formed in the first region 36a is lowered. Therefore, the on-resistance of the MOSFET 501 is reduced.

[0327] On the other hand, the threshold voltage of the MOSFET using the second portion 16 b as the gate electrode is kept relatively high, so the threshold voltage of the MOSFET 501 can be kept high.

[0328] For example, Fig. 27 As shown, by making the position Px where the p-type impurity concentration becomes maximum face the second portion 16b, the threshold voltage of the MOSFET using the second portion 16b as the gate electrode can be further increased.

[0329] From the viewpoint of reducing the on-resistance of the MOSFET 501 , the difference between the work function of the first material and the work function of the second material is, for example, preferably 0.2 eV or more, more preferably 0.5 eV or more, and further preferably 1.0 eV or more.

[0330] According to the MOSFET 501 of the second modification of the fifth embodiment, the on-resistance can be reduced similarly to the MOSFET 500 of the fifth embodiment.

[0331] As described above, according to the fifth embodiment and the modified example, a semiconductor device capable of reducing on-resistance can be realized.

[0332] (Sixth embodiment)

[0333] The semiconductor device of the sixth embodiment comprises: a semiconductor layer having a first surface and a second surface opposite to the first surface, and including a p-type first semiconductor region, an n-type second semiconductor region arranged between the first semiconductor region and the first surface, and a p-type third semiconductor region arranged between the second semiconductor region and the first surface; a first electrode arranged on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region; a second electrode arranged on the second surface side of the semiconductor layer; a gate electrode arranged in the semiconductor layer and electrically connected to the first semiconductor region, the second semiconductor region, and the third semiconductor region. Opposite; and a gate insulating layer, arranged between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region, the second semiconductor region includes the first region and the second region, the first region is arranged between the second region and the first semiconductor region or between the second region and the third semiconductor region, the gate electrode includes a first part and a second part, the first part is opposite to the first region, the second part is opposite to the second region, the first part contains a first material, the second part contains a second material, and the work function of the first material is greater than the work function of the second material.

[0334] The semiconductor device of the sixth embodiment is different from the semiconductor device of the second embodiment in that the gate electrode does not include the third portion. Hereinafter, a part of the description of the contents overlapped with the second embodiment may be omitted.

[0335] Fig.28 It is a schematic cross-sectional view of a semiconductor device according to a sixth embodiment. Fig.28 The second embodiment Fig.21 The corresponding figure. Fig.28 Indicates the impurity concentration distribution of a part of the semiconductor layer.

[0336] The MOSFET 600 according to the sixth embodiment includes a silicon layer 10 , a source electrode 12 , a drain electrode 14 , a gate electrode 16 , a gate insulating layer 18 , an interlayer insulating layer 20 , a gate electrode pad 22 , and a gate wiring 24 .

[0337] The gate electrode 16 includes a first portion 16 a and a second portion 16 b .

[0338] The silicon layer 10 includes a trench 30, a p + The drain region 32 of the p - type drift region 34, n-type main region 36, p + Type source region 38, n + Type of contact area 40.

[0339] The n-type body region 36 is provided in the silicon layer 10. The body region 36 is provided between the drift region 34 and the first surface F1. When the MOSFET 600 is turned on, a channel is formed in a region of the body region 36 along the gate insulating layer 18.

[0340] The body region 36 includes a first region 36 a and a second region 36 b. The first region 36 a is provided between the second region 36 b and the drift region 34 .

[0341] The body region 36 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the body region 36 is, for example, 1×10 16 cm -3 Above and 1×10 18 cm -3 the following.

[0342] The n-type impurity concentration of the second region 36 b is higher than the n-type impurity concentration of the first region 36 a .

[0343] like Fig.28 As shown, the n-type impurity concentration in the depth direction of the region along the gate insulating layer 18 of the body region 36 is maximum at the position Py. The position Py is located in the second region 36b. The n-type impurity concentration distribution in the depth direction of the region along the gate insulating layer 18 of the body region 36 has the maximum peak in the second region 36b.

[0344] The gate electrode 16 includes a first portion 16a and a second portion 16b. The first portion 16a is provided on the second surface F2 side with respect to the second portion 16b.

[0345] The second portion 16b is in contact with the first portion 16a. The first portion 16a and the second portion 16b are electrically connected.

[0346] The first portion 16a faces the first region 36a of the main body region 36 in the second direction. The second portion 16b faces the second region 36b of the main body region 36 in the second direction.

[0347] The first portion 16a includes a first material. The second portion 16b includes a second material. The first portion 16a is formed of, for example, the first material. The second portion 16b is formed of, for example, the second material.

[0348] The work function of the first material is larger than the work function of the second material. The difference between the work function of the first material and the work function of the second material is, for example, 0.2 eV to 4.0 eV.

[0349] The first material and the second material are p-type polysilicon containing p-type impurities. The p-type impurity concentration of the first material is higher than the p-type impurity concentration of the second material.

[0350] like Fig.28 As shown, a position Py where the n-type impurity concentration in the depth direction of the body region 36 along the gate insulating layer 18 becomes maximum is opposed to the second portion 16 b in the second direction, for example.

[0351] In the MOSFET 600 of the sixth embodiment, the gate electrode 16 includes a first portion 16a and a second portion 16b. The work function of the first material included in the first portion 16a is larger than the work function of the second material included in the second portion 16b.

[0352] Since the work function of the first material is larger than the work function of the second material, the threshold voltage of the MOSFET composed of the first portion 16a, the gate insulating layer 18 and the first region 36a is lower than the threshold voltage of the MOSFET composed of the second portion 16b, the gate insulating layer 18 and the second region 36b. In other words, the threshold voltage of the MOSFET using the first portion 16a as the gate electrode is lower than the threshold voltage of the MOSFET using the second portion 16b as the gate electrode.

[0353] In the MOSFET 600 of the sixth embodiment, since the threshold voltage of the MOSFET using the first portion 16 a as the gate electrode is lowered, the channel resistance of the channel formed in the first region 36 a is lowered. Therefore, the on-resistance of the MOSFET 600 is reduced.

[0354] On the other hand, the threshold voltage of the MOSFET using the second portion 16 b as the gate electrode is kept relatively high, so the threshold voltage of the MOSFET 600 can be kept high.

[0355] For example, Fig.28 As shown, by making the position Py where the n-type impurity concentration becomes maximum face the second portion 16b, the threshold voltage of the MOSFET using the second portion 16b as the gate electrode can be further increased.

[0356] From the viewpoint of reducing the on-resistance of MOSFET 600 , the difference between the work function of the first material and the work function of the second material is, for example, preferably 0.2 eV or more, more preferably 0.5 eV or more, and further preferably 1.0 eV or more.

[0357] As described above, according to the MOSFET 600 of the sixth embodiment, the on-resistance can be reduced.

[0358] (First Modification)

[0359] The semiconductor device according to the first modification of the sixth embodiment is different from the semiconductor device according to the sixth embodiment in that the second material is n-type polycrystalline silicon.

[0360] In the MOSFET of the first modified example of the sixth embodiment, the second material included in the second portion 16b of the gate electrode 16 is n-type polysilicon. Also, the first material included in the first portion 16a of the gate electrode 16 is p-type polysilicon.

[0361] By using n-type polysilicon as the second material, the work function of the second material is smaller than when the second material is p-type polysilicon. Therefore, the difference between the work function of the first material and the work function of the second material can be made larger than that of the MOSFET 600 of the sixth embodiment.

[0362] According to the MOSFET of the first modified example of the sixth embodiment, for example, the on-resistance can be further reduced compared with the MOSFET 600 of the sixth embodiment.

[0363] (Second Modification)

[0364] The semiconductor device according to the second modification of the sixth embodiment is different from the semiconductor device according to the sixth embodiment in that the first region of the second semiconductor region is provided between the second region and the third semiconductor region.

[0365] Fig.29 It is a schematic cross-sectional view of a semiconductor device according to a second modified example of the sixth embodiment. Fig.29 The sixth embodiment Fig.28 The corresponding figure. Fig.29: shows the impurity concentration distribution of a part of the semiconductor layer. The semiconductor device according to the second modification of the sixth embodiment is a MOSFET 601 .

[0366] The n-type body region 36 includes a first region 36 a and a second region 36 b . The first region 36 a is provided between the second region 36 b and the source region 38 .

[0367] The body region 36 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the body region 36 is, for example, 1×10 16 cm -3 Above and 1×10 18 cm -3 the following.

[0368] The n-type impurity concentration of the second region 36 b is higher than the n-type impurity concentration of the first region 36 a .

[0369] like Fig.29 As shown, the n-type impurity concentration in the depth direction of the region along the gate insulating layer 18 of the body region 36 is maximum at the position Py. The position Py is located in the second region 36b. The n-type impurity concentration distribution in the depth direction of the region along the gate insulating layer 18 of the body region 36 has the maximum peak in the second region 36b.

[0370] The gate electrode 16 includes a first portion 16a and a second portion 16b. The first portion 16a is provided on the first surface F1 side with respect to the second portion 16b.

[0371] The second portion 16b is in contact with the first portion 16a. The first portion 16a and the second portion 16b are electrically connected.

[0372] The first portion 16a faces the first region 36a of the main body region 36 in the second direction. The second portion 16b faces the second region 36b of the main body region 36 in the second direction.

[0373] The first portion 16a includes a first material. The second portion 16b includes a second material. The first portion 16a is formed of, for example, the first material. The second portion 16b is formed of, for example, the second material.

[0374] The work function of the first material is larger than the work function of the second material. The difference between the work function of the first material and the work function of the second material is, for example, 0.2 eV to 4.0 eV.

[0375] The first material and the second material are p-type polysilicon containing p-type impurities. The p-type impurity concentration of the first material is higher than the p-type impurity concentration of the second material.

[0376] like Fig.29As shown, a position Py where the n-type impurity concentration in the depth direction of the body region 36 along the gate insulating layer 18 becomes maximum is opposed to the second portion 16 b in the second direction, for example.

[0377] In the MOSFET 601 of the second modification of the sixth embodiment, the gate electrode 16 includes a first portion 16a and a second portion 16b. The work function of the first material included in the first portion 16a is larger than the work function of the second material included in the second portion 16b.

[0378] Since the work function of the first material is larger than the work function of the second material, the threshold voltage of the MOSFET composed of the first portion 16a, the gate insulating layer 18 and the first region 36a is lower than the threshold voltage of the MOSFET composed of the second portion 16b, the gate insulating layer 18 and the second region 36b. In other words, the threshold voltage of the MOSFET using the first portion 16a as the gate electrode is lower than the threshold voltage of the MOSFET using the second portion 16b as the gate electrode.

[0379] In the MOSFET 601 of the second modification of the sixth embodiment, the threshold voltage of the MOSFET using the first portion 16a as the gate electrode is lowered, and the channel resistance of the channel formed in the first region 36a is lowered. Therefore, the on-resistance of the MOSFET 601 is reduced.

[0380] On the other hand, the threshold voltage of the MOSFET using the second portion 16 b as the gate electrode is kept relatively high, so the threshold voltage of the MOSFET 601 can be kept high.

[0381] For example, Fig.29 As shown, by making the position Py where the n-type impurity concentration becomes maximum face the second portion 16b, the threshold voltage of the MOSFET using the second portion 16b as the gate electrode can be further increased.

[0382] From the viewpoint of reducing the on-resistance of MOSFET 601 , the difference between the work function of the first material and the work function of the second material is, for example, preferably 0.2 eV or more, more preferably 0.5 eV or more, and further preferably 1.0 eV or more.

[0383] According to the MOSFET 601 of the second modification of the sixth embodiment, the on-resistance can be reduced similarly to the MOSFET 600 of the sixth embodiment.

[0384] As described above, according to the sixth embodiment and the modified example, a semiconductor device capable of reducing on-resistance can be realized.

[0385] In the above, in the first to sixth embodiments, the case where the semiconductor device is a MOSFET is described as an example, but the semiconductor device may also be an IGBT (Insulated Gate Bipolar Transistor).

[0386] Furthermore, in the first to sixth embodiments, silicon is described as an example of a material for the semiconductor layer. However, other materials such as silicon carbide (SiC) and gallium nitride (GaN) may also be used for the semiconductor layer.

[0387] Several embodiments of the present invention are described above, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the main purpose of the invention. For example, the constituent elements of one embodiment can also be replaced or changed to constituent elements of other embodiments. These embodiments and their variations are included in the scope or main purpose of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device, wherein: have: A semiconductor layer having a first surface and a second surface opposite to the first surface, including a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type disposed between the first semiconductor region and the first surface, and a third semiconductor region of the first conductivity type disposed between the second semiconductor region and the first surface; a first electrode disposed on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region; a second electrode disposed on the second surface side of the semiconductor layer; a gate electrode disposed in the semiconductor layer and facing the first semiconductor region, the second semiconductor region, and the third semiconductor region; as well as a gate insulating layer provided between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region, The second semiconductor region includes a first region, a second region, and a third region, the first region is disposed between the second region and the first semiconductor region, and the third region is disposed between the second region and the third semiconductor region. The gate electrode includes a first portion, a second portion, and a third portion, the first portion is opposite to the first region, the second portion is opposite to the second region, the third portion is opposite to the third region, the first portion includes a first material, the second portion includes a second material, and the third portion includes a third material, When the first conductivity type is n-type and the second conductivity type is p-type, the work function of the first material and the work function of the third material are smaller than the work function of the second material. When the first conductivity type is p-type and the second conductivity type is n-type, the work function of the first material and the work function of the third material are larger than the work function of the second material.

2. The semiconductor device according to claim 1, wherein: In a cross section parallel to a direction from the first electrode toward the second electrode and including the gate electrode and the semiconductor layer, a position where the second conductive type impurity concentration becomes maximum in a region of the second semiconductor region along the gate insulating layer is opposite to the second portion.

3. The semiconductor device according to claim 1, wherein: The first material, the second material, and the third material are polycrystalline silicon.

4. The semiconductor device according to claim 3, wherein: The first material, the second material, and the third material are of the same conductivity type, and the impurity concentration of the first material and the impurity concentration of the third material are different from the impurity concentration of the second material.

5. The semiconductor device according to claim 3, wherein: The conductivity type of the first material and the conductivity type of the third material are different from the conductivity type of the second material.

6. The semiconductor device according to claim 1, wherein: A first insulating film is provided between the first portion and the second portion, and a second insulating film is provided between the second portion and the third portion.

7. The semiconductor device according to claim 6, wherein: The first portion, the second portion, and the third portion are electrically connected.

8. The semiconductor device according to claim 1, wherein: A length of the second portion in a direction from the first electrode toward the second electrode is not less than 20% and not more than 70% of a length between the first semiconductor region and the third semiconductor region in the direction.

9. The semiconductor device according to claim 1, wherein: The difference between the work function of the first material and the work function of the second material is 0.2 eV or more, The difference between the work function of the third material and the work function of the second material is 0.2 eV or more.

10. The semiconductor device according to claim 1, wherein The semiconductor layer is a silicon layer.

11. A semiconductor device, wherein: have: A semiconductor layer having a first surface and a second surface opposite to the first surface, and including an n-type first semiconductor region, a p-type second semiconductor region provided between the first semiconductor region and the first surface, and an n-type third semiconductor region provided between the second semiconductor region and the first surface; a first electrode disposed on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region; a second electrode disposed on the second surface side of the semiconductor layer; a gate electrode disposed in the semiconductor layer and facing the first semiconductor region, the second semiconductor region, and the third semiconductor region; as well as a gate insulating layer provided between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region, The second semiconductor region includes a first region and a second region, and the first region is provided between the second region and the first semiconductor region or between the second region and the third semiconductor region. The gate electrode includes a first portion and a second portion, the first portion is opposite to the first region, the second portion is opposite to the second region, the first portion includes a first material, and the second portion includes a second material, The first material is n-type polysilicon, The work function of the first material is smaller than the work function of the second material.

12. The semiconductor device according to claim 11, wherein In a cross section parallel to a direction from the first electrode toward the second electrode and including the gate electrode and the semiconductor layer, a position where the p-type impurity concentration becomes maximum in a region of the second semiconductor region along the gate insulating layer faces the second portion.

13. The semiconductor device according to claim 11, wherein: The second material is polycrystalline silicon.

14. The semiconductor device according to claim 13, wherein: The second material is n-type polycrystalline silicon.

15. The semiconductor device according to claim 13, wherein: The second material is p-type polycrystalline silicon.

16. A semiconductor device, wherein: have: A semiconductor layer having a first surface and a second surface opposite to the first surface, and including a p-type first semiconductor region, an n-type second semiconductor region provided between the first semiconductor region and the first surface, and a p-type third semiconductor region provided between the second semiconductor region and the first surface; a first electrode disposed on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region; a second electrode disposed on the second surface side of the semiconductor layer; a gate electrode disposed in the semiconductor layer and facing the first semiconductor region, the second semiconductor region, and the third semiconductor region; as well as a gate insulating layer provided between the gate electrode and the first semiconductor region, between the gate electrode and the second semiconductor region, and between the gate electrode and the third semiconductor region, The second semiconductor region includes a first region and a second region, and the first region is provided between the second region and the first semiconductor region or between the second region and the third semiconductor region. The gate electrode includes a first portion and a second portion, the first portion is opposite to the first region, the second portion is opposite to the second region, the first portion includes a first material, and the second portion includes a second material, The work function of the first material is larger than the work function of the second material.

17. The semiconductor device according to claim 16, wherein: In a cross section parallel to a direction from the first electrode toward the second electrode and including the gate electrode and the semiconductor layer, a position where the n-type impurity concentration is maximum in a region of the second semiconductor region along the gate insulating layer faces the second portion.

18. The semiconductor device according to claim 16, wherein: The first material and the second material are polysilicon.

19. The semiconductor device according to claim 18, wherein: The first material and the second material are of the same conductivity type, and the impurity concentration of the second material is different from the impurity concentration of the first material.

20. The semiconductor device according to claim 18, wherein The conductivity type of the second material is different from the conductivity type of the first material.

Images