Semiconductor device

Abstract

A semiconductor device includes: a lower pattern extending in a first direction; a first channel pattern on the lower pattern and including a plurality of first sheet patterns; a second channel pattern on the lower pattern including a plurality of second sheet patterns and spaced apart from the first channel pattern; a first gate structure extending around the first sheet pattern and including a first gate electrode and a first gate insulating film; a second gate structure extending around the second sheet pattern and including a second gate electrode and a second gate insulating film; a first gate capping pattern; and a second gate capping pattern. A number of the first sheet patterns is different from a number of the second sheet patterns, and a thickness of the first gate capping pattern is different from a thickness of the second gate capping pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all the benefits of Korean Patent Application No. 10-2023-0115137 filed in the Korean Intellectual Property Office on August 31, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including an MBCFET TM A semiconductor device of (multi-bridge channel field effect transistor) and a method for manufacturing the semiconductor device. Background Art

[0004] As one of the scaling-down technologies for increasing the density of semiconductor devices, a multi-gate transistor has been proposed in which a multi-channel active pattern (or silicon body) having a fin or nanowire shape is formed on a substrate and a gate is formed on a surface of the multi-channel active pattern.

[0005] Since such a multi-gate transistor utilizes a three-dimensional channel, it is easy to scale down. In addition, even without increasing the gate length of the multi-gate transistor, the current control capability can be improved. In addition, the SCE (short channel effect) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed. Summary of the invention

[0006] Aspects of the present disclosure provide a semiconductor device that can improve element performance and reliability.

[0007] However, the embodiments of the present disclosure are not limited to the embodiments described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the detailed description of the present disclosure given below.

[0008] According to some embodiments of the present disclosure, a semiconductor device is provided, including: a lower pattern extending in a first direction; a first channel pattern on the lower pattern and including a plurality of first sheet patterns spaced apart in a second direction; a second channel pattern on the lower pattern, including a plurality of second sheet patterns spaced apart in the second direction and spaced apart from the first channel pattern in the first direction; a first gate structure extending around the first sheet pattern in a plane including the first direction and the second direction and including a first gate electrode and a first gate insulating film; a second gate structure extending around the second sheet pattern in a plane including the first direction and the second direction and including a second gate electrode and a second gate insulating film; a first gate capping pattern on the first gate structure; and a second gate capping pattern on the second gate structure. The number of the first sheet patterns is different from the number of the second sheet patterns, and the thickness of the first gate capping pattern is different from the thickness of the second gate capping pattern.

[0009] According to some embodiments of the present disclosure, a semiconductor device is provided, including: a lower pattern extending in a first direction; a first channel pattern on the lower pattern and including a plurality of first sheet patterns spaced apart in a second direction; a second channel pattern on the lower pattern, including a plurality of second sheet patterns spaced apart in the second direction and spaced apart from the first channel pattern in the first direction; a first gate electrode extending around the first sheet pattern in a plane including the first direction and the second direction; a second gate electrode extending around the second sheet pattern in a plane including the first direction and the second direction; a first gate capping pattern on the first gate electrode; a second gate capping pattern on the second gate electrode; a first gate contact extending into the first gate capping pattern and electrically connected to the first gate electrode; and a second gate contact extending into the second gate capping pattern and electrically connected to the second gate electrode. The number of the first sheet patterns is different from the number of the second sheet patterns. The first gate electrode includes a first portion of the first gate electrode overlapping the first channel pattern in the second direction, and the second gate electrode includes a first portion of the second gate electrode overlapping the second channel pattern in the second direction, and a distance from an upper surface of the lower pattern to an upper surface of the first portion of the first gate electrode is different from a distance from the upper surface of the lower pattern to an upper surface of the first portion of the second gate electrode.

[0010] According to some embodiments of the present disclosure, a semiconductor device is provided, including: a lower pattern extending in a first direction; a first channel pattern on the lower pattern and including a first sheet pattern; a second channel pattern on the lower pattern and including a second sheet pattern, the number of second sheet patterns included in the second channel pattern being less than the number of first sheet patterns included in the first channel pattern; a source / drain pattern on the lower pattern and electrically connected to the first channel pattern and the second channel pattern; a first gate electrode extending around the first sheet pattern in a cross-sectional view; a second gate electrode extending around the second sheet pattern in a cross-sectional view; a first gate capping pattern on the first gate electrode; and a second gate capping pattern on the second gate electrode. In the cross-sectional view, the distance from the upper surface of the lower pattern to the upper surface of the first gate electrode is greater than the distance from the upper surface of the lower pattern to the upper surface of the second gate electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail illustrative embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0012] Figure 1 is an exemplary plan view for illustrating a semiconductor device according to some embodiments;

[0013] Figure 2 is along Figure 1 A cross-sectional view taken along line AA;

[0014] Figure 3 is along Figure 1 A cross-sectional view taken along line BB, line CC, and line DD;

[0015] Figure 4 is along Figure 1 A cross-sectional view taken along line EE, line FF, and line GG;

[0016] Figures 5 to 7 They are Figure 3 An enlarged view of region P, region Q and region R;

[0017] Figures 8 to 11 are diagrams for explaining semiconductor devices according to some embodiments;

[0018] Figure 12 to Figure 14 is a diagram for explaining a semiconductor device according to some embodiments;

[0019] Fig.15 and Fig.16 is a diagram for explaining a semiconductor device according to some embodiments;

[0020] Figures 17 to 34 is a diagram for explaining an intermediate stage of a method for manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0021] Although terms such as first and second are used in this specification to describe various elements or components, it goes without saying that these elements or components are not limited by these terms. These terms are only used to distinguish a single element or component from other elements or components. Therefore, it goes without saying that the first element or component mentioned below can be the second element or component within the technical concept of the present disclosure.

[0022] The semiconductor device according to some embodiments may include a tunneling transistor (tunneling FET), a three-dimensional (3D) transistor or a transistor based on a two-dimensional material (FET based on a 2D material) and a heterostructure thereof. In addition, the semiconductor device according to some embodiments may also include a bipolar junction transistor, a lateral diffused metal oxide semiconductor (LDMOS), etc.

[0023] Reference Figures 1 to 7 A semiconductor device according to some embodiments is described.

[0024] Figure 1 is an example plan view for explaining a semiconductor device according to some embodiments. Figure 2 is along Figure 1 A cross-sectional view taken along line AA. Figure 3 is along Figure 1 A cross-sectional view taken along lines BB, CC and DD in FIG. Figure 4 is along Figure 1 A cross-sectional view taken along line EE, line FF and line GG. Figures 5 to 7 They are shown respectively Figure 3 Enlarged views of region P, region Q and region R.

[0025] For reference, simply show Figure 1 , while the first to third gate insulating films 130 , 230 , and 330 , the first to third gate contacts 175 , 275 , and 375 , the source / drain via 195 , and the like are not shown.

[0026] refer to Figures 1 to 7 , a semiconductor device according to some embodiments may include a first lower pattern BP1, first to third channel patterns CH1, CH2 and CH3, first to third gate structures GS1, GS2 and GS3, first to third gate capping patterns 145, 245, 345, first to fourth source / drain patterns 150, 250, 350 and 450, and first to third gate contacts 175, 275 and 375.

[0027] The substrate 100 may be bulk silicon or silicon on insulator (SOI). In some embodiments, the substrate 100 may be a silicon substrate, or may include but is not limited to silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0028] The first lower pattern BP1 may protrude from the substrate 100 in the third direction D3. The first lower pattern BP1 may extend long in the first direction D1. The first lower pattern BP1 may be a fin-shaped pattern.

[0029] As an example, the first lower pattern BP1 may be disposed in a PMOS formation region. As another example, the first lower pattern BP1 may be disposed in an NMOS formation region.

[0030] The first lower pattern BP1 may be formed by etching a portion of the substrate 100, and may include an epitaxial layer grown from the substrate 100. The first lower pattern BP1 may include silicon or germanium as an elemental semiconductor material. In addition, the first lower pattern BP1 may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0031] Group IV-IV compound semiconductors may include, for example, binary or ternary compounds including at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or compounds obtained by doping these elements with Group IV elements.

[0032] The III-V compound semiconductor may be, for example, a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as III-group elements with one of phosphorus (P), arsenic (As), and antimony (Sb) as V-group elements.

[0033] The field insulating film 105 may be disposed on the substrate 100. The field insulating film 105 may be disposed on the sidewall of the first lower pattern BP1. The field insulating film 105 is not disposed on the upper surface BP1_US of the first lower pattern.

[0034] The field insulating film 105 may completely cover, overlap, or be on the sidewall of the first lower pattern BP1. Unlike the example shown, the field insulating film 105 may cover a portion of the sidewall of the first lower pattern BP1. In this case, a portion of the first lower pattern BP1 may protrude beyond the upper surface of the field insulating film 105 in the third direction D3.

[0035] Although the upper surface of the field insulating film 105 is shown as a plane, the embodiment is not limited thereto. Unlike the example shown, the upper surface of the field insulating film 105 may have a concave shape. The field insulating film 105 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof. Although the field insulating film 105 is shown as a single film, this is only for ease of description, and the embodiment is not limited thereto.

[0036] At least one or more first channel patterns CH1 may be disposed on the first lower pattern BP1. At least one or more second channel patterns CH2 may be disposed on the first lower pattern BP1. At least one or more third channel patterns CH3 may be disposed on the first lower pattern BP1.

[0037] The first channel pattern CH1, the second channel pattern CH2, and the third channel pattern CH3 may be disposed on the upper surface BP1_US of the first lower pattern. The first channel pattern CH1, the second channel pattern CH2, and the third channel pattern CH3 may overlap the first lower pattern BP1 in the third direction D3. The first channel pattern CH1, the second channel pattern CH2, and the third channel pattern CH3 may be spaced apart from the first lower pattern BP1 in the third direction D3.

[0038] The first channel pattern CH1 is spaced apart from the second channel pattern CH2 and the third channel pattern CH3 in the first direction D1. The first channel pattern CH1 may be spaced apart from each other in the first direction D1. The second channel pattern CH2 is spaced apart from the third channel pattern CH3 in the first direction D1. The second channel pattern CH2 may be spaced apart from each other in the first direction D1. The third channel pattern CH3 may be spaced apart from each other in the first direction D1.

[0039] The first channel pattern CH1 may include a plurality of first sheet patterns NS1. The plurality of first sheet patterns NS1 may be disposed on the upper surface BP1_US of the first lower pattern. The plurality of first sheet patterns NS1 are arranged on the first lower pattern BP1 along the third direction D3. Each of the first sheet patterns NS1 may be spaced apart in the third direction D3.

[0040] The second channel pattern CH2 may include a plurality of second sheet patterns NS2. The plurality of second sheet patterns NS2 may be disposed on the upper surface BP1_US of the first lower pattern. The plurality of second sheet patterns NS2 are arranged on the first lower pattern BP1 along the third direction D3. Each second sheet pattern NS2 may be spaced apart in the third direction D3.

[0041] The third channel pattern CH3 may include a plurality of third sheet patterns NS3. The plurality of third sheet patterns NS3 may be disposed on the upper surface BP1_US of the first lower pattern. The plurality of third sheet patterns NS3 are arranged on the first lower pattern BP1 along the third direction D3. Each third sheet pattern NS3 may be spaced apart in the third direction D3. The third direction D3 may be a direction intersecting the first direction D1 and the second direction D2. For example, the third direction D3 may be a thickness direction of the substrate 100. The first direction D1 may be a direction intersecting the second direction D2.

[0042] The number of the first sheet pattern NS1 may be different from the number of the second sheet pattern NS2 and the number of the third sheet pattern NS3. The number of the second sheet pattern NS2 may be different from the number of the third sheet pattern NS3. For example, the number of the first sheet pattern NS1 included in the first channel pattern CH1 may be greater than the number of the second sheet pattern NS2 included in the second channel pattern CH2. The number of the first sheet pattern NS1 included in the first channel pattern CH1 may be greater than the number of the third sheet pattern NS3 included in the third channel pattern CH3. The number of the second sheet pattern NS2 included in the second channel pattern CH2 may be greater than the number of the third sheet pattern NS3 included in the third channel pattern CH3.

[0043] Although each of the first to third channel patterns CH1 , CH2 , and CH3 is illustrated as including a plurality of sheet patterns, the embodiment is not limited thereto. Unlike the illustrated example, the number of third sheet patterns NS3 included in the third channel pattern CH3 may be one.

[0044] The first channel pattern CH1 may include, but is not limited to, one more sheet pattern than the second channel pattern CH2. The second channel pattern CH2 may include, but is not limited to, one more sheet pattern than the third channel pattern CH3.

[0045] Although the second channel pattern CH2 is shown as being disposed between the first channel pattern CH1 and the third channel pattern CH3, this is only for convenience of explanation, and the embodiment is not limited thereto. Of course, the first channel pattern CH1 may be disposed between the second channel pattern CH2 and the third channel pattern CH3.

[0046] Each of the first to third sheet patterns NS1, NS2, and NS3 may include an upper surface and a lower surface. Taking the first sheet pattern NS1 as an example, the upper surface of the first sheet pattern NS1 may be opposite to the lower surface of the first sheet pattern NS1 in the third direction D3. The lower surface of the first sheet pattern NS1 faces the upper surface BP1_US of the first lower pattern.

[0047] The upper surface CH1_US of the first channel pattern may be the upper surface of the first sheet pattern NS1 located at the uppermost portion of the first sheet pattern NS1 included in the first channel pattern CH1. The upper surface CH2_US of the second channel pattern may be the upper surface of the second sheet pattern NS2 located at the uppermost portion of the second sheet pattern NS2 included in the second channel pattern CH2. The upper surface CH3_US of the third channel pattern may be the upper surface of the third sheet pattern NS3 located at the uppermost portion of the third sheet pattern NS3 included in the third channel pattern CH3. The height or distance from the upper surface BP1_US of the first lower pattern to the upper surface CH2_US of the second channel pattern is less than or lower than the height or distance from the upper surface BP1_US of the first lower pattern to the upper surface CH1_US of the first channel pattern. The height or distance from the upper surface BP1_US of the first lower pattern to the upper surface CH2_US of the second channel pattern is greater than or higher than the height or distance from the upper surface BP1_US of the first lower pattern to the upper surface CH3_US of the third channel pattern.

[0048] The first to third sheet patterns NS1, NS2, and NS3 may include one of silicon or germanium, a group IV-IV compound semiconductor, or a group III-V compound semiconductor, silicon or germanium being an elemental semiconductor material. The first sheet pattern NS1 includes the same material as the second sheet pattern NS2. The first sheet pattern NS1 includes the same material as the third sheet pattern NS3.

[0049] The first sheet pattern NS1 may include the same material as the first lower pattern BP1, or may include a different material from the first lower pattern BP1. In the semiconductor device according to some embodiments, the first lower pattern BP1 may be a silicon lower pattern including silicon. The first to third sheet patterns NS1, NS2, and NS3 may each be a silicon sheet pattern including silicon.

[0050] The width of the first sheet pattern NS1 in the second direction D2 may increase or decrease in proportion to the width of the upper surface BP1_US of the first lower pattern in the second direction D2. Although the widths of the first sheet pattern NS1 stacked in the third direction D3 in the second direction D2 are shown to be the same, this is only for ease of explanation, and the embodiment is not limited thereto. Unlike the example shown, the width of the first sheet pattern NS1 stacked in the third direction D3 in the second direction D2 may decrease as it moves away from the first lower pattern BP1. It goes without saying that the above description also applies to the second sheet pattern NS2 and the third sheet pattern NS3.

[0051] Although it has been described above that three channel patterns CH1, CH2, and CH3 including different numbers of sheet patterns are disposed on the first lower pattern BP1, the embodiment is not limited thereto. Unlike the illustrated example, as an example, two channel patterns including different numbers of sheet patterns may be disposed on the first lower pattern BP1. As another example, four or more channel patterns including different numbers of sheet patterns may be disposed on the first lower pattern BP1.

[0052] The first to third gate structures GS1, GS2, and GS3 may be disposed on the first lower pattern BP1. Each of the first to third gate structures GS1, GS2, and GS3 may cross the first lower pattern BP1. The first to third gate structures GS1, GS2, and GS3 may contact the upper surface BP1_US of the first lower pattern.

[0053] The first gate structure GS1 may be spaced apart from the second gate structure GS2 and the third gate structure GS3 in the first direction D1. The second gate structure GS2 may be spaced apart from the third gate structure GS3 in the first direction D1.

[0054] The first gate structure GS1 may surround the first channel pattern CH1 in a cross section of the first direction D1 and the second direction D2. As used herein, the term "surrounding" may be interpreted as surrounding and extending, but may not completely surround. The first gate structure GS1 may surround each first sheet pattern NS1 in a cross section across the first direction D1 and the second direction D2.

[0055] The first gate structure GS1 may include a first inner gate structure GS1_I and a first outer gate structure GS1_O. The first inner gate structure GS1_I may be disposed between first sheet patterns NS1 adjacent to each other in the third direction D3, and between the first lower pattern BP1 and the first sheet pattern NS1. The first outer gate structure GS1_O may be disposed on the upper surface CH1_US of the first channel pattern. For example, Figure 2 The first internal gate structure GS1_I and the first external gate structure GS1_O are defined by the angle of the cross-sectional view.

[0056] The second gate structure GS2 may surround the second channel pattern CH2 in the cross section of the first direction D1 and the second direction D2. The second gate structure GS2 may surround each of the second sheet patterns NS2 in the cross section of the first direction D1 and the second direction D2.

[0057] The second gate structure GS2 may include a second inner gate structure GS2_I and a second outer gate structure GS2_O. The second inner gate structure GS2_I may be disposed between the second sheet patterns NS2 adjacent to each other along the third direction D3 and between the first lower pattern BP1 and the second sheet pattern NS2. The second outer gate structure GS2_O may be disposed on the upper surface CH2_US of the second channel pattern.

[0058] The third gate structure GS3 may surround the third channel pattern CH3 in the cross section of the first direction D1 and the second direction D2. The third gate structure GS3 may surround each of the third sheet patterns NS3 in the cross section of the first direction D1 and the second direction D2.

[0059] The third gate structure GS3 may include a third inner gate structure GS3_I and a third outer gate structure GS3_O. The third inner gate structure GS3_I may be disposed between the third sheet patterns NS3 adjacent to each other along the third direction D3, and between the first lower pattern BP1 and the third sheet pattern NS3. The third outer gate structure GS3_O may be disposed on the upper surface CH3_US of the third channel pattern.

[0060] The first gate structure GS1 may include a first gate electrode 120 and a first gate insulating film 130. The first inner gate structure GS1_I and the first outer gate structure GS1_O each include a first gate electrode 120 and a first gate insulating film 130.

[0061] The first gate electrode 120 may be disposed on the first lower pattern BP1. From the perspective of the cross-sectional view, the first gate electrode 120 may surround each first sheet pattern NS1. The first gate insulating film 130 may be disposed between the first gate electrode 120 and the first channel pattern CH1. The first gate insulating film 130 may be disposed between the first gate electrode 120 and the first sheet pattern NS1.

[0062] The second gate structure GS2 may include a second gate electrode 220 and a second gate insulating film 230. The second inner gate structure GS2_I and the second outer gate structure GS2_O each include a second gate electrode 220 and a second gate insulating film 230. The second gate electrode 220 may be disposed on the first lower pattern BP1. From the perspective of the cross-sectional view, the second gate electrode 220 may surround each second sheet pattern NS2. The second gate insulating film 230 may be disposed between the second gate electrode 220 and the second sheet pattern NS2.

[0063] The third gate structure GS3 may include a third gate electrode 320 and a third gate insulating film 330. The third inner gate structure GS3_I and the third outer gate structure GS3_O each include a third gate electrode 320 and a third gate insulating film 330. The third gate electrode 320 may be disposed on the first lower pattern BP1. From the perspective of the cross-sectional view, the third gate electrode 320 may surround each third sheet pattern NS3. The third gate insulating film 330 may be disposed between the third gate electrode 320 and the third sheet pattern NS3.

[0064] Each of the first to third gate insulating films 130, 230, and 330 may extend along an upper surface of the field insulating film 105 and an upper surface BP1_US of the first lower pattern. Each of the first to third gate insulating films 130, 230, and 330 may contact an upper surface of the field insulating film 105 and an upper surface BP1_US of the first lower pattern.

[0065] Although in Figure 2 In the cross-sectional view in FIG. 1 , the upper surface 120US of the first gate electrode, the upper surface 220US of the second gate electrode, and the upper surface 320US of the third gate electrode are shown as concave surfaces, but the embodiment is not limited thereto. It goes without saying that the upper surface 120US of the first gate electrode, the upper surface 220US of the second gate electrode, and the upper surface 320US of the third gate electrode can be planes.

[0066] exist Figure 3 and Figure 5 In the embodiment, the first gate electrode 120 may include a first portion 120R1 and a second portion 120R2. The first portion 120R1 of the first gate electrode is directly connected to the second portion 120R2 of the first gate electrode. The second portion 120R2 of the first gate electrode may be located on both sides of the first portion 120R1 of the first gate electrode. Unlike the upper surface 220US of the second gate electrode and the upper surface 320US of the third gate electrode, the upper surface 120US of the first gate electrode may be flat. In this case, the first portion 120R1 of the first gate electrode may overlap with the first channel pattern CH1 in the third direction D3. For example, the first portion 120R1 of the first gate electrode may be a portion of the first gate electrode 120 that overlaps with the upper surface CH1_US of the first channel pattern in the third direction D3. The second portion 120R2 of the first gate electrode may not overlap with the first channel pattern CH1 in the third direction D3.

[0067] exist Figure 3 and Figure 6In the embodiment of the present invention, the second gate electrode 220 may include a first portion 220R1 and a second portion 220R2. The first portion 220R1 of the second gate electrode is directly connected to the second portion 220R2 of the second gate electrode. The second portion 220R2 of the second gate electrode may be located on both sides of the first portion 220R1 of the second gate electrode. The upper surface 220US of the second gate electrode may include a region recessed toward the second channel pattern CH2. The first portion 220R1 of the second gate electrode may be a region in which a portion of the second gate electrode 220 is recessed. The first portion 220R1 of the second gate electrode may overlap with the second channel pattern CH2 in the third direction D3. The first portion 220R1 of the second gate electrode may overlap with the upper surface CH2_US of the second channel pattern in the third direction D3. The second portion 220R2 of the second gate electrode may not overlap with the second channel pattern CH2 in the third direction D3.

[0068] exist Figure 3 and Figure 7 In the embodiment of the present invention, the third gate electrode 320 may include a first portion 320R1 and a second portion 320R2. The first portion 320R1 of the third gate electrode is directly connected to the second portion 320R2 of the third gate electrode. The second portion 320R2 of the third gate electrode may be located on both sides of the first portion 320R1 of the third gate electrode. The upper surface 320US of the third gate electrode may include a region recessed toward the third channel pattern CH3. The first portion 320R1 of the third gate electrode may be a region in which a portion of the third gate electrode 320 is recessed. The first portion 320R1 of the third gate electrode may overlap with the third channel pattern CH3 in the third direction D3. The first portion 320R1 of the third gate electrode may overlap with the upper surface CH3_US of the third channel pattern in the third direction D3. The second portion 320R2 of the third gate electrode may not overlap with the third channel pattern CH3 in the third direction D3.

[0069] A height H11 from the upper surface BP1_US of the first lower pattern to the upper surface 120US of the first portion 120R1 of the first gate electrode may be different from a height H21 from the upper surface BP1_US of the first lower pattern to the upper surface 220US of the first portion 220R1 of the second gate electrode. For example, the height H11 from the upper surface BP1_US of the first lower pattern to the upper surface 120US of the first portion 120R1 of the first gate electrode is greater than a height H21 from the upper surface BP1_US of the first lower pattern to the upper surface 220US of the first portion 220R1 of the second gate electrode. The height H21 from the upper surface BP1_US of the first lower pattern to the upper surface 220US of the first portion 220R1 of the second gate electrode is greater than a height H31 from the upper surface BP1_US of the first lower pattern to the upper surface 320US of the first portion 320R1 of the third gate electrode. The second gate electrode 220 is described as an example. A height H21 from the upper surface BP1_US of the first lower pattern to the upper surface 220US of the first portion 220R1 of the second gate electrode is measured on a line passing through the center of the upper surface CH2_US of the second channel pattern.

[0070] For example, the height H21 from the upper surface BP1_US of the first lower pattern to the upper surface 220US of the first portion 220R1 of the second gate electrode may be 1000 mm from the upper surface BP1_US of the first lower pattern to the upper surface 220US of the first portion 220R1 of the second gate electrode. Figure 2 A height H21 of the upper surface 220US of the second gate electrode.

[0071] The height H13 from the upper surface BP1_US of the first lower pattern to the upper surface 120US of the second portion 120R2 of the first gate electrode may be the same as the height H23 from the upper surface BP1_US of the first lower pattern to the upper surface 220US of the second portion 220R2 of the second gate electrode. The height H23 from the upper surface BP1_US of the first lower pattern to the upper surface 220US of the second portion 220R2 of the second gate electrode may be the same as the height H33 from the upper surface BP1_US of the first lower pattern to the upper surface 320US of the second portion 320R2 of the third gate electrode. Here, the meaning of "same height" includes not only the case where the heights at the two positions to be compared are exactly the same, but also includes a slight height difference that may occur due to process margins, etc.

[0072] When Figure 3When the upper surface 120_US of the first gate electrode is shown to be a plane, the height H11 from the upper surface BP1_US of the first lower pattern to the upper surface 120US of the first portion 120R1 of the first gate electrode may be the same as the height H13 from the upper surface BP1_US of the first lower pattern to the upper surface 120US of the second portion 120R2 of the first gate electrode. Unlike the example shown, when the upper surface 120_US of the first gate electrode has a concave shape, the height H11 from the upper surface BP1_US of the first lower pattern to the upper surface 120US of the first portion 120R1 of the first gate electrode may be less than or lower than the height H13 from the upper surface BP1_US of the first lower pattern to the upper surface 120US of the second portion 120R2 of the first gate electrode.

[0073] exist Figure 3 , Figure 6 and Figure 7 , a height H21 from the upper surface BP1_US of the first lower pattern to the upper surface 220US of the first portion 220R1 of the second gate electrode is less than or lower than a height H23 from the upper surface BP1_US of the first lower pattern to the upper surface 220US of the second portion 220R2 of the second gate electrode. A height H31 from the upper surface BP1_US of the first lower pattern to the upper surface 320US of the first portion 320R1 of the third gate electrode is less than or lower than a height H33 from the upper surface BP1_US of the first lower pattern to the upper surface 320US of the second portion 320R2 of the third gate electrode.

[0074] The first gate structure GS1 and the second gate structure GS2 are used as examples for explanation. Figure 2 From the perspective of the cross-sectional view in FIG, when the upper surface 220US of the second gate electrode is located at the same height level as the upper surface 120US of the first gate electrode, the area where the second source / drain contact 270 and the second external gate structure GS2_O face each other is larger than the area where the first source / drain contact 170 and the first external gate structure GS1_O face each other. Therefore, the capacitance between the second source / drain contact 270 and the second external gate structure GS2_O becomes larger than the capacitance between the first source / drain contact 170 and the first external gate structure GS1_O. The larger capacitance between the external gate structure and the source / drain contact may interfere with the operation of the semiconductor device that needs to be driven at high speed. Therefore, the performance and reliability of the semiconductor device may be reduced.

[0075] At the same time, since the upper surface 220US of the second gate electrode becomes lower than the upper surface 120US of the first gate electrode, the capacitance between the second source / drain contact 270 and the second outer gate structure GS2_O can be reduced. That is, the performance and reliability of the semiconductor device can be improved.

[0076] The first to third gate electrodes 120, 220, and 320 may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and / or a conductive metal oxynitride. The first to third gate electrodes 120, 220, and 320 may include, but are not limited to, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), carbonitride (CNT), titanium nitride (TiN), titanium nitride (TiN), titanium nitride (TiAlN), titanium nitride (TiAlCN), titanium nitride (TiAlCN), titanium nitride (TiC), titanium nitride (TiN ... At least one of tantalum (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (NiPt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and / or combinations thereof. The conductive metal oxides and conductive metal oxynitrides may include, but are not limited to, oxidized forms of the above materials.

[0077] The first to third gate insulating films 130, 230, and 330 may include silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, silicon zirconium oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0078] Although the first to third gate insulating films 130, 230, and 330 are shown as a single film, this example is only for ease of explanation and is not limited thereto. The first to third gate insulating films 130, 230, and 330 may each include a plurality of films. The first gate insulating film 130 is described as an example. The first gate insulating film 130 may include an interface layer and a high dielectric constant insulating film disposed between the first channel pattern CH1 and the first gate electrode 120. For example, the interface layer may not be formed along the contour of the upper surface of the field insulating film 105.

[0079] The semiconductor device according to some embodiments may include an NC (negative capacitance) FET using a negative capacitor.For example, the first to third gate insulating films 130, 230, and 330 may each include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0080] The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance is reduced relative to the capacitance of each individual capacitor. On the other hand, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance may be greater than the absolute value of each individual capacitance while having a positive value.

[0081] When a ferroelectric material film having negative capacitance and a paraelectric material film having positive capacitance are connected in series, the total capacitance value of the ferroelectric material film and the paraelectric material film connected in series can be increased. By using the increased total capacitance value, a transistor including the ferroelectric material film can have a subthreshold swing (SS) of less than 60mV / decade at room temperature.

[0082] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and / or oxygen (O).

[0083] The ferroelectric material film may further include a dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film may vary depending on the type of ferroelectric material included in the ferroelectric material film.

[0084] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and / or yttrium (Y).

[0085] When the dopant is aluminum (Al), the ferroelectric material film may include 3 at% (atomic %) to 8 at% of aluminum. Here, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

[0086] When the dopant is silicon (Si), the ferroelectric material film may include 2at% to 10at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may include 2at% to 10at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may include 1at% to 7at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include 50at% to 80at% zirconium.

[0087] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide with a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example but not limited to, at least one of hafnium oxide, zirconium oxide and / or aluminum oxide.

[0088] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film has ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film is different from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0089] The ferroelectric material film may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film may be, for example but not limited to, 0.5 nm to 10 nm. Since the critical thickness that exhibits ferroelectric properties may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0090] As an example, each of the first to third gate insulating films 130, 230, and 330 may include a ferroelectric material film. As another example, each of the first to third gate insulating films 130, 230, and 330 may include a plurality of ferroelectric material films spaced apart from each other. Each of the first to third gate insulating films 130, 230, and 330 may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0091] The first gate spacer 140 may be disposed on the sidewall of the first gate structure GS1. The second gate spacer 240 may be disposed on the sidewall of the second gate structure GS2. The third gate spacer 340 may be disposed on the sidewall of the third gate structure GS3.

[0092] In such Figure 2 In the cross-sectional view in FIG. 1 , the first gate structure GS1 may not enter between the first gate spacer 140 and the first channel pattern CH1 . The first outer gate structure GS1_O may be disposed between the first gate spacers 140 .

[0093] In the semiconductor device according to some embodiments, a portion of the second gate structure GS2 may enter between the second gate spacer 240 and the second channel pattern CH2 or between the second gate spacer 240 and the second channel pattern CH2. A portion of the third gate structure GS3 may enter between the third gate spacer 340 and the third channel pattern CH3 or between the third gate spacer 340 and the third channel pattern CH3.

[0094] In such Figure 2In the cross-sectional view in FIG. 1 , the second gate spacer 240 may have a shape placed on the second external gate structure GS2_O. A portion of the second external gate structure GS2_O may enter between the second gate spacer 240 and the second channel pattern CH2 or between the second gate spacer 240 and the second channel pattern CH2. The third gate spacer 340 may have a shape placed on the third external gate structure GS3_O. A portion of the third external gate structure GS3_O may enter between the third gate spacer 340 and the third channel pattern CH3 or between the third gate spacer 340 and the third channel pattern CH3.

[0095] The first to third gate spacers 140, 240, and 340 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and / or a combination thereof. Although the first to third gate spacers 140, 240, and 340 are shown as a single film, this embodiment is only for ease of explanation and is not limited thereto.

[0096] The first gate capping pattern 145 may be disposed on the first gate structure GS1. The first gate capping pattern 145 may be disposed on the upper surface 120US of the first gate electrode. The first gate capping pattern 145 may include a lower surface 145BS and an upper surface 145US opposite to each other in the third direction D3. The lower surface 145BS of the first gate capping pattern faces the first gate electrode 120. The lower surface 145BS of the first gate capping pattern may contact the upper surface 120US of the first gate electrode.

[0097] The second gate capping pattern 245 may be disposed on the second gate structure GS2. The second gate capping pattern 245 may be disposed on the upper surface 220US of the second gate electrode. The second gate capping pattern 245 may include a lower surface 245BS and an upper surface 245US that are opposite to each other in the third direction D3. The lower surface 245BS of the second gate capping pattern faces the second gate electrode 220. The lower surface 245BS of the second gate capping pattern may contact the upper surface 220US of the second gate electrode.

[0098] The third gate capping pattern 345 may be disposed on the third gate structure GS3. The third gate capping pattern 345 may be disposed on the upper surface 320US of the third gate electrode. The third gate capping pattern 345 may include a lower surface 345BS and an upper surface 345US opposite to each other in the third direction D3. The lower surface 345BS of the third gate capping pattern faces the third gate electrode 320. The lower surface 345BS of the third gate capping pattern may contact the upper surface 320US of the third gate electrode.

[0099] The upper surface 145US of the first gate capping pattern may be disposed on the same plane as the upper surface 245US of the second gate capping pattern. The upper surface 145US of the first gate capping pattern may be disposed on the same plane as the upper surface 345US of the third gate capping pattern. A height H12 from the upper surface BP1_US of the first lower pattern to the upper surface 145US of the first gate capping pattern may be the same as a height H22 from the upper surface BP1_US of the first lower pattern to the upper surface 245US of the second gate capping pattern. A height H12 from the upper surface BP1_US of the first lower pattern to the upper surface 145US of the first gate capping pattern may be the same as a height H32 from the upper surface BP1_US of the first lower pattern to the upper surface 345US of the third gate capping pattern.

[0100] For example, the height H21 from the upper surface BP1_US of the first lower pattern to the upper surface 220US of the first portion 220R1 of the second gate electrode may be the height from the upper surface BP1_US of the first lower pattern to the lower surface 245BS of the second gate capping pattern.

[0101] The second gate capping pattern 245 is described as an example. The thickness t2 of the second gate capping pattern 245 may be the thickness of the second gate capping pattern 245 at a portion where the second gate capping pattern 245 overlaps with the second channel pattern CH2 along the third direction D3. For example, the thickness t2 of the second gate capping pattern 245 may be measured on a line passing through the center of the upper surface CH2_US of the second channel pattern.

[0102] The thickness t1 of the first gate capping pattern 145 may be different from the thickness t2 of the second gate capping pattern 245 and the thickness t3 of the third gate capping pattern 345. The thickness t2 of the second gate capping pattern 245 may be different from the thickness t3 of the third gate capping pattern 345.

[0103] For example, the thickness t3 of the third gate capping pattern 345 may be greater than the thickness t1 of the first gate capping pattern 145 and the thickness t2 of the second gate capping pattern 245. The thickness t2 of the second gate capping pattern 245 may be greater than the thickness t1 of the first gate capping pattern 145. The thickness t1 of the first gate capping pattern 145 at a portion where the first gate capping pattern 145 overlaps with the first channel pattern CH1 along the third direction D3 may be less than or lower than the thickness t2 of the second gate capping pattern 245 at a portion where the second gate capping pattern 245 overlaps with the second channel pattern CH2 along the third direction D3. The thickness t2 of the second gate capping pattern 245 at a portion where the second gate capping pattern 245 overlaps with the second channel pattern CH2 along the third direction D3 may be less than or lower than the thickness t3 of the third gate capping pattern 345 at a portion where the third gate capping pattern 345 overlaps with the third channel pattern CH3 along the third direction D3.

[0104] Taking the first gate spacer 140 and the first gate capping pattern 145 as an example, the first gate capping pattern 145 may be disposed on an upper surface of the first gate spacer 140. Unlike the illustrated example, an upper surface of the first gate spacer 140 may be disposed on the same plane as an upper surface 145US of the first gate capping pattern.

[0105] The first to third gate capping patterns 145 , 245 , and 345 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and / or combinations thereof.

[0106] The gate separation structure GCS may be disposed on the substrate 100. The gate separation structure GCS may be disposed on the field insulation film 105.

[0107] The gate separation structure GCS may be in contact with the field insulation film 105. The gate separation structure GCS may protrude from the upper surface of the field insulation film 105 in the third direction D3. For example, a portion of the gate separation structure GCS may enter the field insulation film 105.

[0108] The first gate structure GS1 may be disposed between the gate separation structures GCS adjacent to each other along the second direction D2. The second gate structure GS2 may be disposed between the gate separation structures GCS adjacent to each other along the second direction D2. The third gate structure GS3 may be disposed between the gate separation structures GCS adjacent to each other along the second direction D2.

[0109] Each of the first to third gate insulating films 130, 230, and 330 may not extend along the sidewall of the gate separation structure GCS in the third direction D3. Taking the first gate insulating film 130 as an example, the first gate insulating film 130 may not extend from the upper surface of the field insulating film 105 to the lower surface 145BS of the first gate capping pattern. The first gate insulating film 130 may not contact the first gate capping pattern 145. Each of the first to third gate electrodes 120, 220, and 320 may contact the sidewall of the gate separation structure GCS.

[0110] An upper surface of the gate separation structure GCS may be disposed on the same plane as an upper surface 145US of the first gate capping pattern, an upper surface 245US of the second gate capping pattern, and / or an upper surface 345US of the third gate capping pattern.

[0111] The gate separation structure GCS includes an insulating material. The gate separation structure GCS may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), and / or a combination thereof. Although the gate separation structure GCS is shown as a single film, this is only for ease of explanation and embodiments are not limited thereto.

[0112] Although the gate separation structure GCS is illustrated as also separating the first to third gate spacers 140 , 240 , and 340 , this is only for convenience of explanation, and embodiments are not limited thereto.

[0113] Although all the first to third gate structures GS1, GS2, and GS3 separated by the gate separation structure GCS are shown as crossing a single lower pattern, this is only for convenience of explanation, and the embodiment is not limited thereto. Unlike the example shown, at least one of the first to third gate structures GS1, GS2, and GS3 separated by the gate separation structure GCS may cross a plurality of lower patterns.

[0114] The first, second, third, and fourth source / drain patterns 150, 250, 350, and 450 may be disposed on the first lower pattern BP1. The first, second, third, and fourth source / drain patterns 150, 250, 350, and 450 contact the first lower pattern BP1.

[0115] The first source / drain pattern 150 may be disposed between the first gate structures GS1 adjacent in the first direction D1. The first source / drain pattern 150 may be connected to the first channel pattern CH1 disposed on both sides. The first source / drain pattern 150 may contact the corresponding first sheet pattern NS1.

[0116] The second source / drain pattern 250 may be disposed between the second gate structures GS2 adjacent in the first direction D1. The second source / drain pattern 250 may be connected to the second channel pattern CH2 disposed on both sides. The second source / drain pattern 250 may contact the corresponding second sheet pattern NS2.

[0117] The third source / drain pattern 350 may be disposed between the third gate structures GS3 adjacent in the first direction D1. The third source / drain pattern 350 may be connected to the third channel pattern CH3 disposed on both sides. The third source / drain pattern 350 may contact each of the third sheet patterns NS3.

[0118] The fourth source / drain pattern 450 may be disposed between the first gate structure GS1 and the second gate structure GS2 adjacent to each other along the first direction D1. The fourth source / drain pattern 450 may be connected to the first channel pattern CH1 and the second channel pattern CH2. The fourth source / drain pattern 450 may be in contact with each first sheet pattern NS1 and each second sheet pattern NS2. In some embodiments, the fourth source / drain pattern 450 may be disposed between the second gate structure GS2 and the third gate structure GS3 adjacent to each other along the first direction D1. The fourth source / drain pattern 450 may be connected to the second channel pattern CH2 and the third channel pattern CH3. The fourth source / drain pattern 450 may be in contact with each second sheet pattern NS2 and each third sheet pattern NS3. Although not shown, the fourth source / drain pattern 450 may be disposed between the first gate structure GS1 and the third gate structure GS3 adjacent to each other along the first direction D1.

[0119] For example, the number of the second sheet patterns NS2 disposed on one side of the fourth source / drain pattern 450 is greater than the number of the third sheet patterns NS3 disposed on the other side of the fourth source / drain pattern 450. Figure 2 From the perspective of the cross-sectional view in FIG. 1 , the uppermost portion on one side of the fourth source / drain pattern 450 may be higher than the uppermost portion on the other side of the fourth source / drain pattern 450. That is, the upper surface of the fourth source / drain pattern 450 may have an inclined surface. When the fourth contact silicide film 455 is disposed on the fourth source / drain pattern 450, it can be inferred that the upper surface of the fourth source / drain pattern 450 has an inclined surface through the upper surface of the fourth contact silicide film 455. The upper surface of the fourth contact silicide film 455 may contact the fourth source / drain contact 470.

[0120] The first internal gate structure GS1_I may contact the first source / drain pattern 150. The first internal gate structure GS1_I may contact the fourth source / drain pattern 450. The first gate insulating film 130 of the first internal gate structure GS1_I may contact the first source / drain pattern 150 and / or the fourth source / drain pattern 450.

[0121] The first outer gate structure GS1_O may not contact the first source / drain pattern 150. The first outer gate structure GS1_O may not contact the fourth source / drain pattern 450.

[0122] The second inner gate structure GS2_I and the second outer gate structure GS2_O may be in contact with the second source / drain pattern 250. The second inner gate structure GS2_I and the second outer gate structure GS2_O may be in contact with the fourth source / drain pattern 450. The second gate insulating film 230 of the second inner gate structure GS2_I and the second outer gate structure GS2_O may be in contact with the second source / drain pattern 250 and / or the fourth source / drain pattern 450.

[0123] The third inner gate structure GS3_I and the third outer gate structure GS3_O may be in contact with the third source / drain pattern 350. The third inner gate structure GS3_I and the third outer gate structure GS3_O may be in contact with the fourth source / drain pattern 450. The third gate insulating film 330 of the third inner gate structure GS3_I and the third gate insulating film 330 of the third outer gate structure GS3_O may be in contact with the third source / drain pattern 350 and / or the fourth source / drain pattern 450.

[0124] An upper surface of the second source / drain pattern 250 is lower than an upper surface of the first source / drain pattern 150 , and is higher than an upper surface of the third source / drain pattern 350 .

[0125] Each of the first to fourth source / drain patterns 150, 250, 350, and 450 may include an epitaxial pattern. Each of the first to fourth source / drain patterns 150, 250, 350, and 450 may include a semiconductor material.

[0126] The first to fourth source / drain patterns 150, 250, 350, and 450 may include dopants of the same conductivity type. The first to fourth source / drain patterns 150, 250, 350, and 450 may include p-type dopants or n-type dopants. The p-type dopant may include, but is not limited to, at least one of boron (B) and / or gallium (Ga). The n-type dopant may include, but is not limited to, at least one of phosphorus (P), arsenic (As), antimony (Sb), and / or bismuth (Bi).

[0127] The source / drain etch stop film 185 may extend along outer walls of the first to third gate spacers 140, 240, and 340 and sidewalls of the first to third source / drain patterns 150, 250, and 350. Although not shown, the source / drain etch stop film 185 may extend along sidewalls of the fourth source / drain pattern 450.

[0128] The source / drain etch stop film 185 may extend along the upper surface of the field insulating film 105. For example, the source / drain etch stop film 185 may contact the sidewalls of the first to third source / drain patterns 150, 250, and 350. Although not shown, the source / drain etch stop film 185 may contact the sidewalls of the fourth source / drain pattern 450.

[0129] The source / drain etch stop film 185 may not extend along the sidewalls of the first gate capping pattern 145, the second gate capping pattern 245, and the third gate capping pattern 345. Unlike the illustrated example, the source / drain etch stop film 185 may extend along the sidewalls of the first to third gate capping patterns 145, 245, and 345.

[0130] The source / drain etch stop film 185 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and / or combinations thereof.

[0131] The first upper interlayer insulating film 190 may be disposed on the substrate 100. The first upper interlayer insulating film 190 may be disposed on the source / drain etch stop film 185.

[0132] The first upper interlayer insulating film 190 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant material. The low dielectric constant material may have a dielectric constant less than or lower than 3.9, which is the dielectric constant of silicon oxide.

[0133] The contact separation structure CSS may be disposed inside the first upper interlayer insulating film 190. The contact separation structure CSS may not extend to the field insulating film 105.

[0134] The contact separation structure CSS may not separate the source / drain etch stop film 185. A portion of the first upper interlayer insulating film 190 may be disposed between the contact separation structure CSS and the field insulating film 105. The width of the contact separation structure CSS in the second direction D2 may increase in a direction away from the field insulating film 105.

[0135] The contact separation structure CSS may be disposed on both sides of the first to fourth source / drain patterns 150, 250, 350, and 450. In other words, the first to fourth source / drain patterns 150, 250, 350, and 450 may each be disposed between the contact separation structures CSS adjacent in the second direction D2.

[0136] The contact separation structure CSS includes an insulating material. The contact separation structure CSS may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), and / or a combination thereof. Although the contact separation structure CSS is shown as a single film, this is only for convenience of explanation and the embodiment is not limited thereto.

[0137] The first source / drain contact 170 may be disposed on the first source / drain pattern 150. The first source / drain contact 170 is electrically connected to the first source / drain pattern 150. The first source / drain contact 170 may be disposed on the first upper interlayer insulating film 190.

[0138] The second source / drain contact 270 may be disposed on the second source / drain pattern 250. The second source / drain contact 270 is electrically connected to the second source / drain pattern 250. The second source / drain contact 270 may be disposed on the first upper interlayer insulating film 190.

[0139] The third source / drain contact 370 may be disposed on the third source / drain pattern 350. The third source / drain contact 370 is electrically connected to the third source / drain pattern 350. The third source / drain contact 370 may be disposed on the first upper interlayer insulating film 190. The fourth source / drain contact 470 may be disposed on the fourth source / drain pattern 450. The fourth source / drain contact 470 is electrically connected to the fourth source / drain pattern 150.

[0140] The first to fourth source / drain contacts 170, 270, 370, and 470 are disposed between the contact separation structures CSS. The first to third source / drain contacts 170, 270, and 370 may contact the contact separation structures CSS. Although not shown, the fourth source / drain contact 470 may contact the contact separation structures CSS.

[0141] The height from the upper surface of the field insulating film 105 to the lower surface of the first source / drain pattern 150 may be the same as the height from the upper surface of the field insulating film 105 to the lower surface of the second source / drain pattern 250. The height from the upper surface of the field insulating film 105 to the lower surface of the first source / drain pattern 150 may be the same as the height from the upper surface of the field insulating film 105 to the lower surface of the third source / drain pattern 350.

[0142] In such Figure 2 In the illustrated cross-sectional view, a lower surface of the fourth source / drain contact 470 connected to an upper surface of the fourth source / drain pattern 450 having an inclined surface may have an inclined surface.

[0143] The first contact silicide film 155 may be disposed between the first source / drain contact 170 and the first source / drain pattern 150. The second contact silicide film 255 may be disposed between the second source / drain contact 270 and the second source / drain pattern 250. The third contact silicide film 355 may be disposed between the third source / drain contact 370 and the third source / drain pattern 350. The fourth contact silicide film 455 may be disposed between the fourth source / drain contact 470 and the fourth source / drain pattern 450.

[0144] Although the first source / drain contact to the fourth source / drain contact 170, 270, 370 and 470 are shown as having a single conductive film structure, the embodiment is not limited thereto. Unlike the example shown, the first source / drain contact to the fourth source / drain contact 170, 270, 370 and 470 may have a multi-conductive film structure, which includes a barrier film and a plug film. The first source / drain contact to the fourth source / drain contact 170, 270, 370 and 470 may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride and / or a two-dimensional material (2D material). The first contact silicide film to the fourth contact silicide film 155, 255, 355 and 455 may include a metal silicide material.

[0145] The 2D material may include a 2D allotrope or a 2D compound, and may include, but is not limited to, at least one of graphene, boron nitride (BN), molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, and / or tantalum sulfide. That is, since the above 2D materials are listed only as examples, the 2D materials that may be included in the semiconductor device of the present disclosure are not limited to the above materials.

[0146] The second upper interlayer insulating film 191 may be disposed on the first to third gate capping patterns 145 , 245 , and 345 and the first to fourth source / drain contacts 170 , 270 , 370 , and 470 .

[0147] The second upper interlayer insulating film 191 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant material. The low dielectric constant material may have a dielectric constant less than or lower than 3.9, which is the dielectric constant of silicon oxide.

[0148] The first gate contact 175 may be disposed inside the second upper interlayer insulating film 191 and the first gate capping pattern 145. The first gate contact 175 may pass through the second upper interlayer insulating film 191 and the first gate capping pattern 145. The first gate contact 175 may be connected to the first gate electrode 120.

[0149] The second gate contact 275 may be disposed inside the second upper interlayer insulating film 191 and the second gate capping pattern 245. The second gate contact 275 may pass through the second upper interlayer insulating film 191 and the second gate capping pattern 245. The second gate contact 275 may be connected to the second gate electrode 220.

[0150] The third gate contact 375 may be disposed inside the second upper interlayer insulating film 191 and the third gate capping pattern 345. The third gate contact 375 may pass through the second upper interlayer insulating film 191 and the third gate capping pattern 345. The third gate contact 375 may be connected to the third gate electrode 320.

[0151] A height H14 from the upper surface BP1_US of the first lower pattern to the lower surface of the first gate contact 175 may be the same as a height H24 from the upper surface BP1_US of the first lower pattern to the lower surface of the second gate contact 275. A height H14 from the upper surface BP1_US of the first lower pattern to the lower surface of the first gate contact 175 may be the same as a height H34 from the upper surface BP1_US of the first lower pattern to the lower surface of the third gate contact 375.

[0152] For example, the second gate contact 275 may be connected to the second portion 220R2 of the second gate electrode. The second gate contact 275 may be in contact with the upper surface 220US of the second portion 220R2 of the second gate electrode. The third gate contact 375 may be connected to the second portion 320R2 of the third gate electrode. The third gate contact 375 may be in contact with the upper surface 320US of the second portion 320R2 of the third gate electrode.

[0153] Although the first gate contact 175 is shown as being connected to the second portion 120R2 of the first gate electrode, the embodiment is not limited thereto. It goes without saying that the first gate contact 175 may be connected to the first portion 120R1 of the first gate electrode.

[0154] Although the first to third gate contacts 175, 275, and 375 are shown as having a single conductive film structure, the embodiment is not limited thereto. Unlike the illustrated example, the first to third gate contacts 175, 275, and 375 may have a multi-conductive film structure including a barrier film and a plug film. The first to third gate contacts 175, 275, and 375 may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and / or a two-dimensional material.

[0155] The source / drain via 195 may be disposed inside the second upper interlayer insulating film 191. The source / drain via 195 may be disposed on the first to third source / drain contacts 170, 270, and 370. The source / drain via 195 may be connected to the first to third source / drain contacts 170, 270, and 370. Although not shown, the source / drain via 195 may be connected to the fourth source / drain contact 470.

[0156] Although the source / drain via 195 is shown as having a single conductive film structure, the embodiment is not limited thereto. Unlike the example shown, the source / drain via 195 may have a multi-conductive film structure including a barrier film and a plug film. The source / drain via 195 may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and / or a two-dimensional material.

[0157] Figures 8 to 11 are respectively used to illustrate semiconductor devices according to some embodiments. Figures 1 to 7 The points described are different.

[0158] For reference, Figures 8 to 10 Along Figure 1 A cross-sectional view taken along line AA. Fig.11 is along Figure 1 Cross-sectional views taken along lines BB, CC, and DD.

[0159] refer to Figure 8 , in the semiconductor device according to some embodiments, the second outer gate structure GS2_O may not contact the second source / drain pattern 250 and / or the fourth source / drain pattern 450 .

[0160] The third outer gate structure GS3_O may not contact the third source / drain pattern 350 and / or the fourth source / drain pattern 450 .

[0161] From the perspective of the cross-sectional view, the second gate spacer 240 is not disposed on the second outer gate structure GS2_O. The second outer gate structure GS2_O does not enter between the second gate spacer 240 and the second channel pattern CH2.

[0162] The third gate spacer 340 is not disposed on the third outer gate structure GS3_O. A portion of the third outer gate structure GS3_O does not enter between the third gate spacer 340 and the third channel pattern CH3.

[0163] refer to Fig. 9 , the semiconductor device according to some embodiments may further include a first inner spacer 140IN, a second inner spacer 240IN, and a third inner spacer 340IN.

[0164] The first inner spacer 140IN may be disposed between the first inner gate structure GS1_I and the first source / drain pattern 150. The first inner spacer 140IN may be disposed between the first inner gate structure GS1_I and the fourth source / drain pattern 450. From the perspective of the cross-sectional view, the first inner spacer 140IN is not disposed on the upper surface CH1_US of the first channel pattern. The first inner spacer 140IN may contact the first inner gate structure GS1_I, the first source / drain pattern 150, and the fourth source / drain pattern 450.

[0165] The second inner spacer 240IN may be disposed between the second inner gate structure GS2_I and the second source / drain pattern 250. The second inner spacer 240IN may be disposed between the second inner gate structure GS2_I and the fourth source / drain pattern 450. The second inner spacer 240IN may contact the second inner gate structure GS2_I, the second source / drain pattern 250, and the fourth source / drain pattern 450.

[0166] The second inner spacer 240IN may be disposed between the second outer gate structure GS2_O and the second source / drain pattern 250. The second inner spacer 240IN may be disposed between the second outer gate structure GS2_O and the fourth source / drain pattern 450. From a cross-sectional view perspective, the second inner spacer 240IN may be disposed on an upper surface CH2_US of the second channel pattern.

[0167] The third inner spacer 340IN may be disposed between the third inner gate structure GS3_I and the third source / drain pattern 350. The third inner spacer 340IN may be disposed between the third inner gate structure GS3_I and the fourth source / drain pattern 450. The third inner spacer 340IN may contact the third inner gate structure GS_I, the third source / drain pattern 350, and the fourth source / drain pattern 450.

[0168] The third inner spacer 340IN may be disposed between the third outer gate structure GS3_O and the third source / drain pattern 350. The third inner spacer 340IN may be disposed between the third outer gate structure GS3_O and the fourth source / drain pattern 450. From a cross-sectional view perspective, the third inner spacer 340IN may be disposed on an upper surface CH3_US of the third channel pattern.

[0169] The first inner spacer 140IN, the second inner spacer 240IN, and the third inner spacer 340IN may each include an insulating material.

[0170] refer to Fig.10 According to some embodiments, the semiconductor device may further include a rear source / drain contact 470_BC and a rear wiring line 50 .

[0171] The first lower pattern BP1 may be disposed on the insulating substrate 290. The insulating substrate 290 may be disposed on a lower surface of the first lower pattern BP1. The lower surface of the first lower pattern BP1 may be opposite to the upper surface BP1_US of the first lower pattern in the third direction D3.

[0172] The insulating substrate 290 includes an insulating material and may include at least one of silicon oxide, silicon nitride, and / or a combination thereof. The insulating substrate 290 may be removed during the manufacturing process. Figures 2 to 4 The substrate 100 is then formed by a vapor deposition process or the like.

[0173] The rear wiring line 50 may be disposed inside the insulating substrate 290. The rear wiring line 50 may include a line portion and a via portion. Although the line portion of the rear wiring line 50 is shown as extending in the first direction D1, this is only for ease of explanation, and the embodiment is not limited thereto. The via portion of the rear wiring line 50 may protrude from the line portion of the rear wiring line 50 in the third direction D3. Unlike the example shown, the rear wiring line 50 may not include a via portion.

[0174] The rear source / drain contact 470_BC may be disposed between the fourth source / drain pattern 450 and the rear wiring line 50. The rear source / drain contact 470_BC electrically connects the fourth source / drain contact 470 and the rear wiring line 50.

[0175] Although the rear source / drain contact 470_BC is illustrated as being connected to a portion of the fourth source / drain pattern 450 , this is only for convenience of explanation and embodiments are not limited thereto.

[0176] Although the rear wiring line 50 is shown as being connected to the fourth source / drain pattern 450 , the embodiment is not limited thereto. The rear wiring line 50 may be connected to at least one of the first to third source / drain patterns 150 , 250 , and 350 .

[0177] The rear contact silicide film 455_BC may be disposed between the rear source / drain contact 470_BC and the fourth source / drain pattern 450. The rear contact silicide film 455_BC may include a metal silicide material.

[0178] Although the rear source / drain contact 470_BC and the rear wiring line 50 are both shown as a single conductive film, the embodiment is not limited thereto. Unlike the example shown, at least one of the rear source / drain contact 470_BC and the rear wiring line 50 may have a multi-conductive film structure including a barrier film and a release film. The rear contact silicide film 455_BC and the rear wiring line 50 may each include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and / or a two-dimensional material.

[0179] refer to Fig.11 In the semiconductor device according to some embodiments, the first to third gate insulating films 130 , 230 , and 330 may all extend along the sidewall of the gate separation structure GCS in the third direction D3 .

[0180] Taking the first gate insulating film 130 as an example, the first gate insulating film 130 may extend from the upper surface of the field insulating film 105 to the lower surface 145BS of the first gate capping pattern. The first gate insulating film 130 may be in contact with the first gate capping pattern 145. From the perspective of the cross-sectional view, each of the first to third gate electrodes 120, 220, and 320 may not be in contact with the sidewall of the gate separation structure GCS.

[0181] Figure 12 to Figure 14 is a diagram for explaining a semiconductor device according to some embodiments. For reference, Fig.12 is an example plan view for explaining a semiconductor device according to some embodiments. Fig.13 is along Fig.12 A cross-sectional view taken along line HH and line JJ. Fig.14 is along Fig.12 A cross-sectional view taken along line KK and line LL.

[0182] Since the description of the lower pattern, channel pattern, gate structure, gate capping pattern, gate contact, etc. to be described below can be the same as that of the embodiment of the present invention. Figures 1 to 11 The descriptions are the same and thus will be simplified or omitted.

[0183] refer to Figure 12 to Figure 14 , according to some embodiments, the semiconductor device may include a second lower pattern BP2, a third lower pattern BP3, a fifth channel pattern CH5, a sixth channel pattern CH6, a fifth gate structure GS5, a sixth gate structure GS6, a fifth gate capping pattern 545, a sixth gate capping pattern 645, a fifth source / drain pattern 550, a sixth source / drain pattern 650, a fifth gate contact 575 and a sixth gate contact 675.

[0184] The substrate 100 may include a first region I and a second region II. The first region I and the second region II may each be one of a logic region, an SRAM region, and an I / O region. As an example, the first region I and the second region II may be regions that perform the same function. As another example, the first region I and the second region II may be regions that perform different functions from each other.

[0185] As an example, the first region I and the second region II may be regions in which transistors of the same conductivity type are formed. As another example, the first region I and the second region II may be regions in which transistors of different conductivity types are formed.

[0186] The second lower pattern BP2 and the third lower pattern BP3 may each protrude in the third direction D3 from the substrate 100. The second lower pattern BP2 and the third lower pattern BP3 may each extend in the first direction D1.

[0187] The field insulating film 105 may cover or overlap at least a portion of a sidewall of the second lower pattern BP2. The field insulating film 105 may cover or overlap at least a portion of a sidewall of the third lower pattern BP3.

[0188] The fifth channel pattern CH5 may be disposed on the second lower pattern BP2. The fifth channel pattern CH5 may be disposed on the upper surface BP2_US of the second lower pattern. The sixth channel pattern CH6 may be disposed on the third lower pattern BP3. The sixth channel pattern CH6 may be disposed on the upper surface BP3_US of the third lower pattern.

[0189] The fifth channel pattern CH5 may include a plurality of fifth sheet patterns NS5. Each of the fifth sheet patterns NS5 may be disposed on the upper surface BP2_US of the second lower pattern to be spaced apart from each other in the third direction D3. The sixth channel pattern CH6 may include a plurality of sixth sheet patterns NS6. Each of the sixth sheet patterns NS6 may be disposed on the upper surface BP3_US of the third lower pattern to be spaced apart from each other in the third direction D3.

[0190] In the semiconductor device according to some embodiments, the number of the fifth sheet patterns NS5 may be different from the number of the sixth sheet patterns NS6. For example, the number of the fifth sheet patterns NS5 included in the fifth channel pattern CH5 may be greater than the number of the sixth sheet patterns NS6 included in the sixth channel pattern CH6.

[0191] The upper surface CH5_US of the fifth channel pattern may be the upper surface of the fifth sheet pattern NS5 disposed at the uppermost portion of the fifth sheet pattern NS5 included in the fifth channel pattern CH5. The upper surface CH6_US of the sixth channel pattern may be the upper surface of the sixth sheet pattern NS6 disposed at the uppermost portion of the sixth sheet pattern NS6 included in the sixth channel pattern CH6. The height from the upper surface BP2_US of the second lower pattern to the upper surface CH5_US of the fifth channel pattern is greater than the height from the upper surface BP3_US of the third lower pattern to the upper surface CH6_US of the sixth channel pattern.

[0192] The fifth gate structure GS5 may be disposed on the second lower pattern BP2. The fifth gate structure GS5 may intersect the second lower pattern BP2. The sixth gate structure GS6 may be disposed on the third lower pattern BP3. The sixth gate structure GS6 may intersect the third lower pattern BP3.

[0193] The fifth gate structure GS5 may surround the fifth channel pattern CH5. The fifth gate structure GS5 may surround each fifth sheet pattern NS5. The fifth gate structure GS5 may include a fifth inner gate structure GS5_I and a fifth outer gate structure GS5_O. The fifth gate structure GS5 may include a fifth gate electrode 520 and a fifth gate insulating film 530.

[0194] The sixth gate structure GS6 may surround the sixth channel pattern CH6 . The sixth gate structure GS6 may surround each sixth sheet pattern NS6 . The sixth gate structure GS6 may include a sixth inner gate structure GS6_I and a sixth outer gate structure GS6_O. The sixth gate structure GS6 may include a sixth gate electrode 620 and a sixth gate insulating film 630 .

[0195] The fifth gate electrode 520 may include a first portion and a second portion. The second portion of the fifth gate electrode 520 may be located on both sides of the first portion of the fifth gate electrode 520. Fig.14 In the cross-sectional view in FIG. 5 , the upper surface 520US of the fifth gate electrode may be flat. The first portion of the fifth gate electrode 520 may overlap the fifth channel pattern CH5 in the third direction D3. The second portion of the fifth gate electrode 520 may not overlap the fifth channel pattern CH5 in the third direction D3.

[0196] The sixth gate electrode 620 may include a first portion and a second portion. The second portion of the sixth gate electrode 620 may be located on both sides of the first portion of the sixth gate electrode 620. Fig.14In the cross-sectional view in FIG. 1 , the upper surface 620US of the sixth gate electrode may include a region recessed toward the sixth channel pattern CH6. The first portion of the sixth gate electrode 620 may be a region in which a portion of the sixth gate electrode 620 is recessed. The first portion of the sixth gate electrode 620 may overlap with the sixth channel pattern CH6 in the third direction D3. The second portion of the sixth gate electrode 620 may not overlap with the sixth channel pattern CH6 in the third direction D3.

[0197] For example, a height H51 from the upper surface BP2_US of the second lower pattern to the upper surface 520US of the first portion of the fifth gate electrode 520 is greater than a height H61 from the upper surface BP3_US of the third lower pattern to the upper surface 620US of the first portion of the sixth gate electrode 620 .

[0198] A height H53 from the upper surface BP2_US of the second lower pattern to the upper surface 520US of the second portion of the fifth gate electrode 520 may be the same as a height H63 from the upper surface BP3_US of the third lower pattern to the upper surface 620US of the second portion of the sixth gate electrode 620 .

[0199] Unlike the example shown, the shape of the fifth gate electrode 520 may be similar to Figure 2 and Figure 3 The shape of the second gate electrode 220 and the shape of the sixth gate electrode 620 may be similar to Figure 2 and Figure 3 In this case, the shape of the third gate electrode 320 is Figure 3 The description of the cross sections of the second gate electrode 220 and the third gate electrode 320 can be applied to the description of the cross sections of the fifth gate electrode 520 and the sixth gate electrode 620 .

[0200] The fifth gate spacer 540 may be disposed on the sidewall of the fifth gate structure GS5. The sixth gate spacer 640 may be disposed on the sidewall of the sixth gate structure GS6.

[0201] For example, in Fig.13 In the cross-sectional view in FIG. 5 , the fifth outer gate structure GS5_O may not enter between the fifth gate spacer 540 and the fifth channel pattern CH5. A portion of the sixth outer gate structure GS6_O may enter between the sixth gate spacer 640 and the sixth channel pattern CH6.

[0202] Unlike the example shown, if the shape of the fifth gate structure GS5 is similar to Figure 2 If the shapes of the second gate structure GS2 and the third gate structure GS3 are different from those of the first gate structure GS2 and the second gate structure GS3, the fifth gate spacer 540 may have a shape placed on the fifth outer gate structure GS5_O.

[0203] The fifth gate capping pattern 545 may be disposed on the upper surface 520US of the fifth gate electrode. A lower surface 545BS of the fifth gate capping pattern may be in contact with the upper surface 520US of the fifth gate electrode.

[0204] The sixth gate capping pattern 645 may be disposed on the upper surface 620US of the sixth gate electrode. A lower surface 645BS of the sixth gate capping pattern may be in contact with the upper surface 620US of the sixth gate electrode.

[0205] The upper surface 545US of the fifth gate capping pattern may be disposed on the same plane as the upper surface 645US of the sixth gate capping pattern. A height H52 from the upper surface BP2_US of the second lower pattern to the upper surface 545US of the fifth gate capping pattern may be the same as a height H62 from the upper surface BP3_US of the third lower pattern to the upper surface 645US of the sixth gate capping pattern.

[0206] The thickness t5 of the fifth gate capping pattern 545 may be different from the thickness t6 of the sixth gate capping pattern 645. The thickness t5 of the fifth gate capping pattern 545 may be less than or lower than the thickness t6 of the sixth gate capping pattern 645.

[0207] The fifth gate structure GS5 and / or the sixth gate structure GS6 may be disposed between the gate separation structures GCS adjacent to each other along the second direction D2.

[0208] The fifth source / drain pattern 550 may be disposed on the second lower pattern BP2. The fifth source / drain pattern 550 may be disposed on both sides of the fifth gate structure GS5. The fifth source / drain pattern 550 may be connected to the fifth channel pattern CH5.

[0209] The sixth source / drain pattern 650 may be disposed on the third lower pattern BP3. The sixth source / drain pattern 650 may be disposed on both sides of the sixth gate structure GS6. The sixth source / drain pattern 650 may be connected to the sixth channel pattern CH6.

[0210] The fifth inner gate structure GS5_I may be in contact with the fifth source / drain pattern 550. The fifth outer gate structure GS5_O may not be in contact with the fifth source / drain pattern 550.

[0211] The sixth inner gate structure GS6_I may be in contact with the sixth source / drain pattern 650. The sixth outer gate structure GS6_O may be in contact with the sixth source / drain pattern 550.

[0212] The fifth source / drain pattern 550 and the sixth source / drain pattern 650 may each include an epitaxial pattern. The fifth source / drain pattern 550 and the sixth source / drain pattern 650 may each include a semiconductor material.

[0213] The fifth source / drain pattern 550 and the sixth source / drain pattern 650 may each be disposed between the contact separation structures CSS adjacent in the second direction D2.

[0214] A fifth source / drain contact 570 may be disposed on the fifth source / drain pattern 550. The fifth source / drain contact 570 is electrically connected to the fifth source / drain pattern 550. A sixth source / drain contact 670 may be disposed on the sixth source / drain pattern 650. The sixth source / drain contact 670 is electrically connected to the sixth source / drain pattern 650.

[0215] The fifth contact silicide film 555 may be disposed between the fifth source / drain contact 570 and the fifth source / drain pattern 550. The sixth contact silicide film 655 may be disposed between the sixth source / drain contact 670 and the sixth source / drain pattern 650.

[0216] The fifth gate contact 575 may pass through the second upper interlayer insulating film 191 and the fifth gate capping pattern 545. The fifth gate contact 575 may be connected to the fifth gate electrode 520.

[0217] The sixth gate contact 675 may pass through the second upper interlayer insulating film 191 and the sixth gate capping pattern 645. The sixth gate contact 675 may be connected to the sixth gate electrode 620.

[0218] A height H54 from the upper surface BP2_US of the second lower pattern to the lower surface of the fifth gate contact 575 may be the same as a height H64 from the upper surface BP3_US of the third lower pattern to the lower surface of the sixth gate contact 675. For example, the sixth gate contact 675 may be connected to the second portion of the sixth gate electrode 620.

[0219] The source / drain via 195 may be disposed on the fifth source / drain contact 570 and the sixth source / drain contact 670. The source / drain via 195 may be connected to the fifth source / drain contact 570 and the sixth source / drain contact 670.

[0220] Fig.15 and Fig.16 is a diagram for illustrating a semiconductor device according to some embodiments. For ease of explanation, the description will focus on the use of Figure 12 to Figure 14 The points explained are different.

[0221] refer to Fig.15 and Fig.16 , in the semiconductor device according to some embodiments, the number of the fifth sheet patterns NS5 included in the fifth channel pattern CH5 may be the same as the number of the sixth sheet patterns NS6 included in the sixth channel pattern.

[0222] A height from the upper surface BP2_US of the second lower pattern to the upper surface CH5_US of the fifth channel pattern may be the same as a height from the upper surface BP3_US of the third lower pattern to the upper surface CH6_US of the sixth channel pattern.

[0223] exist Fig.15 , a height from an upper surface CH5_US of the fifth channel pattern to an upper surface 520US of the fifth gate electrode is greater than a height from an upper surface CH6_US of the sixth channel pattern to an upper surface 620US of the sixth gate electrode.

[0224] The fifth outer gate structure GS5_O may enter between the fifth gate spacer 540 and the fifth channel pattern CH5. The fifth gate spacer 540 may have a shape disposed on the fifth outer gate structure GS5_O.

[0225] Figures 17 to 34 is a diagram for explaining an intermediate stage of a method for manufacturing a semiconductor device according to some embodiments.

[0226] refer to Fig.17 and Fig.18 , a mold fin pattern FMS may be formed on the substrate 100 .

[0227] The mold fin pattern FMS may extend in the first direction D1. The mold fin pattern FMS may include a first lower pattern BP1 and an upper pattern structure UP1. The upper pattern structure UP1 may be formed on the first lower pattern BP1.

[0228] The upper pattern structure UP1 may include a plurality of sacrificial patterns SC_L and a plurality of active patterns ACT_L alternately stacked. For example, the active pattern ACT_L may include a silicon film. The sacrificial pattern SC_L may include a silicon-germanium film. In the upper pattern structure UP1, the active pattern ACT_L may be disposed at the uppermost portion.

[0229] The mold hard mask pattern F_HM may be disposed on the mold fin pattern FMS. The mold hard mask pattern F_HM may be used as a mask for forming the mold fin pattern FMS. For example, the mold hard mask pattern F_HM may include, but is not limited to, silicon nitride.

[0230] Subsequently, a pre-field insulating film 105P may be formed on the substrate 100. The pre-field insulating film 105P may cover or overlap sidewalls of the mold fin pattern FMS and sidewalls of the mold hard mask pattern F_HM. The pre-field insulating film 105P may not cover or may not overlap an upper surface of the mold hard mask pattern F_HM.

[0231] refer to Fig.19 and Fig. 20, a pattern mask PT_M may be formed on the pre-field insulating film 105P and the mold hard mask pattern F_HM.

[0232] The pattern mask PT_M may include a first opening exposing a portion of the mold hard mask pattern F_HM. A first etching process may be performed using the pattern mask PT_M including the first opening.

[0233] When the first etching process is being performed, the molded hard mask pattern F_HM of the portion overlapping the first opening may be removed. In addition, when the first etching process is being performed, at least one or more active patterns ACT_L may be removed from the portion overlapping the first opening. For example, the first etching process may remove a portion of one active pattern ACT_L. For example, when the sacrificial pattern SC_L disposed at the uppermost portion is exposed, the first etching process may be terminated. A first etching trench may be formed by the first etching process.

[0234] refer to Figures 19 to 22 , the first etch trenches formed during the first etch process may be filled with the pattern mask PT_M.

[0235] Next, a second opening exposing another portion of the mold hard mask pattern F_HM may be formed in the pattern mask PT_M. A second etching process may be performed using the pattern mask PT_M including the second opening.

[0236] When the second etching process is being performed, the molded hard mask pattern F_HM of the portion overlapping the second opening may be removed. In addition, when the second etching process is being performed, at least one or more active patterns ACT_L may be removed from the portion overlapping the second opening. For example, the second etching process may remove portions of two active patterns ACT_L. For example, portions of the sacrificial pattern SC_L disposed at the uppermost portion may also be removed during the second etching process. When the sacrificial pattern SC_L located directly below the uppermost portion is exposed, the second etching process may be terminated.

[0237] A plurality of steps having a stair shape may be formed in the mold fin pattern FMS through the first and second etching processes.

[0238] refer to Figure 21 to Figure 24 , the pattern mask PT_M can be removed.

[0239] Thereafter, the mold hard mask pattern F_HM may be removed. A field insulating film 105 may be formed on the substrate 100 by removing a portion of the pre-field insulating film 105P. The field insulating film 105 may cover or overlap a sidewall of the first lower pattern BP1.

[0240] A plurality of dummy gate electrodes 120D may then be formed on the mold fin pattern FMS. The plurality of dummy gate electrodes 120D may not be formed at the stepped portion of the mold fin pattern FMS. In some embodiments, the dummy gate electrodes 120D do not overlap the stepped portion of the mold fin pattern FMS in the third direction D3.

[0241] Each of the dummy gate electrodes 120D may cross the mold fin pattern FMS. Each of the dummy gate electrodes 120D may extend in the second direction D2. Each of the dummy gate electrodes 120D may be spaced apart in the first direction D1.

[0242] A dummy gate insulating film 130D may be formed between the dummy gate electrode 120D and the mold fin pattern FMS. The dummy gate insulating film 130D may be formed along the contour of the mold fin pattern FMS. A dummy gate capping film 120HM may be formed on the dummy gate electrode 120D. The dummy gate electrode 120D may be formed using the dummy gate capping film 120HM as a mask.

[0243] The dummy gate electrode 120D may include, for example, polysilicon, but is not limited thereto. The dummy gate insulating film 130D may include, but is not limited to, silicon oxide. The dummy gate capping film 120HM may include, for example, silicon nitride, but is not limited thereto.

[0244] refer to Figure 23 to Figure 26 , the dummy gate spacer 140D may be formed on the sidewall of the dummy gate electrode 120D.

[0245] When the dummy gate spacer 140D is being formed, a source / drain recess may be formed inside the mold fin pattern FMS. The source / drain recess may be formed between the dummy gate electrodes 120D adjacent in the first direction D1.

[0246] The first to fourth source / drain patterns 150, 250, 350, and 450 may be formed inside the mold fin pattern FMS. The first to fourth source / drain patterns 150, 250, 350, and 450 may fill the source / drain recesses.

[0247] The first to fourth source / drain patterns 150, 250, 350, and 450 may be formed on the first lower pattern BP1. The first to fourth source / drain patterns 150, 250, 350, and 450 may be formed between the dummy gate electrodes 120D adjacent to each other in the first direction D1. An upper surface of the fourth source / drain pattern 450 formed at a stepped portion of the mold fin pattern FMS may have an inclined surface.

[0248] Subsequently, a source / drain etch stop film 185 may be formed on the first to fourth source / drain patterns 150, 250, 350, and 450. The source / drain etch stop film 185 may be formed along contours of the first to fourth source / drain patterns 150, 250, 350, and 450.

[0249] refer to Figure 25 to Figure 28 , a first upper interlayer insulating film 190 may be formed on the source / drain etch stop film 185 .

[0250] A portion of the dummy gate capping film 120HM and the first upper interlayer insulating film 190 may be removed to expose an upper surface of the dummy gate electrode 120D. When the upper surface of the dummy gate electrode 120D is exposed, a first pre-gate spacer 140P may be formed.

[0251] Subsequently, the dummy gate insulating film 130D and the dummy gate electrode 120D may be removed to expose the upper pattern structure UP1 between the first pre-gate spacers 140P.

[0252] Next, by removing the sacrificial pattern SC_L, a first channel pattern CH1 including a first sheet pattern NS1, a second channel pattern CH2 including a second sheet pattern NS2, and a third channel pattern CH3 including a third sheet pattern NS3 may be formed. Gate trenches are correspondingly formed between the first pre-gate spacers 140P.

[0253] Subsequently, a first pre-gate insulating film 130P and a first pre-gate electrode 120P may be formed inside the gate trench. The first pre-gate insulating film 130P and the first pre-gate electrode 120P may surround the first, second, and third sheet patterns NS1, NS2, and NS3 in a cross-sectional plane of the first and third directions D1 and D3.

[0254] refer to Figures 27 to 30 , a portion of the first pre-gate insulating film 130P and a portion of the first pre-gate electrode 120P may be removed to form a first gate structure GS1 surrounding the first sheet pattern NS1.

[0255] When the first gate structure GS1 is being formed, a portion of the first pre-gate spacer 140P may be etched. Thus, the first gate spacer 140 may be formed on the sidewall of the first gate structure GS1.

[0256] By removing a portion of the first pre-gate insulating film 130P and a portion of the first pre-gate electrode 120P, a second pre-gate insulating film 130P1 and a second pre-gate electrode 120P1 surrounding the second sheet pattern NS2 and the third sheet pattern NS3 may be formed. A portion of the first pre-gate spacer 140P may be etched to form a second pre-gate spacer 140P1 on a sidewall of the second pre-gate electrode 120P1.

[0257] refer to Figure 29 to Figure 32 , a gate recess mask RC_M may be formed on the first gate structure GS1 , the second pre-gate insulating film 130P1 , and the second pre-gate electrode 120P1 .

[0258] The gate recess mask RC_M may include a first recess opening. The first recess opening may overlap the second channel pattern CH2 in the third direction D3.

[0259] The first gate recess process may be performed using the gate recess mask RC_M including the first recess opening.

[0260] While the first gate recess process is being performed, a portion of the second pre-gate insulating film 130P1 and a portion of the second pre-gate electrode 120P1 may be etched. A second gate structure GS2 surrounding the second sheet pattern NS2 may be formed accordingly.

[0261] When the second gate structure GS2 is being formed, a portion of the second pre-gate spacer 140P1 may be etched. Thus, the second gate spacer 240 may be formed on the sidewall of the second gate structure GS2.

[0262] refer to Figure 31 to Figure 34 After forming the second gate structure GS2, the gate recess mask RC_M may partially or completely fill the space on the second gate structure GS2 using an additional recess mask material.

[0263] Subsequently, a gate recess mask RC_M including a second recess opening may be formed The second recess opening may overlap the third channel pattern CH3 in the third direction D3.

[0264] The second gate recess process may be performed using a gate recess mask RC_M including a second recess opening. While the second gate recess process is being performed, a portion of the second pre-gate insulating film 130P1 and a portion of the second pre-gate electrode 120P1 may be etched. A third gate structure GS3 surrounding the third sheet pattern NS3 may be formed accordingly.

[0265] When the third gate structure GS3 is being formed, a portion of the second pre-gate spacer 140P1 may be etched. Thus, the third gate spacer 340 may be formed on the sidewall of the third gate structure GS3.

[0266] Subsequently, the gate recess mask RC_M including the second recess opening may be removed.

[0267] Next, refer to Figure 2 and Figure 3 , first to third gate capping patterns 145 , 245 , and 345 may be formed on the first to third gate structures GS1 , GS2 , and GS3 .

[0268] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the preferred embodiment without departing substantially from the principles of the inventive concept. Therefore, the preferred embodiments disclosed by the present invention are for general and descriptive purposes and not for limiting purposes.

Claims

1. A semiconductor device, comprising: a lower pattern extending in a first direction; a first channel pattern on the lower pattern and including a plurality of first sheet patterns spaced apart in a second direction, the second direction being different from the first direction; a second channel pattern on the lower pattern, comprising a plurality of second sheet patterns spaced apart in the second direction and spaced apart from the first channel pattern in the first direction; a first gate structure extending around the first sheet pattern in a plane including the first direction and the second direction and including a first gate electrode and a first gate insulating film; a second gate structure extending around the second sheet-like pattern in the plane including the first direction and the second direction and including a second gate electrode and a second gate insulating film; a first gate capping pattern, on the first gate structure; as well as A second gate capping pattern, on the second gate structure, wherein the number of the first sheet patterns is different from the number of the second sheet patterns, and Wherein, in the second direction, a thickness of the first gate capping pattern is different from a thickness of the second gate capping pattern.

2. The semiconductor device according to claim 1, in, The number of the first sheet patterns is greater than the number of the second sheet patterns, and the thickness of the first gate capping pattern is less than the thickness of the second gate capping pattern.

3. The semiconductor device according to claim 2, in, A distance from an upper surface of the lower pattern to an upper surface of the first gate capping pattern is the same as a distance from the upper surface of the lower pattern to an upper surface of the second gate capping pattern.

4. The semiconductor device according to claim 1, in, A distance from an upper surface of the lower pattern to a lower surface of the first gate capping pattern is different from a distance from the upper surface of the lower pattern to a lower surface of the second gate capping pattern.

5. The semiconductor device according to claim 1, in, A thickness of the first gate capping pattern in a portion overlapping the first channel pattern along the second direction is different from a thickness of the second gate capping pattern in a portion overlapping the second channel pattern along the second direction.

6. The semiconductor device according to claim 1, further comprising: a source / drain pattern on the lower pattern and electrically connected to the first channel pattern and the second channel pattern, The source / drain pattern is in contact with each of the first sheet patterns and each of the second sheet patterns.

7. The semiconductor device according to claim 6, in, The first gate structure includes a first outer gate structure on an upper surface of the first channel pattern, wherein the second gate structure comprises a second outer gate structure on an upper surface of the second channel pattern, wherein the first gate insulating film of the first outer gate structure is spaced apart from the source / drain pattern, and The second gate insulating film of the second outer gate structure is in contact with the source / drain pattern.

8. The semiconductor device according to claim 6, in, The first gate structure includes a first outer gate structure on an upper surface of the first channel pattern, wherein the second gate structure comprises a second outer gate structure on an upper surface of the second channel pattern, and The first gate insulating film of the first outer gate structure and the second gate insulating film of the second outer gate structure are in contact with the source / drain pattern.

9. The semiconductor device according to claim 1, further comprising: a first gate contact extending into the first gate capping pattern and electrically connected to the first gate electrode; and a second gate contact extending into the second gate capping pattern and electrically connected to the second gate electrode, Wherein, a distance from an upper surface of the lower pattern to a lower surface of the first gate contact is equal to a distance from the upper surface of the lower pattern to a lower surface of the second gate contact.

10. The semiconductor device according to claim 9, in, The number of the first sheet patterns is greater than the number of the second sheet patterns, wherein the second gate electrode comprises a first portion and a second portion, and The first portion of the second gate electrode overlaps with the second channel pattern in the second direction, and a distance from the upper surface of the lower pattern to an upper surface of the first portion of the second gate electrode is smaller than a distance from the upper surface of the lower pattern to an upper surface of the second portion of the second gate electrode.

11. The semiconductor device according to claim 10, in, The second gate contact is electrically connected to the second portion of the second gate electrode.

12. A semiconductor device comprising: a lower pattern extending in a first direction; a first channel pattern on the lower pattern and including a plurality of first sheet patterns spaced apart in a second direction, the second direction being different from the first direction; a second channel pattern on the lower pattern, comprising a plurality of second sheet patterns spaced apart in the second direction and spaced apart from the first channel pattern in the first direction; a first gate electrode extending around the first sheet pattern in a plane including the first direction and the second direction; a second gate electrode extending around the second sheet pattern in the plane including the first direction and the second direction; a first gate capping pattern, on the first gate electrode; a second gate capping pattern, on the second gate electrode; a first gate contact extending into the first gate capping pattern and electrically connected to the first gate electrode; as well as a second gate contact extending into the second gate capping pattern and electrically connected to the second gate electrode, wherein the number of the first sheet patterns is different from the number of the second sheet patterns, wherein the first gate electrode includes a first portion of the first gate electrode overlapping the first channel pattern in the second direction, wherein the second gate electrode includes a first portion of the second gate electrode overlapping the second channel pattern in the second direction, and Wherein, a distance from an upper surface of the lower pattern to an upper surface of the first portion of the first gate electrode is different from a distance from the upper surface of the lower pattern to an upper surface of the first portion of the second gate electrode.

13. The semiconductor device according to claim 12, in, The number of the first sheet patterns is greater than the number of the second sheet patterns, and Wherein, a distance from the upper surface of the lower pattern to an upper surface of the first portion of the first gate electrode is greater than a distance from the upper surface of the lower pattern to an upper surface of the first portion of the second gate electrode.

14. The semiconductor device according to claim 12, in, A distance from the upper surface of the lower pattern to a lower surface of the first gate contact is the same as a distance from the upper surface of the lower pattern to a lower surface of the second gate contact.

15. The semiconductor device according to claim 12, in, The first gate electrode includes a second portion of the first gate electrode that is electrically connected to the first portion of the first gate electrode and does not overlap with the first channel pattern in the second direction, and Wherein, a distance from the upper surface of the lower pattern to the upper surface of the first portion of the first gate electrode is smaller than a distance from the upper surface of the lower pattern to the upper surface of the second portion of the first gate electrode.

16. The semiconductor device according to claim 15, in, The first gate contact is in contact with the upper surface of the second portion of the first gate electrode.

17. The semiconductor device according to claim 15, in, The second gate electrode includes a second portion of the second gate electrode that is electrically connected to the first portion of the second gate electrode and does not overlap with the second channel pattern in the second direction, and Wherein, a distance from the upper surface of the lower pattern to an upper surface of the second portion of the second gate electrode is equal to a distance from the upper surface of the lower pattern to an upper surface of the second portion of the first gate electrode.

18. A semiconductor device comprising: Lower pattern; a first channel pattern on the lower pattern and including a plurality of first sheet patterns; a second channel pattern on the lower pattern and comprising a plurality of second sheet patterns, wherein the number of the second sheet patterns included in the second channel pattern is less than the number of the first sheet patterns included in the first channel pattern; a source / drain pattern on the lower pattern and electrically connected to the first channel pattern and the second channel pattern; a first gate electrode extending around the first sheet-like pattern in a cross-sectional view; a second gate electrode extending around the second sheet-like pattern in the cross-sectional view; a first gate capping pattern on the first gate electrode; and a second gate capping pattern, on the second gate electrode, Wherein, in the cross-sectional view, a distance from an upper surface of the lower pattern to an upper surface of the first gate electrode is greater than a distance from the upper surface of the lower pattern to an upper surface of the second gate electrode.

19. The semiconductor device according to claim 18, in, An upper surface of the first gate capping pattern is on the same plane as an upper surface of the second gate capping pattern.

20. The semiconductor device according to claim 18, in, In the cross-sectional view, an upper surface of the source / drain pattern has an inclined surface.

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